Device and method for evaluating influence of power supply noise group on phase noise of phase-locked loop
By establishing a phase-locked loop (PLL) simulation model and evaluating the power supply noise group using the additive superposition principle, the impact of power supply noise on the PLL phase noise was resolved, thereby improving the prediction accuracy of PLL signal quality and the efficiency of power supply model selection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-23
- Publication Date
- 2026-05-15
AI Technical Summary
In traditional phase-locked loop circuits, the impact of power supply noise on phase noise is not fully assessed, leading to a decline in signal quality, especially when continuous power supply noise is superimposed, which severely degrades the signal-to-noise ratio.
A phase-locked loop (PLL) simulation model consisting of a sinusoidal phase detector, a loop filter, and a voltage-controlled oscillator (VCO) is used. The impact of power supply noise clusters on the PLL phase noise is evaluated using the additive superposition principle. Combined with the noise distribution characteristics of linear regulated power supplies, a PLL phase noise model is established, and the optimal power supply model is selected through iterative correction functions.
It improves the accuracy of phase noise prediction in phase-locked loops, effectively selects the most suitable linear regulated power supply model, and improves the signal quality of phase-locked loops.
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Figure CN122052783A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of phase-locked loop (PLL) technology, and more specifically, to a device and method for evaluating the impact of power supply noise clusters on the phase noise of a PLL. Background Technology
[0002] Traditional analog signal processing shifts the spectrum of a low-frequency clock signal to a high-frequency local oscillator signal through direct frequency multiplication, resulting in poor frequency stability of the generated local oscillator signal. With the widespread application of superheterodyne wireless communication systems, phase-locked loop (PLL) circuits have emerged to eliminate noise caused by local oscillator frequency drift, incorporating synchronous detection theory. PLL circuits effectively track the phase of the input signal, and their unique ability to extract high-purity useful signals from noise is a function that other analog circuits cannot achieve. Therefore, any interference that affects the noise of a PLL circuit will affect the quality of the locked signal, and quantifying the quality of the locked signal from the frequency domain using phase noise has always been an important research topic in PLL circuits.
[0003] Factors affecting phase-locked loop (PLL) noise can be categorized into internal and external factors. Internal factors primarily refer to the noise level determined by the PLL's own design under ideal power supply conditions, including the circuit design of frequency and phase detectors, loop filters, voltage-controlled oscillators, and frequency dividers. External factors mainly refer to the impact of the application environment on PLL noise under conditions such as high-speed control signals and actual power supply. Because the control signal is discrete—meaning that once the PLL output signal is locked, the control signal is no longer transmitted—even with a high control signal rate, the quality of the PLL output signal will not be affected in application scenarios such as PLL locking at a fixed frequency point, low frequency hopping rate, and simple frequency modulation waveform. However, power supply is continuous, and power supply noise continuously adds to the PLL circuit noise. When the power supply noise reaches a certain level, it can even modulate the PLL output signal in the form of a noise envelope, severely degrading the signal-to-noise ratio. Therefore, the lower the power supply noise, the lower the phase noise of the PLL output signal, indicating higher output signal purity. Summary of the Invention
[0004] The purpose of this invention is to provide a device and method for evaluating the impact of power supply noise clusters on phase-locked loop (PLL) phase noise, thereby improving the aforementioned problems. To achieve this objective, the technical solution adopted by this invention is as follows: In a first aspect, this application provides an apparatus for evaluating the impact of power supply noise clusters on phase noise of a phase-locked loop, comprising: A sinusoidal phase detector detects the phase difference between an external reference signal and a voltage-controlled oscillator feedback signal. The input of the loop filter is connected to the output of the sinusoidal phase detector. A voltage-controlled oscillator (VCO) has its input connected to the output of a loop filter and outputs a feedback signal to a sinusoidal phase detector. The sinusoidal phase detector includes: a frequency divider, which divides the feedback signal from the voltage-controlled oscillator; a mixer, which mixes the divided signal with an external reference signal and outputs the result; a pre-low-pass filter, which filters the output signal of the mixer to obtain an error voltage signal; a DC power supply, which supplies power to the mixer and the voltage-controlled oscillator and extends to the loop filter; and an AC signal source, which simulates power supply noise signals and combines them with the DC power supply in an additive linear superposition manner to supply power to the corresponding modules.
[0005] Preferably, in the passive loop mode of the phase-locked loop phase noise interference device, the superimposed signal of the DC power supply and the AC signal source is input to the mixer and the voltage-controlled oscillator; in the active loop mode, the superimposed signal is also input to the loop filter.
[0006] Secondly, this application also provides a method for evaluating the impact of power supply noise clusters on phase-locked loop (PLL) phase noise, including: Step 1: Establish a phase-locked loop simulation model consisting of a sinusoidal phase detector, a loop filter, and a voltage-controlled oscillator. Set parameters such as charge pump current, bias current, tuning sensitivity, loop bandwidth, and phase margin. Simulate and calculate the reference phase noise value under ideal power supply conditions. Step 2: Select a linear regulated power supply series and obtain the power supply noise distribution characteristics of different models in the series; and based on the principle of linear superposition, add the power supply noise to the DC power supply signal in an additive manner to construct a phase-locked loop linear phase model with additional power supply noise, thereby calculating the phase noise matrix with power supply noise corresponding to each model. Step 3: Construct the physical circuit of the phase-locked loop based on the simulation model, and power it with different models of linear regulated power supplies. Test and record the measured phase noise data for each model. Step 4: Compare the difference between the simulated phase noise and the measured phase noise for each model, fit the power supply noise group distribution using a power law function, and iteratively correct the function coefficients to make the difference less than the preset tolerance threshold, thereby determining an effective power supply noise evaluation function. Step 5: Repeat steps 3 and 4 for all models and calculate the yield rate of each model that meets the tolerance threshold. The model with the best yield rate and the best measured phase noise performance is determined as the best linear regulated power supply under this phase-locked loop architecture.
[0007] The beneficial effects of this invention are as follows: This invention divides the carrier frequency offset range based on the phase noise characteristics of the phase-locked loop (PLL), and uses the additive superposition principle to superimpose power supply noise groups onto the corresponding carrier frequency offset range, establishing a PLL phase noise model with additional power supply noise groups. The PLL designed using this method not only improves the accuracy of phase noise prediction, but also achieves the optimal solution through extensive training of the power supply noise group distribution model, effectively selecting the most suitable PLL model from the chosen LDO series, thus possessing significant practical engineering application value.
[0008] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description
[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 This is a schematic diagram of the method for evaluating the impact of power supply noise clusters on phase-locked loop phase noise as described in an embodiment of the present invention; Figure 2 This is a schematic diagram of the device for evaluating the impact of power supply noise clusters on phase-locked loop phase noise, as described in an embodiment of the present invention. Detailed Implementation
[0011] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0012] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0013] Compared to traditional methods that use a single-tone power supply noise model to analyze the impact on PLL phase noise while neglecting the influence of power supply noise randomness, analyzing the impact of power supply noise clustering on PLL phase noise more closely reflects the actual physical state. Based on the characteristics of the PLL phase noise, the carrier frequency offset range is defined. The additive principle is then applied to superimpose the power supply noise cluster onto the corresponding carrier frequency offset range, establishing a PLL phase noise model with the added power supply noise cluster. This method can effectively assess the actual impact of power supply noise on PLL phase noise and can be applied in engineering.
[0014] Example 1: This embodiment provides a device for evaluating the impact of power supply noise clusters on phase-locked loop (PLL) phase noise, including: A sinusoidal phase detector detects the phase difference between an external reference signal and a voltage-controlled oscillator feedback signal. The input of the loop filter is connected to the output of the sinusoidal phase detector. A voltage-controlled oscillator (VCO) has its input connected to the output of a loop filter and outputs a feedback signal to a sinusoidal phase detector. The sinusoidal phase detector includes: a frequency divider, which divides the feedback signal from the voltage-controlled oscillator; a mixer, which mixes the divided signal with an external reference signal and outputs the result; a pre-low-pass filter, which filters the output signal of the mixer to obtain an error voltage signal; a DC power supply, which supplies power to the mixer and the voltage-controlled oscillator and extends to the loop filter; and an AC signal source, which simulates power supply noise signals and combines them with the DC power supply in an additive linear superposition manner to supply power to the corresponding modules.
[0015] Preferably, in the passive loop mode of the phase-locked loop phase noise interference device, the superimposed signal of the DC power supply and the AC signal source is input to the mixer and the voltage-controlled oscillator; in the active loop mode, the superimposed signal is also input to the loop filter.
[0016] It should be noted that this application provides an apparatus for evaluating the impact of power supply noise clusters on the phase noise of a phase-locked loop, including a method for detecting an external reference signal. Feedback signal from the voltage-controlled oscillator (VCO) A sinusoidal phase detector (SPD) for the phase difference between the two signals; the SPD includes components for frequency division. The frequency divider NDIV divides the signal into frequency-divided signals. and Mix the output signal The mixer MIX, Output signal through pre-low-pass filter LPF ; Then the output signal is passed through the loop filter LF. Give VCO to achieve The stable output is supplied to the subsequent circuit.
[0017] In a passive phase-locked loop device, a DC power supply powers the MIX and VCO; an AC signal, analog power supply noise group signal, is additively superimposed on the DC signal and then input to the MIX and VCO.
[0018] In the active loop phase-locked loop device, the DC power supply powers MIX, VCO, and LF; the AC signal simulates the power supply noise group signal, which is additively superimposed on the DC signal and then input to MIX, VCO, and LF.
[0019] Example 2: This embodiment provides a method for evaluating the impact of power supply noise clusters on phase-locked loop (PLL) phase noise, including: Step 1: Establish a phase-locked loop simulation model consisting of a sinusoidal phase detector, a loop filter, and a voltage-controlled oscillator. Set parameters such as charge pump current, bias current, tuning sensitivity, loop bandwidth, and phase margin. Simulate and calculate the reference phase noise value under ideal power supply conditions. Step 2: Select a linear regulated power supply series and obtain the power supply noise distribution characteristics of different models in the series; and based on the principle of linear superposition, add the power supply noise to the DC power supply signal in an additive manner to construct a phase-locked loop linear phase model with additional power supply noise, thereby calculating the phase noise matrix with power supply noise corresponding to each model. Step 3: Construct the physical circuit of the phase-locked loop based on the simulation model, and power it with different models of linear regulated power supplies. Test and record the measured phase noise data for each model. Step 4: Compare the difference between the simulated phase noise and the measured phase noise for each model, fit the power supply noise group distribution using a power law function, and iteratively correct the function coefficients to make the difference less than the preset tolerance threshold, thereby determining an effective power supply noise evaluation function. Step 5: Repeat steps 3 and 4 for all models and calculate the yield rate of each model that meets the tolerance threshold. The model with the best yield rate and the best measured phase noise performance is determined as the best linear regulated power supply under this phase-locked loop architecture.
[0020] It should be noted that the construction process in step one is as follows: A sinusoidal phase detector model including a multiplier, a low-pass filter, and a frequency divider is constructed. The charge pump current and bias current are set in the simulation software, and constraints are applied to maintain loop stability. At the same time, the tuning sensitivity, loop bandwidth, and phase margin parameters are set, and the actual device values are generated using the parameter construction function of the simulation software. The reference clock signal is input to the aforementioned sinusoidal phase detector model. After closed-loop processing by a loop filter and a voltage-controlled oscillator, the frequency domain integration operation is performed by the phase noise calculation engine of the simulation software to obtain the reference phase noise value under ideal power supply conditions.
[0021] As shown in Figure 2, this embodiment provides a device for evaluating the impact of power supply noise clusters on the phase noise of a phase-locked loop. The device includes a sinusoidal phase detector (SPD) for detecting phase difference. The SPD includes a frequency divider (NDIV), a mixer (MIX), and a pre-low-pass filter (LPF). An external reference signal is also included. Connect to one input port of the MIX; VCO signal The output terminal is connected to the input terminal of NDIV, and the signal is divided by NDIV. The output terminal is connected to another input port of the MIX; the output terminal of the MIX mixed signal Km is connected to the input terminal of the LPF; the LPF pre-filtered signal... The output terminal is connected to the input terminal of the loop filter LF; the signal after LF filtering The output terminal is connected to the input terminal of the VCO; the VCO is tuned by a voltage... Oscillating lock signal The output is supplied to the subsequent circuit. The power supplies that need to be superimposed with AC power supply noise group and DC power supply voltage are connected to the power supply ports of MIX and VCO, respectively.
[0022] Specifically, the system employs a passive phase-locked loop (PLL) device, therefore the loop filter is passive and does not require power supply, thus preventing power supply noise from interfering with the loop filter. The loop filter uses an RC-type fourth-order low-pass filter structure. On one hand, it can effectively filter out stray and superimposed far-end power supply noise in the tuning voltage. If the order is lower than fourth order, the filtering effect is poor; if it is higher than fourth order, the filter's own thermal noise increases. On the other hand, the RC-type filter has a simple transfer function, making it easy to design, analyze, and perform tolerance analysis, thereby improving the stability of the PLL device.
[0023] It should be noted that while filters can effectively suppress expected spurious noise, they can only suppress a portion of the power supply noise group because power supply noise has random characteristics and a wide bandwidth distribution. By quantifying the power supply noise group distribution, the system can evaluate the impact of the power supply noise group distribution on phase noise based on the characteristics of the phase-locked loop phase noise in different frequency bands. This not only helps improve the accuracy of phase noise prediction, but also allows for the achievement of the optimal solution through extensive training of the power supply noise group distribution model.
[0024] It should be noted that the process of constructing the linear phase-locked loop model with additional power supply noise in step two includes: Select M linear regulated power supply models from the same series. to The voltage noise spectrum of each model's output port was measured. Based on the power-law distribution characteristics, the noise distribution function of each model was obtained by least squares fitting, and the root mean square value of the power supply noise voltage spectral density was extracted. Based on the power-voltage conversion relationship, the noise voltage spectral density of each model is converted into the root mean square value of the power spectral density, and the phase noise matrix with power supply noise corresponding to each model is obtained through matrix operation based on the principle of linear superposition.
[0025] The calculation formula based on the power-voltage conversion relationship is as follows: In the formula, It is the power noise power spectral density root mean square value. It is the root mean square value of the power supply noise voltage spectral density. It is the voltage output port impedance of the LDO.
[0026] It should be noted that the calculation formula for the phase-locked loop phase noise of the additional power supply noise group in the phase noise matrix with power supply noise corresponding to each model, obtained through matrix operations based on the principle of linear superposition, is as follows: In the formula, The phase noise of the phase-locked loop is added to the power supply noise group. It is the power noise power spectral density root mean square value. It is the phase noise of the phase-locked loop of an ideal power supply.
[0027] It should be noted that step three, which involves fabricating the physical phase-locked loop circuit based on the simulation model, powering it with different types of linear regulated power supplies, and testing and recording the measured phase noise data for each type, includes: A phase-locked loop (PLL) circuit was designed based on a simulation model. Signal radiation was suppressed using metal structural components and soldered RF interfaces. After printed circuit board fabrication and component assembly, the following methods were employed: to Power supply construction test environment; Phase noise tests were conducted on phase-locked loops of the same batch under various power supply models. The measured phase noise data matrix was obtained by discrete sampling using a spectrum analyzer, and outlier detection and removal were performed on the sampled data using the Grubbs criterion to retain valid test samples.
[0028] It should be noted that in step four, the process of comparing the difference between the simulated phase noise and the measured phase noise for each model, fitting the power supply noise group distribution with a power-law function, and iteratively correcting the function coefficients to make the difference less than a preset tolerance threshold, to determine the effective power supply noise evaluation function is as follows: Perform element-wise absolute difference calculation on the data of each model to obtain the phase noise error matrix for evaluation and testing, and set the system's tolerable phase noise difference threshold ε as the judgment criterion; To satisfy For each model, its power supply noise distribution function is expanded into a logarithmic field polynomial, and the least squares method is used to iteratively correct the coefficient matrix until all models satisfy the condition. The final corrected function matrix will be used as the reference model for the next batch of products.
[0029] In step five, steps three and four are repeated for all products of each model, and statistical samples are collected to find those that meet the following criteria. The yield rate is set; if the preset conditions are met in multiple batches, the power supply noise evaluation function is determined to be the optimal solution and the power supply model has excellent consistency; among the models that pass the consistency evaluation, the measured phase noise values are compared and sorted according to phase noise performance to select the best linear regulated power supply model under the phase-locked loop architecture, where the yield rate threshold is set to above 95% and the measured phase noise deviates from the simulated phase noise by no more than 1dB.
[0030] In this embodiment, in step 1, under the locked state, the phase detection characteristic exhibits a highly approximate linear characteristic of a sine curve near zero degrees. Therefore, a simple and practically applicable sinusoidal phase detector model is selected, including a sinusoidal phase detector SPD, a loop filter LF, a voltage-controlled oscillator VCO, and an ideal power supply DC. The sinusoidal phase detector SPD model includes a multiplier MIX, a low-pass filter LPF, and a frequency divider NDIV.
[0031] Choose a phase-locked loop (PLL) simulation software, ADIsimPLL, and use the "PLL Configuration" function to set the main parameters of the PLL as follows: In SPD, set the charge pump current I_CP and bias current I_Offset. The designed physical device should meet the condition I_Offset≥I_CP×20%, otherwise it will increase the instability of the PLL; in VCO, set the tuning sensitivity Kv; in LF, select a fourth-order passive loop filter, set the loop bandwidth LP_BW and phase margin LP_Phase, and then use the "Build" function to adjust the LF parameters to the actual device values.
[0032] The reference clock REF is input to the phase-locked loop (PLL). Under the combined action of various components such as the SPD, LF, VCO, and NDIV, the simulation software calculates the phase noise of the PLL under ideal power supply conditions. .
[0033] Step 2: Select a series of linear regulated power supplies (LDOs) and name them according to their specific models. , ... This adds the AC power supply noise to the DC power supply noise additively.
[0034] exist Within the range where the phase detection characteristics are satisfied near zero, the time-domain expression of the phase-locked loop single-tone signal after approximately linear processing is: In the formula, It is the linearized output error voltage of the phase detector model. It is phase detection enhancement. It is the phase of the input reference signal Phase after frequency division of VCO output signal The difference.
[0035] According to the superposition principle of linear systems, the power supply noise is superimposed onto... Above. After linearization, a phase-locked loop linear phase model with added power supply noise is formed.
[0036] Superimposed power supply noise VCO output signal Feedback to the phase detector and Phase detector, phase detector output signal Superimposed power supply noise Therefore, power supply noise and It will be superimposed and sent to the loop filter LF.
[0037] Power supply noise and It conforms to a power-law distribution, and its root mean square power spectral density can represent the power supply noise group. The expression for the power-voltage conversion relationship is as follows: In the formula, It is the power noise power spectral density root mean square value. It is the root mean square value of the power supply noise voltage spectral density. This is the LDO voltage output port impedance. In the same power supply system, It is a constant. According to the principle of linear superposition, the phase noise of the phase-locked loop (PLL) in addition to the power supply noise group is... Expressed as: Transforming the above equation into a matrix, different models... , ... The phase-locked loop phase noise matrices corresponding to the additional power supply noise group are as follows: Understandably, although the LDOs are different models, they are from the same series, thus achieving in-situ package interchangeability in hardware, greatly reducing verification costs; at the same time, power supply noise becomes the only variable, therefore, the phase noise P of the phase-locked loop under ideal power conditions in the above formula is... PLL It is a constant, which improves the reliability of the test results.
[0038] Step 3: Based on the architecture of Step 1, design the phase-locked loop (PLL) circuit, fabricate its printed circuit board (PCB), and assemble the components onto the PCB. To ensure the stability of the test results and the modularity of the product, a metal structural component can be designed. The PCB is mounted on the structural component with screws, and the power and control interfaces are soldered using high-temperature wire bonding. Furthermore, the inner conductor of the RF interface and the surface microstrip line of the PCB are also interconnected using soldering. This design method effectively suppresses the radiation of the lock-in signal from the structural component, resulting in stable and reliable test data. The actual PLL is tested by adjusting the loop filter to correct parameters such as loop bandwidth and phase margin.
[0039] Step 4, Assume , ... yes , ... These correspond to the power-law functions of the power supply noise group, , ... yes , ... The corresponding phase noises are tested respectively. , ... yes , ... The phase noise difference corresponds to the evaluation and testing, respectively.
[0040] Based on steps 2 and 3, we can conclude that: In the formula, the matrix sum matrix It is relevant. Assume the system can tolerate a phase noise difference of... Then it satisfies corresponding It is a reasonable evaluation function; otherwise, it needs to be based on actual measurements. Correction until The chosen power-law function It can be expanded into a polynomial: In the formula, , , , ... is used for correction functions The coefficient matrix, frequency Take the logarithm This is to correspond to the amplitude-frequency curve of commonly used phase noise. Based on actual... Discarding power supply noise group distribution information Higher-order terms, in the form of quadratic curves Basic assessment formula This can greatly simplify the evaluation method, thereby effectively completing the calculations in the above steps.
[0041] Step 5: Based on Step 4, the actual product is affected by factors such as raw materials, processing precision, and component discreteness. The corrected matrix... There may be batch variations, but the matrix for each batch... These can all be used as a reference for the next batch. (Selection) of A product, assuming it satisfies The probability is If in different batches All showed Reaching the set threshold ,Right now Then it is believed It is the current optimal solution function; if in different batches Not all of them can be satisfied Reaching the set threshold Corrected after appropriate adjustments Can meet Then it is considered that the correction is This is the current optimal solution function; if it is not possible to adjust to satisfy the same function in different batches... of Then the power supply model is considered to be The consistency is poor, and further use is not recommended. In conclusion, The fewer the adjustments, the better. Stablize.
[0042] On the other hand, in areas with relatively stable performance In the middle, a comprehensive comparison of the measured phase noise was made. Since phase noise is a measure of the intensity of random phase fluctuations in a signal in the frequency domain, the smaller the phase fluctuation, the better the signal quality; that is, phase noise... The lower the value, the better the performance of the phase-locked loop (PLL) product. This is based on comprehensive analysis. and Parameters, will , ... By ranking the overall performance, the selected products can be effectively filtered out. The model in the series that is best suited to this phase-locked loop architecture.
[0043] It should be noted that the specific methods by which each module performs operations in the system described in the above embodiments have been described in detail in the embodiments related to the method, and will not be elaborated here.
[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A device for evaluating the impact of power supply noise clusters on phase-locked loop (PLL) phase noise, characterized in that, include: A sinusoidal phase detector detects the phase difference between an external reference signal and a voltage-controlled oscillator feedback signal. The input of the loop filter is connected to the output of the sinusoidal phase detector. A voltage-controlled oscillator (VCO) has its input connected to the output of a loop filter and outputs a feedback signal to a sinusoidal phase detector. The sinusoidal phase detector includes: a frequency divider, which divides the feedback signal from the voltage-controlled oscillator; a mixer, which mixes the divided signal with an external reference signal and outputs the result; a pre-low-pass filter, which filters the output signal of the mixer to obtain an error voltage signal; a DC power supply, which supplies power to the mixer and the voltage-controlled oscillator and extends to the loop filter; and an AC signal source, which simulates power supply noise signals and combines them with the DC power supply in an additive linear superposition manner to supply power to the corresponding modules.
2. The apparatus for evaluating the influence of power supply noise clusters on phase-locked loop phase noise according to claim 1, characterized in that, In the passive loop mode of the phase-locked loop phase noise interference device, the superimposed signal of the DC power supply and the AC signal source is input to the mixer and the voltage-controlled oscillator; in the active loop mode, the superimposed signal is also input to the loop filter.
3. A method for evaluating the impact of power supply noise clusters on phase-locked loop (PLL) phase noise, comprising the apparatus for evaluating the impact of power supply noise clusters on PLL phase noise as described in any one of claims 1-2, characterized in that... include: Step 1: Establish a phase-locked loop simulation model consisting of a sinusoidal phase detector, a loop filter, and a voltage-controlled oscillator. Set parameters such as charge pump current, bias current, tuning sensitivity, loop bandwidth, and phase margin. Simulate and calculate the reference phase noise value under ideal power supply conditions. Step 2: Select a linear regulated power supply series and obtain the power supply noise distribution characteristics of different models in the series; and based on the principle of linear superposition, add the power supply noise to the DC power supply signal in an additive manner to construct a phase-locked loop linear phase model with additional power supply noise, thereby calculating the phase noise matrix with power supply noise corresponding to each model. Step 3: Construct the physical circuit of the phase-locked loop based on the simulation model, and power it with different models of linear regulated power supplies. Test and record the measured phase noise data for each model. Step 4: Compare the difference between the simulated phase noise and the measured phase noise for each model, fit the power supply noise group distribution using a power law function, and iteratively correct the function coefficients to make the difference less than the preset tolerance threshold, thereby determining an effective power supply noise evaluation function. Step 5: Repeat steps 3 and 4 for all models and calculate the yield rate of each model that meets the tolerance threshold. The model with the best yield rate and the best measured phase noise performance is determined as the best linear regulated power supply under this phase-locked loop architecture.
4. The method for evaluating the impact of power supply noise clusters on phase-locked loop phase noise according to claim 3, characterized in that, The construction process in step one is as follows: A sinusoidal phase detector model including a multiplier, a low-pass filter, and a frequency divider is constructed. The charge pump current and bias current are set in the simulation software, and constraints are applied to maintain loop stability. At the same time, the tuning sensitivity, loop bandwidth, and phase margin parameters are set, and the actual device values are generated using the parameter construction function of the simulation software. The reference clock signal is input to the aforementioned sinusoidal phase detector model. After closed-loop processing by a loop filter and a voltage-controlled oscillator, the frequency domain integration operation is performed by the phase noise calculation engine of the simulation software to obtain the reference phase noise value under ideal power supply conditions.
5. The method for evaluating the impact of power supply noise clusters on phase-locked loop phase noise according to claim 3, characterized in that, The process of constructing the phase-locked loop linear phase model with additional power supply noise in step two includes: Select M linear regulated power supply models from the same series. to The voltage noise spectrum of each model's output port was measured. Based on the power-law distribution characteristics, the noise distribution function of each model was obtained by least squares fitting, and the root mean square value of the power supply noise voltage spectral density was extracted. Based on the power-voltage conversion relationship, the noise voltage spectral density of each model is converted into the root mean square value of the power spectral density, and the phase noise matrix with power supply noise corresponding to each model is obtained through matrix operation based on the principle of linear superposition.
6. The method for evaluating the impact of power supply noise clusters on phase-locked loop phase noise according to claim 5, characterized in that, The calculation formula based on the power-voltage conversion relationship is as follows: In the formula, It is the power noise power spectral density root mean square value. It is the root mean square value of the power supply noise voltage spectral density. It is the voltage output port impedance of the LDO.
7. The method for evaluating the influence of power supply noise clusters on phase-locked loop phase noise according to claim 1, characterized in that, The formula for calculating the phase-locked loop phase noise of the additional power supply noise group in the phase noise matrix with power supply noise corresponding to each model, obtained through matrix operations based on the principle of linear superposition, is as follows: In the formula, The phase noise of the phase-locked loop is added to the power supply noise group. It is the power noise power spectral density root mean square value. It is the phase noise of the phase-locked loop of an ideal power supply.
8. The method for evaluating the impact of power supply noise clusters on phase-locked loop phase noise according to claim 1, characterized in that, Step three, which involves fabricating the physical phase-locked loop circuit based on the simulation model, powering it with different types of linear regulated power supplies, and testing and recording the measured phase noise data for each type, includes: A phase-locked loop (PLL) circuit was designed based on a simulation model. Signal radiation was suppressed using metal structural components and soldered RF interfaces. After printed circuit board fabrication and component assembly, the following methods were employed: to Power supply construction test environment; Phase noise tests were conducted on phase-locked loops of the same batch under various power supply models. The measured phase noise data matrix was obtained by discrete sampling using a spectrum analyzer, and outlier detection and removal were performed on the sampled data using the Grubbs criterion to retain valid test samples.
9. The method for evaluating the influence of power supply noise clusters on phase-locked loop phase noise according to claim 1, characterized in that, In step four, the difference between the simulated phase noise and the measured phase noise for each model is compared. A power-law function is used to fit the power supply noise group distribution. The function coefficients are iteratively corrected to make the difference less than a preset tolerance threshold. The process of determining an effective power supply noise evaluation function is as follows: Perform element-wise absolute difference calculation on the data of each model to obtain the phase noise error matrix for evaluation and testing, and set the system's tolerable phase noise difference threshold ε as the judgment criterion; To satisfy For each model, its power supply noise distribution function is expanded into a logarithmic field polynomial, and the least squares method is used to iteratively correct the coefficient matrix until all models satisfy the condition. The final corrected function matrix will be used as the reference model for the next batch of products.
10. The method for evaluating the influence of power supply noise clusters on phase-locked loop phase noise according to claim 1, characterized in that, In step five, steps three and four are repeated for all products of the same model, and for each model, a statistical sample is collected that meets the following criteria. The yield rate is set; if the preset conditions are met in multiple batches, the power supply noise evaluation function is determined to be the optimal solution and the power supply model has excellent consistency; among the models that pass the consistency evaluation, the measured phase noise values are compared and sorted according to phase noise performance to select the best linear regulated power supply model under the phase-locked loop architecture, where the yield rate threshold is set to above 95% and the measured phase noise deviates from the simulated phase noise by no more than 1dB.