FPGA-based gray histogram statistics method for avoiding layout delay
By using sequential logic instead of combinational logic in the grayscale histogram statistics of FPGA and using the cal_pix0 and cal_pix1 signals to assist in counting, the timing problem of excessive logic delay at high clock rates is solved, and the stability of layout and routing and the balance of timing are achieved.
Patent Information
- Application Number
- CN202311073249.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-24
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2043-08-24
AI Technical Summary
The existing FPGA-based grayscale histogram statistical method is prone to timing problems caused by excessive logic delay at high operating clock rates, which is especially difficult to avoid when the path is too long during the layout and routing process.
Sequential logic is used instead of combinational logic. Sequential logic is used when adding one to data and writing data. After reading the grayscale pixel count value at port B, one beat is stored. The cal_pix0 and cal_pix1 signals are used to assist in counting. This shortens the logic path and avoids logic delays caused by excessively long paths in layout and routing.
It effectively avoids timing problems caused by excessive logic delay at high clock rates, balances timing, ensures the stability of FPGA layout and routing, and avoids timing problems caused by excessive logic delay.
Smart Images
Figure CN116957995B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of image processing, in particular to a gray histogram statistics method based on FPGA to avoid layout delay. BACKGROUND
[0002] The gray histogram statistics is to count the pixels of each gray in an image and get a gray distribution table from the mathematical point of view. At present, most of the methods based on FPGA are to use double-port block RAM. Referring to Figure 1 , the core idea is to read out the gray pixel count value at port B, Figure 1 , clk is a clock signal, din_vld is an input data valid signal, din is an input data signal, addrb is a block ram port B address signal, doutb is a block ram port B output data signal, wea is a block ram port A write enable signal, addra is a block ram port A address signal, dina is a block ram port A input data signal. The count value is written back after being added one at port A. However, in order to ensure that the read-out gray pixel count value corresponds to the current address each time, the addition and writing of data use combinational logic. When the working clock rate is high, the logic delay may be too large to cause timing problems. SUMMARY
[0003] In view of the deficiencies of the prior art, the present application provides a gray histogram statistics method based on FPGA to avoid layout delay, which mainly uses timing logic instead of combinational logic for the addition and writing of data to avoid the logic delay caused by too long routing path during the layout and routing of FPGA.
[0004] A gray histogram statistics method based on FPGA to avoid layout delay, comprising the following steps:
[0005] Step 1: using double-port block RAM, selecting a simple double-port RAM mode, writing the count value of the current gray pixel at port A, and reading out the count value of the previous gray pixel at port B;
[0006] Step 2: the value of addrb at port B represents the current gray pixel value, and the value of doutb read out according to addrb is the count value of the previous gray value, which is registered for one clock cycle to get doutb_1d, shortening the current logic path;
[0007] Step 3, in the statistical process, if multiple continuous pixel points have the same gray value, cal_pix0 and cal_pix1 are used to assist in representing the count value. When two continuous points or two points with an interval of 1 have the same gray value, the value of cal_pix0 is 1. When three continuous points have the same gray value, the value of cal_pix0 is 2. When two points with an interval of 2 have the same gray value, the value of cal_pix1 is 2.
[0008] Step 4, doutb_1d represents the count value accumulated before the current gray value, cal_pix0 represents the additional count value in the case that two or three continuous points have the same gray value or two points with an interval of 1 have the same gray value, and cal_pix1 represents the additional count value in the case that two points with an interval of 2 have the same gray value. The sum of the three signals is the count value of the current gray value at this moment, and the sum is taken as the value of dina and written into the block RAM.
[0009] The present application has the following advantages: (1) the method uses timing logic, and a beat of the data output by BRAM (block RAM) is registered, so that a certain excessively long path in the layout and routing process is avoided, the timing is balanced, and the timing problem in the layout and routing process is avoided as much as possible. (2) The timing problem caused by excessively large logic delay when the working clock rate is high is avoided. (3) The add-one operation and the writing operation of data do not use combinational logic, but use timing logic to avoid the problem of excessively large logic delay caused by excessively long path in the layout and routing of FPGA. BRIEF DESCRIPTION OF DRAWINGS
[0010] Figure 1 The figure is a timing diagram of the conventional gray histogram statistics in the background art.
[0011] Figure 2 The figure is a timing diagram of the gray histogram statistics method in the embodiment of the present application. DETAILED DESCRIPTION
[0012] The technical solutions of the present application will be further described in detail below with reference to the accompanying drawings.
[0013] In order to achieve the above-mentioned purpose, the technical solutions of the present application are as follows:
[0014] Still read out the gray scale pixel count value at port B, the key point is to register the gray scale pixel count value d out b read out by port B for one beat, so as to shorten the logic path and facilitate layout and wiring. When the gray scale values of adjacent several pixel points are the same, cal_pix0 and cal_pix1 are used to represent the count values in different cases, when the gray scale values of two adjacent pixel points are the same or the interval is 1, cal_pix0 is 1; when the gray scale values of three adjacent pixel points are the same, cal_pix0 is 2; when the gray scale values of two pixel points with an interval of 2 are the same, cal_pix1 is 2. In this way, the result of adding d out b_1d+cal_pix0+cal_pix1 at port A is assigned to dina, and dina is the count value of the gray scale value of the current pixel point.
[0015] Figure 2 For an embodiment of the method, clk is a clock signal, din_vld is an input data valid signal, din is an input data signal, addrb is a block ram port B address signal, d out b is a block ram port B output data signal, doubt_1d is a signal of d out b registered for one beat, cal_pix0 is a continuous pixel statistical count signal, cal_pix1 is an interval pixel statistical count signal, wea is a block ram port A write enable signal, addra is a block ram port A address signal, and dina is a block ram port A input data signal.
[0016] Figure 1 And D0, D1 and D2 in Figure 2 represent the input data, such as data0, data1, data2, etc.
[0017] The numbers in d out b represent the data stored in the address represented by addrb, such as Figure 1 When the first D0 in addrb appears in d out b, it means that the data stored in the current D0 address is 0, and the others are the same.
[0018] The numbers in dina represent the data written into the address represented by addra, such as Figure 1 When the first D0 in addra appears in dina, it means that data 1 is written into the current D0 address, and the others are the same.
[0019] d out b_1d is a signal of d out b registered for one beat, that is, delayed by one clock.
[0020] The above merely describes the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above embodiments, but any equivalent modifications or changes made by those skilled in the art according to the disclosed content of the present application shall be included in the protection scope recorded in the claims.
Claims
1. A grayscale histogram statistics method based on FPGA to avoid layout delay, characterized by: The method comprises the following steps: Step 1: Use a dual-port block RAM to write the current grayscale pixel's count value at port A and read the previous count value of the current grayscale pixel at port B. Step 2: The value of addrb of port B represents the current grayscale pixel value. The value of doutb read from addrb is the cumulative count value before the current grayscale value. Doutb is stored for one beat to obtain doutb_1d, shortening the current logic path. Step 3: During the statistical process, if the grayscale values of multiple consecutive pixels are the same, cal_pix0 and cal_pix1 are used to assist in representing the count value. cal_pix0 represents the additional count value when two or three consecutive pixels have the same grayscale value or when the grayscale value of two pixels with an interval of 1 is the same. cal_pix1 represents the additional count value when the grayscale value of two pixels with an interval of 2 is the same. Step 4: The count value of the current grayscale value at this moment is obtained by adding the three signals doutb_1d, cal_pix0 and cal_pix1, and the sum is used as the value of dina and written into the block RAM.
2. The grayscale histogram statistics method for avoiding layout delay based on FPGA according to claim 1, characterized in that: In step 1, the number in the data signal dina written by block RAM port A represents the data written to the address represented by the current addra.
3. The grayscale histogram statistics method for avoiding layout delay based on FPGA according to claim 1, characterized in that: In step 2, the grayscale pixel count value doutb represents the data stored in the address represented by the block RAM port B address signal addrb.
4. The grayscale histogram statistics method for avoiding layout delay based on FPGA according to claim 1, characterized in that: In step 2, doutb_1d is the signal after doutb registers one beat, that is, delayed by one clock.
5. The grayscale histogram statistics method for avoiding layout delay based on FPGA according to claim 1, characterized in that: In step 3, when the grayscale values of two consecutive points or two points with an interval of 1 are the same, the value of cal_pix0 is 1; when the grayscale values of three consecutive points are the same, the value of cal_pix0 is 2; when the grayscale values of two points with an interval of 2 are the same, the value of cal_pix1 is 2.
Citation Information
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