output buffer

Abstract

An output buffer for a source driver of a panel includes an output stage for outputting an output voltage, an operational transconductance amplifier for controlling the output stage to charge or discharge a panel pixel capacitance, and a detector coupled between the operational transconductance amplifier and the output stage for outputting an enable signal to turn on or turn off the output buffer after the output buffer finishes charging or discharging the panel pixel capacitance, wherein the enable signal is determined according to an output current of the output stage. The output buffer can be turned off after the panel pixel capacitance finishes charging or discharging, thereby reducing the power consumption of the display driver.

Description

Technical Field

[0001] This invention relates to an output buffer, and more particularly to an output buffer that can reduce the power consumption of a display driver. Background Technology

[0002] Current mainstream display devices, such as liquid-crystal displays (LCDs) and organic light-emitting diodes (OLEDs), are capacitive load display devices. The equivalent circuit commonly used in the industry is a multi-stage resistor-capacitor circuit. Depending on the manufacturing process or panel size, the total resistance is approximately 2KΩ to 10KΩ, and the total capacitance is approximately 10pF to 120pF.

[0003] Existing display devices use digital-to-analog converters (DACs) to convert digital grayscale information into analog pixel voltages, and use an output buffer to charge or discharge the pixels of the panel, thereby increasing the driving capability. Please refer to [reference needed]. Figure 1 , Figure 1 This is a schematic diagram of an existing output buffer OB, which includes an operational transconductance amplifier (OTA) and an output stage OS. Figure 2 for Figure 1 A schematic diagram of a voltage waveform and a current waveform of the output buffer OB. (See diagram below.) Figure 2 As shown, the output buffer OB still consumes a fixed quiescent current (e.g., 2μA to 10μA) after charging or discharging the pixel capacitor, thus generating additional power consumption. Therefore, there is a real need to improve the existing technology. Summary of the Invention

[0004] The main objective of this invention is to overcome the shortcomings of the prior art and provide an output buffer to reduce the power consumption of the display driver.

[0005] To achieve the above objectives, the present invention proposes the following technical solution:

[0006] An output buffer for a source driver of a panel includes an output stage for outputting an output voltage; an operational transconductance amplifier for controlling the output stage to charge or discharge panel pixel capacitors; and a detector coupled between the operational transconductance amplifier and the output stage for outputting an enable signal to turn the output buffer on or off after the output buffer has completed charging or discharging the panel pixel capacitors, wherein the enable signal is determined based on an output current of the output stage.

[0007] The beneficial effect of the technical solution of the present invention is that the output buffer of the present invention can be turned off after the panel pixel capacitor has completed charging or discharging, thereby reducing the power consumption of the display driver. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of an existing output buffer.

[0009] Figure 2 for Figure 1 The diagram shows a voltage waveform and a current waveform of an existing output buffer.

[0010] Figure 3 This is a schematic diagram of an output buffer according to an embodiment of the present invention.

[0011] Figure 4 for Figure 3 The diagram shows a voltage waveform and a current waveform of the output buffer.

[0012] Figure 5 This is a schematic diagram of an output buffer according to an embodiment of the present invention.

[0013] Figure 6 for Figure 5 The output buffer is shown in the schematic diagram of the signal waveform.

[0014] Figure 7 This is a schematic diagram of an output buffer according to an embodiment of the present invention.

[0015] Figure 8 This is a schematic diagram of an output buffer according to an embodiment of the present invention.

[0016] Explanation of reference numerals in the attached figures:

[0017] 302: Output Buffer

[0018] 302_DET: Detector

[0019] 302_DET_1: Charging Detector

[0020] 302_DET_2: Discharge Detector

[0021] 302_OS: Output stage

[0022] 302_OTA: Operational transconductance amplifier

[0023] 502: Output Buffer

[0024] 502_DET: Detector

[0025] 502_DET_1: Charging Detector

[0026] 502_DET_2: Discharge Detector

[0027] 502_OS: Output stage

[0028] 502_OTA: Operational transconductance amplifier

[0029] 702: Output Buffer

[0030] 702_DET: Detector

[0031] 702_DET_1: Charging Detector

[0032] 702_DET_2: Discharge Detector

[0033] 702_OS: Output Stage

[0034] 702_OTA: Operational transconductance amplifier

[0035] 802: Output Buffer

[0036] 802_DET: Detector

[0037] 802_DET_1: Charging Detector

[0038] 802_DET_2: Discharge Detector

[0039] 802_OS: Output Stage

[0040] 802_OTA: Operational Transconductance Amplifier

[0041] AVDD: System High Voltage

[0042] AVSS: System Low Voltage

[0043] BIAS: Bias circuit

[0044] Cp: ​​Capacitor

[0045] CS_AMP_1: First common-source amplifier

[0046] CS_AMP_2: Second common-source amplifier

[0047] DAC: Digital-to-Analog Converter

[0048] EN: Enable signal

[0049] Iref_1: Reference current

[0050] Iref_2: Reference current

[0051] M1: First current source

[0052] M2: Second current draw

[0053] M3: First Current Draw

[0054] M4: Second current source

[0055] M5: First output transistor

[0056] M6: Second output transistor

[0057] M7: First Reference Transistor

[0058] M8: Second reference transistor

[0059] M9: Transistor

[0060] M10: Transistor

[0061] M11: Transistor

[0062] M12: Transistor

[0063] NAND: NAND gate

[0064] NOT: NOT gate

[0065] NOT1: First NOT gate

[0066] NOT2: Second NOT gate

[0067] NOT3: Third NOT gate

[0068] NOR: NOR gate

[0069] OB: Output buffer

[0070] OS: Output Stage

[0071] OTA: Operational Transduction Amplifier

[0072] Rp: Resistance

[0073] SPB: Enable Pulse Signal

[0074] TCON: Timing Controller

[0075] T0, T1, T2, T3, T4, T5: Time

[0076] V1: First pressure divider

[0077] V1': Non-first voltage divider

[0078] V2: Second dividing pressure

[0079] VBN: First bias voltage

[0080] VBP: Second bias voltage

[0081] VCOM: Reference voltage

[0082] Vin: Input voltage

[0083] Vout: Output voltage Detailed Implementation

[0084] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Please refer to... Figure 3 , Figure 3 This is a schematic diagram of an output buffer 302 according to an embodiment of the present invention. The output buffer 302 can be used as a source driver for a panel, such as a liquid crystal display (LCD) or an organic light-emitting diode (OLED). The output buffer 302 includes an output stage 302_OS, an operational transconductance amplifier (OTA) 302_OTA, and a detector 302_DET. The output stage 302_OS outputs an output voltage Vout to the pixels of the panel. The operational transconductance amplifier 302_OTA controls the output stage 302_OS to charge or discharge the capacitance of the pixels of the panel. The detector 302_DET is coupled between the operational transconductance amplifier 302_OTA and the output stage 302_OS. After the output buffer 302 completes the charging or discharging of the capacitors of the pixels on the panel, it outputs an enable signal EN to turn the output buffer 302 on or off. The enable signal EN is determined by an output current of the output stage 302_OS.

[0085] Detector 302_DET includes a charge detector 302_DET_1, a discharge detector 302_DET_2, and a NAND gate. Charge detector 302_DET_1 determines a non-first voltage divider V1' based on a charging current from output stage 302_OS and a first bias voltage VBN. Discharge detector 302_DET_2 determines a second voltage divider V2 based on a discharge current from output stage 302_OS and a second bias voltage VBP from the bias circuit. The NAND gate determines the enable signal EN based on the non-first voltage divider V1', the second voltage divider V2, and an enable pulse signal SPB.

[0086] The charging detector 302_DET_1 includes a first current source M1, a first current sink M3, and a NOT gate. The NOT gate is coupled to the first current source M1 and the first current sink M3, and determines a non-first voltage divider V1' based on a first voltage divider V1 of the first current source M1 and the first current sink M3. In one embodiment, the first current source M1 may be a P-type metal-oxide-semiconductor (PMOS), and the first current sink M3 may be an N-type metal-oxide-semiconductor (NMOS). The discharging detector 302_DET_2 includes a second current sink M2 and a second current source M4, and determines a second voltage divider V2 based on the second current sink M2 and the second current source M4. In one embodiment, the second current sink M2 may be an NMOS, and the second current source M4 may be a PMOS.

[0087] Detector 302_DET is used to detect an output current of output buffer 302. First current source M1 and second current sink M2 mirror the currents of a first output transistor M5 and a second output transistor M6 of output stage 302_OS, respectively. In one embodiment, the first output transistor M5 can be a PMOS, and the second output transistor M6 can be an NMOS. First current sink M3 and second current source M4 generate reference currents based on a first bias voltage VBN and a second bias voltage VBP, respectively. Detector 302_DET outputs an enable signal EN based on the enable pulse signal SPB, the first voltage divider V1, and the second voltage divider V2. Furthermore, the enable signal EN is used to control the opening or closing of output buffer 302.

[0088] Figure 4 for Figure 3 The diagram shows a voltage waveform and a current waveform of the output buffer 302. It is worth noting that... Figure 4 The current waveform in the waveform is an absolute value.

[0089] like Figure 4 As shown, the output voltage Vout of the output buffer 302 changes with the current waveform, where the current waveform is related to the change in the output voltage Vout. In this embodiment of the invention, after the output buffer 302 completes charging or discharging of the panel pixel capacitor, the detector 302_DET will turn off the output buffer 302 to reduce power consumption. In other words, the output buffer 302 will be turned off after completing charging or discharging of the panel pixel capacitor, and its quiescent current will be close to zero.

[0090] refer to Figure 5 , Figure 5This is a schematic diagram of the output buffer 502 according to an embodiment of the present invention. The output buffer 502 is a variation of the output buffer 302. The output buffer 502 includes an output stage 502_OS, an operational transconductance amplifier 502_OTA, and a detector 502_DET. The output stage 502_OS is used to output an output voltage Vout. The operational transconductance amplifier 502_OTA controls the output stage 502_OS to charge or discharge the capacitance Cp of a pixel on a panel according to an input voltage Vin of a digital-to-analog converter (DAC). The detector 502_DET is used to output an enable signal EN to turn the output buffer 502 on or off after the output buffer 502 has completed charging or discharging the pixel capacitance of the panel. The enable signal EN is determined by an output current of the output stage 502_OS.

[0091] Detector 502_DET includes a charge detector 502_DET_1, a discharge detector 502_DET_2, and a NAND gate. Charge detector 502_DET_1 determines a non-first voltage divider V1' based on a charging current of output stage 502_OS and a first bias voltage VBN, wherein the first bias voltage VBN is generated by a first reference transistor M7 of a bias circuit BIAS. In one embodiment, the first reference transistor M7 may be an NMOS. Discharge detector 502_DET_2 determines a second voltage divider V2 based on a discharge current of output stage 502_OS and a second bias voltage VBP, wherein the second bias voltage VBP is generated by a second reference transistor M8 of the bias circuit BIAS. In one embodiment, the second reference transistor M8 may be a PMOS. The NAND gate determines the enable signal EN based on the first voltage divider V1', the second voltage divider V2, and the enable pulse signal SPB, where the enable pulse signal SPB is generated by a timing controller TCON.

[0092] The charging detector 502_DET_1 includes a first current source M1, a first current sink M3, and a NOT gate. The NOT gate is coupled to the first current source M1 and the first current sink M3, and determines the non-first voltage sink V1' based on a first voltage divider V1 of the first current source M1 and the first current sink M3.

[0093] Since the first current source M1 and the first output transistor M5 have the same VGS (gate-to-source voltage), a current mirror is formed. The width-to-length ratio of the first current source M1 to the first output transistor M5 is (W1 / L1):(W5 / L5) = 1:M, where M is a positive number. Similarly, the first current source M3 and the first reference transistor M7 have the same VGS voltage, thus forming a current mirror. The width-to-length ratio of the first current source M3 to the first reference transistor M7 is (W3 / L3):(W7 / L7) = 1:N, where N is a positive number.

[0094] Therefore, the first current source M1 and the first current extractor M3 respectively mirror the charging current of the first output transistor M5 and the reference current Iref_1 of the first reference transistor M7.

[0095] The discharge detector 502_DET_2 includes a second current drawer M2 and a second current source M4, and determines the second voltage divider V2 based on the second current drawer M2 and the second current source M4.

[0096] Since the VGS voltages of the second current source M2 and the second output transistor M6 are the same, a current mirror is formed. The width-to-length ratio of the second current source M2 to the second output transistor M6 is (W2 / L2):(W6 / L6) = 1:M, where M is a positive number. Similarly, the VGS voltages of the second current source M4 and the second reference transistor M8 are the same, thus forming a current mirror. The width-to-length ratio of the second current source M4 to the second reference transistor M8 is (W4 / L4):(W8 / L8) = 1:N, where N is a positive number.

[0097] Therefore, the second current source M2 and the second current source M4 respectively mirror the discharge current of the second output transistor M6 and a reference current Iref_2 of the second reference transistor M8.

[0098] Figure 6 for Figure 5 The diagram shows the signal waveform of the output buffer 502. It is worth noting that... Figure 6 The current waveform in the waveform is an absolute value.

[0099] like Figure 6 As shown, the output voltage Vout of the output buffer 502 changes with the current waveform, where the current waveform is related to the change in the output voltage Vout.

[0100] Assuming M = N = 1, at time T0, the enable pulse signal SPB is at a low level and the enable signal EN is at a high level, and the output buffer 502 is turned on. Since the input voltage Vin is higher than the output voltage Vout, the output buffer 502 charges the panel pixel capacitor Cp. In other words, the first output transistor M5 outputs charging current, while the second output transistor M6 does not operate. In this case, both the first voltage divider V1 and the second voltage divider V2 are at a high voltage level.

[0101] At time T1, the enable pulse signal SPB is at a high potential, the second voltage divider V2 is at a high voltage level, and the enable signal EN is determined by the voltage level of the first voltage divider V1.

[0102] At time T2, the charging current of the first current source M1 is less than the reference current Iref_1 mirrored by the first current draw M3, the first voltage divider V1 drops, the enable signal EN is at a low voltage level, and the output buffer 502 is turned off.

[0103] At time T3, the enable pulse signal SPB is at a low voltage level, and the enable signal EN is at a high voltage level. Output buffer 502 is activated again to charge the next pixel on the panel. Since the input voltage Vin is less than the output voltage Vout, output buffer 502 discharges the panel pixel capacitor Cp. In other words, the first output transistor M5 does not operate, while the second output transistor M6 outputs a discharge current. In this situation, both the first voltage divider V1 and the second voltage divider V2 are at low voltage levels.

[0104] At time T4, the enable pulse signal SPB is at a high voltage level, the first voltage divider V1 is at a low voltage level, and the enable signal EN is determined by the voltage level of the second voltage divider V2.

[0105] At time T5, the discharge current drawn by the second current source M2 is less than the reference current Iref_2 mirrored by the second current source M4, the second voltage divider V2 rises, the enable signal is at a low voltage level, and the output buffer 502 is turned off.

[0106] Therefore, after the output buffer 502 completes the charging and discharging of the panel pixel capacitors, the output buffer 502 of this embodiment of the invention is turned off by the detector 502_DET to reduce the power consumption of the output buffer 502.

[0107] refer to Figure 7 , Figure 7This is a schematic diagram of an output buffer 702 according to an embodiment of the present invention. Output buffer 702 is a variation of output buffer 502. Output buffer 702 includes an output stage 702_OS, an operational transconductance amplifier 702_OTA, and a detector 702_DET, wherein detector 702_DET includes a charge detector 702_DET_1, a discharge detector 702_DET_2, and a NAND gate. Charge detector 702_DET_1 includes a first current source M1, a first current sink M3, and a first NOT gate NOT1. Discharge detector 702_DET_2 includes a second current sink M2, a second current source M4, a second NOT gate NOT2, and a third NOT gate NOT3. The second NOT gate NOT2 is coupled to the second current source M4 and the second current sink M2, and the third NOT gate NOT3 is coupled to the second NOT gate NOT2. In this embodiment, the second voltage divider V2 is determined based on the second current source M4 and the second current draw M2.

[0108] In this example, the second NOT gate NOT2 and the third NOT gate NOT3 are used to increase the voltage gain of the second voltage divider V2 and reduce the transition time of the output buffer 702.

[0109] It is worth noting that for detailed operation methods of output buffer 702, please refer to the relevant operation of output buffer 502; for the sake of simplicity, it will not be repeated here.

[0110] refer to Figure 8 , Figure 8This is a schematic diagram of an output buffer 802 according to an embodiment of the present invention. Output buffer 802 is a variation of output buffer 502. Output buffer 802 includes an output stage 802_OS, an operational transconductance amplifier 802_OTA, and a detector 802_DET, wherein detector 802_DET includes a charge detector 802_DET_1, a discharge detector 802_DET_2, and a NAND gate. Charge detector 802_DET_1 includes a first current source M1, a first current sink M3, and a first common-source amplifier CS_AMP_1, wherein the first common-source amplifier CS_AMP_1 includes transistors M9 and M11, and the first common-source amplifier CS_AMP_1 is coupled to the first current source M1 and the first current sink M3. In one embodiment, transistor M9 may be a PMOS, and transistor M11 may be an NMOS. The discharge detector 802_DET_2 includes a second current draw M2, a second current source M4, a NOR gate, and a second common-source amplifier CS_AMP_2. The second common-source amplifier CS_AMP_2 includes transistors M10 and M12 and is coupled to the second current source M4 and the second current draw M2. The NOR gate is coupled between the second common-source amplifier CS_AMP_2 and the NAND gate. In one embodiment, transistor M10 may be an NMOS, and transistor M12 may be a PMOS.

[0111] In this embodiment, the first common-source amplifier CS_AMP_1 and the second common-source amplifier CS_AMP_2 are used to increase the voltage gain. Furthermore, since the enable pulse signal SPB is output to a NOR gate via a NOT gate, the transition current of the output buffer 802 can be reduced.

[0112] It is worth noting that for detailed operation methods of output buffer 802, please refer to the relevant operation of output buffer 502; for the sake of simplicity, it will not be repeated here.

[0113] In summary, the present invention provides an output buffer that is turned off after the panel pixel capacitors have completed charging and discharging, which can reduce the power consumption of the display driver.

[0114] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, several equivalent substitutions or obvious modifications can be made without departing from the concept of the present invention, and all such modifications, achieving the same performance or purpose, should be considered within the scope of protection of the present invention.

Claims

1. An output buffer for a source driver on a panel, characterized in that, include: One output stage is used to output an output voltage; An operational transconductance amplifier is used to control the output stage to charge or discharge the panel pixel capacitors; as well as A detector, coupled between the operational transconductance amplifier and the output stage, is used to output an enable signal to turn the output buffer on or off after the output buffer has completed charging or discharging the panel pixel capacitor, wherein the enable signal is determined based on an output current of the output stage. The detector includes: A charging detector is configured to determine a non-first voltage divider based on a charging current of the output stage and a first bias voltage of a bias circuit; and A discharge detector is used to determine a second voltage divider based on a discharge current of the output stage and a second bias voltage of the bias circuit.

2. The output buffer as described in claim 1, characterized in that, Also includes: A bias circuit is used to provide a first bias voltage and a second bias voltage to the detector; as well as A timing controller is used to provide a consistent energy pulse signal to the detector.

3. The output buffer as described in claim 2, characterized in that, The detector further includes: A NAND gate is used to determine the enable signal based on the first voltage divider, the second voltage divider, and the enable pulse signal.

4. The output buffer as described in claim 3, characterized in that, The charging detector includes: A first current source; A first current draw; and A NOT gate, coupled to the first current source and the first current draw, is used to determine the non-first voltage divider based on the first current source and the first current draw.

5. The output buffer as described in claim 4, characterized in that, The output buffer is turned off when a charging current from the first current source of the charging detector is less than a mirror current drawn by the first current.

6. The output buffer as described in claim 4, characterized in that, The first current source and a first output transistor of the output stage form a current mirror, and the first current draw and a first reference transistor of the bias circuit form another current mirror.

7. The output buffer as described in claim 3, characterized in that, The discharge detector includes: A second current draw; and A second current source; The second voltage divider is determined based on the second current source and the second current draw.

8. The output buffer as described in claim 7, characterized in that, The output buffer is turned off when the discharge current drawn by the second current of the discharge detector is less than the mirror current of the second current source.

9. The output buffer as described in claim 7, characterized in that, The second current source and a second reference transistor of the bias circuit form a current mirror, and the second current draw and a second output transistor of the output stage form another current mirror.

10. The output buffer as claimed in claim 1, characterized in that, The operational transconductance amplifier is used to compare an input voltage and an output voltage of the output buffer, and to charge or discharge the panel pixel capacitor when the output buffer is turned on.

11. The output buffer as claimed in claim 10, characterized in that, When the input voltage is higher than the output voltage, the output buffer charges the panel pixel capacitor, and a first output transistor of the output stage is used to output a charging current.

12. The output buffer as claimed in claim 10, characterized in that, When the input voltage is lower than the output voltage, the output buffer discharges the panel pixel capacitor, and a second output transistor of the output stage is used to output a discharge current.

13. The output buffer as described in claim 3, characterized in that, The discharge detector includes: A second current is drawn in; A second current source; A second NOT gate, coupled to the second current source and the second current draw; and A third NOT gate is coupled to the second NOT gate; The second voltage divider is determined based on the second current source and the second current draw.

14. The output buffer as described in claim 3, characterized in that, The charging detector includes: A first current source; A first current draw; and A first common-source amplifier, coupled to the first current source and the first current draw, is used to increase a voltage gain.

15. The output buffer as described in claim 3, characterized in that, The discharge detector includes: A second current is drawn in; A second current source; A second common-source amplifier, coupled to the second current source and the second current draw, is used to increase a voltage gain; and A NOR gate, coupled between the second common-source amplifier and the NAND gate, is used to reduce a transition current.

16. The output buffer as claimed in claim 1, characterized in that, After the output buffer has completed charging or discharging the panel pixel capacitor, and when the output buffer is turned off, the static current of the output buffer is close to zero.

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