A fast response low dropout (LDO) circuit

Abstract

The application discloses a kind of fast response low dropout LDO circuits, including bias generation circuit, capacitive coupling circuit, push-pull output circuit.Bias generation circuit receives reference voltage Vref, output control voltage Vctrl, bias voltage VBIAS1, And bias voltage VBIAS2 to push-pull output circuit, push-pull output circuit output voltage Vout to capacitive coupling circuit, after receiving voltage Vout, the voltage is coupled and then output to push-pull output circuit.Capacity coupling circuit.The structure makes full use of the characteristics of the common reduction of the gate voltage of push-pull output structure, greatly improves the ability of pull current.Through increasing NMOS feedback loop and PMOS feedback loop, when load current suddenly increases or decreases, it can respond quickly, and the power supply noise rejection ratio at low frequency is improved.In addition, the capacitive coupling path is adopted, which makes up for the problem that the response speed of PMOS feedback loop is slower than that of NMOS feedback loop, and improves the transient response speed when load current suddenly increases.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuits, and specifically relates to a fast-response low-dropout LDO circuit. Background Technology

[0002] Low-dropout linear regulators (LDOs) play a crucial role in integrated circuits and are key circuits in wired and wireless communication systems. Currently, many LDO circuits primarily employ traditional single-transistor or FVF (Flip-Voltage-Fluid) structures. Traditional single-transistor LDOs typically consist of a negative feedback loop composed of an error amplifier and a regulating transistor, and their response speed to loads is mainly limited by bandwidth and slew rate. Compared to traditional LDOs, FVF LDOs are simpler in structure and consume less quiescent current, while possessing their own feedback loop and a larger slew rate, thus achieving a fast response. However, the folded circuit topology reduces the loop gain of the FVF LDO, leading to a decrease in power supply noise rejection ratio (PSRR), a phenomenon particularly pronounced in nanometer-scale processes. Achieving a high PSRR generally involves adding a gain stage, but this also slows down the response speed. Therefore, designing LDO circuits that rationally balance high response speed with a high PSRR is crucial.

[0003] The literature “M. El-Nozahi, A. Amer, J. Torres, K. Entesari and E. Sanchez-Sinencio, “High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique,” ​​in IEEE Journal of Solid-State Circuits, vol.45, no.3, pp.565-577, March 2010, doi:10.1109 / JSSC.2009.2039685.” describes an LDO circuit structure. This structure employs a traditional single-regulator transistor design. The circuit utilizes a feedforward ripple cancellation (FFRC) method to improve the power supply noise rejection ratio, but this approach cannot improve transient response speed.

[0004] The paper “Y.Lu, W.-H.Ki and CPYue,” 17.11A 0.65ns-response-time 3.01ps FOMfully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014, pp.306-307, doi:10.1109 / ISSCC.2014.6757446,” describes an LDO circuit structure. This structure employs a flip-flop voltage follower and uses a buffer impedance attenuation structure to improve loop bandwidth, thereby improving transient response speed. However, this approach cannot improve loop gain, thus failing to achieve a good power supply noise rejection ratio, and its current-pull capability is limited. Summary of the Invention

[0005] To address the above technical problems, this invention proposes a fast-response low-dropout LDO circuit that fully utilizes the characteristic of a common reduction in gate voltage in a push-pull output structure, significantly improving the pull-up current capability. By adding NMOS and PMOS feedback loops, it can respond quickly to sudden increases or decreases in load current, while also improving the power supply noise rejection ratio at low frequencies.

[0006] This invention provides the following technical solution: a fast-response low-dropout LDO circuit, comprising a bias generation circuit, a capacitive coupling circuit, and a push-pull output circuit. The bias generation circuit receives a reference voltage Vref and outputs a control voltage Vctrl, a bias voltage VBIAS1, and a bias voltage VBIAS2 to the push-pull output circuit. The push-pull output circuit receives the control voltage Vctrl, the bias voltage VBIAS1, and the bias voltage VBIAS2 from the bias generation circuit and outputs a voltage Vout to the capacitive coupling circuit. The capacitive coupling circuit forms a negative feedback loop. When Vout decreases, the capacitive coupling circuit responds quickly according to the change in Vout, generating a feedback voltage. By adjusting the push-pull output circuit connected to it, the voltage Vout is increased.

[0007] Furthermore, the aforementioned bias generation circuit includes: an operational amplifier (OPA), a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, and a twenty-second MOSFET;

[0008] The positive input terminal of the operational amplifier serves as the input terminal of the bias generation circuit, receiving the reference voltage Vref. The inverting input terminal of the operational amplifier, the output terminal of the operational amplifier, and the source of the tenth MOSFET are connected together.

[0009] The drain of the tenth MOSFET, the gate of the tenth MOSFET, and the drain of the eleventh MOSFET are connected together. The gate of the tenth MOSFET outputs a control voltage Vctrl.

[0010] The source of the fifth MOSFET, the source of the sixth MOSFET, and the source of the seventh MOSFET are connected to a power supply, and the gate of the fifth MOSFET, the gate of the sixth MOSFET, and the gate of the seventh MOSFET are connected together.

[0011] The gate of the fifth MOSFET is connected to the drain of the fifth MOSFET, the source of the twenty-second MOSFET, the source of the eleventh MOSFET, and the source of the thirteenth MOSFET.

[0012] The drain of the sixth MOSFET, the drain of the twenty-second MOSFET, the gate of the twenty-second MOSFET, and the gate of the eleventh MOSFET are connected together.

[0013] The drain of the seventh MOSFET, the drain of the twelfth MOSFET, and the gate of the twelfth MOSFET are connected together, and the gate of the twelfth MOSFET outputs a bias voltage VBIAS1.

[0014] The source of the twelfth MOSFET, the drain of the thirteenth MOSFET, and the gate of the thirteenth MOSFET are connected together, and the gate of the thirteenth MOSFET outputs a bias voltage VBIAS2.

[0015] The drain of the fifth MOSFET, the source of the twenty-second MOSFET, the source of the eleventh MOSFET, and the source of the thirteenth MOSFET are connected together and grounded.

[0016] Furthermore, the aforementioned push-pull output circuit includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a ninth MOSFET, an eighteenth MOSFET, and a first capacitor;

[0017] The gate of the first MOS transistor receives the bias voltage VBIAS1 output by the bias generation circuit, and the drain of the first MOS transistor, the drain of the ninth MOS transistor, and the gate of the second MOS transistor are connected together.

[0018] The source of the ninth MOSFET is connected to the power supply via the source of the second MOSFET.

[0019] The gate of the third MOS transistor receives the control voltage Vctrl output by the bias generation circuit, and the drain of the third MOS transistor, the source of the first MOS transistor, the drain of the eighteenth MOS transistor, and the gate of the fourth MOS transistor are connected.

[0020] The gate of the eighteenth MOS transistor receives the bias voltage VBIAS2 output by the bias generation circuit. The source of the eighteenth MOS transistor is connected to the source of the fourth MOS transistor and one end of the first capacitor and grounded.

[0021] The source of the third MOSFET is connected to the drain of the second MOSFET, the drain of the fourth MOSFET, and the other end of the first capacitor. This connection forms the output voltage Vout of the push-pull output circuit.

[0022] Furthermore, the aforementioned capacitive coupling circuit includes an eighth MOSFET, a fourteenth MOSFET, a nineteenth MOSFET, a fifteenth MOSFET, a twentieth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, a second capacitor, and a third capacitor;

[0023] The source of the eighth MOSFET is connected to the power supply of the source of the nineteenth MOSFET, the source of the twentieth MOSFET, and the source of the twenty-first MOSFET.

[0024] The drain of the eighth MOSFET is connected to the drain of the fourteenth MOSFET, the gate of the fourteenth MOSFET, and the gate of the fifteenth MOSFET.

[0025] The gate of the eighth MOSFET is connected to the gate of the twenty-first MOSFET and the gate of the ninth MOSFET.

[0026] The source of the fourteenth MOSFET is connected to the source of the fifteenth MOSFET, the source of the sixteenth MOSFET, and the source of the seventeenth MOSFET and grounded.

[0027] The drain of the nineteenth MOSFET is connected to the gate of the nineteenth MOSFET, the drain of the fifteenth MOSFET, the gate of the twentieth MOSFET, and one end of the second capacitor. The other end of the second capacitor serves as the receiving end of the capacitive coupling circuit to receive the voltage Vout output from the push-pull output circuit.

[0028] The drain of the twentieth MOSFET is connected to the drain of the sixteenth MOSFET, the gate of the sixteenth MOSFET, and the gate of the seventeenth MOSFET.

[0029] The drain of the 21st MOSFET is connected to one end of the third capacitor and the drain of the 17th MOSFET. The other end of the third capacitor forms the output terminal of the capacitive coupling circuit, which outputs voltage to the push-pull output circuit. The other end of the third capacitor is connected to the drain of the first MOSFET, the drain of the ninth MOSFET, and the gate of the second MOSFET.

[0030] Furthermore, in the aforementioned fast-response low-dropout LDO circuit, the second capacitance stage is 10pF; and the third capacitance stage is 1pF.

[0031] Compared with the prior art, the beneficial technical effects of the present invention using the above technical solution are as follows:

[0032] 1. This invention fully utilizes the characteristic of the gate voltage of the push-pull output structure to reduce the voltage, thus solving the problem of weak current-pulling capability of low-dropout linear regulators based on the flip-flop voltage follower structure.

[0033] 2. This invention adds NMOS and PMOS feedback loops, which can respond quickly when the load current suddenly increases or decreases, solving the problem of slow discharge of traditional resistors and improving the power supply noise suppression ratio.

[0034] 3. This invention employs a capacitive coupling path, which improves the transient response speed when the load current increases by constructing a faster loop.

[0035] This structure fully utilizes the characteristic of a common reduction in gate voltage in a push-pull output structure, significantly improving the pull-up current capability. By adding NMOS and PMOS feedback loops, it can respond quickly to sudden increases or decreases in load current, while also improving the power supply noise rejection ratio at low frequencies. Furthermore, a capacitive coupling path is employed to compensate for the slower response speed of the PMOS feedback loop compared to the NMOS feedback loop, thereby improving the transient response speed when the load current suddenly increases. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a fast-response low-dropout LDO circuit according to the present invention;

[0037] In the diagram: M1 is the first MOSFET, M2 is the second MOSFET, M3 is the third MOSFET, M4 is the fourth MOSFET, M5 is the fifth MOSFET, M6 is the sixth MOSFET, M7 is the seventh MOSFET, M8 is the eighth MOSFET, M9 is the ninth MOSFET, M10 is the tenth MOSFET, M11 is the eleventh MOSFET, M12 is the twelfth MOSFET, M13 is the thirteenth MOSFET, M14 is the fourteenth MOSFET, M15 is the fifteenth MOSFET, M16 is the sixteenth MOSFET, M17 is the seventeenth MOSFET, M18 is the eighteenth MOSFET, M19 is the nineteenth MOSFET, M20 is the twentieth MOSFET, M21 is the twenty-first MOSFET, M22 is the twenty-second MOSFET, C1 is the first capacitor, C2 is the second capacitor, and C3 is the third capacitor.

[0038] Figure 2 This is a block diagram of the negative feedback system of the present invention.

[0039] Figure 3 The circuit diagram of the single-regulating LDO described in document 10.1109 / JSSC.2009.2039685.

[0040] Figure 4 This is a circuit diagram of a flip-flop voltage follower (LDO) described in document 10.1109 / ISSCC.2014.6757446.

[0041] Figure 5 This is a comparison diagram of the transient response capability of the LDO circuit described in this invention and the LDO circuit described in document 10.1109 / ISSCC.2014.6757446.

[0042] Figure 6 This is a comparison chart of the power supply noise suppression ratio of the LDO circuit described in this invention and the LDO circuit described in document 10.1109 / ISSCC.2014.6757446. Detailed Implementation

[0043] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0044] In this invention, various aspects of the invention are described with reference to the accompanying drawings, in which numerous illustrative embodiments are shown. Embodiments of the invention are not limited to those depicted in the drawings. It should be understood that the invention is implemented through any of the various concepts and embodiments described above, as well as the concepts and embodiments described in detail below, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.

[0045] like Figure 1 As shown, the present invention provides a fast-response low-dropout LDO circuit, including a bias generation circuit, a capacitive coupling circuit, and a push-pull output circuit. The bias generation circuit receives a reference voltage Vref and outputs a control voltage Vctrl, a bias voltage VBIAS1, and a bias voltage VBIAS2 to the push-pull output circuit. The push-pull output circuit receives the control voltage Vctrl, the bias voltage VBIAS1, and the bias voltage VBIAS2 from the bias generation circuit and outputs a voltage Vout to the capacitive coupling circuit. The capacitive coupling circuit receives the voltage Vout, couples the voltage, and then outputs it to the push-pull output circuit.

[0046] The bias generation circuit includes: an operational amplifier (OPA), a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, and a twenty-second MOSFET;

[0047] The positive input terminal of the operational amplifier serves as the input terminal of the bias generation circuit, receiving the reference voltage Vref. The inverting input terminal of the operational amplifier, the output terminal of the operational amplifier, and the source of the tenth MOSFET are connected together. The operational amplifier forms a unity-gain negative feedback structure, and the output voltage is equal to the reference voltage.

[0048] The drain of the tenth MOSFET, the gate of the tenth MOSFET, and the drain of the eleventh MOSFET are connected together. The gate of the tenth MOSFET outputs a control voltage Vctrl.

[0049] The source of the fifth MOSFET, the source of the sixth MOSFET, and the source of the seventh MOSFET are connected to a power supply, and the gate of the fifth MOSFET, the gate of the sixth MOSFET, and the gate of the seventh MOSFET are connected together.

[0050] The gate of the fifth MOSFET is connected to the drain of the fifth MOSFET, the source of the twenty-second MOSFET, the source of the eleventh MOSFET, and the source of the thirteenth MOSFET.

[0051] The drain of the sixth MOSFET, the drain of the twenty-second MOSFET, the gate of the twenty-second MOSFET, and the gate of the eleventh MOSFET are connected together.

[0052] The drain of the seventh MOSFET, the drain of the twelfth MOSFET, and the gate of the twelfth MOSFET are connected together, and the gate of the twelfth MOSFET outputs a bias voltage VBIAS1.

[0053] The source of the twelfth MOSFET, the drain of the thirteenth MOSFET, and the gate of the thirteenth MOSFET are connected together, and the gate of the thirteenth MOSFET outputs a bias voltage VBIAS2.

[0054] The drain of the fifth MOSFET, the source of the twenty-second MOSFET, the source of the eleventh MOSFET, and the source of the thirteenth MOSFET are connected together and grounded.

[0055] The push-pull output circuit includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a ninth MOSFET, an eighteenth MOSFET, and a first capacitor;

[0056] The gate of the first MOS transistor receives the bias voltage VBIAS1 output by the bias generation circuit, and the drain of the first MOS transistor, the drain of the ninth MOS transistor, and the gate of the second MOS transistor are connected together.

[0057] The source of the ninth MOSFET is connected to the power supply via the source of the second MOSFET.

[0058] The gate of the third MOS transistor receives the control voltage Vctrl output by the bias generation circuit, and the drain of the third MOS transistor, the source of the first MOS transistor, the drain of the eighteenth MOS transistor, and the gate of the fourth MOS transistor are connected.

[0059] The gate of the eighteenth MOS transistor receives the bias voltage VBIAS2 output by the bias generation circuit. The source of the eighteenth MOS transistor is connected to the source of the fourth MOS transistor and one end of the first capacitor and grounded.

[0060] The source of the third MOSFET is connected to the drain of the second MOSFET, the drain of the fourth MOSFET, and the other end of the first capacitor. This connection forms the output voltage Vout of the push-pull output circuit.

[0061] The capacitive coupling circuit includes an eighth MOSFET, a fourteenth MOSFET, a nineteenth MOSFET, a fifteenth MOSFET, a twentieth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, a second capacitor, and a third capacitor;

[0062] The source of the eighth MOSFET is connected to the power supply of the source of the nineteenth MOSFET, the source of the twentieth MOSFET, and the source of the twenty-first MOSFET.

[0063] The drain of the eighth MOSFET is connected to the drain of the fourteenth MOSFET, the gate of the fourteenth MOSFET, and the gate of the fifteenth MOSFET.

[0064] The source of the fourteenth MOSFET is connected to the source of the fifteenth MOSFET, the source of the sixteenth MOSFET, and the source of the seventeenth MOSFET and grounded.

[0065] The drain of the nineteenth MOSFET is connected to the gate of the nineteenth MOSFET, the drain of the fifteenth MOSFET, the gate of the twentieth MOSFET, and one end of the second capacitor. The other end of the second capacitor serves as the receiving end of the capacitive coupling circuit to receive the voltage Vout output from the push-pull output circuit.

[0066] The drain of the twentieth MOSFET is connected to the drain of the sixteenth MOSFET, the gate of the sixteenth MOSFET, and the gate of the seventeenth MOSFET.

[0067] The drain of the 21st MOSFET is connected to one end of the third capacitor and the drain of the 17th MOSFET. The other end of the third capacitor forms the output terminal of the capacitive coupling circuit, which outputs voltage to the push-off output circuit. The other end of the third capacitor is connected to the drain of the first MOSFET, the drain of the ninth MOSFET, and the gate of the second MOSFET.

[0068] The eighteenth and eleventh MOSFETs form a current mirror, and the ratio of the currents in the two branches... Ratio to gate width Equal. The ratio of the gate width of the third MOSFET to that of the tenth MOSFET. Therefore, the source potentials of the third and tenth MOSFETs are equal, making the output voltage equal to the reference voltage. The fifth, sixth, seventh, eighth, and ninth MOSFETs form a current mirror, replicating the current from the current source ISS to each branch. The twelfth and thirteenth MOSFETs are diode-connected, providing bias voltage to the first and eighteenth MOSFETs.

[0069] refer to Figure 1 When the power supply voltage changes, the circuit reduces the impact on the output voltage through PMOS and NMOS feedback loops, thereby improving the power supply noise rejection ratio. The closed-loop transfer function is calculated as follows:

[0070] V dd ·A CG2 -V out ·A CG3 ·(A CS4 +A CG1 ·A CS2 ) = V out Where V dd It is the power supply voltage, V out It is the output voltage, A CG2 It is the common-gate gain of the second MOSFET, A. CG3 It is the common-gate gain of the third MOSFET, A. CS4 It is the common-source gain of the fourth MOSFET, A. CG1 It is the common-gate gain of the first MOSFET, A. CS2This is the common-source gain of the second MOSFET. Therefore PSR stands for Power Supply Noise Rejection Ratio.

[0071] like Figure 2 As shown,

[0072]

[0073]

[0074]

[0075]

[0076] Substituting into the transfer function yields the power supply rejection ratio at low frequencies. It can be seen that due to the low output impedance of the output node, A... CG2 The lower noise level results in a higher power supply noise rejection ratio.

[0077] When the load current suddenly decreases, the output Vout rises rapidly. The NMOS feedback loop can respond quickly, the gate voltage of the fourth MOSFET rises rapidly, the leakage current increases, and Vout begins to fall rapidly. When the load current suddenly increases, the output Vout falls rapidly. The PMOS feedback loop can respond quickly, the gate voltage of the second MOSFET falls rapidly, the leakage current increases, and Vout begins to rise rapidly.

[0078] Because the response speed of the PMOS feedback loop is slower than that of the NMOS feedback loop, a capacitive coupling path is added to compensate for the slower response speed of the PMOS feedback loop. When Vout drops rapidly, it is quickly coupled to the gate of the twentieth MOS transistor through the second capacitor, causing the drain current of the twentieth MOS transistor to increase rapidly. Consequently, the gate voltage of the seventeenth MOS transistor rises rapidly, and the drain current of the seventeenth MOS transistor increases rapidly, thus causing the drain voltage of the seventeenth MOS transistor to drop. Then, it is coupled to the gate of the second MOS transistor through the third capacitor, causing the drain current of the second MOS transistor to increase, and Vout begins to rise.

[0079] The size of the second capacitor depends on the series voltage division between the second capacitor and the gate parasitic capacitance of the twentieth MOSFET, and is on the order of approximately 10pF; the size of the third capacitor depends on the series voltage division between the third capacitor and the gate parasitic capacitance of the second MOSFET, and is on the order of approximately 1pF.

[0080] When the load current suddenly increases, the response process is as follows. The load capacitor first discharges, causing the output voltage V to drop. outThe leakage current of the third MOSFET decreases rapidly, leading to a decrease in its drain voltage (i.e., the gate voltage of the fourth MOSFET), which in turn reduces its leakage current. Therefore, some current from the second MOSFET flows to the load. Furthermore, because the drain voltage of the third MOSFET (i.e., the source voltage of the first MOSFET) decreases, the leakage current of the first MOSFET increases. Consequently, the gate capacitance of the second MOSFET discharges rapidly in response, resulting in a decrease in its gate voltage and thus an increase in its leakage current. Simultaneously, the coupling capacitors second and third feed through, causing a decrease in the gate voltage of the nineteenth MOSFET and a decrease in the drain voltage of the twenty-first MOSFET. This leads to the discharge of the gate capacitance of the second MOSFET, resulting in a decrease in its gate voltage and an increase in its leakage current.

[0081] The above transient response continues until the second MOSFET is sufficient to provide the load current, the output capacitor stops discharging, and the output voltage no longer decreases.

[0082] like Figure 3 The image shows an LDO circuit structure from the literature “M. El-Nozahi, A. Amer, J. Torres, K. Entesari and E. Sanchez-Sinencio, High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique,” ​​in IEEE Journal of Solid-State Circuits, vol.45, no.3, pp.565-577, March 2010, doi:10.1109 / JSSC.2009.2039685.” This structure employs a traditional single-regulator transistor design. While the circuit utilizes a feedforward ripple cancellation (FFRC) method to improve the power supply noise rejection ratio, this approach fails to enhance transient response speed.

[0083] like Figure 4The image shows an LDO circuit structure from the literature “Y.Lu,W.-H.Ki and CPYue,” 17.11A 0.65ns-response-time 3.01ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014, pp.306-307, doi:10.1109 / ISSCC.2014.6757446.” This structure employs a flip-flop voltage follower. The circuit utilizes a buffer impedance attenuation structure to increase loop bandwidth, thereby improving transient response speed. However, this approach cannot improve loop gain, thus failing to achieve a good power supply noise rejection ratio, and its current-pull capability is limited.

[0084] like Figure 5 As shown in the figure, the transient response effect of the LDO circuit described in reference 10.1109 / ISSCC.2014.6757446 is shown by the dashed line in the figure. The transient response simulation diagram of the LDO circuit described in this invention is shown by the solid line in the figure. It can be seen that by adopting the structure of this invention, the transient response speed is rapidly improved.

[0085] like Figure 6 As shown in reference 10.1109 / ISSCC.2014.6757446, the power supply noise suppression ratio of the LDO circuit is approximately -55dB at 10kHz. The power supply noise suppression ratio of the LDO circuit of this invention is approximately -67dB at 10kHz. It can be seen that by adopting the structure of this invention, the power supply noise suppression ratio is optimized, with an improvement of 12dB at 10kHz.

[0086] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A fast-response low-dropout LDO circuit, characterized in that, It includes a bias generation circuit, a capacitive coupling circuit, and a push-pull output circuit. The bias generation circuit receives a reference voltage Vref and outputs a control voltage Vctrl, a bias voltage VBIAS1, and a bias voltage VBIAS2 to the push-pull output circuit. The push-pull output circuit receives the control voltage Vctrl, the bias voltage VBIAS1, and the bias voltage VBIAS2 from the bias generation circuit and outputs a voltage Vout to the capacitive coupling circuit. The capacitive coupling circuit forms a negative feedback loop. When Vout decreases, the capacitive coupling circuit responds quickly according to the change in Vout and generates a feedback voltage. By adjusting the push-pull output circuit connected to it, the voltage Vout is increased. The bias generation circuit includes: an operational amplifier (OPA), a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, and a twenty-second MOSFET; The positive input terminal of the operational amplifier serves as the input terminal of the bias generation circuit, receiving the reference voltage Vref. The inverting input terminal of the operational amplifier, the output terminal of the operational amplifier, and the source of the tenth MOSFET are connected together. The drain of the tenth MOSFET, the gate of the tenth MOSFET, and the drain of the eleventh MOSFET are connected together. The gate of the tenth MOSFET outputs a control voltage Vctrl. The source of the fifth MOSFET, the source of the sixth MOSFET, and the source of the seventh MOSFET are connected to a power supply, and the gate of the fifth MOSFET, the gate of the sixth MOSFET, and the gate of the seventh MOSFET are connected together. The gate of the fifth MOSFET is connected to the drain of the fifth MOSFET, the source of the twenty-second MOSFET, the source of the eleventh MOSFET, and the source of the thirteenth MOSFET. The drain of the sixth MOSFET, the drain of the twenty-second MOSFET, the gate of the twenty-second MOSFET, and the gate of the eleventh MOSFET are connected together. The drain of the seventh MOSFET, the drain of the twelfth MOSFET, and the gate of the twelfth MOSFET are connected together, and the gate of the twelfth MOSFET outputs a bias voltage VBIAS1. The source of the twelfth MOSFET, the drain of the thirteenth MOSFET, and the gate of the thirteenth MOSFET are connected together, and the gate of the thirteenth MOSFET outputs a bias voltage VBIAS2. The drain of the fifth MOSFET, the source of the twenty-second MOSFET, the source of the eleventh MOSFET, and the source of the thirteenth MOSFET are connected to and grounded. The push-pull output circuit includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a ninth MOSFET, an eighteenth MOSFET, and a first capacitor; The gate of the first MOS transistor receives the bias voltage VBIAS1 output by the bias generation circuit, and the drain of the first MOS transistor, the drain of the ninth MOS transistor, and the gate of the second MOS transistor are connected together. The source of the ninth MOSFET is connected to the power supply via the source of the second MOSFET. The gate of the third MOS transistor receives the control voltage Vctrl output by the bias generation circuit, and the drain of the third MOS transistor, the source of the first MOS transistor, the drain of the eighteenth MOS transistor, and the gate of the fourth MOS transistor are connected. The gate of the eighteenth MOS transistor receives the bias voltage VBIAS2 output by the bias generation circuit. The source of the eighteenth MOS transistor is connected to the source of the fourth MOS transistor and one end of the first capacitor and grounded. The source of the third MOSFET is connected to the drain of the second MOSFET, the drain of the fourth MOSFET, and the other end of the first capacitor. This connection forms the output voltage Vout of the push-pull output circuit. The capacitive coupling circuit includes an eighth MOSFET, a fourteenth MOSFET, a nineteenth MOSFET, a fifteenth MOSFET, a twentieth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, a second capacitor, and a third capacitor; The source of the eighth MOSFET is connected to the power supply of the source of the nineteenth MOSFET, the source of the twentieth MOSFET, and the source of the twenty-first MOSFET. The drain of the eighth MOSFET is connected to the drain of the fourteenth MOSFET, the gate of the fourteenth MOSFET, and the gate of the fifteenth MOSFET. The gate of the eighth MOSFET is connected to the gate of the twenty-first MOSFET and the gate of the ninth MOSFET. The source of the fourteenth MOSFET is connected to the source of the fifteenth MOSFET, the source of the sixteenth MOSFET, and the source of the seventeenth MOSFET and grounded. The drain of the nineteenth MOSFET is connected to the gate of the nineteenth MOSFET, the drain of the fifteenth MOSFET, the gate of the twentieth MOSFET, and one end of the second capacitor. The other end of the second capacitor serves as the receiving end of the capacitive coupling circuit to receive the voltage Vout output from the push-pull output circuit. The drain of the twentieth MOSFET is connected to the drain of the sixteenth MOSFET, the gate of the sixteenth MOSFET, and the gate of the seventeenth MOSFET. The drain of the 21st MOSFET is connected to one end of the third capacitor and the drain of the 17th MOSFET; the other end of the third capacitor forms the output terminal of the capacitive coupling circuit, which outputs voltage to the push-pull output circuit. The other end of the third capacitor is connected to the drain of the first MOSFET, the drain of the ninth MOSFET, and the gate of the second MOSFET. The gate of the eighth MOSFET is connected to the gate of the seventh MOSFET.

2. The fast-response low-dropout LDO circuit according to claim 1, characterized in that, The second capacitance level is 10pF; the third capacitance level is 1pF.

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