Semiconductor memory device and method of operating a semiconductor memory device

Abstract

Semiconductor memory devices and methods of operating semiconductor memory devices are disclosed. One method includes replacing an address of a first regular memory cell in a first column of regular memory cells of a first memory block with a target address, the target address being an address of a second regular memory cell in a second column of regular memory cells of the first memory block; and reassigning an address of the second regular memory cell in the second column of regular memory cells of the first memory block to an address of a first redundant memory cell of a first redundant block of the at least one redundant block.

Description

[0001] This application is a divisional application of patent application No. 201910246502.5, filed on March 26, 2019, entitled "Semiconductor memory device and method of operating semiconductor memory device".

[0002] This application claims priority to Korean Patent Application No. 10-2018-0036291, filed on March 29, 2018, with the Korean Intellectual Property Office; Korean Patent Application No. 10-2018-0079345, filed on July 9, 2018, with the Korean Intellectual Property Office; Korean Patent Application No. 10-2018-0119317, filed on October 5, 2018, with the Korean Intellectual Property Office; Korean Patent Application No. 10-2019-0011563, filed on January 30, 2019, with the Korean Intellectual Property Office; and U.S. Application No. 16 / 283,650, filed on February 22, 2019, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to memory, and more specifically, to semiconductor memory devices, methods of operating semiconductor memory devices, and memory systems. Background Technology

[0004] Semiconductor chips are manufactured using semiconductor manufacturing processes and then tested in wafer, die, or package states using testing equipment. Testing identifies defective portions of the chip, and if some memory cells are defective, repair operations are performed to save semiconductor chips. Currently, semiconductor chips, such as Dynamic Random Access Memory (DRAM), continue to shrink in size through refined processes, thus increasing the likelihood of errors occurring during manufacturing. Furthermore, if defects are not detected during the initial testing process, errors may occur during chip operation.

[0005] One method for correcting errors is to use redundant memory blocks, which consist of arrays of memory cells that serve as backups for cells that fail in regular memory blocks. However, adding redundant memory blocks typically increases the overall size of the memory cell array and the memory chip. Therefore, it is beneficial to implement redundancy in a way that allows for a smaller increase in the size of the memory chip. Summary of the Invention

[0006] Therefore, the repair control circuitry in a semiconductor memory device repairs a faulty cell in at least one memory block of a plurality of memory blocks to at least one normal cell in the same memory block at least once, and can replace a normal cell with a redundant cell in a redundant block. Thus, the semiconductor memory device can utilize redundant resources in the redundant block with greater efficiency.

[0007] According to an exemplary embodiment, which may be part of one or more embodiments described elsewhere in the present invention, a method is provided for replacing a memory cell in a first column of conventional memory cells of a memory block in a memory device comprising a plurality of memory blocks and at least one redundant block. The method includes: replacing an address of a first conventional memory cell in a first column of conventional memory cells of a first memory block of the plurality of memory blocks with a target address, wherein the target address is an address of a second conventional memory cell in a second column of conventional memory cells of the first memory block; and reassigning the address of the second conventional memory cell in the second column of conventional memory cells of the first memory block to an address of a first redundant memory cell in a first redundant block of the at least one redundant block of the memory device.

[0008] According to an exemplary embodiment that may be part of one or more embodiments described elsewhere in the present invention, a memory device includes: a plurality of memory blocks, each memory block including a plurality of columns of conventional memory cells; at least one redundant block, each redundant block including a plurality of columns of redundant memory cells; and repair control circuitry. The repair control circuitry is configured to: use a second column of conventional memory cells from a first memory block of the plurality of memory blocks as a target column for a first column of conventional memory cells in the first memory block, and to store data destined for a second column of conventional memory cells in a first redundant block of the at least one redundant block.

[0009] According to an exemplary embodiment, which may be part of one or more embodiments described elsewhere in this invention, a memory device includes: a plurality of memory blocks, each memory block including a plurality of columns of conventional memory cells; at least one redundant block, each redundant block including a plurality of columns of redundant memory cells; and repair control circuitry. The repair control circuitry is configured to: replace a first conventional memory cell in a first column of conventional memory cells of a first memory block of the plurality of memory blocks with a second conventional memory cell in a second column of conventional memory cells of the first memory block, and replace a second conventional memory cell in a second column of conventional memory cells of the first memory block with a first redundant memory cell in a first redundant block of the at least one redundant block. The step of replacing a second conventional memory cell with a first redundant memory cell includes causing the first redundant memory cell to store data destined for the second conventional memory cell.

[0010] According to an exemplary embodiment, which may be part of one or more embodiments described elsewhere in the present invention, a memory device includes: a plurality of memory blocks, each memory block including a plurality of columns of conventional memory cells; at least one redundant block, each redundant block including a plurality of columns of redundant memory cells; and repair control circuitry. The repair control circuitry is configured to: replace a first conventional memory cell in a first column of conventional memory cells of a first memory block of the plurality of memory blocks with a second conventional memory cell in a second column of conventional memory cells of the first memory block, and replace a second conventional memory cell in a second column of conventional memory cells of a first memory block with a first redundant memory cell in a first redundant block of the at least one redundant block. The step of replacing a second conventional memory cell with a first redundant memory cell may include: replacing the second conventional memory cell with a third memory cell in a first column of conventional memory cells of a second memory block of the plurality of memory blocks, and replacing a conventional memory cell in a second conventional memory cell and another conventional memory cell in a second memory block or another memory block of the plurality of memory blocks with a first redundant memory cell.

[0011] According to an exemplary embodiment, which may be part of one or more embodiments described elsewhere in the present invention, a memory device includes: a plurality of memory blocks, each memory block including a plurality of columns of conventional memory cells; at least one redundant block, each redundant block including a plurality of columns of redundant memory cells; and repair control circuitry. The repair control circuitry is configured to: replace a first conventional memory cell in a first column of conventional memory cells of a first memory block of the plurality of memory blocks with a second conventional memory cell in a second column of conventional memory cells of the first memory block, and replace a second conventional memory cell in a second column of conventional memory cells of a first memory block with a first redundant memory cell in a first redundant block of the at least one redundant block. The step of replacing a second conventional memory cell with a first redundant memory cell may include: replacing the second conventional memory cell with a third conventional memory cell in a first column of conventional memory cells of a second memory block of the plurality of memory blocks, and replacing a conventional memory cell in a second conventional memory cell and another conventional memory cell in a second memory block or another memory block of the plurality of memory blocks with a first redundant memory cell.

[0012] According to an exemplary embodiment, which may be part of one or more embodiments described elsewhere in this invention, a memory device includes: a plurality of memory blocks, each memory block including a plurality of columns of conventional memory cells; at least one redundant block, each redundant block including a plurality of columns of redundant memory cells; a plurality of column select lines for selecting the plurality of columns of conventional memory cells and the plurality of columns of redundant memory cells, each column select line being associated with a column address; and repair control circuitry. The repair control circuitry is configured to: replace a first source address with a first target address, wherein the first source address is an address of a first column select line connected to a first column of memory cells in a first memory block of the plurality of memory blocks, and the first target address is an address of a second column select line connected to a second column of memory cells in a second memory cell of the first memory block; and replace the address of the second column select line with the address of a first column select line connected to a first column of redundant memory cells in a first column of redundant memory cells in the at least one redundant block. Attached Figure Description

[0013] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings.

[0014] Figure 1 This is a block diagram illustrating a memory system according to an exemplary embodiment.

[0015] Figure 2A This illustrates an exemplary embodiment. Figure 1 A block diagram of an example semiconductor memory device.

[0016] Figure 2B Showing according to an exemplary embodiment Figure 2A It is part of a semiconductor memory device.

[0017] Figure 3 This illustrates an exemplary embodiment. Figure 2A A block diagram of a portion of a semiconductor memory device.

[0018] Figure 4A This illustrates an exemplary embodiment. Figure 3 A block diagram of an example of a first cell repair controller in a semiconductor memory device.

[0019] Figure 4B It is shown Figure 4A The circuit diagram is an example of a column selection line driver in the first unit repair controller.

[0020] Figure 5 This illustrates an exemplary embodiment. Figure 3 A block diagram of an example of a redundancy repair controller in a semiconductor memory device.

[0021] Figure 6A Shown in Figure 3 Repair operations performed in semiconductor memory devices.

[0022] Figure 6B Shown in Figure 2B Repair operations performed in semiconductor memory devices.

[0023] Figure 6C Showing when execution Figure 6A Data input / output during repair operations.

[0024] Figure 6D Showing when execution Figure 6B Data input / output during repair operations.

[0025] Figure 7 Show Figure 4A The first unit in the example repairs the address storage table in the controller.

[0026] Figure 8 It is shown Figure 7 A diagram illustrating an example of an address storage table.

[0027] Figures 9A to 9C This is a diagram illustrating a method of replacing a faulty cell with a regular cell in the same memory block and replacing the regular cell with a redundant cell.

[0028] Figure 10 This is a flowchart illustrating a method for operating a semiconductor memory device according to an exemplary embodiment.

[0029] Figure 11 This illustrates an exemplary embodiment. Figure 1 A block diagram of another example of a semiconductor memory device in a memory system.

[0030] Figure 12 Show Figure 11 An example of a first memory bank array in a semiconductor memory device.

[0031] Figure 13 This illustrates an exemplary embodiment. Figure 11 A block diagram of the repair control circuitry included in each bank column decoder of a semiconductor memory device.

[0032] Figure 14 Showing according to an exemplary embodiment Figure 13 An example of a fault address storage circuit in a repair control circuit.

[0033] Figure 15 Showing according to an exemplary embodiment Figure 11 It is part of a semiconductor memory device.

[0034] Figure 16A The example shown is in Figure 15 Repair operations performed in semiconductor memory devices.

[0035] Figure 16B Show Figure 15 Another example of a first memory bank array in a semiconductor memory device.

[0036] Figure 16C Show Figure 15 Another example of a first memory bank array in a semiconductor memory device.

[0037] Figure 17A Showing according to an exemplary embodiment Figure 13 An example of repairing the address storage table in the control circuit.

[0038] Figure 17B An example of reducing several fuses associated with a repair operation is shown according to an example embodiment.

[0039] Figure 17C Another example of reducing several fuses associated with a repair operation according to an example embodiment is shown.

[0040] Figure 17D Implementation details Figure 17C An example of an example.

[0041] Figure 17E An example of a cell repair controller according to an example embodiment is shown.

[0042] Figure 17F Another example of a cell repair controller according to an example embodiment is shown.

[0043] Figure 17G Another example of a cell repair controller according to an example embodiment is shown.

[0044] Figure 17H Another example of a cell repair controller according to an example embodiment is shown.

[0045] Figure 18 This is a flowchart illustrating a method for operating a semiconductor memory device according to an exemplary embodiment.

[0046] Figure 19 This is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0047] Figure 20 This is an adoption based on an exemplary embodiment. Figure 19 A cross-sectional view of the 3D chip structure of a semiconductor memory device. Detailed Implementation

[0048] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0049] As seen in the various claims and the specification, the naming conventions such as “first,” “second,” “third,” etc., are used to describe certain items described herein. Unless the context otherwise requires, these terms are used only to distinguish items from each other and do not necessarily indicate the physical location or operational order of the items. Therefore, depending on the context of the discussion, different naming terms (such as “first,” “second,” etc.) may be used to refer to specific items or objects in the specification or different claims.

[0050] Figure 1 This is a block diagram illustrating a memory system according to an exemplary embodiment.

[0051] Reference Figure 1 The memory system 20 may include a memory controller 100 and a semiconductor memory device 200.

[0052] The memory controller 100 controls the overall operation of the memory system 20. The memory controller 100 controls the overall data exchange between the external host and the semiconductor memory device 200. For example, the memory controller 100 can write data to or read data from the semiconductor memory device 200 in response to a request from the host. Additionally, the memory controller 100 can issue operation commands to the semiconductor memory device 200 to control it.

[0053] In some embodiments, the semiconductor memory device 200 is a memory device including dynamic memory cells (such as dynamic random access memory (DRAM), double data rate 4 (DDR4) synchronous DRAM (SDRAM), low power DDR4 (LPDDR4) SDRAM, or LPDDR5 SDRAM).

[0054] The memory controller 100 sends the clock signal CLK, the command CMD, and the address (signal) ADDR to the semiconductor memory device 200, and exchanges data DQ with the semiconductor memory device 200.

[0055] Semiconductor memory device 200 includes: a memory cell array (MCA) 300 for storing data DQ, control logic circuitry 210, and repair control circuitry 400. The memory cell array 300 may include multiple memory blocks and at least one redundant block.

[0056] The control logic circuit 210 controls access to the memory cell array 300 based on the command CMD and the address ADDR, and the repair control circuit 400 can repair faulty cells in the first memory block of the multiple memory blocks, thereby replacing the faulty cells in the first memory block of the multiple memory blocks with first normal cells in the first memory block, and can replace the first normal cells with redundant cells in the redundant block. Therefore, the repair control circuit 400 can use the redundant resources in the redundant block with higher efficiency.

[0057] For example, the repair control circuit 400 can replace a memory cell in a memory block with a regular cell in the same memory block at least once, and then replace the regular cell with a redundant cell. Therefore, instead of simply repairing a faulty cell with a redundant cell, the memory cell initially replaced can be a faulty cell that can be repaired with a regular cell, and this regular cell can be replaced with a redundant cell or other regular cells, such that the final regular cell in a series of replacements is replaced by a redundant cell. Thus, the repair control circuit 400 can utilize redundant resources in a redundant block with greater efficiency.

[0058] Figure 2A This illustrates an exemplary embodiment. Figure 1 A block diagram of an example semiconductor memory device.

[0059] Reference Figure 2A The semiconductor memory device 200a may include control logic circuitry 210a, address buffer 251, repair control circuitry 400a, row decoder 261, input / output (I / O) gate circuitry 290a, data I / O buffer 296, and memory cell array 301.

[0060] Control logic circuit 210a receives command CMD and access address ADDR. Control logic circuit 210a can control the operation of semiconductor memory device 200a based on command CMD and access address ADDR. Control logic circuit 210a can also control line decoder 261, I / O gate circuit 290a, and repair control circuit 400a based on command CMD and access address ADDR.

[0061] Address buffer 251 receives access address ADDR, provides the row address RADDR of access address ADDR to row decoder 261, and provides the column address CADDR of access address ADDR to repair control circuit 400a. Repair control circuit 400a can repair faulty cells in the same memory block at least once using regular cells in a memory block, and can replace regular cells with redundant cells based on a comparison between column address CADDR and the stored faulty column address.

[0062] The line decoder 261 is connected to the memory cell array 301 via the word line WL, and the I / O gate circuit 290a is connected to the memory cell array 301 via the bit line BTL. The I / O gate circuit 290a receives data DQ from the memory controller 100 and sends data DQ to the memory controller 100 via the data I / O buffer 296.

[0063] Figure 2B Showing according to an exemplary embodiment Figure 2A It is part of a semiconductor memory device.

[0064] exist Figure 2B The image shows a memory cell array 301, an I / O gate circuit 290a, a data I / O buffer 296, and a repair control circuit 400a.

[0065] Reference Figure 2B The memory cell array 301 includes a conventional cell array NCA and a redundant cell array RCA. The conventional cell array NCA includes multiple memory blocks MB0, MB1, MB2, and MB3, and the redundant cell array RCA includes at least one redundant block RMB. The conventional cell array NCA includes memory cells MC connected to word lines WL and bit lines BTL, and the redundant block RMB includes redundant cells RMC connected to word lines WL and redundant bit lines RBTL.

[0066] I / O gate circuit 290a includes multiple I / O circuits 291a, 291b, 291c, 291d, 291e and multiple column select circuits 293a to 293e, and the column select circuits 293a to 293e can connect the I / O circuits 291a to 291e to a corresponding one of the memory blocks MB0 to MB3 and the redundant block RMB. Each column select circuit 293a to 293e may include multiple column select transistors 294a to 294d, and the multiple column select transistors 294a to 294d respectively respond to the column select line signals CSLa to CSLe to connect multiple bit lines or one bit line in the corresponding memory block or the redundant block RMB to the corresponding I / O circuit. In response to the first control signal CTL1 from the control logic circuit 210a, the multiple I / O circuits 291a to 291e can be connected to the data I / O buffer 296 via the data line GIO.

[0067] Although not shown, column select line signal CSLb can be applied to column select circuit 293b, column select line signal CSLc can be applied to column select circuit 293c, column select line signal CSLd can be applied to column select circuit 293d, and column select line signal CSLe can be applied to column select circuit 293e.

[0068] The repair control circuit 400a, in response to accessing the column address CADDR, provides a corresponding one of the column select line signals CSLa to CSLe to a corresponding one of the column select circuits 293a to 293e. Accessing the column address CADDR is from... Figure 2A The address buffer 251 in the memory provides the address, and the access column address CADDR is used to specify the address of a bit line without considering at least one faulty cell in memory blocks MB0 to MB3. Each of the column select line signals CSLa to CSLd is a signal that simultaneously selects the corresponding bit line in memory blocks MB0 to MB3 based on the access column address CADDR. The semiconductor memory device 200a can simultaneously input and output data of a size corresponding to the burst length in response to each of the column select line signals CSLa to CSLd.

[0069] Figure 3 This illustrates an exemplary embodiment. Figure 2A A block diagram of a portion of a semiconductor memory device.

[0070] exist Figure 3 The diagram shows a memory cell array 301, an I / O gate circuit 290a, a repair control circuit 400a, and a data I / O buffer 296. When... Figure 3 and Figure 2BThe repair control circuit 400a is shown in detail during the comparison, and the repair control circuit 400a will be described in detail.

[0071] Reference Figure 3 The memory cell array 301 includes a conventional cell array (NCA) and a redundant cell array (RCA). The conventional cell array (NCA) includes multiple memory blocks MB0, MB1, MB2, and MB3, and the redundant cell array (RCA) includes at least one redundant block RMB. The conventional cell array (NCA) includes memory cells connected to word lines (WL) and bit lines, and the redundant block RMB includes redundant cells connected to word lines and redundant bit lines.

[0072] The repair control circuit 400a may include a plurality of cell repair controllers 401a to 401d and a redundancy repair controller 401e, the cell repair controllers 401a to 401d and the redundancy repair controller 401e corresponding to memory blocks MB0, MB1, MB2 and MB3 and a redundant block RMB. The repair control circuit 400a may be included in a column decoder, for example, in a semiconductor memory device 200a.

[0073] Multiple I / O circuits 291a, 291b, 291c, 291d, and 291e can respond to a first control signal CTL1 to control the connection between memory blocks MB0, MB1, MB2, and MB3, as well as the redundant block RMB, and the data I / O buffer 296. Column select circuits 293a to 293e can connect one of the I / O circuits 291a to 291e to a corresponding one of the memory blocks MB0 to MB3 and the redundant block RMB.

[0074] Cell repair controllers 401a to 401d and redundancy repair controller 401e typically receive the access column address (i.e., column address) CADDR and provide the column select line signals CSLa to CSLe, applied to memory blocks MB0, MB1, MB2, and MB3 and the redundant block RMB, to the corresponding column select circuits 293a to 293e. For example, at a given time, the same access column address can be sent to each of the cell repair controllers 401a to 401e. Based on the state of each cell repair controller 401a to 401e and the information stored in each cell repair controller 401a to 401e, the cell repair controllers 401a to 401e send an output to each of the corresponding column select circuits 293a to 293e for selecting the column used for memory access.

[0075] When memory blocks MB0, MB1, MB2, and MB3 do not contain faulty cells, I / O circuit 291e disconnects the redundant block RMB and data I / O buffer 296 in response to the first control signal CTL1. I / O circuits 291a to 291d can, in response to the first control signal CTL1, transfer data DQ from memory blocks MB0, MB1, MB2, and MB3 to data I / O buffer 296 via column select transistors 294a to 294d, or transfer data DQ from data I / O buffer 296 to memory blocks MB0, MB1, MB2, and MB3. In this case, in each memory block MB0, MB1, MB2, and MB3, one or more bit lines at the same location (e.g., the same relative location within each memory block) can be selected in response to a corresponding column select line signal CSLa to CSLd. The semiconductor memory device 200a can simultaneously input and output data of a size corresponding to the burst length of the semiconductor memory device 200a.

[0076] When at least one of the memory blocks MB0, MB1, MB2 and MB3 includes at least one faulty cell, the I / O circuit 291e is connected to the redundant block RMB in response to the first control signal CTL1, and a repair operation for at least one faulty cell can be performed.

[0077] For example, when each of the memory blocks MB0, MB1, MB2, and MB3 includes at least one faulty cell on the first bit line typically selected by the column select line signal CSL0, the faulty cell in memory block MB0 is repaired by a regular cell in memory block MB0 by enabling the column select line signal CSL3 instead of CSL0, as shown by reference numeral 511. For example, column select transistor 294c is connected to memory block MB0 and data I / O buffer 291a by enabling column select line signal CSL3 instead of CSL0. As further described below, a corresponding cell repair controller can cause column select line signal CSL3 to be enabled instead of CSL0. Additionally, by selecting a redundant bit line instead of a bit line in memory block MB0, a regular cell (e.g., a non-redundant cell, which is not a faulty cell in this example) in memory block MB0 is replaced by a redundant cell in redundant block RMB, as shown by reference numeral 512. For example, the repair control circuit 400a can repair the first faulty unit using the first normal unit by selecting the second bit line connected to the first normal unit using the enable column select line signal CSL3 instead of selecting the first bit line connected to the first faulty unit using the enable column select line signal CSL0.

[0078] Assume that memory block MB1 does not contain faulty cells, and therefore none of the columns of memory block MB1 need to be reassigned to other columns or replaced with other columns.

[0079] By enabling column select line signal CSL2 instead of column select line signal CSL0, faulty cells in memory block MB2 are repaired by regular cells in memory block MB2, as shown by reference numeral 513. Additionally, by selecting redundant bit lines instead of bit lines in memory block MB2, redundant cells in redundant block RMB replace regular cells in memory block MB2, as shown by reference numeral 514. By selecting redundant bit lines instead of bit lines in memory block MB3, faulty cells in redundant block RMB are repaired by redundant cells in redundant block RMB, as shown by reference numeral 515.

[0080] Figure 4A This illustrates an exemplary embodiment. Figure 3 A block diagram of an example of a first cell repair controller in a semiconductor memory device.

[0081] Reference Figure 4A The first unit repair controller 401a may include a table pointer 405, an address storage table 420, a column address comparator 430, a selection circuit 440, and a column selection line (CSL) driver 450.

[0082] Table pointer 405 can generate a toggling table pointer signal TPS in response to sequentially changing column addresses CADDR. Address storage table 420 can store at least one source column address SRCA and at least one destination column address DSCA corresponding to the at least one source column address SRCA as fuse information.

[0083] Column address comparator 430 compares the access column address CADDR with the source column address SRCA from address memory table 420 and outputs a first match signal MTH1 indicating the comparison result. Selection circuit 440, in response to the first match signal MTH1, selects one of the target column address DSCA and the access column address CADDR from address memory table 420, outputting the selected one as the target column address CA. Column select line driver 450 outputs a column select line signal CSLa for selecting (enabling) the bit line corresponding to the target column address CA.

[0084] When the access column address CADDR does not match the source column address SRCA, the selection circuit 440 may respond to a first matching signal MTH1 (e.g., having a first value) and output the access column address CADDR as the target column address CA. When the access column address CADDR matches the source column address SRCA, the selection circuit 440 may respond to a first matching signal MTH1 (e.g., having a second value) and output the destination column address DSCA as the target column address CA. Therefore, when the column address of the bit line connected to at least one faulty cell in memory block MB0 is stored in address storage table 420 as the source column address SRCA and used as fuse information, and the column address of the bit line connected to a regular cell that replaces the faulty cell in memory block MB0 is stored in address storage table 420 as the target column address DSCA and used as fuse information, the faulty cell in memory block MB0 is repaired and thus replaced by a regular cell in memory block MB. Alternatively, a regular cell may be replaced with a redundant cell in redundant block RMB, or a regular cell may be reassigned to a redundant cell in redundant block RMB.

[0085] In an exemplary embodiment, the selection circuit 440 may be configured as an address translation circuit to perform an XOR operation on some high-order bits of the access column address CADDR and bits of the target column address DSCA in response to the match signal MTH1. For example, when the access column address CADDR comprises 6 bits and the target column address DSCA comprises 3 bits, the address translation circuit performs an XOR operation on the higher 3 bits of the access column address CADDR and the 3 bits of the target column address DSCA to output the target column address in response to the match signal MTH1 having a logic high level.

[0086] Figure 3 The configuration of each unit repair controller in unit repair controllers 401b, 401c, and 401d can be broadly similar to... Figure 4A The configuration of the first unit repair controller 401a is the same.

[0087] Figure 4B It is shown Figure 4A The circuit diagram of an example of a column selection line driver in the first unit repair controller.

[0088] Reference Figure 4B The column select line driver 450 may include drive transistors 451, 452, 423 and 454, inverters 455 and 456, and NAND gate 457.

[0089] NAND gate 457 performs a NAND operation on the target column address CA and the enable master signal PCSLE. Driver transistor 451 has a source connected to the power supply voltage VDD, a gate receiving the output of NAND gate 457, and a drain connected to the first node NO1. Driver transistor 452 includes a drain connected to the first node NO1, a gate receiving the disable master signal PCSLD, and a source connected to driver transistor 453. Driver transistor 453 includes a drain connected to driver transistor 452, a gate receiving the output of NAND gate 457, and a source connected to ground voltage VSS.

[0090] Inverter 455 inverts the logic level at the first node NO1 to provide its output at the second node NO2, and inverter 456 inverts the logic level at the second node NO2 to output the column select line signal CSLa. The driving transistor 454 includes a drain connected to the first node NO1, a gate connected to the second node NO2, and a source connected to ground voltage VSS.

[0091] When the target column address CA is applied with a logic high level and the enable master signal PCSLE is applied with a logic high level, the output of NAND gate 457 becomes a logic low level. Therefore, drive transistor 451 turns on and drive transistor 453 turns off. Consequently, the first node NO1 becomes high, drive transistor 454 turns off, and inverter 456 outputs a column select line signal CSLa with a high level.

[0092] When the target column address CA is applied a logic low level and the enable master signal PCSLE is applied a logic high level, the output of NAND gate 457 becomes a logic high level. Therefore, drive transistor 451 is turned off, and drive transistors 452 and 453 are turned on. Consequently, inverter 456 outputs a column select line signal CSLa with a low level. The enable master signal PCSLE and the disable master signal PCSLD can be provided from the pre-decoder in the repair control circuit 400a or from the column decoder including the repair control circuit 400a. The pre-decoder can control the logic levels of the enable master signal PCSLE and the disable master signal PCSLD by referring to fuse information associated with the faulty cell and fuse information associated with the column select line information stored in the fuse circuit included in the redundancy repair controller 401e. Therefore, by controlling the enable master signal PCSLE and the disable master signal PCSLD, the repair control circuit 400a can select a first normal cell to replace the first faulty cell and can select a first redundant cell to replace the first normal cell.

[0093] Figure 5 This illustrates an exemplary embodiment. Figure 3 A block diagram of an example of a redundancy repair controller in a semiconductor memory device.

[0094] Reference Figure 5 The redundancy repair controller 401e includes a table pointer 460, a fuse circuit 480, and a redundant column select line (CSL) driver 470.

[0095] Table pointer 460 generates a repeatedly switching table pointer signal TPS in response to the sequentially changing column address CADDR. Fuse circuit 480 stores column select line information associated with each redundant bit line in the redundant bit lines of the redundant block RMB. Fuse circuit 480 also stores information about the memory blocks MB3, MB2, and MB0 that are repaired when column select line signals CSL0, CSL2, and CSL3 are enabled, respectively.

[0096] The redundant column select line driver 470 can respond to the table pointer signal TPS by referring to the column select line information in the fuse circuit 480 and output the redundant column select line signal CSLe to select some of the redundant bit lines.

[0097] Therefore, refer to Figures 3 to 5 The repair control circuit 400a repairs the first faulty cell using the first regular cell in the same memory block and replaces the first regular cell with the first redundant cell in the redundant block.

[0098] Figure 6A It is shown that, according to one embodiment, Figure 3 Repair operations performed in semiconductor memory devices.

[0099] exist Figure 6A In this context, it is assumed that the repair conditions for memory cell array 301 correspond to the situation shown by reference numeral 521. The repair status of memory cell array 301 can be determined by considering the location of the faulty cell in each of the memory blocks MB0 to MB3. The repair status of memory cell array 301 can be determined such that redundant resources for repairing faulty cells or replacing regular cells in memory blocks MB0, MB2, and MB3 do not overlap, and burst operation of semiconductor memory device 200a can be supported.

[0100] Reference Figures 3 to 6AWhen CSL0 operation 522 is specified in each of the memory blocks MB0 to MB3 via access column address CADDR, a first normal cell corresponding to CSL3 is selected instead of a faulty cell in memory block MB0 (e.g., column selection transistor 294d is turned on instead of column selection transistor 294a in memory block MB0), a normal cell corresponding to CSL0 is selected in memory block MB1, a normal cell corresponding to CSL2 is selected instead of a faulty cell in memory block MB2, and a redundant cell corresponding to CSL0 is selected instead of a faulty cell in memory block MB3. During CSL0 operation, a repair operation for repairing the faulty cell using the corresponding normal cell is performed in each of the memory blocks MB0 and MB2.

[0101] When CSL1 operation 523 is specified in each of memory blocks MB0 to MB3 via access column address CADDR, a regular cell corresponding to CSL1 is selected in each of memory blocks MB0 to MB3. When CSL2 operation 524 is specified in each of memory blocks MB0 to MB3 via access column address CADDR, a regular cell corresponding to CSL2 is selected in each of memory blocks MB0, MB1, and MB3, and a redundant cell corresponding to CSL2 is selected in redundant block RMB instead of a regular cell corresponding to CSL2 in memory block MB2.

[0102] When CSL3 operation 525 is specified in each of the memory blocks MB0 to MB3 via access column address CADDR, a regular cell corresponding to CSL3 is selected in each of the memory blocks MB1, MB2, and MB3, and a redundant cell corresponding to CSL3 in a redundant block is selected instead of a regular cell corresponding to CSL3 in memory block MB0. In this way, and in conjunction with the above... Figures 1 to 5The repair control circuit is configured to use a second column of regular memory cells in the first memory block (e.g., column 3 of MB0) as the target column for a first column of regular memory cells in the first memory block (e.g., column 0 of MB0), and to store data destined for the second column of regular memory cells in the first memory block in the first column of redundant memory cells in the redundant memory block (e.g., column 3 of RMB). The first column may be a column of the first memory block having at least one faulty memory cell. For read operations, the repair control circuit can be configured to use a second column of regular memory cells in the first memory block as the target read column for the first column of regular memory cells in the first memory block, and to use a first column of redundant memory cells in the redundant memory block as the target read column for the second column of regular memory cells in the first memory block. For write operations, the repair control circuit reassigns data destined for the first faulty column to the second column and reassigns data destined for the second column to the redundant block. A similar process can occur in memory block MB2. In this way, regular memory cells in the second column of the first memory block can be used to repair and thus replace the first memory cells in the first column of the first memory block.

[0103] As described above, the fuse circuit (480) can be part of the repair control circuit and can store the correlation between the column select lines of the redundant block and the column select lines of the memory blocks of the multiple memory blocks. Additionally, the address storage table can store source addresses and corresponding destination addresses for use by the repair control circuit when making the second column of regular memory cells of the first memory block a target column for the first column of regular memory cells of the first memory block. The repair control circuit also uses the source address and corresponding destination address when making the first column of redundant memory cells of the redundant memory block store data destined for the second column of regular memory cells of the first memory block. Figure 6A As shown in the examples and other examples, a first column of redundant memory cells in a first redundant block (e.g., column number 3 of RMB) may have the same relative position within the first redundant block as a second column of the first memory block (e.g., column number 3 of MB0) within the first memory block. Similarly, a second column of redundant memory cells in a first redundant block (e.g., column number 2 of RMB) may have the same relative position within the first redundant block as a second column of a second memory block (e.g., column number 2 of MB2, used to repair faulty cells in column 0 of MB2) within the second memory block. A second column of a first memory block (e.g., column 3 of MB0) may have a different relative position within the first memory block than a second column of a second memory block (e.g., column 2 of MB2).

[0104] Figure 6B Shown in Figure 2B Repair operations performed in semiconductor memory devices.

[0105] Reference Figure 2B and Figure 6B The repair procedure 521a for memory cell array 301 is as follows: Memory block MB0 includes faulty cells associated with column select line signal CSL1. Faulty cells in memory block MB0 associated with the first column of memory block MB0 are repaired using first normal cells by enabling column select line signal CSL3 associated with the second column of memory block MB0 instead of column select line signal CSL1, as shown by reference numeral 511a. The first normal cells in memory block MB0 are replaced with second normal cells in memory block MB1, which is different from MB0, as shown by reference numeral 512a. Furthermore, the second normal cells in memory block MB1 are replaced with first redundant cells in redundant block RMB, as shown by reference numerals 513a, 514a, and 515a. The repair control circuit 400a repairs a first faulty cell in the first memory block MB0 using a first normal cell in the first memory block MB0, replaces the first normal cell with a second normal cell in a second memory block MB1 (different from the first memory block MB0), replaces the second normal cell with a third normal cell in a third memory block MB2 (different from the second memory block MB1), replaces the third normal cell with a fourth normal cell in a fourth memory block MB3 (different from the third memory block MB2), and replaces the fourth normal cell with a first redundant cell in the redundant block RMB. The first normal cell, second normal cell, third normal cell, fourth normal cell, and first redundant cell may have the same column select line address. In this way, the first normal cell (e.g., in column 3 of the redundant block RMB) is replaced by a first redundant memory cell (e.g., in column 3 of the redundant block RMB) through a shift operation. For example, the shift operation may include: replacing a first regular cell (e.g., in column 3 of memory block MB0) with a second regular memory cell in a first column of a second memory block of the memory device (e.g., in column 3 of memory block MB1), then replacing a column of memory cells in each memory block (instead of the last memory block of the plurality of memory blocks) with a column of memory cells from an adjacent memory block, and replacing a column in the last memory block of the plurality of memory blocks with the first column of redundant memory cells of a redundant block.

[0106] When CSL0 operation 526 is specified in each of memory blocks MB0 to MB3 and redundant blocks RMB via access column address CADDR, a regular cell corresponding to CSL0 is selected in each of memory blocks MB0 to MB3. When CSL1 operation 527 is specified in each of memory blocks MB0 to MB3 and redundant blocks RMB via access column address CADDR, a first regular cell corresponding to CSL3 is selected in memory block MB0 instead of a first fault cell corresponding to CSL1, and a regular cell corresponding to CSL1 is selected in each of memory blocks MB1 to MB3.

[0107] When CSL1 operation 528 is specified in each of memory blocks MB0 to MB3 and redundant block RMB via access column address CADDR, the second regular cell corresponding to CSL3 in memory block MB1 is selected instead of the first regular cell corresponding to CSL3 in memory block MB0; the third regular cell corresponding to CSL3 in memory block MB2 is selected instead of the second regular cell corresponding to CSL3 in memory block MB1; the fourth regular cell corresponding to CSL3 in memory block MB3 is selected instead of the third regular cell corresponding to CSL3 in memory block MB2; and the first redundant cell corresponding to CSL3 in redundant block RMB is selected instead of the fourth regular cell corresponding to CSL3 in memory block MB3. Therefore, semiconductor memory device 200a can use redundant resources in redundant block RMB that support data input / output with a size corresponding to the burst length.

[0108] Figure 6C Showing when execution Figure 6A Data input / output during repair operations.

[0109] Reference Figure 6C When the repair status of memory cell array 301 corresponds to the status indicated by reference numeral 521, data selected from memory blocks MB0 to MB3 and redundant block RMB by column selection circuits 293a to 293e and selection circuits 2911 to 2915 in I / O gate circuit 290a is provided to data I / O buffer 296 in units of burst lengths BL0 to BL3. That is, selection circuit 2911 can select the output of one of column selection circuits 293a and 293e, selection circuit 2912 can select the output of one of column selection circuits 293b and 293e, selection circuit 2913 can select the output of one of column selection circuits 293c and 293e, and selection circuit 2914 can select the output of one of column selection circuits 293d and 293e.

[0110] In CSL0 operation, in response to the signal {0, 0, 0, 1} from selection circuit 2915, selection circuit 2911 can select data output from memory block MB0, selection circuit 2912 can select data output from memory block MB1, selection circuit 2913 can select data output from memory block MB2, and selection circuit 2914 can select data output from redundant block RMB.

[0111] Figure 6D Showing when execution Figure 6B Data input / output during repair operations.

[0112] Reference Figure 6D When the repair status of the memory cell array 301 corresponds to the status indicated by reference numeral 521a, the data selected from memory blocks MB0 to MB3 and redundant blocks RMB by column selection circuits 293a to 293e and selection circuits 2916 to 2919 in the I / O gating circuit 290a is provided to the data I / O buffer 296 in units of burst lengths BL0 to BL3. That is, selection circuit 2916 can select the output of one of the adjacent column selection circuits 293a and 293b, selection circuit 2917 can select the output of one of the adjacent column selection circuits 293b and 293c, selection circuit 2918 can select the output of one of the adjacent column selection circuits 293c and 293d, and selection circuit 2919 can select the output of one of the adjacent column selection circuits 293d and 293e.

[0113] In CSL4 operation, in response to the signal {1, 1, 1, 1} from selection circuit 2915, selection circuit 2916 can select data output from memory block MB1, selection circuit 2917 can select data output from memory block MB2, selection circuit 2918 can select data output from memory block MB3, and selection circuit 2919 can select data output from redundant block RMB.

[0114] Figure 7 Show Figure 4A The first unit in the example repairs the address storage table in the controller.

[0115] Reference Figure 7Address storage table 420 includes a first memory cell 421, a second memory cell 423, and a sensing unit 425. The first memory cell 421 may be a circuit and stores the source column address SRCA to be repaired. The second memory cell 423 may be a circuit and stores the target column address DSCA for replacing the source column address SRCA. Address storage table 420 may be implemented as an antifuse array or content-addressable memory (CAM). Sensing unit 425, in response to a pointer signal TPS, outputs the source column address SRCA and the target column address DSCA stored in the locations (indicated by the pointer signal TPS) in the first memory cell 421 and the second memory cell 423. Figure 7 In this configuration, address storage table 420 stores column address CADDR1 associated with CSL0 and column address CADDR4 associated with CSL3 as source column addresses SRCA, and stores column address CADDR4 used to replace column address CADDR1 and redundant column address RCADDR4 used to replace column address CADDR4 as target column addresses DSCA. In this way, the address (CADDR1) of the first regular memory cell in the first column of the first memory block is replaced with the target address, which is the address (CADDR4) of the second regular memory cell in the second column of the first memory block, and the address (CADDR4) of the second regular memory cell in the second column of the first memory block is replaced with the address (RCADDR4) of the first redundant memory cell in the redundant block of the memory device, and is reassigned to the address (RCADDR4) of the first redundant memory cell in the redundant block of the memory device. It should be noted that in some embodiments, particularly when the redundant block RMB has the same memory cells as memory blocks MB0 to MB3, the address storage table does not need to store the reassignment of the second regular memory cell to the first redundant memory cell. Methods such as... Figure 5 The fuse circuit 480 is used to complete this redistribution.

[0116] Figure 8 This illustrates an exemplary embodiment. Figure 7 A diagram illustrating an example of an address storage table.

[0117] Reference Figure 8 The address storage table 420 can be implemented by an array of antifuse 422s. Each antifuse 422 has electrical characteristics opposite to those of a fuse element. The antifuse 422 is a resistive fuse element, wherein it has a relatively high resistance value when unprogrammed and a relatively low resistance value when programmed. The address storage table 420 can store the source column address SRCA and the destination column address DSCA by selectively programming the antifuse 422s.

[0118] Sensing unit 425 includes a first sub-sensing unit 4251 and a second sub-sensing unit 4252, respectively connected to the first memory unit 421 and the second memory unit 423. Each sub-sensing unit in the first sub-sensing unit 4251 and the second sub-sensing unit 4252 can be implemented using an NMOS transistor 426. Therefore, in response to the pointer signal TPS, sensing unit 425 provides the source column address SRCA to the column address comparator 430 and the target column address DSCA to the selection circuit 440.

[0119] Figures 9A to 9C This is a diagram illustrating a method of replacing a faulty cell with a regular cell in the same memory block and then replacing that regular cell with a redundant cell.

[0120] exist Figures 9A to 9C In this memory block, MB0 includes memory cells connected to word lines WL1 to WLu and bit lines BTL1 to BTLv, and the redundant block RMB includes redundant cells connected to word lines WL1 to WLu and redundant bit lines RBTL1 to RBTLv. In some embodiments, the number of redundant bit lines in the redundant block RMB is the same as the number of bit lines in each memory block (such as MB0) in a conventional memory block. However, in other embodiments, the number of redundant bit lines in the redundant block RMB is less than or greater than the number of bit lines in each memory block in a conventional memory block.

[0121] Figure 9A This is a diagram used to describe the substitutions between bit lines. For example, when a fault occurs in a memory cell connected to word line WL1 and bit line BTL1, bit line BTL1 is replaced with bit line BTL4, and bit line BTL4 can be replaced with redundant bit line RBTL4.

[0122] Figure 9B This is a diagram used to describe the replacement between multiple parts (e.g., multiple segments) of a bit line. A single bit line may be divided into two or more segments, each segment connected to at least one memory cell. For example, when a fault occurs in a memory cell connected to word line WL1 and bit line BTL1, a segment in bit line BTL1 is replaced with a segment in bit line BTL4, and said segment in bit line BTL4 may be replaced with a segment in redundant bit line RBTL4.

[0123] Figure 9C This is a diagram used to describe the replacement between memory cells. For example, when a fault occurs in a memory cell connected to word line WL1 and bit line BTL1, the faulty memory cell is replaced with a memory cell connected to bit line BTL4, and the memory cell connected to bit line BTL4 can be replaced with a memory cell connected to redundant bit line RBTL4.

[0124] Figure 10 This is a flowchart illustrating a method for operating a semiconductor memory device according to an exemplary embodiment.

[0125] Reference Figures 2A to 10 In a method of operating a semiconductor memory device comprising a memory cell array including multiple memory blocks and at least one redundant block, a repair control circuit 400a repairs a first faulty cell in a first memory block using a first normal cell in a first memory block (S100). Before repairing the first faulty cell in the first memory block using a first normal cell in the first memory block, the repair control circuit 400a may determine whether an access column address matches a first column address that specifies a bit line connected to the first faulty cell. When the access column address matches the first column address (source column address), the repair control circuit 400a performs the repair operation.

[0126] The first faulty cell and the first normal cell in the first memory block may have different column select line addresses. For example, the first faulty cell and the first normal cell in the first memory block are connected to different bit lines selected by different column select line (CSL) signals. The first faulty cell and the first normal cell in the first memory block may be connected to the same I / O circuit. The repair control circuit 400a replaces the first normal cell in the first memory block with the first redundant cell in the redundant block (S200). The first normal cell and the first redundant cell may have the same column select line address. The first normal cell and the first redundant cell may be connected to different I / O circuits respectively.

[0127] Figure 11 This illustrates an exemplary embodiment. Figure 1 A block diagram of another example of a semiconductor memory device in a memory system.

[0128] Reference Figure 11 The semiconductor memory device 200b includes control logic circuitry 210, address register 220, memory bank control logic 230, refresh counter 245, row address selection circuit (RAMUX) 240, column address (CA) latch 250, memory bank row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, I / O gate circuitry 290, and data I / O buffer 295.

[0129] In an exemplary embodiment, the semiconductor memory device 200b may include an error correction code (ECC) engine 280.

[0130] The control logic circuit 210, the repair control circuit 400, and the timing control circuit 500 can form the access control circuit 205.

[0131] The memory cell array 300 includes a first memory cell array 310 to an eighth memory cell array 380. The memory cell row decoder 260 includes first memory cell row decoders 260a to 260h respectively connected to the first memory cell array 310 to the eighth memory cell array 380; the column decoder 270 includes first memory cell column decoders 270a to 270h respectively connected to the first memory cell array 310 to the eighth memory cell array 380; and the sense amplifier unit 285 includes first memory cell sense amplifiers 285a to 285h respectively connected to the first memory cell array 310 to the eighth memory cell array 380. First memory bank arrays 310 to 380, first memory bank row decoders 260a to 260h, first memory bank column decoders 270a to 270h, and first memory bank sense amplifiers 285a to 285h can form first to eighth memory banks. Each memory bank array in the first memory bank arrays 310 to 380 includes multiple memory cells MC formed at the intersections of multiple word lines WL and multiple bit lines BTL.

[0132] Address register 220 receives address ADDR from memory controller 100, where address ADDR includes bank address BANK_ADDR, row address RADDR, and column address CADDR. Address register 220 provides the received bank address BANK_ADDR to bank control logic 230, the received row address RADDR to row address selection circuit 240, and the received column address CADDR to column address latch 250.

[0133] The memory bank control logic 230 generates a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, one of the first memory bank row decoders 260a to the eighth memory bank row decoder 260h corresponding to the memory bank address BANK_ADDR is activated, and in response to the memory bank control signal, one of the first memory bank column decoders 270a to the eighth memory bank column decoder 270h corresponding to the memory bank address BANK_ADDR is activated.

[0134] The row address selection circuit 240 receives the row address RADDR from the address register 220 and the refresh row address REF_ADDR from the refresh counter 245. The row address selection circuit 240 selectively outputs either the row address RADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address selection circuit 240 is applied to the first memory bank row decoders 260a to the eighth memory bank row decoders 260h.

[0135] One of the bank row decoders 260a to 260h, activated by the bank control logic 230, decodes the row address RA output from the row address selection circuit 240 and activates the word line corresponding to the row address RA. For example, the activated bank row decoder applies a word line drive voltage to the word line corresponding to the row address RA. Additionally, the activated bank row decoder activates the spare word line corresponding to the spare row address SRA output from the repair control circuit 400, and simultaneously activates the word line corresponding to the row address RA.

[0136] Column address latch 250 receives column address CADDR from address register 220 and temporarily stores the received column address CADDR. In some embodiments, in burst mode, column address latch 250 generates a column address incremented from the received column address CADDR. Column address latch 250 applies the temporarily stored or generated column address to first bank column decoders 270a to eighth bank column decoders 270h.

[0137] An activated memory bank column decoder among the first to eighth memory bank column decoders 270a and 270h activates a sense amplifier corresponding to the memory bank address BANK_ADDR and column address CADDR via I / O gating circuitry 290. Each of the first to eighth memory bank column decoders 270a and 270h may include repair control circuitry, and the repair control circuitry included in an activated memory bank column decoder among the first to eighth memory bank column decoders 270a and 270h may repair a faulty cell in the same memory block using a first normal cell in at least one memory block of the corresponding memory bank array, and may replace the first normal cell with a first redundant cell in a redundant block of the corresponding memory bank array.

[0138] I / O gate circuit 290 includes circuitry for gating input / output data, and further includes a read data latch for storing data output from the first memory array 310 to the eighth memory array 380, and a write driver for writing data to the first memory array 310 to the eighth memory array 380.

[0139] Data read from one of the memory arrays 310 to 380 is sensed by a sense amplifier connected to said memory array (from which data will be read) and stored in a read data latch. The data stored in the read data latch can be provided to the memory controller 100 via a data I / O buffer 295. Data to be written to one of the memory arrays 310 to 380 can be written to that memory array by a write driver.

[0140] When the semiconductor memory device 200b includes an ECC engine 280, the ECC engine 280 can perform ECC encoding on the data to be written to provide codewords to the I / O gate circuit 290, and can perform ECC decoding on the read codewords to provide corrected data to the data I / O buffer 295.

[0141] The data I / O buffer 295 can provide data DQ from the memory controller 100 to the ECC engine 280 during write operations of the semiconductor memory device 200b based on the clock signal CLK, and can also provide data DQ from the ECC engine 280 to the memory controller 100 during read operations of the semiconductor memory device 200b.

[0142] Control logic circuit 210 can control the control operations of semiconductor memory device 200b. For example, control logic circuit 210 can generate control signals for semiconductor memory device 200b to perform write or read operations. Control logic circuit 210 includes command decoder 211 and mode register 212, wherein command decoder 211 decodes commands (CMD) received from memory controller 100, and mode register 212 sets the operating mode of semiconductor memory device 200b.

[0143] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding the write enable signal, row address strobe signal, column address strobe signal, chip select signal, etc. The control logic circuit 210 provides the first control signal CTL1 to the I / O gate circuit 290 and the second control signal CTL2 to the ECC engine 280.

[0144] Figure 12 Show Figure 11 An example of a first memory bank array in a semiconductor memory device.

[0145] Reference Figure 12The first memory bank array 310 includes a conventional cell array (NCA) and a redundant cell array (RCA). The conventional cell array (NCA) includes multiple word lines WL1 to WLm (m is a natural number greater than 2), multiple bit lines BTL1 to BTLn (n is a natural number greater than 2), and multiple memory cells (MCs), wherein the multiple memory cells (MCs) are arranged at the intersections between word lines WL1 to WLm and bit lines BTL1 to BTLn. The redundant cell array (RCA) includes multiple redundant cells (RMCs), wherein the multiple redundant cells (RMCs) are arranged at the intersections between word lines WL1 to WLm and multiple redundant bit lines RBTL1 to RBTLt.

[0146] Figure 13 This illustrates an exemplary embodiment. Figure 11 A block diagram of the repair control circuitry included in each bank column decoder of a semiconductor memory device.

[0147] Reference Figure 13 The repair control circuit 400b may include a fault address storage circuit 410, a row address comparator 415, and a cell repair controller 402a.

[0148] Although the repair control circuit 400b is shown to include a unit repair controller 402a, the repair control circuit 400b may include multiple unit repair controllers and redundant repair controllers, such as... Figure 15 As shown.

[0149] The fault address storage circuit 410 stores the row address information FRAI and column address information FCAI of at least one defective cell (i.e., faulty cell) appearing in the conventional cell array of the memory cell array 300. The fault address storage circuit 410 includes a non-volatile memory device for storing the location information of at least one defective cell. For example, the fault address storage circuit 410 may include an antifuse for storing the location information of at least one defective cell. The location information of the at least one defective cell stored in the fault address storage circuit 410 can be updated.

[0150] For example, the location information of defective cells appearing in a conventional cell array due to continuous use of the semiconductor memory device 200b can be updated in the fault address storage circuit 410. Additionally, the location information of additional defective cells appearing after the semiconductor memory device 200b is packaged can be updated in the fault address storage circuit 410. This location information of defective cells can be obtained by testing whether a fault bit appears in the semiconductor memory device 200b. Testing can be performed before the semiconductor memory device 200b is packaged (i.e., at the wafer level) or after the semiconductor memory device 200b is packaged. According to an exemplary embodiment, post-package repair (PPR) can be performed using the repair control circuit 400.

[0151] The location information of the at least one faulty unit may be the row address information FRAI and the column address information FCAI of the at least one faulty unit.

[0152] Row address comparator 415 stores row address information FRAI received from fault address storage circuit 410. Row address comparator 415 can receive row address information FRAI from fault address storage circuit 410 simultaneously with or during a desired time period after the semiconductor memory device 200b is driven. Row address comparator 415 receives the row address RADDR of access address ADDR, compares row address RADDR with row address information FRAI, and outputs a row match signal RM when row address RADDR matches row address information FRAI.

[0153] The unit repair controller 402a may include a table pointer 405, an address storage table 420b, a column address comparator 430, an AND gate 435, a selection circuit 440, and a column selection line driver 450.

[0154] Address storage table 420b can sequentially store the column address information FCAI of the faulty cell and the column address information of the first normal cell used to repair the faulty cell as the source column address SRCA, and can sequentially store the column address information of the first normal cell and the column address information of the second normal cell used to repair the first normal cell as the target column address DSCA. Table pointer 405 can generate a repeatedly switching table pointer signal TPS to address storage table 420b in response to the sequentially changing access column address CADDR. Address storage table 420b can output the source column address SRCA and the target column address DSCA corresponding to the source column address SRCA in response to the table pointer signal TPS.

[0155] Column address comparator 430 compares the access column address CADDR with the source column address SRCA from address memory table 420b and outputs a first match signal MTH1 indicating the comparison result. AND gate 435 performs an AND operation on the row match signal RM and the first match signal MTH1 to output a second match signal MTH2. Selection circuit 440, in response to the second match signal MTH2, selects one of the target column address DSCA and the access column address CADDR from address memory table 420b, outputting the selected one as the target column address CA. Column select line driver 450 outputs a column select line signal CSLa for selecting (enabling) the bit line corresponding to the target column address CA.

[0156] For example, when the row match signal RM is low or when the access column address CADDR does not match the source column address SRCA, the selection circuit 440 may respond to the second match signal MTH2 and output the access column address CADDR as the target column address CA. For example, when the row match signal RM is high or when the access column address CADDR matches the source column address SRCA, the selection circuit 440 may respond to the second match signal MTH2 and output the destination column address DSCA as the target column address CA.

[0157] Figure 14 Show Figure 13 An example of a fault address storage circuit in a repair control circuit.

[0158] Reference Figure 14 The fault address storage circuit 410 includes an antifuse array 411, a control unit 412, a sensing unit 413, and a register unit 414.

[0159] The antifuse array 411 includes p×q antifuses (AFs) connected to the intersections of p rows and q columns. The antifuse array 411 includes p word lines AWL1 to AWLp and q bit lines ABL1 to ABLq, wherein the p word lines AWL1 to AWLp are used to access the antifuses (AFs) arranged on the p rows, and the q bit lines ABL1 to ABLq are arranged to correspond to the q columns in order to transmit information read from the antifuses (AFs).

[0160] The control unit 412 programs the location information of the faulty cell in the antifuse array 411, or reads the location information of the faulty cell from the antifuse array 411. The sensing unit 413 senses and amplifies the location information of the faulty cell received from the antifuse array 411, and outputs the amplified result. The register unit 414 temporarily stores the location information of the faulty cell received from the sensing unit 413. The register unit 414 outputs the row address information FRAI and column address information FCAI of the faulty cell to the row address comparator 420 and the address storage table 420b, respectively.

[0161] Figure 15 Show Figure 11 It is part of a semiconductor memory device.

[0162] exist Figure 15 The diagram shows a first memory array 310, an I / O gate circuit 290, a column decoder 270a, and a data I / O buffer 295.

[0163] Reference Figure 15 The first memory array 310 includes a conventional cell array (NCA) and a redundant cell array (RCA). The conventional cell array (NCA) includes multiple memory blocks MB0 to MB15 (i.e., 311 to 313), and the redundant cell array (RCA) includes at least one redundant block 314. Memory blocks 311 to 313 are memory blocks that determine the memory capacity of the semiconductor memory device 200b. Redundant block 314 is used for redundancy repair.

[0164] In each of the memory blocks 311 to 313, multiple memory cells are arranged in rows and columns. In the redundant block 314, multiple redundant cells are arranged in rows and columns.

[0165] I / O gating circuit 290 includes multiple I / O circuits 292a to 292d and multiple column select circuits 296a to 296d, and the column select circuits 296a to 296d can connect one of the I / O circuits 292a to 292d to a corresponding one of the memory blocks 311, 312, and 313 and the redundant block 314. Each column select circuit 296a to 296d may include multiple column select transistors 297a to 297h, and the multiple column select transistors 297a to 297h respectively respond to column select line signals CSLa to CSLg to connect multiple bit lines or one bit line in the corresponding memory block or redundant block 314 to the corresponding I / O circuit. The multiple I / O circuits 292a to 292d can be connected to the data I / O buffer 296 via a data line (not shown) in response to a first control signal CTL1 from the control logic circuit 210. For example, when a column select line signal is applied to column select transistor 297a, one or more bit lines connected to column select transistor 297a in each of memory blocks 311 to 313 and redundant blocks can be selected simultaneously. When a column select line signal is applied to column select transistor 297h, one or more bit lines connected to column select transistor 297h in each of memory blocks 311 to 313 and redundant blocks can be selected simultaneously.

[0166] The column decoder 270a may include a pre-decoder (not shown), multiple cell repair controllers 402a to 402c, and a redundancy repair controller 402d. The pre-decoder may decode the access column address CADDR to typically provide the decoded column address to the multiple cell repair controllers 402a to 402c and the redundancy repair controller 402d.

[0167] Cell repair controllers 402a to 402c and redundancy repair controller 402d can typically receive access column address CADDR or decoded column address, and can provide column select line signals CSLa to CSLg applied to memory blocks 311 to 313 and redundancy block 314 for the corresponding column select circuits 296a to 296d.

[0168] The repair control circuit 400b repairs at least one faulty cell in at least one of the memory blocks 311 to 313 to a first normal cell in the same memory block, replaces the first normal cell with a second normal cell in the same memory block, and replaces the second normal cell with a first redundant cell in the redundant block 314. Therefore, the repair control circuit 400b can utilize the redundant resources in the redundant block 314 with substantially maximum efficiency.

[0169] Figure 16A Shown in Figure 15 Repair operations performed in semiconductor memory devices.

[0170] Reference Figure 16A The repair process 541 of the first memory array 310 is as follows. Each memory block in memory blocks MB0 and MB15 includes a faulty cell on a bit line selected by column select line signal CSL0. As shown by reference numeral 531, the faulty cell in memory block MB0 is repaired with a first normal cell in memory block MB0 by enabling column select line signal CSL3 instead of column select line signal CSL0. As shown by reference numeral 532, the first normal cell in memory block MB0 is replaced by enabling column select line signal CSL7 instead of column select line signal CSL3. And as shown by reference numeral 533, the second normal cell in memory block MB0 is replaced with a corresponding redundant cell in redundant block 314. In addition, the faulty cell in memory block MB15 associated with CSL0 is repaired with a corresponding redundant cell in redundant block 314, as shown by reference numeral 534.

[0171] When CSL0 operation 542 is specified in each of the memory blocks 311 to 314 via access column address CADDR, the first normal cell corresponding to CSL3 is selected instead of the faulty cell in memory block MB0, the normal cell corresponding to CSL0 is selected in memory block MB1, and the redundant cell corresponding to CSL0 is selected instead of the faulty cell in memory block MB15.

[0172] When CSL3 operation 543 is specified in each of the memory blocks 311 to 314 by accessing the column address CADDR, the second regular cell corresponding to CSL7 is selected instead of the first regular cell in memory block MB0, the regular cell corresponding to CSL3 is selected in memory block MB1, and the regular cell corresponding to CSL3 is selected in memory block MB15.

[0173] When CSL7 operation 544 is specified in each of the memory blocks 311 to 314 by accessing the column address CADDR, the corresponding redundant cell corresponding to CSL7 is selected instead of the regular cell corresponding to CSL7 in memory block MB0, the regular cell corresponding to CSL7 is selected in memory block MB1, and the regular cell corresponding to CSL7 is selected in memory block MB15.

[0174] like Figure 16A As can be seen, with Figure 6A Similarly, the repair control circuit is configured to: replace a first regular memory cell in a first column of a first memory block (e.g., a cell in column 3 of memory block MB0) with a second regular memory cell in a second column of the first memory block (e.g., a cell in column 7 of memory block MB0), and replace the second regular memory cell in the second column of the first memory block with a first redundant memory cell in a first column of redundant memory cells of a first redundant block (e.g., column 7 of redundant block RMB). In this example, the step of replacing the second regular memory cell with the first redundant memory cell includes: causing the first redundant memory cell to store data destined for the second regular memory cell. Figure 16A As further shown, the repair control circuit is also configured to repair a faulty memory cell in another column of the first memory block (e.g., column number 0 in memory block MB0) using a first conventional memory cell (e.g., a cell in column number 3 of memory block MB0).

[0175] Figure 16B Show Figure 15 Another example of a first memory bank array in a semiconductor memory device.

[0176] exist Figure 16BIn the first memory array 310b, the size of each memory block in memory blocks MB0 to MB3 is larger than the size of the redundant block RMB2; however, in Figure 16A In the first memory array 310, the size of each memory block in memory blocks MB0 to MB15 is the same as the size of the redundant block RMB. Figure 16B In the first memory array 310b, the size of each memory block in memory blocks MB0 to MB3 is twice the size of the redundant block RMB2.

[0177] exist Figure 16B In this configuration, each memory block from MB0 to MB3 can be divided into upper blocks corresponding to CSL0 to CSL3 and lower blocks corresponding to CSL4 to CSL7 based on the most significant bit (MSB) of the access column address. When a faulty cell is... Figure 16B When distributed in that manner, the burst operation of the semiconductor memory device 200b can be supported by determining the repair status so that the faulty cells in memory blocks MB0, MB1 and MB2 and the redundant resources in the redundant block RMB do not overlap.

[0178] In other words, the fuse information FI_MB1 associated with memory block MB1 is set to select the normal cell corresponding to CSL5 instead of the fault cell corresponding to CSL4, and the fuse information FI_MB2 associated with memory block MB2 is set to select the normal cell corresponding to CSL2 instead of the fault cell corresponding to CSL0. Additionally, when CSL0 and CSL4 are specified in each of the memory blocks MB0 to MB3, the redundant cell corresponding to CSL0 is selected in the redundant block RMB2. The fuse circuit 480b can store fuse information MB0_L, MB1_H, and MB2_L for CSL0 operation, CSL1 operation, and CSL2 operation, respectively.

[0179] Figure 16C Show Figure 15 Another example of a first memory bank array in a semiconductor memory device.

[0180] exist Figure 16C In the first memory array 310c, the size of each memory block in memory blocks MB0 to MB7 is the same as the size of the redundant block RMB3.

[0181] Reference Figure 16C The first memory array 310c may include multiple memory blocks MB0 to MB7 and a redundant block RMB3.

[0182] Memory block MB0 includes a first faulty cell and a second faulty cell on the bit lines selected by column select line signals CSL0 and CSL1, and redundant block RMB3 includes a first faulty redundant cell and a second faulty redundant cell on the bit lines selected by column select line signals CSL0 and CSL1. The first faulty cell in memory block MB0 is repaired by a first normal cell in memory block MB0 by enabling column select line signal CSL2 instead of column select line signal CSL0. The first normal cell in memory block MB0 is sequentially replaced by a second normal cell in each of memory blocks MB1 to MB7 and a third redundant cell in redundant block RMB3. The second faulty cell in memory block MB0 associated with CSL1 is sequentially replaced by a second normal cell in each of memory blocks MB1 to MB7 and a second redundant cell in redundant block RMB3, and because the second redundant cell in redundant block RMB3 is a faulty redundant cell, it is replaced by a fourth redundant cell in redundant block RMB3.

[0183] exist Figure 16C In this context, burst operation of the semiconductor memory device 200b can be supported by determining the repair conditions for repairing faulty cells in memory block MB0, ensuring that redundant resources in RMB3 do not overlap.

[0184] In other words, the fuse information FI_MB0 associated with memory block MB0 is set to select the normal cell corresponding to CSL2 instead of the fault cell corresponding to CSL0, and the fuse information FI_MB3 associated with redundant cell RMB3 is set to select the redundant cell corresponding to CSL3 instead of the faulty redundant cell corresponding to CSL1. The fuse circuit 480c can store fuse information for CSL1 and CSL2 respectively.

[0185] Figure 17A Show Figure 13 An example of repairing the address storage table in the control circuit.

[0186] Reference Figure 17A Address storage table 420b includes a first memory cell 421b, a second memory cell 423b, and a sensing unit 425b. The first memory cell 421b stores the source column address SRCA to be repaired, and the second memory cell 423b stores the target column address DSCA to replace the source column address SRCA. Address storage table 420b can be implemented as an antifuse array or content-addressable memory (CAM). Sensing unit 425b, in response to a pointer signal TPS, outputs the source column address SRCA and the target column address DSCA stored in the first memory cell 421b and the second memory cell 423b at the locations indicated by the pointer signal TPS. Figure 17AIn the address storage table 420b, the column address CADDR1 associated with CSL0, the column address CADDR4 associated with CSL3, and the column address CADDR8 associated with CSL7 are stored as source column addresses SRCA, and the column address CADDR4 used to replace column address CADDR1, the column address CADDR8 used to replace column address CADDR4, and the redundant column address RCADDR4 used to replace column address CADDR8 are stored as target column addresses DSCA.

[0187] Figure 17B An example of reducing several fuses associated with a repair operation is shown according to an example embodiment.

[0188] Reference Figure 17B The Master Fuse Information (MFB) can include two bits, and the MFB can have one of "00", "01", "10", and "11". Figure 17B In this process, the main fuse information (MFB) is merged with the faulty unit's fuse information (FFI).

[0189] exist Figure 17B In this configuration, 6 bits of fuse information can specify 48 addresses. For example, the main fuse information MFB "00" can indicate that no repair operation should be applied, and the main fuse information MFBs "01", "10", and "11" can be used to specify the faulty cell. Additionally, the 4-bit fuse information for the faulty cell can specify 16 addresses. That is, each of the main fuse information MFBs "01", "10", and "11" combined with the faulty cell's fuse information FFI can specify 16 addresses, and the 6 bits of fuse information can specify 48 addresses. When 34 of the 48 addresses are used, one of the 6 bits of fuse information can be reduced.

[0190] Figure 17C Another example of reducing several fuses associated with a repair operation according to an example embodiment is shown.

[0191] Reference Figure 17C It can merge one of the source information SR and the target information DS with the main fuse information MFB. Figure 17C This illustrates merging the target information DS with the main fuse information MFB, generating merged information MFB&DS. The merged information MFB&DS consists of 3 bits, and the source fuse information SRFI consists of 6 bits. Figure 17C In this configuration, one bit associated with a memory block (MB) is shared by two adjacent column blocks, which can reduce the number of fuses.

[0192] Figure 17D Implementation details Figure 17C An example of an example.

[0193] Reference Figure 17D The main fuse information MFB' merged with the target information (and) Figure 17C The merge information MFB&DS in the main fuse information (correspondingly) may include three-bit patterns S[9]S[8]S[7]. When pattern S[9]S[8]S[7] has a value of "000", it indicates that no repair operation is used. When pattern S[9]S[8]S[7] has a value other than "000", the main fuse information MFB' may include multiple bits of the target information or a portion of multiple bits used to specify the address of a regular cell. Figure 17D As shown, the column address CADDR, which is a regular unit of the target information, can be obtained by selectively flipping the high bits CA9, CA8, and CA7 of the source information.

[0194] Figure 17E An example of a cell repair controller according to an example embodiment is shown.

[0195] Reference Figure 17E The unit repair controller 501 may include a column address comparator 510, a conventional decoder 520, a target decoder 530, a selection circuit (MUX) 540, and a column selection line (CSL) driver 550.

[0196] Column address comparator 510 will access column address CADDR and from Figure 13 The source column address SRCA output from address storage table 420b is compared, and a hit signal HIT1 indicating the comparison result between the access column address CADDR and the source column address SRCA is output. The conventional decoder 520 decodes the access column address CADDR in response to the column selection master signal PCSLM to output the first decoded column address DCADDR.

[0197] The target decoder 530 responds to the column selection master signal PCSLM to decode the target column address DSCA output from the address storage table 420b to output the second decoded column address DDCSA.

[0198] In response to the hit signal HIT, selection circuit 540 selects one of the first decoded column address DCADDR and the second decoded column address DDCSA, so that the selected output is the decoded target column address DCA. Column select line driver 550 receives the decoded target column address DCA and outputs column select line signal CSL to select (activate) the bit line corresponding to the decoded target column address DCA.

[0199] Figure 17F Another example of a cell repair controller according to an example embodiment is shown.

[0200] Reference Figure 17FThe unit repair controller 502 may include a column address comparator 515, an inverter 517, a selection circuit (MUX) 545, a conventional decoder 525, and a column selection line (CSL) driver 555.

[0201] Column address comparator 515 compares the access column address CADDR with the source column address SRCA and the additional bit AB1, and outputs a hit signal HIT21 indicating the result of the comparison between the access column address CADDR and the source column address SRCA and the additional bit AB1. The additional bit AB1 may include 4 bits.

[0202] The three bits in the additional AB1 can be equivalent to the reference as follows Figure 17C The description includes the main fuse information MFB merged with the target information DS, and one bit in the additional bit AB1 can be a bit shared by two adjacent column blocks.

[0203] Accessing the column address CADDR may include the high-order CADDR_MSB and the low-order CADDR_LSB. Inverter 517 inverts the high-order CADDR_MSB of the access column address CADDR. In response to the hit signal HIT21, selection circuit 545 outputs one of the following: the output of inverter 517, and the high-order CADDR_MSB of the access column address CADDR.

[0204] The conventional decoder 525, in response to the column select master signal PCSLM, decodes the output of the select circuit 545 and the low-order CADDR_LSB of the access column address CADDR to output the decoded target column address DCA. The column select line driver 555 receives the decoded target column address DCA and outputs the column select line signal CSL to select (activate) the bit line corresponding to the decoded target column address DCA.

[0205] The high-order CADDR_MSB of the access column address CADDR can be encoded as follows: Figure 17D As shown.

[0206] When a faulty cell in a memory block is repaired using a regular cell in the same memory block, it can be used Figure 17E Unit repair controller 501 and Figure 17F Unit repair controller 502.

[0207] Figure 17G Another example of a cell repair controller according to an example embodiment is shown.

[0208] Reference Figure 17G The unit repair controller 503 may include a column address comparator 516, an inverter 517, a selection circuit (MUX) 545, a conventional decoder 525, and a column selection line (CSL) driver 555.

[0209] Column address comparator 516 compares the access column address CADDR with the source column address SRCA and the additional bit AB2, and outputs a hit signal HIT22 indicating the comparison result of the access column address CADDR with the source column address SRCA and the additional bit AB2. The additional bit AB2 may include 3 bits.

[0210] Accessing the column address CADDR may include the high-order CADDR_MSB and the low-order CADDR_LSB. Inverter 517 inverts the high-order CADDR_MSB of the access column address CADDR. In response to the hit signal HIT22, selection circuit 545 outputs one of the following: the output of inverter 517, and the high-order CADDR_MSB of the access column address CADDR.

[0211] The conventional decoder 525, in response to the column select master signal PCSLM, decodes the output of the select circuit 545 and the low-order CADDR_LSB of the access column address CADDR to output the decoded target column address DCA. The column select line driver 555 receives the decoded target column address DCA and outputs the column select line signal CSL to select (activate) the bit line corresponding to the decoded target column address DCA.

[0212] The high-order CADDR_MSB of the access column address CADDR can be encoded as follows: Figure 17D As shown.

[0213] Because two adjacent memory blocks share a fuse, additional bit AB2 consists of 3 bits. This is used when a faulty cell in a memory block is repaired using a regular cell in the same memory block. Figure 17G Unit repair controller 503.

[0214] Figure 17H Another example of a cell repair controller according to an example embodiment is shown.

[0215] Reference Figure 17H The unit repair controller 504 may include a column address comparator 515, an inverter 517, a select circuit (MUX) 546, a decoder 526, a column select line (CSL) driver 556, a column address comparator 518, an inverter 519, a select circuit (MUX) 548, a decoder 527, and a column select line (CSL) driver 557.

[0216] The column address comparator 515 compares the access column address CADDR with the source column address SRCA and an additional 4-bit bit AB1, and outputs a hit signal HIT31, which indicates the comparison result of the access column address CADDR with the source column address SRCA and the additional bit AB1.

[0217] The access column address CADDR can include the high-order CADDR_MSB and the low-order CADDR_LSB. Inverter 517 inverts the high-order CADDR_MSB of the access column address CADDR.

[0218] The column address comparator 518 compares the access column address CADDR with the source column address SRCA and the additional bit AB1, and outputs a hit signal HIT32, which indicates the comparison result between the access column address CADDR and the source column address SRCA and the additional bit AB1.

[0219] Inverter 519 inverts the high-order CADDR_MSB of the accessed column address CADDR.

[0220] The selection circuit 546 outputs one of the following: the output of the inverter 517, and the high-order bit CADDR_MSB of the access column address CADDR. The decoder 526 decodes the output of the selection circuit 546 and the low-order bit CADDR_LSB of the access column address CADDR to output the decoded target column address DCA. The column select line driver 556 receives the decoded target column address DCA and outputs the column select line signal CSLa1 to select (activate) the bit line corresponding to the decoded target column address DCA.

[0221] The selection circuit 548 outputs one of the following: the output of the inverter 519, and the high-order bit CADDR_MSB of the access column address CADDR. The decoder 527 decodes the output of the selection circuit 548 and the low-order bit CADDR_LSB of the access column address CADDR to output the decoded target column address DCA'. The column select line driver 557 receives the decoded target column address DCA' and outputs the column select line signal CSLa2 to select (activate) the bit line corresponding to the decoded target column address DCA'.

[0222] When the faulty cell is repaired using regular cells from two adjacent memory blocks, it can be used Figure 17H Unit repair controller 504.

[0223] Figure 18 This is a flowchart illustrating a method for operating a semiconductor memory device according to an exemplary embodiment.

[0224] Reference Figures 11 to 18In a method of operating a semiconductor memory device 200b comprising a memory cell array 300 containing multiple memory blocks and at least one redundant block, a repair control circuit 400b repairs a first faulty cell in a first memory block using a first normal cell in a first memory block of the multiple memory blocks (S310). The repair control circuit 400b repairs the first faulty cell using a first normal cell by swapping a first column address specifying a bit line connected to the first faulty cell with a second column address specifying a second bit line connected to the first normal cell. The repair control circuit 400b then replaces the first normal cell in the first memory block of the multiple memory blocks with a second normal cell in the first memory block (S330). The first faulty cell, the first normal cell, and the second normal cell in the first memory block may have different column select line addresses. For example, the first faulty cell, the first normal cell, and the second normal cell in the first memory block can be connected to different bit lines selected by different column select line (CSL) signals. The first faulty cell, the first normal cell, and the second normal cell in the first memory block can be connected to the same I / O circuit.

[0225] The repair control circuit 400a replaces the second regular cell in the first memory block with the first redundant cell in the redundant block (S350). The second regular cell and the first redundant cell may have the same column select line address and may have the same relative position within the corresponding memory block array. The second regular cell and the first redundant cell may be connected to different I / O circuits.

[0226] Figure 19 This is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0227] Reference Figure 19 The semiconductor memory device 600 may include a first set of dies 610 and a second set of dies 620 that provide soft error analysis and correction functions in a stacked chip structure.

[0228] The first set of dies 610 may include at least one buffer die 611. The second set of dies 620 may include a plurality of memory dies 620-1 to 620-r stacked on the first set of dies 610 and transmitting data through a plurality of through-silicon vias (TSVs).

[0229] At least one of the memory dies 620-1 to 620-r may include a first type error correction code (ECC) engine 622, wherein the first type ECC engine 622 generates transmission parity bits based on the transmission data to be sent to the first set of dies 610. The first type ECC engine 622 may be referred to as a "cell core ECC engine".

[0230] The buffer die 611 may include a second type ECC engine 612, wherein, when a transmission error is detected from transmitted data received via the TSV line, the second type ECC engine 612 uses transmission parity bits to correct the transmission error and generate error-corrected data. The second type ECC engine 612 may be referred to as a "traffic ECC engine". The buffer die 611 may include a repair control circuit 614, and the repair control circuit 614 can use... Figure 13 Repair control circuit 400b.

[0231] The semiconductor memory device 600 can be a stacked chip-type memory device or a stacked memory device that transmits data and control signals via TSV lines. TSV lines can also be referred to as "through electrodes".

[0232] The first type of ECC engine 622 can perform error correction on the data output from the memory die 620-p before sending the transmission data.

[0233] Based on the above description, a TSV line group 632 formed at a memory die 620-r may include multiple TSV lines L1 to Lp, and a parity TSV line group 634 may include multiple parity TSV lines L10 to Lq. The TSV lines L1 to Lp of the data TSV line group 632 and the parity TSV lines L10 to Lq of the parity TSV line group 634 can be connected to corresponding microbumps MCB formed between memory dies 620-1 to 620-r.

[0234] At least one of the memory dies 620-1 to 620-r may include a DRAM cell, each DRAM cell including at least one access transistor and a memory capacitor.

[0235] The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the memory controller via a data bus B10. The first set of dies 610 may be connected to the memory controller via the data bus B10.

[0236] The first-type ECC engine 622, referred to as the unit core ECC engine, can output parity bits and data transmission through parity check TSV line group 634 and data TSV line group 632, respectively. The output transmission data can be data corrected by the first-type ECC engine 622.

[0237] The second type ECC engine 612, referred to as the routing ECC engine, can determine whether a transmission error has occurred in the transmitted data received via the data TSV line group 632 based on the transmission parity bits received via the parity check TSV line group 634. When a transmission error is detected, the second type ECC engine 612 can use the transmission parity bits to correct the transmission error. When the transmission error is uncorrectable, the second type ECC engine 612 can output information indicating the occurrence of an uncorrectable data error.

[0238] Figure 20 This is an adoption based on an exemplary embodiment. Figure 19 A cross-sectional view of the 3D chip structure of a semiconductor memory device.

[0239] Figure 20 This illustrates a 3D chip structure 700 in which the host and high-bandwidth memory (HBM) are directly connected without an inserter layer.

[0240] Reference Figure 20 Flip-chip bumps (FBs) can be used to arrange host dies 720 (such as system-on-a-chip (SoC), central processing unit (CPU), or graphics processing unit (GPU)) on a printed circuit board (PCB) 710. Memory dies D11 through D14 can be stacked on the host die 720 to implement an HBM structure. Figure 20 In the middle, the following was omitted. Figure 19 The buffer die 611 or logic die can be used. However, the buffer die 611 or logic die can be positioned between the memory die D11 and the host die 720. To implement the HBM(620) structure, TSV lines can be formed at memory dies D11 and D14. The TSV lines can be electrically connected to the microbumps MCB positioned between the memory dies.

[0241] The aspects of the present invention can be applied to systems using semiconductor memory devices.

[0242] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept.

Claims

1. A memory device, comprising: Multiple memory blocks, including a first memory block, each memory block comprising multiple columns of conventional memory cells; The first redundant block includes multiple columns of redundant memory cells; as well as Repair the control circuit, including: The repair control circuit is configured to: make the second column of regular memory cells of the first memory block a target column for the first column of regular memory cells of the first memory block, and make the first column of redundant memory cells of the first redundant block store data destined for the second column of regular memory cells of the first memory block.

2. The memory device of claim 1, wherein: The repair control circuit is configured to: use the second column of regular memory cells of the first memory block as the target read column for the first column of regular memory cells of the first memory block, and use the first column of redundant memory cells of the first redundant block as the target read column for the second column of regular memory cells of the first memory block.

3. The memory device of claim 2, wherein: The first column of regular memory cells in the first memory block is a column of the first memory block that has at least one faulty memory cell.

4. The memory device of claim 3, wherein: The repair control circuit redistributes data destined for the first column of regular memory cells in the first memory block to the second column of regular memory cells, and redistributes data destined for the second column of regular memory cells to the first redundant block.

5. The memory device of claim 3, wherein: The repair control circuit is configured to: use the second column of regular memory cells of the second memory block in the plurality of memory blocks as the target column for the first column of regular memory cells of the second memory block, and to store the data destined for the second column of regular memory cells of the second memory block in the second column of redundant memory cells of the first redundant block.

6. The memory device of claim 5, further comprising: The fuse circuit serves as part of the repair control circuit and stores the correlation between the column select line of the first redundant block and the column select line of the memory blocks among the plurality of memory blocks.

7. The memory device of claim 3, further comprising: An address storage table stores source addresses and corresponding target addresses for use by the repair control circuit when using the second column of regular memory cells in the first memory block as the target column for the first column of regular memory cells in the first memory block.

8. The memory device of claim 7, wherein, When the first column of redundant memory cells in the first redundant block stores data destined for the second column of regular memory cells in the first memory block, the repair control circuit also uses the source address and the corresponding destination address.

9. A memory device, comprising: Multiple memory blocks, including a first memory block, each memory block comprising multiple columns of conventional memory cells; The first redundant block includes multiple columns of redundant memory cells; and Repair the control circuit, including: The repair control circuit is configured to: replace a first conventional memory cell in a first column of a first memory block with a second conventional memory cell in a second column of the first memory block, and replace the second conventional memory cell in a second column of a first memory block with a first redundant memory cell in a first redundant column of a first redundant block, wherein: The step of replacing a second conventional memory cell with a first redundant memory cell includes having the first redundant memory cell store data destined for the second conventional memory cell.

10. The memory device of claim 9, wherein, The first column of redundant memory cells in the first redundant block has the same relative position as the second column of the first memory block within the first redundant block.

11. The memory device of claim 10, wherein, The first conventional memory cell is the fault cell. The step of replacing the first conventional memory cell with the second conventional memory cell includes repairing the first conventional memory cell.

12. The memory device of claim 9, wherein, The repair control circuit is configured to: replace the third conventional memory cell in the first column of the second memory block of the plurality of memory blocks with the fourth conventional memory cell in the second column of the second memory block, and replace the fourth conventional memory cell in the second column of the second memory block with the first redundant memory cell in the second column of the first redundant block.

13. The memory device of claim 12, wherein, The first column of the first memory block has the same relative position within the first memory block as the first column of the second memory block within the second memory block, and The second column of the first memory block has a relative position within the first memory block that is different from the relative position of the second column of the second memory block within the second memory block.

14. The memory device of claim 13, wherein, The second column of the first memory block has the same relative position within the first memory block as the first column of redundant memory cells in the first redundant block, and The second column of the second memory block has the same relative position within the second memory block as the second column of the redundant memory cells in the first redundant block.

15. The memory device of claim 9, wherein, The repair control circuit is also configured as follows: Repair the faulty memory cell in another column of the first memory block using the first conventional memory cell.

16. A memory device, comprising: Multiple conventional memory blocks, including a first memory block, each conventional memory block comprising multiple columns of conventional memory cells; The first redundant block includes multiple columns of redundant memory cells; Multiple column selection lines are used to select the multiple columns of conventional memory cells and the multiple columns of redundant memory cells, and each column selection line is associated with a column address; and The control circuit was repaired and configured as follows: Replace the first source address with the first destination address, where the first source address is the address of the first column select line of the first column memory cell in the first memory block, and the first destination address is the address of the second column select line of the second column memory cell in the first memory block. Replace the address of the second column selection line with the address of the first column selection line connected to the first column of the first redundant block.

17. The memory device of claim 16, wherein: The first column of memory cells in the first memory block includes faulty memory cells, such that the first source address is a faulty address.

18. The memory device of claim 17, further comprising: A fuse circuit stores the correlation between the column select line of the first redundant block and the column select lines of the memory blocks in the plurality of conventional memory blocks.

19. The memory device of claim 18, wherein: An address storage table is used for each regular memory block. Each address storage table stores the source address associated with the column select line and the destination address associated with the column select line, so that each source address is mapped to a different destination address.

20. The memory device of claim 16, wherein: The relative positions of the second column memory cells of the first memory block with respect to the first memory block are the same as the relative positions of the first column of the first redundant block with respect to the first redundant block.

Images