Interrupt generator with synchronization function

Abstract

This application relates to an interrupt generation device with synchronization function. By using one of the interrupt generation modules as a reference interrupt module, when the synchronization signal output by the synchronization output module arrives, the reference timing module adjusts the count of each interrupt module according to the synchronization signal, the reference count of the reference interrupt module, and the timing duration of the reference timing module itself, so as to change the output time of each subsequent interrupt signal. This makes the output reference interrupt signal synchronized with the synchronization signal, and other interrupt signals still maintain the initial phase relationship with the reference interrupt signal before adjustment, and eventually synchronize with the synchronization signal. In this way, only one synchronization signal is needed to ensure that the synchronization of all interrupt signals is achieved without changing the phase relationship between the interrupt signals of each interrupt generation module. The method is simple and has high synchronization accuracy.

Description

Technical Field

[0001] This application relates to the field of synchronization control technology, and in particular to an interrupt generation device with synchronization function. Background Technology

[0002] Interrupt generators can be used to generate interrupt signals, which are then output to the central processing unit for further processing. A system may have multiple interrupt generators. When it is necessary to synchronize each interrupt signal with an external synchronization signal, since the interrupt signals output by each interrupt generator may have a specific phase difference, it is necessary to dynamically adjust the output time of each interrupt generator's interrupt signal to ensure that while each interrupt signal is synchronized with the synchronization signal, it also maintains a specific phase relationship with the other interrupt signals.

[0003] The common approach to this is to use multiple synchronization signals with the same phase relationship to synchronize each interrupt generator, ensuring that each interrupt signal is synchronized with its corresponding synchronization signal, ultimately resulting in the same phase relationship among the interrupt signals. However, using multiple synchronization signals for individual interrupt synchronization is cumbersome and difficult to control. Furthermore, if there is a deviation in the phase relationship between the synchronization signals, the synchronized interrupt signals will not meet the specific phase relationship, leading to low synchronization accuracy. Summary of the Invention

[0004] This application provides an interrupt generator with synchronization function, which can achieve high-precision synchronization function with only one synchronization signal.

[0005] An interrupt generator with synchronization function includes:

[0006] Synchronous output module, used to output synchronization signal;

[0007] The reference timing module is connected to the synchronization output module and is used to time the reference cycle, and outputs a reference pulse after each reference cycle is completed.

[0008] Multiple interrupt generation modules, each of which includes:

[0009] A periodic counting unit, connected to the reference timing module, is used to periodically count the reference pulses to obtain the count quantity;

[0010] A waveform generation unit, connected to the period counting unit, is used to output an interrupt signal if the count reaches the interrupt number.

[0011] The reference timing module is also used to acquire a reference count, and adjust each of the counts according to the synchronization signal, the reference count, and its own timing duration, so as to adjust the timing of the waveform generation unit outputting the interrupt signal, so that the adjusted reference interrupt signal is synchronized with the synchronization signal, and the interrupt signals output by the other interrupt generation modules besides the reference interrupt module maintain an initial phase relationship with the reference interrupt signal; wherein the reference count is the count of the reference interrupt module; the reference interrupt module is one of the multiple interrupt generation modules.

[0012] In one embodiment, the reference timing module is further configured to:

[0013] If the timing duration is above the timing threshold and the reference count is above the quantity threshold when the synchronization signal is received, then a preset number of reference pulses are output and timing restarts; wherein the preset number is equal to the difference between the reference interrupt number and the reference count; the reference interrupt number is the number of interrupts of the reference interrupt module.

[0014] In one embodiment, the quantity threshold is equal to the difference between the reference interruption quantity and 1, and the preset quantity is 1.

[0015] In one embodiment, the reference timing module is further configured to restart timing if the timing duration has not reached the timing threshold or the reference count has not reached the count threshold when the synchronization signal is received;

[0016] Each of the aforementioned interrupt generation modules further includes:

[0017] A delay processing unit, connected to the reference timing module and the cycle counting unit respectively, is used to acquire and calculate the delay period based on the reference count, the number of interrupts, and the reference number of interrupts; wherein if the number of interrupts is greater than or equal to the number of reference interrupts, the delay period is equal to the number of reference counts; if the number of interrupts is less than the number of reference interrupts, the delay period is equal to the remainder of the quotient of the number of reference counts and the number of interrupts.

[0018] The delay counting unit is connected to the delay processing unit and the synchronization output module respectively, and is used to control the period counting unit to pause the counting of the reference pulse according to the delay period if the reference pulse is not received when the synchronization signal is received.

[0019] In one embodiment, the delay processing unit is further configured to periodically count the reference pulses using the reference interrupt number as the counting period to obtain the reference count number.

[0020] In one embodiment, the interrupt generating device further includes:

[0021] An interrupt selection module is connected to the delay processing unit and the cycle counting unit of each interrupt generation module, respectively, and is used to obtain the number of interrupts of each interrupt generation module from each cycle counting unit, and select the reference interrupt number from it and output it to each delay processing unit.

[0022] In one embodiment, the reference timing module is further configured to restart timing if the timing duration has not reached the timing threshold or the reference count has not reached the count threshold when the synchronization signal is received;

[0023] Each of the aforementioned interrupt generation modules further includes:

[0024] The delay processing unit is connected to the period counting unit of the reference interrupt module, and is used to periodically count the reference pulse with the number of interrupts as the counting period, and to clear the count when the reference count reaches the reference interrupt number, so as to obtain the delay period.

[0025] The delay counting unit is connected to the delay processing unit and the synchronization output module respectively, and is used to control the period counting unit to pause the counting of the reference pulse according to the delay period if the reference pulse is not received when the synchronization signal is received.

[0026] In one embodiment, each of the cycle counting units is further configured to output a trigger signal if the count reaches the interruption number;

[0027] The interrupt generating device further includes:

[0028] An interrupt selection module is connected to the delay processing unit and the cycle counting unit of each interrupt generation module, respectively, and is used to receive the trigger signal from each cycle counting unit and select the trigger signal of the reference interrupt module to output to each delay processing unit.

[0029] The delay processing unit is also used to reset the count to zero according to the trigger signal.

[0030] In one embodiment, the delay counting unit is also connected to the reference timing module, and is used to count down the delay count value according to the received reference pulse, using the value of the delay period as the delay count value, until the delay count value is 0, and then end the pause control of the period counting unit.

[0031] In one embodiment, the synchronous output module includes:

[0032] An input selection unit is configured to select one of the external source signals from a plurality of external source signals as a target source signal;

[0033] The edge detection unit is connected to the input selection unit, the reference timing module, and the delay counting unit, respectively, and is used to generate a pulse waveform when the target edge of the target source signal is detected to obtain the synchronization signal.

[0034] In one embodiment, the interrupt generation module further includes:

[0035] An output delay unit is connected to the period counting unit and the waveform generation unit respectively, and is used to delay the output of the interrupt signal.

[0036] In one embodiment, the interrupt generating device further includes:

[0037] The synchronization protection module is connected to the synchronization output module, the reference timing module, and each of the delay counting units respectively. If the synchronization signal is received at the current time, the module controls the reference timing module and each of the delay counting units to block the synchronization signal at the next time until the interrupt signal is received, at which point the blocking control is exited.

[0038] The aforementioned interrupt generation device uses one of the interrupt generation modules as a reference interrupt module. When the synchronization signal output by the synchronization output module arrives, the reference timing module adjusts the count of each interrupt module according to the synchronization signal, the reference count of the reference interrupt module, and the timing duration of the reference timing module itself. This changes the output time of each subsequent interrupt signal, ensuring that the output reference interrupt signal is synchronized with the synchronization signal. Furthermore, other interrupt signals maintain their initial phase relationship with the reference interrupt signal before adjustment and eventually synchronize with the synchronization signal. In this way, only one synchronization signal is needed to ensure the synchronization of all interrupt signals while keeping the phase relationship between the interrupt signals of each interrupt generation module unchanged. The method is simple and has high synchronization accuracy. Attached Figure Description

[0039] Figure 1 This is a structural block diagram of an interrupt generation device according to an embodiment of this application;

[0040] Figure 2 This is a schematic diagram showing the timing adjustment of signal S1 when signal S1 lags behind the synchronization signal in this application.

[0041] Figure 3 This is a structural block diagram of an interrupt generation device according to another embodiment of this application;

[0042] Figure 4This is a schematic diagram illustrating the timing adjustment of signals A, B, and C when signal B lags behind the synchronization signal in this application.

[0043] Figure 5 This is a schematic diagram illustrating the timing adjustment of signal S2 when it leads the synchronization signal in this application.

[0044] Figure 6 This is a schematic diagram illustrating the timing adjustment of signals B and C when signal B leads the synchronization signal in this application.

[0045] Figure 7 This is a schematic diagram illustrating the timing adjustment of signals A and B when signal B leads the synchronization signal in this application.

[0046] Figure 8 This is a structural block diagram of an interrupt generation device according to another embodiment of this application;

[0047] Figure 9 This is a structural block diagram of an interrupt generation device according to another embodiment of this application;

[0048] Figure 10 This is a structural block diagram of an interrupt generation device according to another embodiment of this application;

[0049] Figure 11 This is a structural block diagram of an interrupt generation device according to another embodiment of this application;

[0050] Figure 12 This is a structural block diagram of an interrupt generation device according to another embodiment of this application. Detailed Implementation

[0051] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0053] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly. The connection can be a direct connection or an indirect connection.

[0054] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0055] Figure 1 This is a structural block diagram of an interrupt generator with synchronization function according to an embodiment, such as... Figure 1 As shown, the interrupt generation device includes a synchronization output module 11, a reference timing module 12, and multiple interrupt generation modules (represented by 13a, 13b...13n in the figure); the synchronization output module 11 is used to output a synchronization signal; the reference timing module 12 is connected to the synchronization output module 11 and is used to time the reference cycle, and outputs a reference pulse after each reference cycle is completed; each interrupt generation module includes a cycle counting unit 131 and a waveform generation unit 132, the cycle counting unit 131 is connected to the reference timing module 12 and is used to periodically count the reference pulses to obtain the count quantity; the waveform generation unit 13... 2 is connected to the period counting unit 131 and is used to output an interrupt signal if the count reaches the interruption number; the reference timing module 12 is also used to obtain the reference count and adjust each count according to the synchronization signal, the reference count and its own timing duration, so as to adjust the timing of the interrupt signal output by the waveform generation unit 132, so that the adjusted reference interrupt signal is synchronized with the synchronization signal, and the interrupt signals output by other interrupt generation modules except the reference interrupt module maintain the initial phase relationship with the reference interrupt signal; wherein the reference count is the count of the reference interrupt module; the reference interrupt module is one of multiple interrupt generation modules.

[0056] The reference timing module 12 is used to implement periodic timing, with a timing period of one reference period, and outputs a reference pulse after each reference period is completed. The reference timing module 12 can be a 16-bit counter.

[0057] Each interrupt generation module's cycle counting unit 131 can receive reference pulses and periodically count the number of reference pulses. Once the count reaches the interrupt quantity, the counting restarts, and the waveform generation unit 132 outputs an interrupt signal. Thus, each interrupt generation module outputs an interrupt signal according to its own interrupt cycle; the product of the interrupt quantity and the reference cycle is the interrupt cycle of the interrupt signal output by each interrupt generation module. The interrupt quantity of each cycle counting unit 131 can be the same or different. The waveform generation unit 132 can select, via an internal register, to output either a level signal or a pulse signal as an interrupt signal. When a pulse signal is selected, the interrupt signal is a pulse signal; when a level signal is selected, the output signal level toggles each time an interrupt is triggered.

[0058] The frequency of the synchronization signal can be less than or equal to the frequency of the reference interrupt signal, and the two satisfy an integer multiple relationship. It can be understood that the synchronization signal can be a short pulse signal, and the synchronization output module 11 can continuously output the synchronization signal. Based on the relationship between the frequency of the synchronization signal and the frequency of the reference interrupt signal, after the reference interrupt module is aligned with the first synchronization signal, under normal circumstances, subsequent reference interrupt signals can also be aligned with the corresponding synchronization signals.

[0059] The number of interrupt generation modules can be up to eight, responsible for generating a series of interrupt signals with interrupt periods that are integer multiples of the reference period. The reference interrupt module is one of the multiple interrupt generation modules and can be manually selected. Each interrupt generation module's period counting unit 131 obtains a count when counting the reference pulses. The reference timing module 12 obtains the reference count from the reference interrupt module. When the synchronization signal arrives, combining the reference count and its own timing duration, the reference timing module 12 can adjust the count of each period counting unit 131, thereby changing the timing of the interrupt signal output by each waveform generation unit 132. This ensures that the subsequent output reference interrupt signal is synchronized with the synchronization signal, and that the interrupt signals output by other interrupt generation modules maintain the initial phase relationship with the reference interrupt signal output by the reference interrupt module, ultimately achieving synchronization of all interrupt signals with the synchronization signal. Each period counting unit 131 obtains its count by measuring the number of reference pulses; therefore, the reference timing module 12 can change the count by adjusting the number of output reference pulses.

[0060] The interrupt generator in this embodiment is equipped with a clock management module to provide a working clock to each module. The clock frequency can be 200MHz. The interrupt generator's operating state can be manually controlled. By setting its working register to 1, it enters the working state and continuously outputs interrupt signals; conversely, setting the working register to 0 puts it into a reset state, in which case no interrupt signal is output. Registers for setting other operating parameters should be configured when the working register is set to 0, i.e., when there is no interrupt signal output. When the working register is set to 1, other registers cannot be configured.

[0061] The aforementioned interrupt generation device uses a reference timing module 12 to time a reference period and outputs a reference pulse after each reference period is completed. The period counting unit 131 of each interrupt generation module periodically counts the reference pulses, and then the waveform generation unit 132 outputs an interrupt signal when the count reaches the interrupt number. To achieve synchronization between each interrupt module and the synchronization signal, one of the interrupt generation modules can be used as a reference interrupt module. When the synchronization signal output by the synchronization output module 11 arrives, the reference timing module 12 adjusts the count of each interrupt module according to the synchronization signal, the reference count of the reference interrupt module, and the timing duration of the reference timing module 12 itself, so as to change the output time of each subsequent interrupt signal, so that the output reference interrupt signal is synchronized with the synchronization signal, and other interrupt signals still maintain the initial phase relationship with the reference interrupt signal before adjustment, and eventually synchronize with the synchronization signal. In this way, only one synchronization signal is needed to ensure that the phase relationship between the interrupt signals of each interrupt generation module remains unchanged, and all interrupt signals can be synchronized. The method is simple and has high synchronization accuracy.

[0062] In one embodiment, the reference timing module 12 is further configured to: if the timing duration is above the timing threshold and the reference count is above the quantity threshold when the synchronization signal is received, output a preset number of reference pulses and restart timing; wherein the preset number is equal to the difference between the reference interrupt number and the reference count number; the reference interrupt number is the number of interrupts of the reference interrupt module.

[0063] The timing duration is the duration during which the reference timing module 12 performs reference period timing. The timing threshold and quantity threshold can be set manually. If the reference timing module 12 receives a synchronization signal and its own timing duration is above the timing threshold, and the acquired reference count is above the quantity threshold, then the reference interrupt signal is considered to lag behind the synchronization signal. In this case, the reference timing module 12 can directly output a preset number of reference pulses. The preset number is equal to the difference between the reference interrupt number and the reference count number. In this way, all interrupt generation modules can output interrupt signals in advance by (n*T_base-td) time, where n is the preset number, T_base is one reference period, and td is the timing duration of the reference timing module 12 when the synchronization pulse arrives. Figure 2 For example, let the reference interrupt signal of the reference interrupt module be signal S1, the number of interrupts be 4, the original signal of signal S1 is emitted at time t1, t2 is the time when the synchronization signal arrives, the reference interrupt lag time is (T_base-td), and the reference count is 3. Therefore, the preset count is 4-3=1. At this time, the reference timing module 12 directly emits 1 reference pulse and performs timing reset. At this time, all interrupt signals, including signal S, will be output in advance, and the advance time is equal to the reference interrupt lag time.

[0064] It should be understood that the count quantity is the number of reference pulses being measured. When the periodic counting unit 131 is counting, if the initial count value is equal to 0, then the count quantity is equal to the count value; if the initial count value is not 0, then the count quantity is equal to the difference between the count value and the initial count value. For example... Figure 2 As shown, the initial count value of the periodic counting unit 131 is 1. When the synchronization signal arrives at time t2, the count value is 4, so the reference count is equal to 3.

[0065] Specifically, for the reference interrupt module, after receiving a preset number of reference pulses, its reference count will reach the reference interrupt count. At this time, the reference interrupt module meets the interrupt trigger condition, and its waveform generation unit 132 outputs a reference interrupt signal, thereby achieving synchronization with the synchronization signal; reference Figure 3 As shown, let signal B be the reference interrupt signal, and its original signal was emitted at time t. B1 At time t0, the synchronization signal arrives, so signal B is output at time t0 to achieve synchronization with the synchronization signal. For interrupt modules other than the reference interrupt module, since their advance time is the same as that of the reference interrupt module, the other interrupt signals maintain their initial phase relationship with the reference interrupt signal, thus ultimately achieving synchronization with the synchronization signal as well. Figure 3 For example, signals A and C are the other two interrupt signals, where signal A has an interruption count of 2, and its original signal was emitted at time t. A1When the synchronization signal arrives, signal A is output at time t0; signal C has 5 interruptions, and its original signal output time is t0. C1 When the synchronization signal arrives, signal C is advanced to t. C2 Output at any given time. The initial phase relationship between signals A, B, and C remains unchanged.

[0066] In this way, the reference timing module 12 can determine whether the reference interrupt signal lags behind the synchronization signal based on the synchronization signal, the reference count, and its own timing duration. If lag is determined, it controls the interrupt signal to be output earlier by resetting the timing and outputting a preset number of reference pulses. Ultimately, this ensures that subsequent reference interrupt signals are aligned with the synchronization signal, thus achieving synchronization. Other interrupt signals are synchronized with the reference interrupt signal, i.e., synchronized with the synchronization signal. This method is simple, and because all interrupt signals are synchronized together, the synchronization accuracy is higher.

[0067] In one embodiment, the quantity threshold can be equal to the difference between the reference interruption quantity and 1, with the preset quantity being 1.

[0068] It can be understood that the quantity threshold equals the difference between the reference interrupt quantity and 1, and the preset quantity equals the difference between the reference interrupt quantity and the reference count quantity, which is 1. This indicates that the synchronization signal arrives during the last reference cycle within the interrupt cycle of the reference interrupt module, and the original reference interrupt signal is about to be issued at the next moment. To synchronize each interrupt signal with the synchronization signal, only one reference pulse needs to be output at this time; the method is simple and easy to implement. Figure 3 Taking the reference interrupt signal B as an example, the number of reference interrupts is 4, the number threshold is 3, when the synchronization signal arrives at time t0, it is in the 4th reference cycle of the reference interrupt module. At this time, the number of reference counts is 3, and the design duration td is above the timing threshold. At this time, the reference timing module 12 is reset to zero and outputs a reference pulse.

[0069] Thus, by setting the quantity threshold to the difference between the number of reference interrupts and 1, the reference timing module 12 can directly output a reference pulse when the synchronization signal arrives at the moment when the reference interrupt signal is about to be issued, thereby realizing the synchronization of each interrupt signal and the synchronization signal. The method is simple and easy to implement.

[0070] In one embodiment, such as Figure 4As shown, the reference timing module 12 is also used to restart timing if the timing duration has not reached the timing threshold or the reference count has not reached the quantity threshold when a synchronization signal is received; each interrupt generation module also includes a delay processing unit 133 and a delay counting unit 134. The delay processing unit 133 is connected to the reference timing module 12 and the cycle counting unit 131 respectively, and is used to acquire and calculate the delay period based on the reference count, the number of interrupts, and the number of reference interrupts; wherein, if the number of interrupts is greater than or equal to the number of reference interrupts, the delay period is equal to the number of reference counts; if the number of interrupts is less than the number of reference interrupts, the delay period is equal to the remainder of the quotient of the number of reference counts and the number of interrupts; the delay counting unit 134 is connected to the delay processing unit 133 and the synchronization output module 11 respectively, and is used to control the cycle counting unit 131 to pause the counting of the reference pulse according to the delay period if no reference pulse is received when a synchronization signal is received.

[0071] Specifically, for each interrupt generation module, its delay processing unit 133 can obtain the reference count through the reference timing module 12, or it can obtain the reference count through the cycle counting unit 131 of the reference interrupt module; the number of interrupts can be stored in each interrupt generation module in advance, and the delay processing unit 133 can obtain it directly; the number of reference interrupts can be obtained by obtaining it from the reference interrupt module.

[0072] Furthermore, after obtaining the reference count, the number of interrupts, and the number of reference interrupts, each delay processing unit 133 uses the reference count as the delay period if the number of interrupts is greater than or equal to the number of reference interrupts; otherwise, it uses the remainder of the quotient of the reference count and the number of interrupts as the delay period. The delay period is calculated in real time. Since the number of reference counts remains constant, the delay period also changes continuously. When the delay counting unit 134 pauses the reference pulse counting, the specific value of the delay period used is related to the reference interrupt count value at the moment the synchronization pulse arrives.

[0073] The delay counting unit 134 controls the cycle counting unit 131 to pause the counting of reference pulses according to the delay period. That is, the cycle counting unit 131 pauses the counting of a certain number of reference pulses, and the value of this number is equal to the value of the delay period. For example, if the delay period is 2, then the cycle counting unit 131 pauses the counting of 2 reference pulses.

[0074] When the synchronization signal arrives, the reference timing module 12 determines whether the timing duration has reached the timing threshold and whether the number of reference counts has reached the number threshold. If neither condition is met, the reference interrupt signal is considered to be ahead of the synchronization signal, and the reference interrupt lead time is (k*T_base+td), where k is the number of reference counts, T_base is one reference period, and td is the timing duration of the reference timing module 12 when the synchronization pulse arrives. At this time, all interrupt signals need to be delayed. To address this, on the one hand, the reference timing module 12 restarts timing, that is, the delay time of each interrupt signal is td; on the other hand, since the reference timing module 12 does not output a reference pulse when the synchronization signal arrives, the delay counting unit 134 can know that the reference interrupt signal is ahead of the synchronization signal based on the absence of a reference pulse. At this time, further delay is performed, and each interrupt is delayed by k reference periods, so that the total delay time reaches (k*T_base+td), thus achieving the synchronization effect. However, to avoid excessively long delay times, the delay time can be divided into two cases based on the relationship between the number of interrupts and the number of reference interrupts. If the number of interrupts is greater than or equal to the reference number of interrupts, the delay period is equal to the reference count number k. The delay counting unit 134 controls the cycle counting unit 131 to pause the counting of the reference pulse according to the delay period, that is, the delay duration is (k*T_base). If the number of interrupts is less than the reference number of interrupts, the delay period is equal to the remainder of the quotient of the reference count number and the number of interrupts, that is, the delay duration is (k%M)*T_base, where M represents the number of interrupts of the interrupt generation module.

[0075] by Figure 5 For example, let the reference interrupt signal be signal S2, the number of reference interrupts be 4, the original signal of signal S2 is issued at time t3, and t4 is the time when the synchronization signal arrives. When it is determined that the reference interrupt signal leads the synchronization signal, the number of reference counts k is equal to 0. Therefore, the lead time of the reference interrupt is equal to td, the delay period of signal S2 is equal to the number of reference counts 0, and the count of the reference timing module 12 is cleared. Therefore, the total delay time of each interrupt signal is td, which is equal to the lead time of the reference interrupt, thus achieving the synchronization effect.

[0076] For cases where the number of interrupts is greater than or equal to the reference number of interrupts, Figure 6 For example, suppose signal B is a reference interrupt signal, the number of reference interrupts is 4, and the original signal of signal B is emitted at time t. B2At time t3, the arrival time of the synchronization signal, when it is determined that the reference interrupt signal leads the synchronization signal, the reference count k equals 2. Therefore, the reference interrupt lead time equals 2*T_base+td. The delay period of signal B equals the reference count 2. At the same time, the count of the reference timing module 12 is cleared. Therefore, the total delay time of signal B is 2*T_base+td, which is equal to the reference interrupt lead time. After the delay, the signal emission time of signal B becomes t. B3 At time t, synchronization is achieved. The original signal of signal C was emitted at time t. C3 At time t, the interrupt count of signal C is 5, which is greater than the reference interrupt count of 4. The delay period of signal B is equal to the reference count of 2. At the same time, the count of the reference timing module 12 is reset to zero. Therefore, the total delay time of signal C is also 2*T_base+td, which is equal to the total delay time of the reference interrupt signal. Therefore, the initial phase relationship between signal C and signal B remains unchanged, and signal C is also synchronized with the synchronization signal. After the delay, the signal emission time of signal C becomes t. C4 time.

[0077] For cases where the number of interrupts is less than the reference number of interrupts, Figure 7 Taking signal A as an example, where signal B is the reference interrupt signal, for comparison, Figure 7 The timing adjustment of signal B is also shown; let t5 be the arrival time of the synchronization signal, at which time the reference count of signal B is 3, the total delay of signal B is 3*T_base+td, and the original signal of signal B was emitted at t B4 At time t, after the delay, the time when signal B is emitted becomes t. B5 At time t, the original signal of signal A was emitted at time t. B4 At time t, the number of interrupts for signal A is 2, which is less than the reference number of interrupts (4). The delay period of signal A is equal to the remainder of the quotient of the reference count and the number of interrupts, i.e., 3%2 = 1. Simultaneously, the count of the reference timing module 12 is reset to zero. Therefore, the total delay time of signal A is T_base + td, and the signal transmission time of signal A after the delay becomes t. A2 At time 1, the initial phase relationship between signal A and signal B remains unchanged, therefore signal C is also synchronized with the synchronization signal.

[0078] Thus, the delay period is calculated by the delay processing unit 133 of the interrupt generation module, and the reference timing module 12 determines whether the timeout condition is met. If the reference interrupt signal is found to be ahead, the reference timing module 12 is directly cleared to zero, and the delay counting unit 134 of the interrupt generation module pauses the counting of the reference pulse according to the delay period control period technology unit. Finally, the synchronization of each interrupt signal and the synchronization signal is achieved. The implementation method is simple and reliable.

[0079] In one embodiment, the delay processing unit 133 is further configured to periodically count the reference pulses using the reference interrupt number as the counting period to obtain the reference count number.

[0080] It is understood that the delay processing unit 133 is connected to the reference timing module 12, and can receive the reference pulse output by the reference timing module 12. Then, like the period counting unit 131 of the reference interrupt module, it performs periodic counting with the number of reference interrupts as the counting period to obtain the reference count, which is then used to calculate the delay period. In this way, compared with directly obtaining the reference count through other methods, the delay processing unit 133 obtains the count through its own counting, without data transmission delay, and the acquisition is more timely and accurate.

[0081] In one embodiment, the interrupt generating device further includes an interrupt selection module 14, such as... Figure 8 As shown, the interrupt selection module 14 is connected to the delay processing unit 133 and the cycle counting unit 131 of each interrupt generation module, respectively. It is used to obtain the number of interrupts of each interrupt generation module from each cycle counting unit 131, and select the reference interrupt number from it to output to each delay processing unit 133.

[0082] It is understood that the delay processing unit 133 can obtain the reference interrupt count from the interrupt selection module 14. Specifically, the interrupt selection module 14 can obtain the interrupt count of all interrupt generation modules. The interrupt count of each interrupt generation module can have a different identifier. After determining the reference interrupt module, the interrupt selection module 14 can select the reference interrupt count from the interrupt counts and then transmit it to each delay processing unit 133 for delay period calculation.

[0083] In one embodiment, the reference timing module is further configured to restart timing if the timing duration has not reached the timing threshold or the reference count has not reached the quantity threshold when a synchronization signal is received; each interrupt generation module further includes a delay processing unit and a delay counting unit; the delay processing unit is connected to the periodic counting unit of the reference interrupt module, and is configured to periodically count the reference pulse with the number of interrupts as the counting period, and reset the count to zero when the number of reference counts reaches the number of reference interrupts, thereby obtaining the delay period; the delay counting unit is connected to the delay processing unit and the synchronization output module respectively, and is configured to control the periodic counting unit to pause the counting of the reference pulse according to the delay period if no reference pulse is received when a synchronization signal is received.

[0084] In this embodiment, the interrupt generation device and Figure 3 In the interrupt generation device of the embodiment, the reference timing module and the delay counting unit have the same working principle, the only difference being the working process of the delay processing unit.

[0085] Specifically, the delay processing unit of each interrupt generation module periodically counts the reference pulses, with the counting period being the reference period. That is, each time the count reaches the reference period, it is reset to zero and starts counting again. On the other hand, the delay processing unit also resets the count to zero when the reference count reaches the reference interrupt number. That is, when the delay processing unit periodically counts the reference period, it will reset to zero and start counting again when the count reaches its interrupt period or when the reference count reaches the reference interrupt number. The count obtained in this case can be used as the delay period.

[0086] For example, with Figure 6 For example, let signal B be the reference interrupt signal with a period of 4, and the interrupt period of signal C be 5. Let the interrupt generation module for output signal B be 12b, and the interrupt generation module for output signal C be 12c. The actual counting period of interrupt generation module 12b is equal to the reference interrupt period. Its delay processing unit resets to zero and restarts counting when it reaches the 4th reference period. When the synchronization signal arrives, its count is 2, so its delay period is also equal to 2. The delay processing unit of interrupt generation module 12c resets to zero and restarts counting when it reaches the 4th and 5th reference periods. Since count 4 arrives before count 5, the delay processing unit of interrupt generation module 12c cannot actually count to 5. Therefore, its actual counting period is 4, the same as the reference interrupt period. Thus, the counting of the delay processing unit of interrupt generation module 12c is actually equal to... Figure 6 The reference count number k is the same in the embodiments, according to Figure 6 In the specific description of the embodiment, the reference count k can be directly used as the delay period. Therefore, when the number of interrupts is greater than or equal to the reference interrupt count, the count of the delay processing unit in this case can be used as the delay period.

[0087] against Figure 7 The interrupt period of signal A is 2. The interrupt generation module for output signal A is denoted as 12a. The delay processing unit of interrupt generation module 12a resets to zero and restarts counting when the count reaches the 2nd and 4th reference cycles. When the synchronization signal arrives, the count of the delay processing unit of interrupt generation module 12a is 1, therefore the delay period is also 1. (This is consistent with the above...) Figure 7 The reference count used in the embodiment is the same as the remainder of the quotient of the number of interruptions.

[0088] In summary, the delay processing unit uses the number of interrupts as the counting period to periodically count the reference pulses, and resets the count to zero when the reference count reaches the reference interrupt count, thus obtaining the delay period to achieve synchronization of each signal.

[0089] In one embodiment, each cycle counting unit is further configured to output a trigger signal if the count reaches the interruption count; the interrupt generation device further includes an interrupt selection module, which is connected to the delay processing unit and the cycle counting unit of each interrupt generation module respectively, and is configured to receive the trigger signal from each cycle counting unit and select the trigger signal of the reference interrupt module to output to each delay processing unit; the delay processing unit is further configured to clear the count according to the trigger signal.

[0090] It is understandable that the delay processing unit can determine when the reference count reaches the reference interrupt number through the interrupt selection module. Specifically, each cycle counting unit can output a trigger signal when the count reaches the interrupt number. The interrupt selection module selects the trigger signal of the reference interrupt module from the trigger signals and outputs it to the delay processing unit to notify the delay processing unit that the reference count has reached the reference interrupt number. This method is simple and effective.

[0091] In addition, the waveform generation unit can also output the interrupt signal based on the trigger signal.

[0092] In one embodiment, the delay counting unit 134 is also connected to the reference timing module 12, and is used to count down the delay count value according to the received reference pulse, using the value of the delay period as the delay count value, until the delay count value is 0, and then end the pause control of the period counting unit 131.

[0093] It is understandable that the initial default value of the delay count can be 0, in which case no delay is performed. To enable the periodic counting unit 131 to pause the counting of the reference pulse according to the delay period, the delay counting unit 134 can be used to count down according to the reference pulse. First, the delay count value is set to the value of the delay period. When the delay count value is not 0, the delay counting unit 134 will control the periodic counting unit 131 to pause counting. Whenever a reference pulse is received, the delay count value will be decremented by 1. When the number of received reference pulses is equal to the delay period, the delay count value will be reduced to 0. At this time, the delay counting unit 134 releases control over the periodic counting unit 131. This is how the periodic counting unit 131 pauses the counting of the reference pulse according to the delay period. The implementation method is simple.

[0094] In one embodiment, such as Figure 9 As shown, the synchronization output module 11 includes an input selection unit 111 and an edge detection unit 112. The input selection unit 111 is used to select one external source signal from multiple external source signals as the target source signal. The edge detection unit 112 is connected to the input selection unit 111, the reference timing module 12 and the delay counting unit 134 respectively, and is used to generate a pulse waveform when the target edge of the target source signal is detected to obtain a synchronization signal.

[0095] It is understandable that, considering the possibility of synchronization requirements at different times, multiple external source signals can be received. Each external source signal can carry different synchronization signal information. The input selection unit 111 can select one external source signal as the target source signal as needed. Then, the edge detection unit 112 converts the target source signal into a valid synchronization pulse, obtaining a short pulse form of synchronization signal for direct use. The edge detection unit 112 can support rising edge synchronization or falling edge synchronization.

[0096] In one embodiment, such as Figure 10 As shown, the interrupt generation module also includes an output delay unit 135, which is connected to the cycle counting unit 131 and the waveform generation unit 132 respectively, and is used to output the interrupt signal with a delay.

[0097] It can be understood that when the count reaches the interruption count, the cycle counting unit 131 can output a pulse that triggers the waveform generation unit 132 to output an interrupt signal. The output delay unit 135 can delay the interrupt signal output by the waveform generation unit 132 by delaying the pulse. In this way, the interrupt output time of the interrupt generation module can be delayed, thereby controlling the order of multiple interrupt signals. In addition, the output delay unit 135 can provide a short delay with high delay accuracy, which can meet the small-range delay requirements of each interrupt generation module.

[0098] In one embodiment, the interrupt generating device further includes a synchronization protection module 15, such as... Figure 11 As shown, the synchronization protection module 15 is connected to the synchronization output module 11, the reference timing module 12 and each delay counting unit 134 respectively. If a synchronization signal is received at the current time, the reference timing module 12 and each delay counting unit 134 are controlled to shield the synchronization signal at the next time until an interrupt signal is received, at which point the shielding control is exited.

[0099] It is understandable that whenever a synchronization signal arrives, the synchronization protection module 15 can activate the synchronization protection function, controlling the delay counting unit 134 of the reference timing module 12 and each interrupt generation module to shield the synchronization signal of the next moment, so as to avoid the situation where the interrupt signal cannot be output normally due to the excessive frequency of the external source signal, until the protection is released when the reference interrupt module outputs the interrupt signal.

[0100] This invention also provides an interrupt generation device, such as... Figure 12As shown, it includes a synchronous output module 11, a reference timing module 12, multiple interrupt generation modules, an interrupt selection module 14, and a synchronous protection module 15; wherein the synchronous output module 11 includes an input selection unit 111 and an edge detection unit 112; each interrupt generation module includes a cycle counting unit 131, a waveform generation unit 132, a delay processing unit 133, a delay counting unit 134, and an output delay unit 135; the connection relationship and working principle of each component in this interrupt generation device can be referred to the above embodiment, and will not be repeated here.

[0101] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An interrupt generator with synchronization function, characterized in that, include: Synchronous output module, used to output synchronization signal; The reference timing module is connected to the synchronization output module and is used to time the reference cycle, and outputs a reference pulse after each reference cycle is completed. Multiple interrupt generation modules, each of which includes: A periodic counting unit, connected to the reference timing module, is used to periodically count the reference pulses to obtain the count quantity; A waveform generation unit, connected to the period counting unit, is used to output an interrupt signal if the count reaches the interruption threshold. The reference timing module is also used to acquire a reference count, and adjust each of the counts according to the synchronization signal, the reference count, and its own timing duration, so as to adjust the timing of the waveform generation unit outputting the interrupt signal, so that the adjusted reference interrupt signal is synchronized with the synchronization signal, and the interrupt signals output by the other interrupt generation modules besides the reference interrupt module maintain an initial phase relationship with the reference interrupt signal; wherein the reference count is the count of the reference interrupt module; the reference interrupt module is one of the multiple interrupt generation modules.

2. The interrupt generating apparatus according to claim 1, wherein The reference timing module is also used for: If the timing duration is above the timing threshold and the reference count is above the quantity threshold when the synchronization signal is received, then a preset number of reference pulses are output and timing restarts; wherein the preset number is equal to the difference between the reference interrupt number and the reference count; the reference interrupt number is the number of interrupts of the reference interrupt module.

3. The interrupt generating apparatus according to claim 2, wherein The quantity threshold is equal to the difference between the reference interruption quantity and 1, and the preset quantity is 1.

4. The interrupt generating apparatus according to claim 2, wherein The reference timing module is also used to restart timing if the timing duration has not reached the timing threshold or the reference count has not reached the count threshold when the synchronization signal is received; Each of the aforementioned interrupt generation modules further includes: A delay processing unit, connected to the reference timing module and the cycle counting unit respectively, is used to acquire and calculate the delay period based on the reference count, the number of interrupts, and the reference number of interrupts; wherein if the number of interrupts is greater than or equal to the number of reference interrupts, the delay period is equal to the number of reference counts; if the number of interrupts is less than the number of reference interrupts, the delay period is equal to the remainder of the quotient of the number of reference counts and the number of interrupts. The delay counting unit is connected to the delay processing unit and the synchronization output module respectively, and is used to control the period counting unit to pause the counting of the reference pulse according to the delay period if the reference pulse is not received when the synchronization signal is received.

5. The interrupt generating apparatus according to claim 4, wherein The delay processing unit is further configured to periodically count the reference pulses using the reference interrupt number as the counting period to obtain the reference count number.

6. The interrupt generating apparatus according to claim 4, wherein The interrupt generating device further includes: An interrupt selection module is connected to the delay processing unit and the cycle counting unit of each interrupt generation module, respectively, and is used to obtain the number of interrupts of each interrupt generation module from each cycle counting unit, and select the reference interrupt number from it and output it to each delay processing unit.

7. The interrupt generating apparatus according to claim 2, wherein The reference timing module is also used to restart timing if the timing duration has not reached the timing threshold or the reference count has not reached the count threshold when the synchronization signal is received; Each of the aforementioned interrupt generation modules further includes: The delay processing unit is connected to the period counting unit of the reference interrupt module, and is used to periodically count the reference pulse with the number of interrupts as the counting period, and clear the count when the reference count reaches the reference interrupt number to obtain the delay period. The delay counting unit is connected to the delay processing unit and the synchronization output module respectively, and is used to control the period counting unit to pause the counting of the reference pulse according to the delay period if the reference pulse is not received when the synchronization signal is received.

8. The interrupt generating apparatus according to claim 7, wherein Each of the aforementioned cycle counting units is further configured to output a trigger signal if the count reaches the interruption count; The interrupt generating device further includes: An interrupt selection module is connected to the delay processing unit and the cycle counting unit of each interrupt generation module, respectively, and is used to receive the trigger signal from each cycle counting unit and select the trigger signal of the reference interrupt module to output to each delay processing unit. The delay processing unit is also used to reset the count to zero according to the trigger signal.

9. The interrupt generating apparatus according to claim 4 or 7, wherein The delay counting unit is also connected to the reference timing module and is used to count down the delay count value according to the received reference pulse, using the value of the delay period as the delay count value, until the delay count value is 0, and then end the pause control of the period counting unit.

10. The interrupt generating device according to claim 9, characterized in that, The synchronous output module includes: An input selection unit is configured to select one of the external source signals from a plurality of external source signals as a target source signal; The edge detection unit is connected to the input selection unit, the reference timing module, and the delay counting unit, respectively, and is used to generate a pulse waveform when the target edge of the target source signal is detected to obtain the synchronization signal.

11. The interrupt generating device according to claim 4, characterized in that, The interrupt generation module also includes: An output delay unit is connected to the period counting unit and the waveform generation unit respectively, and is used to delay the output of the interrupt signal.

12. The interrupt generating device according to claim 4, characterized in that, The interrupt generating device further includes: The synchronization protection module is connected to the synchronization output module, the reference timing module, and each of the delay counting units respectively. If the synchronization signal is received at the current time, the module controls the reference timing module and each of the delay counting units to block the synchronization signal at the next time until the interrupt signal is received, at which point the blocking control is exited.

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