Method and apparatus for testing semiconductor memory

Abstract

The present disclosure provides a semiconductor memory testing method and device, including writing test data into a memory block, the memory block including a plurality of marked word lines and unmarked word lines, the marked word lines and the unmarked word lines being arranged at intervals, test data being different in each of two adjacent memory cells on each marked word line, test data being the same in each memory cell on each unmarked word line, test data in the memory cells on the word lines around a target word line being refreshed, a sense amplifier connected to each bit line in the memory block being controlled to be in an enabled state, test data in the memory cells on the target word line being refreshed, a sense amplifier connected to one of two adjacent bit lines in the memory block being controlled to be in an enabled state, and a sense amplifier connected to the other bit line being controlled to be in an inactivated state, data in the memory cells on the target word line being read, and a test result being obtained according to the read data and the test data in the memory cells on the target word line.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a test method and apparatus for a semiconductor memory. Background Technology

[0002] There is often a very slight leakage current between adjacent memory cells in a memory, and this leakage current can worsen into a severe leakage current over time, causing the memory cell to fail.

[0003] To detect memory cells with slight leakage, we refer to these cells as target cells. Typically, this requires subjecting the target cell and its adjacent cells to a prolonged period of high-voltage leakage. When the target and adjacent cells are on different word lines (i.e., in different columns), leakage testing can maintain the high-voltage difference between them by continuously refreshing the word lines of the adjacent cells.

[0004] However, if the adjacent memory cell and the target memory cell are located on the same word line, that is, if the adjacent memory cell and the target memory cell are located in the same column, refreshing the word line will not create a high voltage difference between the adjacent memory cell and the target memory cell, and therefore it will be impossible to test the leakage current of the memory cell on the same word line. Summary of the Invention

[0005] This disclosure provides a method for testing semiconductor memory, including:

[0006] Test data is written into the storage block, which includes multiple marked word lines and multiple unmarked word lines. The marked word lines and unmarked word lines are spaced apart. The test data in two adjacent storage cells on each marked word line is different, while the test data in each storage cell on each unmarked word line is the same.

[0007] Refresh the test data in the memory cells on the word lines surrounding the target word line, and enable the sensitive amplifier connected to each bit line in the memory block; where the target word line is one of the marker word lines;

[0008] Refresh the test data in the memory cell on the target word line, enable the sensitive amplifier connected to one of the two adjacent bit lines in the memory block, and disable the sensitive amplifier connected to the other bit line of the two adjacent bit lines in the memory block.

[0009] Data is read from the storage unit on the target word line, and the test result is obtained based on the read data and the test data in the storage unit on the target word line.

[0010] In some embodiments, first data is stored in the even-numbered storage unit on each tag word line; second data is stored in the odd-numbered storage unit on each tag word line; and second data is stored in each storage unit on each non-tag word line.

[0011] In some embodiments, when the storage cell stores first data, the voltage of the lower plate of the capacitor in the storage cell is greater than or equal to the first reference voltage; when the storage cell stores second data, the voltage of the lower plate of the capacitor in the storage cell is less than the first reference voltage.

[0012] In some embodiments, refreshing the test data in the memory cell on the target word line, controlling one of the two adjacent bit lines in the memory block to be connected to an enabled sensitive amplifier, and controlling the other of the two adjacent bit lines in the memory block to be connected to an disabled sensitive amplifier, specifically includes:

[0013] Activate the target word line to enable the sensitive amplifier connected to the even-numbered bit line, and disable the sensitive amplifier connected to the odd-numbered bit line.

[0014] In some embodiments, activating the target word line enables the sensitive amplifier connected to the even-numbered bit line and disables the sensitive amplifier connected to the odd-numbered bit line. Specifically, this includes:

[0015] The pre-charge voltage of the even-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the even-numbered bit line are both controlled to be the second reference voltage, thereby activating the target word line and controlling the sensitive amplifier to amplify the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line; wherein, the first reference voltage is less than the second reference voltage;

[0016] The pre-charge voltage of the odd-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the odd-numbered bit line are both grounded, the target word line is activated, and the sensitive amplifier is controlled to stop amplifying the charge-sharing voltage between the odd-numbered bit line and the complementary bit line corresponding to the odd-numbered bit line; wherein, the grounded voltage is less than the second reference voltage.

[0017] In some embodiments, controlling the sensitive amplifier to amplify the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line specifically includes:

[0018] The delay and sensitivity amplifier amplifies the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line at the start time, increasing the duration of the voltage difference between two adjacent memory cells on the target word line.

[0019] In some embodiments, refreshing the test data in the storage cells on the word lines surrounding the target word line specifically includes:

[0020] Increase the voltage of the upper plate of the memory cell on the target word line;

[0021] Activate word lines around the target word line and enable the sensitive amplifier connected to each bit line in the memory block;

[0022] Restore the voltage of the upper plate of the memory cell on the target word line.

[0023] In some embodiments, activating word lines around the target word line and controlling the sensitive amplifier connected to each bit line in the memory block specifically includes:

[0024] The pre-charge voltage of each bit line in the memory block and the pre-charge voltage of the complementary bit line corresponding to each bit line are both the first reference voltage. The word lines around the target word line are activated, and the sensitive amplifier is controlled to amplify the charge-sharing voltage between each bit line and the complementary bit line corresponding to each bit line in the memory block. The first reference voltage is less than the second reference voltage.

[0025] One embodiment of this application provides a testing apparatus for a semiconductor memory, comprising:

[0026] The write module writes test data into the storage block, which includes multiple marked word lines and multiple unmarked word lines. The marked word lines and unmarked word lines are spaced apart. The test data in two adjacent storage cells on each marked word line is different, while the test data in each storage cell on each unmarked word line is the same.

[0027] The refresh module is used to refresh the test data in the memory cells on the word lines surrounding the target word line and to enable the sensitive amplifier connected to each bit line in the memory block; the target word line is one of the marker word lines.

[0028] The refresh module is also used to refresh the test data in the memory cell on the target word line, control the sensitive amplifier connected to one of the two adjacent bit lines in the memory block to be in an enabled state, and control the sensitive amplifier connected to the other bit line of the two adjacent bit lines in the memory block to be in a disabled state.

[0029] The comparison module is used to read data from the storage unit on the target word line and obtain the test result based on the read data and the test data in the storage unit on the target word line.

[0030] In some embodiments, first data is stored in the even-numbered storage unit on each tag word line; second data is stored in the odd-numbered storage unit on each tag word line; and second data is stored in each storage unit on each non-tag word line.

[0031] In some embodiments, when the storage cell stores first data, the voltage of the lower plate of the capacitor in the storage cell is greater than or equal to the first reference voltage; when the storage cell stores second data, the voltage of the lower plate of the capacitor in the storage cell is less than the first reference voltage.

[0032] In some embodiments, the refresh module is specifically used for:

[0033] Activate the target word line to enable the sensitive amplifier connected to the even-numbered bit line, and disable the sensitive amplifier connected to the odd-numbered bit line.

[0034] In some embodiments, the refresh module is specifically used for:

[0035] The pre-charge voltage of the even-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the even-numbered bit line are both controlled to be the second reference voltage, thereby activating the target word line and controlling the sensitive amplifier to amplify the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line; wherein, the first reference voltage is less than the second reference voltage;

[0036] The pre-charge voltage of the odd-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the odd-numbered bit line are both grounded, the target word line is activated, and the sensitive amplifier is controlled to stop amplifying the charge-sharing voltage between the odd-numbered bit line and the complementary bit line corresponding to the odd-numbered bit line; wherein, the grounded voltage is less than the second reference voltage.

[0037] In some embodiments, the refresh module is specifically used for:

[0038] The delay and sensitivity amplifier amplifies the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line at the start time, increasing the duration of the voltage difference between two adjacent memory cells on the target word line.

[0039] One embodiment of this disclosure provides a control device for performing the methods involved in the above embodiments.

[0040] One embodiment of this disclosure provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods involved in the above embodiments.

[0041] The semiconductor memory testing method and apparatus disclosed herein utilize the following steps: First, test data is stored in a memory block, ensuring that the data between two adjacent memory cells on a marked word line is different, while the data between two adjacent memory cells on a non-marked word line is the same. A target word line is selected from the marked word lines, and the test data stored in the two adjacent memory cells on the target word line is different. Second, the memory cells on word lines surrounding the target word line are refreshed, enabling the sensitive amplifier connected to each bit line within the memory block and maintaining the voltage difference between the memory cells on the target word line and those on surrounding word lines, creating an environment more prone to leakage on the target word line. Third, the memory cells on the target word line are refreshed, enabling one of the sensitive amplifiers connected to two adjacent bit lines within the memory block and disabling the other, maintaining the voltage difference between adjacent memory cells on the target word line, creating an environment more prone to leakage between adjacent memory cells on the same word line, and suppressing channel leakage within the memory cells. Finally, the test data of the memory cells on the target word line is read, and the test result is determined based on the read data and the test data, thus achieving leakage testing of memory cells on the same word line. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0043] Figure 1 This is a schematic diagram of the structure of a semiconductor memory.

[0044] Figure 2 This is a schematic diagram of the structure of a memory cell in a semiconductor memory.

[0045] Figure 3 A flowchart illustrating a testing method for a semiconductor memory provided in this disclosure;

[0046] Figure 4 This is a test schematic diagram of a semiconductor memory provided in this disclosure;

[0047] Figure 5A This is another test schematic diagram of a semiconductor memory provided in this disclosure;

[0048] Figure 5B This is yet another test schematic diagram of a semiconductor memory provided in this disclosure;

[0049] Figure 6A This is another test schematic diagram of a semiconductor memory provided in this disclosure;

[0050] Figure 6B This is yet another test schematic diagram of a semiconductor memory provided in this disclosure;

[0051] Figure 7 This is another test schematic diagram of a semiconductor memory provided in this disclosure;

[0052] Figure 8 This is a schematic diagram of the structure of a semiconductor memory testing device provided in this disclosure.

[0053] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0054] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0055] like Figure 1 As shown, a semiconductor memory includes multiple memory blocks 100 and multiple sensitive amplifiers 140, with the memory blocks 100 arranged in an array. Multiple columns of sensitive amplifiers are also arranged in an array. Each column of sensitive amplifiers is located between two adjacent memory blocks 100.

[0056] Each memory block 100 includes multiple bit lines 130, multiple word lines 120, and multiple arrayed memory cells 110. Memory cells 110 in the same column are connected to the same word line 120, and memory cells 110 in the same row are connected to the same bit line 130.

[0057] Based on the arrangement order of the sensitive amplifiers in each column, each column of sensitive amplifiers is divided into odd-numbered column sensitive amplifiers and even-numbered column sensitive amplifiers.

[0058] In each memory block, the bit lines 130 are divided into even-numbered bit lines 130 and odd-numbered bit lines 130 according to their arrangement order.

[0059] In each memory block, the even-numbered bit line 130 is connected to a sensitive amplifier 140 in the even-numbered column of sensitive amplifiers. The other bit line connected to the sensitive amplifier 140 is in the adjacent memory block. That is, the complementary bit line corresponding to the even-numbered bit line is in the adjacent memory block, and the memory cell on the even-numbered bit line 130 is called the even-numbered memory cell.

[0060] In each memory block, the odd-numbered bit line 130 is connected to a sensitive amplifier 140 in the odd-numbered column of sensitive amplifiers. The other bit line connected to the sensitive amplifier 140 is in the adjacent memory block. That is, the complementary bit line corresponding to the odd-numbered bit line is in the adjacent memory block, and the memory cell on the odd-numbered bit line 130 is called the odd-numbered memory cell.

[0061] By stopping the even-numbered column of sensitive amplifiers, the data in storage cell 110 on the even-numbered bit line 130 of storage block 100 can be prevented from being amplified. By stopping the odd-numbered column of sensitive amplifiers, the data in storage cell 110 on the odd-numbered bit line 130 of storage block 100 can be prevented from being amplified.

[0062] For example, the memory includes four memory blocks and three columns of sensitive amplifiers, labeled sequentially as Block 0, Block 1, Block 2, and Block 3. The three columns of sensitive amplifiers are labeled sequentially as SA0, SA1, and SA2.

[0063] Each memory block includes a first bit line BL0, a second bit line BL1, a third bit line BL2, a fourth bit line BL3, a fifth bit line BL4, a sixth bit line BL5, and a seventh bit line BL6.

[0064] Each memory block includes a first word line WL0, a second word line WL1, a third word line WL2, a fourth word line WL3, a fifth word line WL4, a sixth word line WL5, a seventh word line WL6, and an eighth word line WL7.

[0065] Taking the second memory block, Block 1, as an example, the first bit line BL0 is connected to the first sensitive amplifier in the first column of sensitive amplifiers, SA0. The other bit line connected to the first sensitive amplifier in the first column of sensitive amplifiers, SA0, is also in the first memory block, Block 0. The third bit line BL2 is connected to the second sensitive amplifier in the first column of sensitive amplifiers, SA0. The other bit line connected to the second sensitive amplifier in the first column of sensitive amplifiers, SA0, is also in the first memory block, Block 0. The fifth bit line BL4 is connected to the third sensitive amplifier in the first column of sensitive amplifiers, SA0. The other bit line connected to the third sensitive amplifier in the first column of sensitive amplifiers, SA0, is also in the first memory block, Block 0. The seventh bit line BL6 is connected to the fourth sensitive amplifier in the first column of sensitive amplifiers, SA0. The other bit line connected to the fourth sensitive amplifier in the first column of sensitive amplifiers, SA0, is also in the first memory block, Block 0.

[0066] The second bit line BL1 is connected to the first sensitive amplifier in the second column of sensitive amplifiers SA1. The other bit line connected to the first sensitive amplifier in the second column of sensitive amplifiers SA1 is in the third memory block, Block 2. The fourth bit line BL3 is connected to the second sensitive amplifier in the second column of sensitive amplifiers SA1. The other bit line connected to the second sensitive amplifier in the second column of sensitive amplifiers SA1 is in the third memory block, Block 2. The sixth bit line BL5 is connected to the third sensitive amplifier in the second column of sensitive amplifiers SA1. The other bit line connected to the third sensitive amplifier in the second column of sensitive amplifiers SA1 is in the third memory block, Block 2.

[0067] In some embodiments, the first column of sensitive amplifiers SA0 and the third column of sensitive amplifiers SA2 are referred to as the even-numbered sensitive amplifiers, and the second column of sensitive amplifiers SA1 is referred to as the odd-numbered sensitive amplifiers.

[0068] Accordingly, the first bit line BL0, the third bit line BL2, the fifth bit line BL4, and the seventh bit line BL6 are called the even-numbered bit lines. The second bit line BL1, the fourth bit line BL3, and the sixth bit line BL5 are called the odd-numbered bit lines.

[0069] Accordingly, the first character line WL0, the third character line WL2, ... and the seventh character line WL6 are called the even-numbered character lines, and the second character line WL2, the fourth character line WL3, ... and the eighth character line WL7 are called the odd-numbered character lines.

[0070] In some embodiments, the first column of sensitive amplifiers SA0 and the third column of sensitive amplifiers SA2 are referred to as the odd-numbered sensitive amplifiers, and the second column of sensitive amplifiers SA1 is referred to as the even-numbered sensitive amplifier.

[0071] Accordingly, the first bit line BL0, the third bit line BL2, the fifth bit line BL4, and the seventh bit line BL6 are called the odd-numbered bit lines. The second bit line BL1, the fourth bit line BL3, and the sixth bit line BL5 are called the even-numbered bit lines.

[0072] Accordingly, the first character line WL0, the third character line WL2, ... and the seventh character line WL6 are called the odd-numbered character lines, and the second character line WL2, the fourth character line WL3, ... and the eighth character line WL7 are called the even-numbered character lines.

[0073] like Figure 2 As shown, a memory cell 110 is a structure consisting of a transistor T1 and a capacitor C1. The drain of transistor T1 is connected to the bit line, the source of transistor T1 is connected to the lower plate of the capacitor, the upper plate of capacitor C1 is connected to a fixed power supply, and the gate of transistor T1 is connected to the word line 140.

[0074] However, very slight leakage current often exists between adjacent memory cells, and this leakage current can worsen into severe leakage current over time, causing the memory cells to fail.

[0075] To detect memory cells with slight leakage, we refer to these cells as target cells. Typically, this requires subjecting the target cell and its adjacent cells to a prolonged period of high-voltage leakage. When the target and adjacent cells are on different word lines (i.e., in different columns), leakage testing can maintain the high-voltage difference between them by continuously refreshing the word lines of the adjacent cells.

[0076] However, if the adjacent memory cell and the target memory cell are located on the same word line, that is, in the same column, refreshing the word line will not create a high voltage difference between the adjacent memory cell and the target memory cell. Therefore, existing methods of refreshing the word line cannot test for leakage current between two memory cells on the same word line.

[0077] This disclosure provides a testing method and apparatus for a semiconductor memory. Word lines are divided into spaced-apart marked word lines and unmarked word lines. Test data is stored in the memory block, ensuring that the test data is different for adjacent memory cells on each marked word line, and the test data is the same for each memory cell on each unmarked word line. By activating a sensitive amplifier connected to each bit line in the memory block, and activating sensitive amplifiers connected to all bit lines in the memory block when refreshing the surrounding word lines of the target word line, a voltage difference is created between the memory cells on the target word line and the memory cells on the surrounding word lines. Furthermore, when refreshing the target word line, one of the sensitive amplifiers connected to two adjacent bit lines in the memory block is deactivated while the other is activated. This creates a voltage difference between two adjacent memory cells on the same word line, producing an environment more prone to leakage, thus enabling leakage current testing between two memory cells on the same word line.

[0078] like Figure 3 As shown, one embodiment of this disclosure provides a method for testing a semiconductor memory, the method comprising the following steps:

[0079] S101. Write test data into the storage block.

[0080] In this step, the storage block includes multiple marker word lines and multiple unmarked word lines. The marker word lines and unmarked word lines are spaced apart.

[0081] The word lines arranged from left to right in a memory block are called the first word line WL0, the second word line WL1, ... and the (N+1)th word line WLn.

[0082] Then, the first word line WL0, the third word line WL2, ... and the 2kth word line WL2k are marked word lines, where k is an integer. The second word line WL2, the fourth word line WL3, ... and the 2k+1th word line WL2k+1 are unmarked word lines.

[0083] The test data is different in two adjacent memory cells on each marked word line. The test data is the same in each memory cell on each unmarked word line.

[0084] For example, on a marker word line, one of two adjacent memory cells stores the data "1", and the other stores the data "0". On a non-marker word line, each memory cell stores either the data "0" or the data "1".

[0085] S102, refresh the test data in the memory cells on the word lines surrounding the target word line, and control the sensitive amplifier connected to each bit line in the memory block to be in the enabled state.

[0086] Among them, a target word line is selected from multiple marked word lines, and word lines adjacent to the target word line or word lines separated from the target word line by multiple word lines are taken as word lines surrounding the target word line, and the test data in the storage unit on the word lines surrounding the target word line is refreshed.

[0087] In some embodiments, the character lines adjacent to the target character line or the character lines separated from the target character line by one character line are defined as the character lines surrounding the target character line. For example, the target character line is the third character line, and the character lines surrounding the target character line are the second, fourth, and fifth character lines.

[0088] The target word line is selected from multiple marker word lines. The test data stored in two adjacent memory cells on the target word line is different from the test data stored in each memory cell on each adjacent word line. This creates a voltage difference between two adjacent memory cells on the target word line, and also creates a voltage difference between the memory cells on the target word line and the memory cells on the surrounding word lines. The memory cells on the surrounding word lines are refreshed, enabling the sensitive amplifier connected to each bit line in the memory block, maintaining the voltage difference between the memory cells on the target word line and the memory cells on the surrounding word lines, and creating an environment on the target word line that is more prone to leakage.

[0089] S103. Refresh the test data in the memory cell on the target word line, enable the sensitive amplifier connected to one of the two adjacent bit lines in the memory block, and disable the sensitive amplifier connected to the other bit line in the two adjacent bit lines of the memory block.

[0090] In this step, the sensitive amplifier connected to one of the two adjacent bit lines in the control block is enabled. The bit line connected to the enabled sensitive amplifier is called the first target bit line. When the first target bit line is active, it activates the target word line. The sensitive amplifier amplifies the data in the memory cell jointly controlled by the first target bit line and the target word line, causing the potential on the first target bit line to rise to the power supply voltage or fall to ground voltage. Conversely, the sensitive amplifier connected to the other bit line in the control block is disabled. The bit line connected to the disabled sensitive amplifier is called the second target bit line. When the second target bit line is inactive, the sensitive amplifier cannot amplify the data in the memory cell jointly controlled by the second target bit line and the target word line, maintaining the potential on the second target bit line at the voltage after charge sharing.

[0091] Furthermore, since the first target bit line and the second target bit line are adjacent bit lines, the difference between the charge-shared voltage and the power supply voltage is relatively large, or the difference between the charge-shared voltage and the ground voltage is relatively large. This configuration creates a large voltage difference between two adjacent memory cells on the target word line, creating an environment more prone to leakage. Additionally, by controlling the sensitive amplifier connected to the second target bit line within the memory block to be in a disabled state, channel leakage within the memory cells on the second target bit line is reduced, thus enabling leakage detection between two adjacent memory cells on the target word line.

[0092] S104. Read data from the storage unit on the target word line, and obtain the test result based on the read data and the test data in the storage unit on the target word line.

[0093] Specifically, by creating an environment more prone to leakage between two adjacent memory cells on the target word line, the test data within the memory cells on the target word line will change if leakage exists between them. Data is read from the memory cells on the target word line and compared with the test data. If they match, it is determined that there is no leakage between the memory cells on the target word line. If they do not match, it is determined that there is leakage between the memory cells on the target word line.

[0094] In the above technical solution, test data is stored in the memory block to make the data different between two adjacent memory cells on a marked word line and the data the same between two adjacent memory cells on a non-marked word line. A target word line is selected from the marked word lines, and the test data stored in the two adjacent memory cells on the target word line are different. The memory cells on the word lines surrounding the target word line are refreshed, enabling the sensitive amplifier connected to each bit line in the memory block, maintaining the voltage difference between the memory cells on the target word line and the memory cells on the surrounding word lines, creating an environment more prone to leakage on the target word line. The memory cells on the target word line are refreshed again, controlling the sensitive amplifier connected to one bit line of two adjacent bit lines in the memory block to be enabled and the sensitive amplifier connected to the other bit line to be disabled, forming a larger voltage difference between the two adjacent memory cells on the target word line, creating an environment more prone to leakage between the two adjacent memory cells on the same word line, and suppressing channel leakage within the memory cell. Finally, by reading the test data of the memory cells on the target word line, the test result is determined based on the read data and the test data, realizing the leakage test of the memory cells on the same word line.

[0095] One embodiment of this disclosure provides a testing method for a semiconductor memory, the testing method comprising the following steps:

[0096] S201. Write test data into the storage block.

[0097] The storage block consists of multiple marker word lines and multiple unmarked word lines. The marker word lines and unmarked word lines are spaced apart.

[0098] The first data is stored in the even-numbered storage unit on each tag word line, the second data is stored in the odd-numbered storage unit on each tag word line, and the second data is stored in each storage unit on each non-tag word line.

[0099] The bit line is divided into an even-numbered bit line and an odd-numbered bit line. The first part of the storage cells on the even-numbered bit line stores the first data, and the second part stores the second data. Each storage cell on the odd-numbered bit line stores the second data.

[0100] Specifically, when the first data is stored in the memory cell, the voltage of the lower plate of the capacitor in the memory cell is greater than or equal to the first reference voltage. When the second data is stored in the memory cell, the voltage of the lower plate of the capacitor in the memory cell is less than the first reference voltage. The first reference voltage is the pre-charge voltage of the bit line and the complementary bit line. That is, the first data represents the data "1", and the second data represents the data "0".

[0101] Table 1 and Figure 4The word lines arranged from left to right in the memory block are called the first word line WL0, the second word line WL1, ..., and the eighth word line WL7. The first word line WL0, the third word line WL2, ..., and the seventh word line WL6 are called the even-numbered word lines, and the second word line WL2, the fourth word line WL3, ..., and the eighth word line WL7 are called the odd-numbered word lines.

[0102] The even-numbered memory cell on the even-numbered word line stores the data "1", and the odd-numbered memory cell on the even-numbered word line stores the data "0". The data stored in each memory cell on the odd-numbered word line is "0".

[0103] Table 1 Test Data

[0104] BL0 1 0 1 0 1 0 1 0 BL1 0 0 0 0 0 0 0 0 BL2 1 0 1 0 1 0 1 0 BL3 0 0 0 0 0 0 0 0 BL4 1 0 1 0 1 0 1 0 BL5 0 0 0 0 0 0 0 0 BL6 1 0 1 0 1 0 1 0

[0105] S202, refresh the test data in the memory cells on the word lines surrounding the target word line, and control the sensitive amplifier connected to each bit line in the memory block to be in the enabled state.

[0106] In this step, the test data in the storage cells on the word lines surrounding the target word line is refreshed, specifically including the following steps:

[0107] S31, Increase the voltage of the upper plate of the memory cell on the target word line.

[0108] Specifically, when the voltage of the upper plate of the memory cell on the target word line is increased, the voltage of the lower plate of the memory cell also changes abruptly, maintaining a constant voltage difference between the upper and lower plates. By increasing the voltage of the memory cell on the target word line, the voltage difference between the memory cell on the target word line and the memory cells on surrounding word lines is increased, creating an environment on the target word line where leakage is more likely to occur.

[0109] For example, when the voltage of the upper plate of a memory cell is 0.5V, the voltage of the lower plate is 1.0V, indicating that the memory cell contains the data "1". When the voltage of the upper plate of a memory cell is 0.5V, the voltage of the lower plate is 0V, indicating that the memory cell contains the data "0".

[0110] When the voltage of the upper plate of the memory cell on the target word line is increased to 1.0V, the voltage of the lower plate of the memory cell storing data "1" becomes 1.5V, and the voltage of the lower plate of the memory cell storing data "0" is 0.5V.

[0111] like Figure 5A As shown, without raising the voltage of the upper plate of the memory cell on the target word line, the voltage difference between the memory cell on the target word line and the memory cells on the surrounding word lines is 1V. Figure 5BAs shown, after increasing the voltage of the upper plate of the memory cell on the target word line, the voltage difference between the memory cell on the target word line and the memory cells on the surrounding word lines is 1.5V. This increases the voltage difference between the memory cell on the target word line and the memory cells on the surrounding word lines, creating an environment on the target word line where leakage is more likely to occur.

[0112] S32. Activate the word lines around the target word line and enable the sensitive amplifier connected to each bit line in the memory block.

[0113] In this configuration, the pre-charge voltage of each bit line in the control memory block and the pre-charge voltage of the corresponding complementary bit line are both used as the first reference voltage. The word lines surrounding the target word line are activated, enabling charge sharing between the memory cells on these surrounding word lines and the bit lines. This creates a charge-sharing voltage on the bit lines and the complementary bit lines, which is then amplified by a sensitive amplifier. This setup maintains the voltage difference between the memory cells on the target word line and the memory cells on the surrounding word lines, creating an environment on the target word line where leakage is more likely to occur.

[0114] In some embodiments, the four character lines containing the target character line are grouped together, and three of the non-target character lines are selected as character lines surrounding the target character line for activation.

[0115] Assuming the target character line is the first or last character line, for example, if the target character line is the first character line WL0, select the character lines on one side of the target character line, group the first character line WL0, the second character line WL1, the second character line WL2, and the third character line WL3 together, and then activate the second character line WL1, the second character line WL2, and the third character line WL3.

[0116] Assuming the target character line is not the first or last character line, for example, if the target character line is the third character line WL2, select the character lines on both sides of the third character line WL2, and group the first character line WL0, the second character line WL1, the second character line WL2, and the third character line WL3 together, and then activate the second character line WL1, the second character line WL2, and the third character line WL3.

[0117] S33. Restore the voltage of the upper plate of the memory cell on the target word line.

[0118] After activating the word lines around the target word line, enabling charge sharing between the memory cells on the word lines around the target word line and the bit lines, and controlling the sensitive amplifier to amplify the charge-sharing voltage on the bit lines and complementary bit lines, the upper plate voltage of the memory cells on the target word line is restored to its original value.

[0119] For example, if the voltage of the lower plate of the memory cell is increased from 0.5V to 1.0V, then the voltage of the lower plate of the memory cell is restored from 1.0V to 0.5V.

[0120] S203. Refresh the test data in the memory cell on the target word line, enable the sensitive amplifier connected to one of the two adjacent bit lines in the memory block, and disable the sensitive amplifier connected to the other bit line in the two adjacent bit lines of the memory block.

[0121] In this step, the target word line is activated, the even-numbered bit line connected to the sensitive amplifier is enabled, and the odd-numbered bit line connected to the sensitive amplifier is disabled.

[0122] In some embodiments, such as Figure 6A As shown, the pre-charge voltage of the even-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the even-numbered bit line are both second reference voltages, wherein the first reference voltage is less than the second reference voltage. The target word line is activated, causing the even-numbered memory cell jointly controlled by the target word line and the even-numbered bit line to share charge with the even-numbered bit line. A sensitive amplifier is then used to amplify the charge-sharing voltage between the even-numbered bit line and its corresponding complementary bit line, raising the voltage of the even-numbered bit line to the power supply voltage.

[0123] like Figure 6B As shown, the pre-charge voltage of the odd-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the odd-numbered bit line are both ground voltages, which are less than the second reference voltage. The target word line is activated, causing the odd-numbered memory cells controlled by the target word line and the odd-numbered bit line to share charge with the odd-numbered bit line. The sensitive amplifier is then controlled to stop amplifying the charge-sharing voltage between the odd-numbered bit line and its corresponding complementary bit line, causing the voltage of the odd-numbered bit line to drop to the ground voltage.

[0124] like Figure 7 As shown, curve 1 represents the potential of the storage cell storing data "1" on the target word line, and this storage cell is marked as the first storage cell. Curve 2 represents the potential of the storage cell storing data "0" on the target word line, and this storage cell is marked as the second storage cell. The first storage cell and the second storage cell are two adjacent storage cells on the same word line.

[0125] Before the target word line is activated, that is, during the idle period, the word line is in the off state. The charge of the first memory cell continues to decrease due to leakage, and the charge of the second memory cell continues to increase due to leakage. At the end of the idle period, the voltage difference between the first memory cell and the second memory cell is ΔV1.

[0126] After the target word line is activated and during the charge sharing period (SDT), the first memory cell shares charge with the bit line, and the charge decreases further. Since the pre-charge voltage on the bit line is the second reference voltage, which is greater than 0.5 times the power supply voltage, compared to the case where the pre-charge voltage on the bit line is the first reference voltage, the charge decrease rate on the first memory cell is slower when the first memory cell shares charge with the bit line where the pre-charge voltage is the second reference voltage.

[0127] After the target word line is activated, the second memory cell shares charge with the bit line. Since the pre-charge voltage of the bit line is the ground voltage, the voltage of the second memory cell drops to the ground voltage.

[0128] During charge sharing time (SDT), the voltage difference between the first and second memory cells is ΔV2. By setting the bit line precharge voltage connected to the first memory cell to the second reference voltage and the bit line precharge voltage connected to the second memory cell to the ground voltage, the voltage difference ΔV2 between the first and second memory cells during charge sharing time is greater than the voltage difference ΔV1 between the first and second memory cells during idle time, further creating an environment that makes leakage between the two memory cells more likely.

[0129] In some embodiments, the starting moment when the delay sensitive amplifier amplifies the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line, which is the time of delayed charge sharing, increases the duration of the voltage difference between two adjacent memory cells on the target word line, further deteriorates the leakage environment between the two memory cells, and can also reduce the signal margin of the memory cells on the target word line, making it difficult to read the first data in the memory cell.

[0130] S204. Read data from the storage unit on the target word line, and obtain the test result based on the read data and the test data in the storage unit on the target word line.

[0131] In the above technical solution, the voltage of the lower plate of the capacitor in the memory cell on the target word line is increased, and the test data in the memory cells on the surrounding word lines is refreshed, creating a larger voltage difference between the memory cell on the target word line and the memory cells on the surrounding word lines. Refreshing the test data in the memory cell on the target word line involves controlling one of the sensitive amplifiers connected to two adjacent bit lines in the memory block to be enabled, while the other sensitive amplifier is disabled. The even-numbered bit line pre-charge voltage is set to the second reference voltage, and the odd-numbered bit line pre-charge voltage is set to ground voltage. This increases the duration of charge sharing, creating an environment more prone to leakage between the two adjacent memory cells on the target word line, suppressing channel leakage in the memory cell, making it difficult to read the first data in the memory cell, and facilitating the testing of leakage between two adjacent memory cells on the same word line.

[0132] like Figure 8 As shown, another embodiment of this disclosure provides a test apparatus for a semiconductor memory. The test apparatus 400 includes:

[0133] The write module 401 is used to write test data into the storage block, wherein the storage block includes multiple marker word lines and multiple unmarked word lines, the marker word lines and unmarked word lines are set alternately, the test data in two adjacent storage cells on each marker word line is different, and the test data in each storage cell on each unmarked word line is the same;

[0134] The refresh module 402 is used to refresh the test data in the storage cells on the word lines surrounding the target word line and to control the sensitive amplifier connected to each bit line in the storage block to be in an enabled state; wherein, the target word line is one of the marker word lines;

[0135] The refresh module 402 is also used to refresh the test data in the memory cell on the target word line, control the sensitive amplifier connected to one of the two adjacent bit lines in the memory block to be in an enabled state, and control the sensitive amplifier connected to the other bit line of the two adjacent bit lines in the memory block to be in a disabled state.

[0136] The comparison module 403 is used to read data from the storage unit on the target word line and obtain the test result based on the read data and the test data in the storage unit on the target word line.

[0137] In some embodiments, first data is stored in the even-numbered storage unit on each tag word line; second data is stored in the odd-numbered storage unit on each tag word line; and second data is stored in each storage unit on each non-tag word line.

[0138] In some embodiments, when the storage cell stores first data, the voltage of the lower plate of the capacitor in the storage cell is greater than or equal to the first reference voltage; when the storage cell stores second data, the voltage of the lower plate of the capacitor in the storage cell is less than the first reference voltage.

[0139] In some embodiments, the refresh module 402 is specifically used for:

[0140] Activate the target word line to enable the sensitive amplifier connected to the even-numbered bit line, and disable the sensitive amplifier connected to the odd-numbered bit line.

[0141] In some embodiments, the refresh module 402 is specifically used for:

[0142] The pre-charge voltage of the even-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the even-numbered bit line are both controlled to be the second reference voltage, thereby activating the target word line and controlling the sensitive amplifier to amplify the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line; wherein, the first reference voltage is less than the second reference voltage;

[0143] The pre-charge voltage of the odd-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the odd-numbered bit line are both grounded, the target word line is activated, and the sensitive amplifier is controlled to stop amplifying the charge-sharing voltage between the odd-numbered bit line and the complementary bit line corresponding to the odd-numbered bit line; wherein, the grounded voltage is less than the second reference voltage.

[0144] In some embodiments, the refresh module 402 is specifically used for:

[0145] The delay-sensitive amplifier amplifies the charge-sharing voltage between the even-numbered bit line and its corresponding complementary bit line at the start time, increasing the duration of the voltage difference between two adjacent memory cells on the target word line.

[0146] In some embodiments, the refresh module 402 is specifically used for:

[0147] Increase the voltage of the upper plate of the memory cell on the target word line;

[0148] Activate the word lines around the target word line and enable the sensitive amplifier connected to each bit line in the memory block;

[0149] Restore the voltage of the upper plate of the memory cell on the target word line.

[0150] In some embodiments, the refresh module 402 is specifically used for:

[0151] The pre-charge voltage of each bit line in the memory block and the pre-charge voltage of the complementary bit line corresponding to each bit line are both controlled to be a first reference voltage, thereby activating the word lines around the target word line, and controlling a sensitive amplifier to amplify the charge-sharing voltage between each bit line in the memory block and the complementary bit line corresponding to each bit line; wherein, the first reference voltage is less than the second reference voltage.

[0152] This disclosure also provides a control device for implementing the steps in the methods described above.

[0153] This disclosure also provides a computer-readable storage medium storing computer instructions, which, when executed by a processor, implement the steps of the methods described above.

[0154] This disclosure also provides a computer program product, including computer instructions that, when executed by a processor, implement the steps of the methods described above.

[0155] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0156] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A testing method for a semiconductor memory, characterized in that, include: Test data is written into a storage block, wherein the storage block includes multiple marker word lines and multiple unmarked word lines, the marker word lines and the unmarked word lines are spaced apart, the test data in two adjacent storage cells on each marker word line is different, and the test data in each storage cell on each unmarked word line is the same; Refresh the test data in the storage cells on the word lines surrounding the target word line, and enable the sensitive amplifier connected to each bit line in the storage block; wherein, the target word line is one of the marker word lines; Refresh the test data in the memory cell on the target word line, enable the sensitive amplifier connected to one of the two adjacent bit lines in the memory block, and disable the sensitive amplifier connected to the other bit line of the two adjacent bit lines in the memory block. Data is read from the storage unit on the target word line, and test results are obtained based on the read data and the test data in the storage unit on the target word line.

2. The test method according to claim 1, characterized in that, First data is stored in the even-numbered storage unit on each of the marker word lines; second data is stored in the odd-numbered storage unit on each of the marker word lines; and the second data is stored in each storage unit on each of the non-mark word lines.

3. The test method according to claim 2, characterized in that, When the first data is stored in the storage unit, the voltage of the lower plate of the capacitor in the storage unit is greater than or equal to the first reference voltage; when the second data is stored in the storage unit, the voltage of the lower plate of the capacitor in the storage unit is less than the first reference voltage.

4. The test method according to claim 2, characterized in that, Refresh the test data in the memory cell on the target word line, enable the sensitive amplifier connected to one of the two adjacent bit lines in the memory block, and disable the sensitive amplifier connected to the other bit line of the two adjacent bit lines in the memory block. Specifically, this includes: Activate the target word line, control the sensitive amplifier connected to the even-numbered bit line to be in an enabled state, and control the sensitive amplifier connected to the odd-numbered bit line to be in a disabled state.

5. The test method according to claim 4, characterized in that, Activating the target word line enables the sensitive amplifier connected to the even-numbered bit line and disables the sensitive amplifier connected to the odd-numbered bit line, specifically including: The pre-charge voltage of the even-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the even-numbered bit line are both controlled to be the second reference voltage, thereby activating the target word line and controlling the sensitive amplifier to amplify the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line; wherein, the first reference voltage is less than the second reference voltage; The target word line is activated by controlling the pre-charge voltage of the odd-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the odd-numbered bit line to be ground voltage, and the sensitive amplifier is controlled to stop amplifying the charge-sharing voltage between the odd-numbered bit line and the complementary bit line corresponding to the odd-numbered bit line; wherein the ground voltage is less than the second reference voltage.

6. The test method according to claim 5, characterized in that, The control of the sensitive amplifier amplifies the charge-sharing voltage between the even-numbered bit line and its corresponding complementary bit line, specifically including: The delay is used to amplify the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line, thereby increasing the duration of the voltage difference between two adjacent memory cells on the target word line.

7. The test method according to any one of claims 1 to 6, characterized in that, The test data in the storage units on the word lines surrounding the target word line that is being refreshed specifically includes: Increase the voltage of the upper plate of the memory cell on the target word line; Activate the word lines around the target word line and enable the sensitive amplifier connected to each bit line in the memory block; Restore the voltage of the upper plate of the memory cell on the target word line.

8. The test method according to claim 7, characterized in that, Activating word lines around the target word line and controlling the sensitive amplifier connected to each bit line in the memory block, specifically including: The pre-charge voltage of each bit line in the memory block and the pre-charge voltage of the complementary bit line corresponding to each bit line are both controlled to be a first reference voltage, thereby activating the word lines around the target word line, and controlling a sensitive amplifier to amplify the charge-sharing voltage between each bit line in the memory block and the complementary bit line corresponding to each bit line; wherein, the first reference voltage is less than the second reference voltage.

9. A testing apparatus for a semiconductor memory, characterized in that, include: The write module writes test data into a storage block, wherein the storage block includes multiple marker word lines and multiple unmarked word lines, the marker word lines and the unmarked word lines are spaced apart, the test data in two adjacent storage cells on each marker word line is different, and the test data in each storage cell on each unmarked word line is the same; A refresh module is used to refresh the test data in the storage cells on the word lines surrounding the target word line, and to control the sensitive amplifier connected to each bit line in the storage block to be in an enabled state; wherein, the target word line is one of the marker word lines; The refresh module is also used to refresh the test data in the storage unit on the target word line, control the sensitive amplifier connected to one of the two adjacent bit lines in the storage block to be in an enabled state, and control the sensitive amplifier connected to the other bit line of the two adjacent bit lines in the storage block to be in a disabled state. The comparison module is used to read data from the storage unit on the target word line and obtain a test result based on the read data and the test data in the storage unit on the target word line.

10. The testing apparatus according to claim 9, characterized in that, First data is stored in the even-numbered storage unit on each tag word line; second data is stored in the odd-numbered storage unit on each tag word line; and the second data is stored in each storage unit on each non-tag word line.

11. The testing apparatus according to claim 10, characterized in that, When the storage unit stores the first data, the voltage of the lower plate of the capacitor in the storage unit is greater than or equal to the first reference voltage; when the storage unit stores the second data, the voltage of the lower plate of the capacitor in the storage unit is less than the first reference voltage.

12. The testing apparatus according to claim 10, characterized in that, The refresh module is specifically used for: Activate the target word line, control the sensitive amplifier connected to the even-numbered bit line to be in an enabled state, and control the sensitive amplifier connected to the odd-numbered bit line to be in a disabled state.

13. The testing apparatus according to claim 12, characterized in that, The refresh module is specifically used for: The pre-charge voltage of the even-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the even-numbered bit line are both controlled to be the second reference voltage, thereby activating the target word line and controlling the sensitive amplifier to amplify the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line; wherein, the first reference voltage is less than the second reference voltage; The target word line is activated by controlling the pre-charge voltage of the odd-numbered bit line and the pre-charge voltage of the complementary bit line corresponding to the odd-numbered bit line to be ground voltage, and the sensitive amplifier is controlled to stop amplifying the charge-sharing voltage between the odd-numbered bit line and the complementary bit line corresponding to the odd-numbered bit line; wherein the ground voltage is less than the second reference voltage.

14. The testing apparatus according to claim 13, characterized in that, The refresh module is specifically used for: The delay is used to amplify the charge-sharing voltage between the even-numbered bit line and the complementary bit line corresponding to the even-numbered bit line, thereby increasing the duration of the voltage difference between two adjacent memory cells on the target word line.

15. A control device, characterized in that, Used to perform the method as described in any one of claims 1 to 8.

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