Simulation Detection Method for Dynamic Conditioning of Detector Serial Image Data

By changing the correspondence between the count value and data bit of the serial data transmitter and using a simulation detection system to perform dynamic correction training of the CMOS detector, the problem of unstable data transmission caused by the timing reset signal is solved, ensuring the accuracy and stability of image data in harsh environments.

CN117939315BActive Publication Date: 2025-09-09CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI
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Patent Information

Application Number
CN202410107341.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-01-25
Publication Date
2025-09-09
Estimated Expiration
2044-01-25

AI Technical Summary

Technical Problem

In a high-energy particle environment, the phase change of the timing reset signal of the CMOS detector causes the starting position of the serial image data transmission to be unstable, requiring dynamic word correction and channel correction, but the correctness of the existing detection method needs to be verified.

Method used

By changing the correspondence between the count value and data bit of the serial data transmitter, the data transmission process in the training stage and the imaging stage is simulated by the simulation detection system. The dynamic correction training is carried out using the imaging controller and the detector simulator to determine whether the delay position of each channel is stable. The synchronous and asynchronous data are output to correct the data combination mode.

Benefits of technology

It avoids timing reset errors during the full-state conditioning process in the training phase, ensures that image data in different spectral bands work normally under different line periods, covers all states of actual applications, and improves the data transmission accuracy of the detector in harsh space environments.

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Abstract

The present invention relates to the field of CMOS detectors, and more particularly to a simulation detection method for dynamic conditioning of detector serial image data. The method simulates a change in the serial data combination mode caused by a timing reset by changing the corresponding relationship between the count value of a serial data transmitter and the data bit. During the detector training phase, the method detects the full state conditioning process and sends constant training words and single training word serial data in a step-by-step manner. During the non-training imaging phase, whenever a line synchronization (SYNC) signal pulse is detected, four synchronization words are sequentially output, followed by non-synchronization word data, and the corresponding relationship between the count value of the serial data transmitter and the data bit is changed once. The method detects the full state conditioning process during the training phase and sends constant training words and single training word serial data in a step-by-step manner, thereby preventing errors in the normal training state caused by changes in the serial data sequence due to the simulated timing reset.
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Description

Technical Field

[0001] The present invention relates to the technical field of CMOS detectors, and in particular to a simulation detection method for dynamic conditioning of detector serial image data. Background Art

[0002] When CMOS detectors are used in orbit, especially in harsh space environments, they are prone to high-energy particles that can disrupt the detector's internal logic and cause timing errors. One way to improve adaptability to the space environment is to perform a timing reset on the detector for each line of imaging. For high-frequency, high-power, and fast-heating detectors, there may be a significant difference between the temperature during conditioning of the detector serial image data and the temperature during the imaging process. As the ambient temperature changes, when the timing reset is performed for each line, the phase of the detector timing reset signal changes, which may cause the transmission start position of the output serial image data to change. Therefore, dynamic word correction and channel correction operations need to be performed on each line of the serial data output by the detector. The method of dynamically correcting the combination of serial data based on the detection of synchronization words can overcome the data combination errors caused by the timing reset signal, but the correctness of the relevant implementation method needs to be tested and verified. Summary of the Invention

[0003] In view of the above problems, the present invention proposes a simulation detection method for dynamic conditioning of detector serial image data. The method simulates the change in the serial data combination mode caused by timing reset by changing the corresponding relationship between the count value of the serial data transmitter and the data bit. During the detector training phase, the full state conditioning process is detected, and constant training words and single training word serial data are sent in accordance with the steps. During the non-training imaging phase, whenever a line synchronization (SYNC) signal pulse is detected, four synchronization words are output in sequence, followed by the data of the non-synchronous word, and the corresponding relationship between the count value of the serial data transmitter and the data bit is changed once.

[0004] The simulation detection method for dynamic conditioning of detector serial image data provided by the present invention is implemented based on a simulation detection system, which includes an imaging controller and a detector simulator; wherein,

[0005] The imaging controller includes a dynamic correction training module, which outputs a serial clock, a training state signal, a multi-spectral line synchronization signal, a full-color line synchronization signal, a port delay control signal of each channel, and a training control signal to the detector simulator;

[0006] The detector simulator includes a full-color row synchronous receiving cycle counter, a multi-spectral row synchronous receiving cycle counter, a binary frequency divider, a full-color controllable parallel data source, a multi-spectral controllable parallel data source, a controllable full-color serial data source transmitter, and a controllable multi-spectral serial data source transmitter;

[0007] The detector simulator determines whether the delay position of each channel is in an unstable area based on the port delay control signal of each channel output by the dynamic correction training module;

[0008] The detector simulator returns the serial data's companion clock, multi-spectral serial data, and full-color serial data to the dynamic correction training module. The serial data's companion clock is obtained by dividing the serial clock output by the dynamic correction training module by a two-divider.

[0009] The simulation detection method includes:

[0010] When the training status signal received by the detector simulator is at a high level:

[0011] When the training control signal received by the detector simulator is at a valid level and the corresponding delay position is in a stable region, the full-color controllable parallel data source and the multi-spectral controllable parallel data source respectively output training words;

[0012] When the training control signal received by the detector simulator is at a valid level and the corresponding delay position is in an unstable region, the full-color controllable parallel data source and the multi-spectral controllable parallel data source respectively output parallel data different from the training word;

[0013] When the training control signal received by the detector simulator is at an invalid level, the full-color controllable parallel data source and the multi-spectral controllable parallel data source output parallel data different from the training word;

[0014] The count value of the transmission counter in the controllable full-color serial data source transmitter is the same as the number of bits of the parallel data sent into the controllable full-color serial data source transmitter, and the count value of the transmission counter in the controllable multi-spectral serial data source transmitter is the same as the number of bits of the parallel data sent into the controllable multi-spectral serial data source transmitter;

[0015] When the training status signal received by the detector simulator is at a low level:

[0016] After detecting the rising edge of the full-color line synchronization signal, the full-color controllable parallel data source first outputs four synchronization words and then outputs random parallel data different from the four synchronization words;

[0017] After detecting the rising edge of the multi-spectral row synchronization signal, the multi-spectral controllable parallel data source first outputs four synchronization words and then outputs random parallel data different from the four synchronization words;

[0018] The count value of the sending counter in the controllable full-color serial data source transmitter is the sum of the number of bits of random parallel data sent into the controllable full-color serial data source transmitter and the count value of the full-color row synchronous receiving cycle counter. The count value of the sending counter in the controllable multi-spectral serial data source transmitter is the sum of the number of bits of random parallel data sent into the controllable multi-spectral serial data source transmitter and the count value of the multi-spectral row synchronous receiving cycle counter.

[0019] Preferably, the number of count values ​​of the full-color row synchronization receiving loop counter is the same as the number of quantization bits n of the random parallel data output by the full-color controllable parallel data source, and is cyclically increased by 1 each time the rising edge of the full-color row synchronization signal is detected, and the count value varies in the range of 0 to n-1; the number of count values ​​of the multi-spectral row synchronization receiving loop counter is the same as the number of quantization bits n of the random parallel data output by the multi-spectral controllable parallel data source, and is cyclically increased by 1 each time the rising edge of the multi-spectral row synchronization signal is detected, and the count value varies in the range of 0 to n-1.

[0020] Preferably, the four synchronization words are different, the highest bit of the first synchronization word is 1, and the rest are 0; the lowest bit of the second synchronization word is 0, and the rest are 1; the third synchronization word is the inverse of the training word, and the fourth synchronization word is the inverse of the lowest bit of the training word.

[0021] Preferably, the detector simulator is established in a simulation test platform testbench in the FPGA software.

[0022] Preferably, the method for determining whether the delay position of each channel is in an unstable area is: performing continuous sampling at the delay position for a predetermined number of times, if all the sampling values ​​are equal, then the delay position is determined to be in a stable area, otherwise the delay position is determined to be in an unstable area.

[0023] Compared with the prior art, the present invention can achieve the following technical effects:

[0024] 1. During the training phase, the full state conditioning process is tested, and constant training words and single training word serial data are sent in steps to avoid errors in the normal training state caused by changes in the serial data sequence caused by the simulation timing reset;

[0025] 2. During the non-training phase, whenever a line synchronization signal pulse is detected, the four synchronization words are output in sequence, followed by the data of the non-synchronization words. The serial data sent is differentiated by spectrum segment, ensuring that image data of different spectrum segments can work properly when applied in different line cycles.

[0026] 3. The position of the output synchronization word can be set with multiple change rules, and various starting positions can be cycled to simulate all states of actual application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the logical structure of a traditional imaging system with a time sequence per line;

[0028] Figure 2 A schematic diagram of the logical structure of a simulation detection system provided according to an embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of a state when a training state signal is at a high level during a training phase according to an embodiment of the present invention;

[0030] Figure 4 3 is a schematic diagram of a state in which a training state signal is at a low level in a non-training imaging stage according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, identical modules are denoted by identical reference numerals. In the case of identical reference numerals, their names and functions are also identical. Therefore, their detailed description will not be repeated.

[0032] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation of the present invention.

[0033] Traditional imaging systems with sequential lines such as Figure 1 As shown, the imaging detector primarily comprises an imaging detector, a drive and control circuit, an imaging controller, a memory, and a data transmission interface circuit. The imaging controller provides a serial clock for the imaging detector. The drive and control signals generated by the imaging controller are fed into the imaging detector after passing through the drive and control circuit. The timing reset signal generated by the imaging controller resets the detector for each row. The training control signal generated by the controller controls the detector's training state. The full-color row synchronization signal, sync_p, and the multi-spectral row synchronization signal, sync_b, control the detector's output valid data. The digital image data output by the imaging detector is conditioned by the imaging controller and then output via the data transmission interface circuit. In the camera mode, each row first outputs four synchronization words, sync_code, followed by the photosensitive image data. These four synchronization words are all different: the first synchronization word has the most significant bit set to 1, and the remaining bits are 0; the second synchronization word has the least significant bit set to 0, and the remaining bits are 1; the third synchronization word is the inverse of the training word, and the fourth synchronization word is the inverse of the least significant bit of the training word.

[0034] The low level pulse of the timing reset signal clk_rst_n precedes the positive pulse of the horizontal synchronization signal sync_b of the b-spectrum (multi-spectral spectrum band).

[0035] As shown in Table 1, the timing reset signal clk_rst_n has only one low-level reset pulse during the power-on reset phase and is at a constant high level during the training phase. During the imaging phase of the output timing, a low-level reset pulse repeatedly appears for each b-spectrum timing sequence. This low-level reset pulse is generated before the positive pulse of sync_b of each b-spectrum.

[0036] Therefore, a word correction is required within each multispectral line cycle; each word correction is initiated using the multispectral sync_b signal. The full-color and multispectral data valid signals are not generated based on the full-color and multispectral line synchronization signals sync_p and sync_b. Instead, they are generated after detecting four synchronization words, sync_code (the four synchronization words are different: the first synchronization word has the most significant bit 1 and the remaining bits are 0; the second synchronization word has the least significant bit 0 and the remaining bits are 1; the third synchronization word is the training word with all bits inverted, and the fourth synchronization word is the training word with the least significant bit inverted).

[0037] Table 1 Status of timing reset signal at different stages

[0038]

[0039] The simulation detection method for dynamic conditioning of detector serial image data provided by the embodiment of the present invention is implemented based on a simulation detection system, such as Figure 2 As shown, the simulation detection system includes an imaging controller and a detector simulator; wherein the imaging controller includes a dynamic correction training module, which outputs a serial clock, a training status signal, a multi-spectral row synchronization sync_b signal, a full-color row synchronization sync_p signal, a port delay iodelay control signal of each channel, and a training control signal train to the detector simulator.

[0040] The detector simulator is established in the simulation test platform testbench in the FPGA software. The detector simulator returns the accompanying clock, multi-spectral serial data and full-color serial data of the serial data to the dynamic correction training module.

[0041] The detector simulator includes a full-color row synchronous receiving cycle counter, a multi-spectral row synchronous receiving cycle counter, a binary frequency divider, a full-color controllable parallel data source, a multi-spectral controllable parallel data source, a controllable full-color serial data source transmitter, and a controllable multi-spectral serial data source transmitter.

[0042] The detector simulator determines whether the delay position of each channel is in an unstable area according to the port delay device iodelay control signal of each channel output by the dynamic correction training module.

[0043] The method for determining whether the delay position of each channel is in an unstable area is: performing continuous sampling at the delay position for a predetermined number of times (for example, 64 times). If the sampling values ​​of all times are equal, the delay position is determined to be in a stable area; otherwise, the delay position is determined to be in an unstable area.

[0044] The accompanying clock of the serial data is obtained by dividing the serial clock output by the dynamic correction training module through a two-divider.

[0045] The high level of the training state signal represents that the dynamic correction training module is in the training state, and the low level of the training state signal represents that the dynamic correction training module is in the non-training imaging state.

[0046] The simulation detection method includes:

[0047] During the training phase, when the training state signal is at a high level, the full-color controllable parallel data source and the multi-spectral controllable parallel data source are controlled by the training control signal "train." When the training control signal "train" is at an active level and the corresponding delay position is in an unstable region, the full-color controllable parallel data source and the multi-spectral controllable parallel data source each output parallel data that differs from the training word (having a different number of zeros). When the training control signal "train" is at an active level and the corresponding delay position is in a stable region, the full-color controllable parallel data source and the multi-spectral controllable parallel data source each output a training word. When the training control signal "train" is at an inactive level, the full-color controllable parallel data source and the multi-spectral controllable parallel data source each output parallel data that differs from the training word (having a different number of zeros). The parallel data output by the full-color controllable parallel data source is fed into the controllable full-color serial data source transmitter, and the parallel data output by the multi-spectral controllable parallel data source is fed into the controllable multi-spectral serial data source transmitter.

[0048] During the non-training imaging phase, when the training state signal is at a low level, the full-color controllable parallel data source is controlled by the full-color row synchronization signal sync_p, and the multi-spectral controllable parallel data source is controlled by the multi-spectral row synchronization signal sync_b. Upon detecting the rising edge of the full-color row synchronization signal sync_p, the full-color controllable parallel data source first outputs four synchronization words sync_code (each different), followed by random parallel data different from the four synchronization words sync_code. This random parallel data is then fed into the controllable full-color serial data source transmitter. Upon detecting the rising edge of the multi-spectral row synchronization signal sync_b, the multi-spectral controllable parallel data source first outputs four synchronization words sync_code, followed by random parallel data different from the four synchronization words sync_code. This random parallel data is then fed into the controllable multi-spectral serial data source transmitter.

[0049] The number of count values ​​of the full-color row synchronization receiving loop counter is the same as the quantization bit number n of the random parallel data output by the full-color controllable parallel data source. It is cyclically increased by 1 after each rising edge of the full-color row synchronization signal is detected, and the count value range is 0 to n-1; the number of count values ​​of the multi-spectral row synchronization receiving loop counter is the same as the quantization bit number n of the random parallel data output by the multi-spectral controllable parallel data source. It is cyclically increased by 1 after each rising edge of the multi-spectral row synchronization signal is detected, and the count value range is 0 to n-1.

[0050] like Figure 3 As shown, in the training phase when the training state signal is at a high level, the count value of the sending counter in the controllable full-color serial data source transmitter is the same as the number of bits of the parallel data sent into the controllable full-color serial data source transmitter (output by the full-color controllable parallel data source); the count value of the sending counter in the controllable multi-spectral serial data source transmitter is the same as the number of bits of the parallel data sent into the controllable multi-spectral serial data source transmitter (output by the multi-spectral controllable parallel data source).

[0051] like Figure 4 As shown, in the non-training imaging stage where the training state signal is at a low level, the count value of the sending counter in the controllable full-color serial data source transmitter is the sum of the number of bits of the random parallel data sent into the controllable full-color serial data source transmitter (output by the full-color controllable parallel data source) and the count value of the full-color row synchronous receiving cycle counter; the count value of the sending counter in the controllable multi-spectral serial data source transmitter is the sum of the number of bits of the random parallel data sent into the controllable multi-spectral serial data source transmitter (output by the multi-spectral controllable parallel data source) and the count value of the multi-spectral row synchronous receiving cycle counter.

[0052] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved. This is not limited herein.

[0053] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A simulation detection method for dynamic conditioning of detector serial image data, characterized in that: It is implemented based on a simulation detection system, which includes an imaging controller and a detector simulator; The imaging controller includes a dynamic correction training module, which outputs a serial clock, a training state signal, a multi-spectral line synchronization signal, a full-color line synchronization signal, a port delay control signal of each channel, and a training control signal to the detector simulator; The detector simulator includes a full-color row synchronous receiving cycle counter, a multi-spectral row synchronous receiving cycle counter, a binary frequency divider, a full-color controllable parallel data source, a multi-spectral controllable parallel data source, a controllable full-color serial data source transmitter, and a controllable multi-spectral serial data source transmitter; The detector simulator determines whether the delay position of each channel is in an unstable area based on the port delay control signal of each channel output by the dynamic correction training module; The detector simulator returns the serial data's companion clock, multi-spectral serial data, and full-color serial data to the dynamic correction training module. The serial data's companion clock is obtained by dividing the serial clock output by the dynamic correction training module by a two-divider. The simulation detection method includes: When the training status signal received by the detector simulator is at a high level: When the training control signal received by the detector simulator is at a valid level and the corresponding delay position is in a stable region, the full-color controllable parallel data source and the multi-spectral controllable parallel data source respectively output training words; When the training control signal received by the detector simulator is at a valid level and the corresponding delay position is in an unstable region, the full-color controllable parallel data source and the multi-spectral controllable parallel data source respectively output parallel data different from the training word; When the training control signal received by the detector simulator is at an invalid level, the full-color controllable parallel data source and the multi-spectral controllable parallel data source output parallel data different from the training word; The count value of the transmission counter in the controllable full-color serial data source transmitter is the same as the number of bits of the parallel data sent into the controllable full-color serial data source transmitter, and the count value of the transmission counter in the controllable multi-spectral serial data source transmitter is the same as the number of bits of the parallel data sent into the controllable multi-spectral serial data source transmitter; When the training status signal received by the detector simulator is at a low level: After detecting the rising edge of the full-color line synchronization signal, the full-color controllable parallel data source first outputs four synchronization words and then outputs random parallel data different from the four synchronization words; After detecting the rising edge of the multi-spectral row synchronization signal, the multi-spectral controllable parallel data source first outputs four synchronization words and then outputs random parallel data different from the four synchronization words; The count value of the sending counter in the controllable full-color serial data source transmitter is the sum of the number of bits of random parallel data sent into the controllable full-color serial data source transmitter and the count value of the full-color row synchronous receiving cycle counter. The count value of the sending counter in the controllable multi-spectral serial data source transmitter is the sum of the number of bits of random parallel data sent into the controllable multi-spectral serial data source transmitter and the count value of the multi-spectral row synchronous receiving cycle counter.

2. The simulation detection method for dynamic conditioning of detector serial image data according to claim 1, characterized in that: The number of count values ​​of the full-color row synchronization receiving loop counter is the same as the quantization bit number n of the random parallel data output by the full-color controllable parallel data source. It is cyclically increased by 1 after each rising edge of the full-color row synchronization signal is detected, and the count value range is 0 to n-1; the number of count values ​​of the multi-spectral row synchronization receiving loop counter is the same as the quantization bit number n of the random parallel data output by the multi-spectral controllable parallel data source. It is cyclically increased by 1 after each rising edge of the multi-spectral row synchronization signal is detected, and the count value range is 0 to n-1.

3. The simulation detection method for dynamic conditioning of detector serial image data according to claim 1, characterized in that: The four synchronization words are all different. The highest bit of the first synchronization word is 1 and the rest are 0; the lowest bit of the second synchronization word is 0 and the rest are 1; the third synchronization word is the inverse of the training word, and the fourth synchronization word is the inverse of the lowest bit of the training word.

4. The simulation detection method for dynamic conditioning of detector serial image data according to claim 1, characterized in that: The detector simulator is established in the simulation test platform testbench in the FPGA software.

5. The simulation detection method for dynamic conditioning of detector serial image data according to claim 1, characterized in that: The method for determining whether the delay position of each channel is in the unstable area is: performing continuous sampling at the delay position for a predetermined number of times. If all the sampling values ​​are equal, the delay position is determined to be in the stable area; otherwise, the delay position is determined to be in the unstable area.

Citation Information

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