A reconfigurable array processing circuit for interpolation algorithms

Abstract

This invention discloses a reconfigurable array processing circuit for interpolation algorithms, relating to the field of circuit design. It includes a data buffer system module for receiving raw image pixel data and transmitting the raw image pixel data to a reconfigurable processing operator array module; a state controller module for acquiring a target interpolation algorithm and adjusting the configuration of the reconfigurable processing operator array module according to the target interpolation algorithm; the target interpolation algorithm includes nearest neighbor interpolation, bilinear interpolation, and bicubic interpolation; the reconfigurable processing operator array module, after adjustment by the state controller module, performs interpolation processing on the raw image based on the raw image pixel data to obtain the processed image. This invention can significantly improve processing efficiency and meet bandwidth requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit design, in particular to a reconfigurable array processing circuit for interpolation algorithm. BACKGROUND

[0002] Interpolation algorithm plays a crucial role in the field of display, which fills in the gaps between data and improves the quality of images and graphics. In digital image processing, interpolation is used to enlarge or reduce images, ensuring that the images remain smooth and continuous at different resolutions. In addition, in computer graphics, interpolation is used to generate smooth curves and surfaces, making them appear realistic and smooth on the screen. Various interpolation algorithms, such as bilinear interpolation, bicubic interpolation, etc., not only play a role in static images, but also are widely used in dynamic images and videos. However, with the continuous evolution of display technology, interpolation algorithms face many pressures when facing the challenges of high resolution and large-scale data. In ultra-high definition and 4K display, traditional interpolation methods may exhibit distortion or high computational complexity, resulting in a decline in image quality or performance impairment. Image distortion and computational complexity are mutually exclusive problems, and improving image quality will inevitably bring high computational complexity.

[0003] In the field of digital image processing, the most commonly used interpolation algorithms include nearest neighbor interpolation, bilinear interpolation and bicubic interpolation. Nearest neighbor interpolation is a simple and efficient algorithm that selects the nearest known pixel value for interpolation at the target location. Although fast, it may cause jagged edges and distortion when enlarging images. Bilinear interpolation considers the four nearest neighbor pixel points around the target location and uses linear weights for interpolation. This improves image quality compared to nearest neighbor interpolation, but may still cause some blurring, especially when enlarged. Bicubic interpolation is a more complex method that considers more surrounding pixel points and uses cubic interpolation weights to more accurately approximate image details and color changes. However, this also comes with higher computational complexity. Currently, image scaling interpolation algorithms face some challenges. First, while improving image quality, the computational efficiency of the algorithm must be maintained. With the increase in image resolution and the demand for real-time applications, higher requirements are placed on the speed and efficiency of the algorithm. In addition, for specific application scenarios such as medical imaging or computer vision tasks, higher accuracy and detail retention requirements are also a challenge. SUMMARY

[0004] The purpose of the present application is to provide a reconfigurable array processing circuit for interpolation algorithm, which can greatly improve the processing efficiency and meet the demand for bandwidth.

[0005] To achieve the above purpose, the present application provides the following scheme:

[0006] A reconfigurable array processing circuit for an interpolation algorithm comprises a reconfigurable processing operator array module, a state controller module and a data buffer system module;

[0007] The reconfigurable processing operator array module is connected with the state controller module and the data buffer system module respectively;

[0008] The data buffer system module is configured to receive raw image pixel data and transmit the raw image pixel data to the reconfigurable processing operator array module;

[0009] The state controller module is configured to obtain a target interpolation algorithm and regulate and control the configuration of the reconfigurable processing operator array module according to the target interpolation algorithm; the target interpolation algorithm comprises a nearest neighbor interpolation algorithm, a bilinear interpolation algorithm and a bicubic interpolation algorithm;

[0010] The reconfigurable processing operator array module is configured to perform interpolation processing on a raw image based on the raw image pixel data to obtain a processed image after the regulation and control of the state controller module.

[0011] Optionally, the reconfigurable processing operator array module comprises a processing operator array.

[0012] The processing operator array is connected with the state controller module and the data buffer system module respectively.

[0013] Optionally, the processing operator array comprises a plurality of processing operators.

[0014] Each processing operator is connected with the state controller module and the data buffer system module.

[0015] The state controller module regulates and controls the configuration of each processing operator according to the target interpolation algorithm.

[0016] Optionally, the configuration comprises addition and subtraction and multiplication and division.

[0017] Optionally, the multiplication is a base-4-booth algorithm.

[0018] Optionally, the reconfigurable processing operator array module further comprises an auxiliary unit.

[0019] Each processing operator is further connected with the auxiliary unit.

[0020] The auxiliary unit is configured to perform optimization processing on the output of the processing operator to obtain a processed image.

[0021] Optionally, the state controller module is a finite state machine.

[0022] Optionally, the data buffering system module is further configured to receive the processed image and perform reshaping processing on the processed image.

[0023] Optionally, the data buffering system module comprises an input reshaping module, an output reshaping module and a line buffer.

[0024] Each processing operator is connected with the input reshaping module and the output reshaping module; the input reshaping module is further connected with the line buffer.

[0025] The line buffer is configured to receive raw image pixel data and transmit the raw image pixel data to the input reshaping module.

[0026] The input reshaping module is configured to integrate the raw image pixel data and transmit the raw image pixel data to the processing operator.

[0027] The output reshaping module is configured to receive the processed image and perform reshaping processing on the processed image.

[0028] Optionally, the data buffering system module is further configured to cache the processed image.

[0029] According to the embodiments of the present application, the following technical effects are provided.

[0030] The present application discloses a reconfigurable array processing circuit for interpolation algorithm, and relates to the field of circuit design, comprising a data buffering system module configured to receive raw image pixel data and transmit the raw image pixel data to a reconfigurable processing operator array module; a state controller module configured to obtain a target interpolation algorithm and regulate and control the configuration of the reconfigurable processing operator array module according to the target interpolation algorithm; the target interpolation algorithm comprises a nearest neighbor interpolation algorithm, a bilinear interpolation algorithm and a bicubic interpolation algorithm; the reconfigurable processing operator array module is configured to perform interpolation processing on a raw image based on the raw image pixel data after the regulation and control of the state controller module, and obtain a processed image, which can greatly improve the processing efficiency and meet the demand for bandwidth. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0032] Figure 1 The reconfigurable array processing circuit for interpolation algorithm provided by the present application is shown in the schematic diagram.

[0033] Figure 2 This is the first schematic diagram of the weight calculation formula decomposition;

[0034] Figure 3 This is the second schematic diagram of the weight calculation formula decomposition;

[0035] Figure 4 A schematic diagram of a base-4 booth multiplier. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] The purpose of this invention is to provide a reconfigurable array processing circuit for interpolation algorithms, which can greatly improve processing efficiency and meet bandwidth requirements.

[0038] This invention can implement three traditional interpolation algorithms, and by configuring and combining the PEA (Power Estimation Area), multiple calculation processes can be completed in parallel, greatly improving processing efficiency and meeting bandwidth requirements. The multiplier design in the PE (Power Estimation Area) adopts the radix-4 booth algorithm, simplifying the multiplier design, reducing hardware power consumption, and improving the energy efficiency of the hardware architecture. This invention features a high-energy-efficiency, high-bandwidth hardware processing structure.

[0039] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] Example 1

[0041] like Figure 1 As shown, a reconfigurable array processing circuit for interpolation algorithms in this embodiment includes: a reconfigurable processing operator array module, a state controller module, and a data buffer system module.

[0042] The reconfigurable processing operator array module is connected to the state controller module and the data buffer system module, respectively.

[0043] The data buffer system module is used to receive raw image pixel data and transmit the raw image pixel data to the reconfigurable processing operator array module.

[0044] The data buffer system module is also used for data rearrangement and storage of intermediate data.

[0045] The state controller module is configured to obtain a target interpolation algorithm and regulate the configuration of the reconfigurable processing operator array module according to the target interpolation algorithm; the target interpolation algorithm includes a nearest neighbor interpolation algorithm, a bilinear interpolation algorithm and a bicubic interpolation algorithm.

[0046] The state controller module controls the orderly work of the reconfigurable array processing circuit for the interpolation algorithm, and controls the working mode of the processing operator and the data buffer system.

[0047] The reconfigurable processing operator array module is configured to perform interpolation processing on the original image based on the original image pixel data after the regulation of the state controller module, to obtain a processed image.

[0048] As an embodiment, the reconfigurable processing operator array module includes a processing operator array.

[0049] The processing operator array is connected with the state controller module and the data buffer system module.

[0050] In a specific implementation, the reconfigurable processing operator array module refers to a processing operator array (PEA, Process Element Array) composed of 64 processing operators (PE, Process Element).

[0051] As an embodiment, the processing operator array includes a plurality of processing operators.

[0052] Each processing operator is connected with the state controller module and the data buffer system module.

[0053] The state controller module regulates the configuration of each processing operator according to the target interpolation algorithm.

[0054] Based on the characteristics that the interpolation algorithm calculation can be decomposed into multiplication and addition, a dynamic reconfigurable array processor is designed. The calculation function is completed by a reconfigurable processing operator array module, and the main body is an 8*8 operator array, with a total of 64 processing operators. Each processing operator has a context buffer to store configuration information. All processing operators and units determine their data input and function according to the configuration information stored in the context buffer. The processing operator has two working modes, namely the blocking mode and the non-blocking mode. When the processing operator is in the blocking mode, the processing operator performs a function once for each configuration. When the processing operator is in the non-blocking mode, it can repeatedly execute the same function, thereby reducing unnecessary configuration time and power consumption. In addition, all processing operators have a data buffer to temporarily store reused data, thereby reducing data loading time and power consumption.

[0055] As an embodiment, the configuration includes addition and subtraction and multiplication and division.

[0056] As an example, the multiplication is a base 4-booth algorithm.

[0057] Through the joint work of the processing operator array, multiple interpolation calculations can be implemented in parallel, greatly improving the processing speed of the interpolation algorithm. Meanwhile, the multiplication of the processing operator is implemented by the base 4-booth algorithm, which reduces the processing power consumption, thereby further improving the energy efficiency of the reconfigurable hardware architecture.

[0058] The PEA is a main calculation unit, which includes 64 PEs in total. Each PE is controlled by the FSM and can be configured as an addition-subtraction or multiplication-division according to the requirements. The multiplier is implemented by the base 4-booth algorithm, which simplifies the design of the multiplier and reduces the power consumption, as shown in FIG. 2. Different formula operations are implemented through the combination of different operators. The results can be output to the AU or the OSU. The AU is an auxiliary calculation unit, which can further process the results of the PEA to obtain the final results and output the results to the OSU. Figure 4

[0059] As an example, the reconfigurable processing operator array module further includes an auxiliary unit (AU).

[0060] Each processing operator is further connected with the auxiliary unit.

[0061] The auxiliary unit is configured to perform optimization processing on the output of the processing operator to obtain a processed image.

[0062] As an example, the state controller module is a finite state machine (FSM).

[0063] As shown in FIG. 3, the FSM serves as a controller of the system and is connected with all the modules to control the working modes and data flow directions of the other modules. Figure 1

[0064] As an example, the data buffering system module is further configured to receive the processed image and perform shaping processing on the processed image.

[0065] As an example, the data buffering system module includes an input shaping module (ISU), an output shaping module (OSU), and a line buffer.

[0066] Each processing operator is connected with the input shaping module and the output shaping module; and the input shaping module is further connected with the line buffer.

[0067] ​​The line buffer is used to receive the raw image pixel data and transmit the raw image pixel data to the input shaping module.

[0068] The input shaping module is used to integrate the raw image pixel data and transmit the raw image pixel data to the processing operator.

[0069] The ISU is an input structure of the PEA, which is used to integrate the data required by the PEA, and the data source can come from the FSM, the weight memory and the line buffer.

[0070] The output shaping module is used to receive the processed image and perform shaping processing on the processed image.

[0071] The OSU is an output shaping unit, which is used to shape the result of the PEA or the AU according to the command of the FSM, and then transmit the result to the WeightMemory module or directly output to the outside. The WeightMemory is a weight coefficient storage module, which is used to temporarily store the weight coefficient.

[0072] As an embodiment, the data buffering system module is further used to buffer the processed image.

[0073] As shown in Figure 1 The data buffering system module further includes a weight memory (Weight Memory), which is used to temporarily store the multi-line pixel data of the source image.

[0074] Taking the bicubic interpolation algorithm as an example:

[0075] Step 1: First, the first five lines of raw image pixel data of the source image are buffered in the buffer.

[0076] Step 2: Perform the weight calculation formula The weight calculation formula can be decomposed into Figure 2 and Figure 3 As shown. The first to fourth lines of each two-column processing operator are configured as Figure 2 The calculation function corresponding to the formula, and the fifth to eighth lines of each two-column processing operator are configured as Figure 3 The calculation function corresponding to the formula. The required calculation data is integrated by the data buffering system module and sent to the corresponding processing operator.

[0077] Step 3: When the weight calculation is completed, the calculated data will be stored in the weight memory. Until all the weight coefficients of the target image are calculated.

[0078] Step 4: Next, the interpolation calculation is implemented, and the bicubic interpolation calculation is to take the 4*4 original pixel values around the interpolation point and the corresponding row and column weight coefficients to perform convolution operation. The 8*8 processing operator can be decomposed into four 4*4 convolution operations, each 4*4 array corresponds to the calculation of a row of pixels, and all operators are configured as multiplication operation. The required data is integrated by the data buffer system module and sent to the corresponding processing operator. After the processing operator completes the calculation, the result is sent to the auxiliary unit, and the result obtained after the input is accumulated by the auxiliary unit is the interpolation calculation result.

[0079] Step 5: Repeat step 4 until the interpolation calculation of four rows is completed.

[0080] Step 6: Buffer the original image pixel data of the next four rows in the data buffer system module.

[0081] Step 7: Perform steps 4-6 until the interpolation algorithm of a frame of image is completed.

[0082] The interpolation algorithm is a commonly used algorithm for image scaling, and the commonly used interpolation algorithms include the nearest neighbor interpolation algorithm, the bilinear interpolation algorithm and the bicubic interpolation algorithm. The interpolation algorithm includes a plurality of calculation formulas, and the main operation can be decomposed into multiplication and division and addition and subtraction.

[0083] 1. The FSM configures 64 PEs according to the calculation formula of the interpolation algorithm, and the plurality of PEs can complete the operation of a plurality of different formulas, and the three commonly used interpolation algorithms can be mapped in the PE array to be implemented.

[0084] 2. The present application improves the parallelism of algorithm execution. Through the combination of 64 PEs, a plurality of calculation formulas can be completed in parallel, which greatly improves the hardware processing rate and meets the bandwidth requirement.

[0085] 3. The multiplier in the PE adopts the base 4-booth algorithm, which simplifies the design of the multiplier, reduces the hardware resources, reduces the power consumption of the hardware architecture, and further improves the energy consumption of the hardware architecture.

[0086] The technical features of the above embodiments can be combined in any way. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0087] The principles and implementation modes of the present application are described by using specific examples in this paper, and the above embodiments are only used to help understand the method and core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In view of the above, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A reconfigurable array processing circuit for an interpolation algorithm, characterized by The reconfigurable array processing circuit for the interpolation algorithm comprises a reconfigurable processing operator array module, a state controller module and a data buffer system module; The reconfigurable processing operator array module is connected with the state controller module and the data buffer system module respectively; The data buffer system module is used for receiving original image pixel data and transmitting the original image pixel data to the reconfigurable processing operator array module; The state controller module is used for obtaining a target interpolation algorithm and regulating and controlling the configuration of the reconfigurable processing operator array module according to the target interpolation algorithm; the target interpolation algorithm comprises a nearest neighbor interpolation algorithm, a bilinear interpolation algorithm and a bicubic interpolation algorithm; The reconfigurable processing operator array module is used for performing interpolation processing on an original image based on the original image pixel data to obtain a processed image after the regulation and control of the state controller module; The reconfigurable processing operator array module comprises a processing operator array; The processing operator array is connected with the state controller module and the data buffer system module respectively; the processing operator array comprises a plurality of processing operators; Each processing operator is connected with the state controller module and the data buffer system module; The state controller module regulates and controls the configuration of each processing operator according to the target interpolation algorithm; The configuration comprises addition and subtraction and multiplication and division; Based on the characteristics of the interpolation algorithm calculation decomposed into multiplication and addition, a dynamic reconfigurable array processor is designed; the calculation function is completed by the reconfigurable processing operator array module, the main body of the reconfigurable processing operator array module is an 8 8 operator array, a total of 64 processing operators; the processing operator has two working modes, which are blocking mode and non-blocking mode respectively; when the processing operator is in blocking mode, the processing operator executes a function once for each configuration; when the processing operator is in non-blocking mode, the same function is repeatedly executed.

2. The reconfigurable array processing circuit for an interpolation algorithm of claim 1, wherein, The multiplication is a base-4-booth algorithm.

3. The reconfigurable array processing circuit for an interpolation algorithm of claim 1, wherein, The reconfigurable processing operator array module further comprises an auxiliary unit; Each processing operator is further connected with the auxiliary unit; The auxiliary unit is used for optimizing the output of the processing operator to obtain a processed image.

4. The reconfigurable array processing circuit for an interpolation algorithm of claim 1, wherein, The state controller module is a finite state machine.

5. The reconfigurable array processing circuit for an interpolation algorithm of claim 1, wherein, The data buffer system module is further used for receiving the processed image and performing shaping processing on the processed image.

6. The reconfigurable array processing circuit for an interpolation algorithm of claim 5, wherein, The data buffer system module comprises an input shaping module, an output shaping module and a line buffer; Each processing operator is connected with the input shaping module and the output shaping module; the input shaping module is further connected with the line buffer; The line buffer is used for receiving original image pixel data and transmitting the original image pixel data to the input shaping module; The input shaping module is used for integrating the original image pixel data and transmitting the original image pixel data to the processing operator; The output shaping module is used for receiving the processed image and performing shaping processing on the processed image.

7. The reconfigurable array processing circuit for an interpolation algorithm of claim 1, wherein, The data buffer system module is further used for buffering the processed image.

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