Photoelectric in-situ active pixel sensor and manufacturing method thereof

Abstract

The present invention discloses a photoelectric in-situ active pixel sensor, wherein a device unit structure is formed on a hybrid substrate, wherein the hybrid substrate is composed of an SOI substrate and a semiconductor substrate. The device unit structure includes a MOS transistor and a photosensitive structure. The MOS transistor is formed on the semiconductor top layer of the SOI substrate, and the channel region of the MOS transistor is composed of the semiconductor top layer. The photosensitive structure includes an embedded PN diode, which includes a first electrode region heavily doped with a first conductivity type formed in the surface region of the semiconductor epitaxial layer, and a second electrode region composed of the semiconductor epitaxial layer and the semiconductor top layer at the bottom of the first electrode region. The first interface at the bottom of the dielectric buried layer at the bottom of the MOS transistor serves as a photogenerated carrier collection end. The first electrode region is connected to a first electrode composed of a front metal layer through a contact hole. The present invention also discloses a method for manufacturing a photoelectric in-situ active pixel sensor. The present invention can expand the depletion region and increase the separation and migration rate of photogenerated carriers.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device technology, and in particular to a photoelectron in-situ active pixel sensor (PISD). The present invention also relates to a method for manufacturing the PISD. Background Art

[0002] Existing traditional image sensors mainly include charge-coupled devices (CCDs) and CMOS image sensors (CISs). These two technologies have been relatively mature and widely used, but based on the working mechanism of charge transfer, these two technologies have insurmountable disadvantages, such as complex structure, high power consumption, and quantum efficiency. In order to overcome the various shortcomings of traditional image sensors, the inventors have proposed a photoelectric in-situ active pixel sensor (PISD) based on a fully depleted silicon-on-insulator (SOI) substrate, which uses the interface coupling effect of the SOI substrate as a photoelectric sensing mechanism. For N-substrate P-type PISD, the N-type substrate indicates that the semiconductor main layer at the bottom of the SOI substrate is N-type doped, and the P-type PISD indicates that the MOS transistor formed in the semiconductor top layer of the SOI substrate is PMOS. The materials of the semiconductor main layer and the semiconductor top layer are usually silicon. When a positive electric pulse is applied to the substrate of the N-substrate P-type PISD, a depletion layer is formed under the buried oxide layer / substrate. After illumination, the photogenerated holes generated in the depletion layer will be transferred to the bottom of the buried oxide layer / substrate interface under the action of the electric field in the depletion region, and the threshold voltage of the top silicon channel is increased through the interface coupling effect, thereby reducing the output current and the source output voltage, thereby achieving a sensing effect.

[0003] Based on traditional PISDs, device sensitivity and dynamic range can be adjusted by modifying the gate structure to meet diverse application requirements. PISD devices with adjustable performance during use have also been developed. However, the depletion of existing PISD devices still depends on the applied power pulse. The depletion region is concentrated near the gate and the depletion level is low, resulting in slow separation and migration of photogenerated carriers in the substrate. Furthermore, the carrier lifetime in the device is short, leading to a significant dark current effect. Overall, the device sensitivity is low, making it difficult to meet practical needs. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a photoelectric in-situ active pixel sensor that can expand the depletion region of the photosensitive structure, increase the separation and migration rate of photogenerated carriers, increase carrier lifetime, and reduce dark current. To this end, the present invention also provides a method for manufacturing the photoelectric in-situ active pixel sensor.

[0005] In order to solve the above technical problems, the device unit structure of the photoelectric in-situ active pixel sensor provided by the present invention is formed on a hybrid substrate, and the hybrid substrate is composed of an SOI substrate and a semiconductor substrate.

[0006] The SOI substrate comprises a semiconductor main layer, a dielectric buried layer and a semiconductor top layer. The dielectric buried layer is formed on the surface of the semiconductor main layer, and the semiconductor top layer is formed on the surface of the dielectric buried layer.

[0007] The semiconductor substrate includes the semiconductor main layer and a semiconductor epitaxial layer formed on the surface of the semiconductor main layer.

[0008] The semiconductor main layer is lightly doped with the second conductivity type, and the semiconductor epitaxial layer is lightly doped with the second conductivity type.

[0009] The device unit structure includes a MOS transistor and a photosensitive structure.

[0010] The MOS transistor is formed on the semiconductor top layer, and the channel region of the MOS transistor is formed by the semiconductor top layer.

[0011] The photosensitive structure includes an embedded PN diode, which includes a first electrode region heavily doped with a first conductivity type formed in the surface area of ​​the semiconductor epitaxial layer and a second electrode region composed of the semiconductor epitaxial layer at the bottom of the first electrode region and the semiconductor top layer.

[0012] The first interface between the dielectric buried layer and the semiconductor main layer at the bottom of the MOS transistor serves as a photogenerated carrier collection end of the second conductivity type.

[0013] The first electrode region is connected to a first electrode composed of a front metal layer through a contact hole, and the first electrode is used to connect to a reverse bias voltage.

[0014] When the device unit structure is in a working state, the reverse bias voltage depletes the second electrode region of the embedded PN diode and forms a first depletion region for photosensitivity. The reverse bias voltage also transfers photogenerated carriers of the second conductivity type generated in the first depletion region to the first interface; the photogenerated carriers at the first interface change the threshold voltage of the MOS transistor through an interface coupling effect.

[0015] A further improvement is that the MOS transistor is formed in a first active area surrounded by shallow trench isolation, and the bottom area of ​​the shallow trench isolation enters into the semiconductor body layer.

[0016] A further improvement is that the gate structure of the MOS transistor is a planar gate, the gate structure is formed on the top surface of the semiconductor top layer, and the semiconductor top layer covered by the gate structure serves as the channel region.

[0017] A heavily doped source region and a heavily doped drain region are respectively formed on both sides of the gate structure. The doping type of the source region and the drain region is the same and opposite to the doping type of the channel region.

[0018] A further improvement is that the MOS transistor is an NMOS, and the source region and the drain region are both heavily N-type doped;

[0019] Alternatively, the MOS transistor is a PMOS, and both the source region and the drain region are heavily P-type doped.

[0020] A further improvement is that deep trench isolation is formed on the peripheral side of the device unit structure.

[0021] The deep trench isolation passes through the semiconductor substrate.

[0022] A further improvement is that a first cladding layer of the first conductivity type is formed on the side surface of the deep trench of the deep trench isolation.

[0023] A further improvement is that the area covered by the first electrode region accounts for 10% to 100% of the area of ​​the semiconductor substrate within the region surrounded by the deep trench isolation.

[0024] A further improvement is that the device unit structure further includes:

[0025] A back oxide layer is formed on the back side of the semiconductor body layer.

[0026] A back silicon nitride, a back polysilicon or a back transparent electrode is formed on the back side of the back oxide layer.

[0027] A further improvement is that the number of the MOS transistor in the device unit structure is one, and the photoelectric in-situ active pixel sensor is a single-transistor active pixel sensor.

[0028] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

[0029] To solve the above technical problems, the present invention provides a method for manufacturing a photoelectric in-situ active pixel sensor, comprising the following steps:

[0030] Step 1: providing a hybrid substrate, wherein the hybrid substrate is composed of an SOI substrate and a semiconductor substrate.

[0031] The SOI substrate comprises a semiconductor main layer, a dielectric buried layer and a semiconductor top layer. The dielectric buried layer is formed on the surface of the semiconductor main layer, and the semiconductor top layer is formed on the surface of the dielectric buried layer.

[0032] The semiconductor substrate includes the semiconductor main layer and a semiconductor epitaxial layer formed on the surface of the semiconductor main layer.

[0033] The semiconductor main layer is lightly doped with the second conductivity type, and the semiconductor epitaxial layer is lightly doped with the second conductivity type.

[0034] Step 2: forming a MOS transistor of a device unit structure on the top semiconductor layer.

[0035] The channel region of the MOS transistor is composed of the semiconductor top layer.

[0036] Step three: forming a first electrode region heavily doped with the first conductivity type of the embedded PN diode in the surface region of the semiconductor epitaxial layer.

[0037] The semiconductor epitaxial layer and the semiconductor top layer at the bottom of the first electrode region constitute a second electrode region of the embedded PN diode.

[0038] The photosensitive structure of the device unit structure includes the embedded PN diode.

[0039] Step 4: forming a contact hole and an electrode composed of a front metal layer, wherein the electrode includes a first electrode connected to the first electrode region through the contact hole, and the first electrode is used to connect a reverse bias voltage.

[0040] The first interface between the dielectric buried layer and the semiconductor main layer at the bottom of the MOS transistor serves as a photogenerated carrier collection end of the second conductivity type.

[0041] When the device unit structure is in a working state, the reverse bias voltage depletes the second electrode region of the embedded PN diode and forms a first depletion region for photosensitivity. The reverse bias voltage also transfers photogenerated carriers of the second conductivity type generated in the first depletion region to the first interface; the photogenerated carriers at the first interface change the threshold voltage of the MOS transistor through an interface coupling effect.

[0042] A further improvement is that before proceeding to step 2, the following is also included:

[0043] A shallow trench isolation is formed, wherein the bottom region of the shallow trench isolation enters into the semiconductor main layer.

[0044] The MOS transistor is formed in a first active region surrounded by the shallow trench isolation.

[0045] A further improvement is that step 2 includes the following sub-steps:

[0046] A gate structure of the MOS transistor is formed. The gate structure is a planar gate. The gate structure is formed on the top surface of the semiconductor top layer. The semiconductor top layer covered by the gate structure serves as the channel region.

[0047] Heavily doped source and drain regions are simultaneously formed on both sides of the gate structure. The doping type of the source region is the same as that of the channel region and is opposite to that of the channel region.

[0048] A further improvement is that the MOS transistor is NMOS, and the source region and the drain region are both heavily N-type doped.

[0049] Alternatively, the MOS transistor is a PMOS, and both the source region and the drain region are heavily P-type doped.

[0050] A further improvement is that before step 2, the following is also included:

[0051] A deep trench is formed on a peripheral side of the device unit structure, and the deep trench is located in the semiconductor substrate.

[0052] A dielectric layer is filled in the deep trench to form deep trench isolation.

[0053] A further improvement is that after the deep trench is formed and before the dielectric layer is filled in the deep trench, the method further includes:

[0054] A first cladding layer of a first conductivity type is formed on a side surface of the deep trench of the deep trench isolation.

[0055] The first cladding layer is formed by epitaxial growth and in-situ doping of the first conductivity type, or the first cladding layer is formed by ion implantation of the first conductivity type.

[0056] A further improvement is that the area covered by the first electrode region accounts for 10% to 100% of the area of ​​the semiconductor substrate within the region surrounded by the deep trench isolation.

[0057] Further improvements include the following back-side processes:

[0058] The semiconductor main layer is thinned, and after thinning, the deep trench isolation passes through the semiconductor substrate.

[0059] A back oxide layer is formed on the back side of the semiconductor body layer, and the back oxide layer also covers the back side of the deep trench isolation.

[0060] A back silicon nitride, a back polysilicon or a back transparent electrode is formed on the back side of the back oxide layer.

[0061] A further improvement is that the number of the MOS transistor in the device unit structure is one, and the photoelectric in-situ active pixel sensor is a single-transistor active pixel sensor.

[0062] The present invention introduces an embedded PN diode into a photosensitive structure primarily composed of a semiconductor substrate. Compared to a back-gate structure with a single doping concentration directly composed of a semiconductor substrate, the embedded PN diode of the present invention inherently has a spontaneous space charge region. When a reverse bias voltage is applied, the depletion region formed by the embedded PN diode, namely the first depletion region, further expands, and the degree of depletion deepens. After the depletion region expands, photogenerated carriers are generated, which not only increases the photosensitive area, thereby generating more photogenerated carriers, but also increases the electric field effect within the depletion region, thereby increasing the separation and migration rate of photogenerated carriers.

[0063] In addition, the present invention can further be combined with forming a first cladding layer with a doping type opposite to that of the second electrode region on the peripheral side of the semiconductor substrate corresponding to the second electrode region of the embedded PN diode, forming a back oxide layer at the bottom of the semiconductor substrate, and superimposing back silicon nitride, back polysilicon or a back transparent electrode on the back side of the back oxide layer, which can produce a passivation effect on the first depletion region. In this way, the defects on the peripheral side of the first depletion region will be reduced, and the amount of photogenerated carriers recombined by defects will be reduced, thereby extending the carrier lifetime and reducing the dark current.

[0064] Therefore, the present invention can expand the depletion region of the photosensitive structure, increase the separation and migration rate of photogenerated carriers, increase the carrier lifetime and reduce the dark current, and finally improve the detection sensitivity of the sensor and optimize the photoelectric sensing performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0066] Figure 1 1 is a schematic structural diagram of a photoelectric in-situ active pixel sensor according to a first embodiment of the present invention;

[0067] Figure 2 1 is a schematic structural diagram of a photoelectric in-situ active pixel sensor according to a second embodiment of the present invention;

[0068] Figure 3 1 is a schematic structural diagram of a photoelectric in-situ active pixel sensor according to a third embodiment of the present invention;

[0069] Figure 4 1 is a schematic structural diagram of a photoelectric in-situ active pixel sensor according to a fourth embodiment of the present invention;

[0070] Figures 5A-5KSchematic diagram of the device structure in each step of the manufacturing method of the photoelectric in-situ active pixel sensor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0071] like Figure 1 , which is a schematic structural diagram of the photoelectric in-situ active pixel sensor according to the first embodiment of the present invention; the device unit structure of the photoelectric in-situ active pixel sensor according to the first embodiment of the present invention is formed on a hybrid substrate, and the hybrid substrate is composed of an SOI substrate and a semiconductor substrate. Figure 1 In the embodiment, the SOI substrate is located in the region indicated by the bracket 201, and the semiconductor substrate is located in the region indicated by the bracket 202. Figure 1 Only a cross-sectional structural diagram of the device unit structure is shown.

[0072] The SOI substrate includes a semiconductor main layer 101 , a dielectric buried layer 102 and a semiconductor top layer 103 . The dielectric buried layer 102 is formed on the surface of the semiconductor main layer 101 , and the semiconductor top layer 103 is formed on the surface of the dielectric buried layer 102 .

[0073] The semiconductor substrate includes the semiconductor main layer 101 and a semiconductor epitaxial layer 101a formed on the surface of the semiconductor main layer 101. The semiconductor epitaxial layer 101a is formed by removing the semiconductor top layer 103 and the dielectric buried layer 102 in the semiconductor substrate formation area and then performing epitaxial growth. Figure 5B The semiconductor main layer 101 in each region is an integral structure. In the region where the SOI substrate is formed, the semiconductor main layer 101 cannot be connected to the region above. In the region where the semiconductor substrate is formed, the semiconductor main layer 101 can be connected to the top electrode through the semiconductor epitaxial layer 101a on top.

[0074] In some embodiments, the material of the semiconductor main layer 101 includes silicon, germanium, silicon germanium, gallium nitride, or indium gallium arsenide. The material of the semiconductor epitaxial layer 101a includes silicon, germanium, silicon germanium, gallium nitride, or indium gallium arsenide. The material of the semiconductor top layer 103 includes silicon, germanium, silicon germanium, gallium nitride, or indium gallium arsenide.

[0075] In some embodiments, the material of the buried dielectric layer 102 includes insulating materials such as silicon dioxide, aluminum oxide, and hafnium oxide.

[0076] The semiconductor main layer 101 is lightly doped with the second conductivity type, and the semiconductor epitaxial layer 101 a is lightly doped with the second conductivity type.

[0077] The device unit structure includes a MOS transistor 203 and a photosensitive structure.

[0078] The MOS transistor 203 is formed on the semiconductor top layer 103 , and a channel region of the MOS transistor 203 is formed by the semiconductor top layer 103 .

[0079] The photosensitive structure includes an embedded PN diode, which includes a first electrode region 107 heavily doped with a first conductive type formed in the surface area of ​​the semiconductor epitaxial layer 101a and a second electrode region composed of the semiconductor epitaxial layer 101a and the semiconductor main layer 101 at the bottom of the first electrode region 107.

[0080] The first interface between the dielectric buried layer 102 and the semiconductor main layer 101 at the bottom of the MOS transistor 203 serves as a collecting end for photogenerated carriers of the second conductivity type.

[0081] The first electrode region 107 is connected to a first electrode formed by a front metal layer through a contact hole 113 , and the first electrode is used to connect to a reverse bias voltage.

[0082] When the device unit structure is in operation, the reverse bias voltage depletes the second electrode region of the embedded PN diode, forming a first depletion region for light sensing. The reverse bias voltage also causes photogenerated carriers of the second conductivity type generated in the first depletion region to transfer to the first interface. The photogenerated carriers at the first interface cause the threshold voltage of the MOS transistor 203 to change through an interface coupling effect. When the threshold voltage of the MOS transistor 203 changes, the source-drain current of the MOS transistor 203 also changes, and the output signal, such as the output current or output voltage, also changes, thereby achieving a light signal sensing effect.

[0083] In the first embodiment of the present invention, the MOS transistor 203 is formed in a first active region surrounded by shallow trench isolation 104 , and the bottom region of the shallow trench isolation 104 enters into the semiconductor body layer 101 .

[0084] The gate structure of the MOS transistor 203 is a planar gate. The gate structure is formed on the top surface of the semiconductor top layer 103 . The semiconductor top layer 103 covered by the gate structure serves as the channel region.

[0085] The gate structure includes a stacked gate dielectric layer 108 and a gate conductive material layer 109. In some embodiments, the gate dielectric layer 108 is a gate oxide layer, and the gate conductive material layer is a polysilicon gate. In some embodiments, the gate dielectric layer 108 can also be a high-k dielectric layer, and the gate conductive material layer 109 can be a metal gate.

[0086] A sidewall spacer 110 is formed on the side of the gate structure.

[0087] A heavily doped source region 111 and a drain region 112 are respectively formed on both sides of the gate structure. The doping type of the source region 111 and the drain region 112 is the same and opposite to the doping type of the channel region. Figure 1 In the embodiment, the source region 111 and the drain region 112 are symmetrical structures, and the source region 111 and the drain region 112 are self-aligned with the corresponding sidewall spacer 110 .

[0088] In the first embodiment of the present invention, the top of the gate structure is connected to the gate composed of the front metal layer through the contact hole 113;

[0089] The top of the source region 111 is connected to the source electrode composed of the front metal layer through a contact hole 113;

[0090] The top of the drain region 112 is connected to the drain electrode formed by the front metal layer through a contact hole 113 .

[0091] In the first embodiment of the present invention, the MOS transistor 203 is a PMOS, and both the source region 111 and the drain region 112 are heavily doped with P-type.

[0092] A deep trench isolation 105 is formed around the device unit structure to isolate different device unit structures and prevent optical or electrical interference between the different device unit structures.

[0093] The deep trench isolation 105 passes through the semiconductor substrate.

[0094] A first cladding layer 106 of a first conductivity type is formed on the side of the deep trench of the deep trench isolation 105. The first cladding layer 106 has a conductivity type opposite to that of the semiconductor substrate, and can prevent the defects on the side of the deep trench isolation 105 from adversely affecting photogenerated carriers, thereby preventing the formation of dark current.

[0095] In the first embodiment of the present invention, the area covered by the first electrode region 107 accounts for 10% to 100% of the area of ​​the semiconductor substrate within the region surrounded by the deep trench isolation 105 . Figure 1 , the area covered by the first electrode region 107 accounts for 100% of the area of ​​the semiconductor substrate within the region enclosed by the deep trench isolation 105. In other specific embodiments, the range of the area covered by the first electrode region 107 as a percentage of the area of ​​the semiconductor substrate within the region enclosed by the deep trench isolation 105 can be adjusted as needed.

[0096] In the first embodiment of the present invention, the device unit structure further includes:

[0097] A back oxide layer 114 is formed on the back side of the semiconductor body layer 101. In some embodiments, the back oxide layer 114 is made of insulating materials such as silicon dioxide, aluminum oxide, and hafnium oxide.

[0098] A back silicon nitride 115 is formed on the back surface of the back oxide layer 114 .

[0099] In the first embodiment of the present invention, the number of the MOS transistor 203 in the device unit structure is one, and the photoelectric in-situ active pixel sensor is a single-transistor active pixel sensor.

[0100] In the first embodiment of the present invention, the first conductivity type is N-type, and the second conductivity type is P-type. That is, the first electrode region 107 is heavily N-type doped, and the semiconductor substrate is lightly P-type doped. When a positive voltage is applied to the first electrode, the embedded PN diode will be reverse biased, and when the device unit structure is in an operating state, the photogenerated carriers collected at the first interface are photogenerated holes. Since the MOS transistor 203 is a PMOS in the first embodiment of the present invention, after the photogenerated holes are collected at the first interface, the surface of the dielectric buried layer 102 on the side of the channel region, i.e., the upper surface, will induce electrons through the capacitive coupling formed by the dielectric buried layer 102. In this way, the depletion difficulty of the channel region will increase, so the threshold voltage of the PMOS will increase, and the output current and the source output voltage will decrease.

[0101] In the first embodiment of the present invention, the doping concentration of the semiconductor main layer 101 is 1E13 cm -3 ~1E15cm -3 , the doping concentration of the semiconductor epitaxial layer 101a is the same as the doping concentration of the semiconductor main layer 101;

[0102] The doping concentration of the first cladding layer 106 is 1E16 cm -3 ~1E18cm -3 .

[0103] The doping concentration of the first electrode region 107 is 1E19 cm -3 ~1E21cm -3 .

[0104] The doping concentration of the source region 111 is 1E19 cm -3 ~1E21cm -3 .

[0105] The doping concentration of the drain region 112 is the same as the doping concentration of the source region 111 .

[0106] The first embodiment of the present invention uses an embedded PN diode as the substrate, creating a spontaneous space charge region (depletion region) in the device. When a reverse voltage is applied to the substrate electrode, the depletion region further expands and deepens, enabling rapid separation, migration, and collection of photogenerated carriers. A transparent electrode, such as a silicon oxide layer and a silicon nitride layer or polysilicon, is introduced on the backside, acting together with the substrate cladding to provide passivation, extending carrier lifetime and reducing dark current. By modifying the existing PISD substrate, the first embodiment of the present invention improves device sensitivity, resulting in a photosensor with superior performance.

[0107] The first embodiment of the present invention introduces an embedded PN diode into a photosensitive structure primarily composed of a semiconductor substrate. Compared to a back-gate structure with a single doping concentration directly composed of a semiconductor substrate, the embedded PN diode of the first embodiment of the present invention inherently has a spontaneous space charge region. When a reverse bias voltage is applied, the depletion region formed by the embedded PN diode, namely the first depletion region, will further expand, and the degree of depletion will deepen. After the depletion region expands, not only does the photosensitive area increase, thereby generating more photogenerated carriers, but after the photogenerated carriers are generated, they will be subjected to a larger electric field in the depletion region, thereby increasing the separation and migration rate of the photogenerated carriers.

[0108] In addition, the first embodiment of the present invention can be further combined with forming a first cladding layer 106 with a doping type opposite to that of the second electrode region on the peripheral side of the semiconductor substrate corresponding to the second electrode region of the embedded PN diode, forming a back oxide layer 114 at the bottom of the semiconductor substrate, and superimposing a back silicon nitride 115, back polysilicon or a back transparent electrode on the back side of the back oxide layer 114, which can produce a passivation effect on the first depletion region. In this way, the defects on the peripheral side of the first depletion region will be reduced, and the amount of photogenerated carriers recombined by defects will be reduced, thereby extending the carrier lifetime and reducing the dark current.

[0109] Therefore, the first embodiment of the present invention can expand the depletion region of the photosensitive structure, increase the separation and migration rate of photogenerated carriers, increase the carrier lifetime and reduce the dark current, and finally improve the detection sensitivity of the sensor and optimize the photoelectric sensing performance.

[0110] like Figure 2FIG. 1 is a schematic diagram of the structure of a photoelectric in-situ active pixel sensor according to a second embodiment of the present invention. The difference from the photoelectric in-situ active pixel sensor according to the first embodiment of the present invention is that in the second embodiment of the present invention, the MOS transistor 203 is an NMOS, and the source region 111a and the drain region 112a are both heavily N-type doped. Compared to the PMOS according to the first embodiment of the present invention, the photogenerated carriers collected at the first interface also cause changes in the threshold voltage of the NMOS, and thus in the output current and output voltage. Changes in the output current or output voltage of the MOS transistor 203 can be used to detect whether the corresponding device unit structure has sensed a light signal.

[0111] like Figure 3 , which is a schematic structural diagram of the photoelectric in-situ active pixel sensor according to the third embodiment of the present invention; the difference from the photoelectric in-situ active pixel sensor according to the first embodiment of the present invention is that in the photoelectric in-situ active pixel sensor according to the third embodiment of the present invention, the back film layer 115a formed on the back side of the back oxide layer 114 is back polysilicon or a back transparent electrode.

[0112] like Figure 4 FIG. 1 is a schematic diagram of the structure of a photoelectric in-situ active pixel sensor according to a fourth embodiment of the present invention. The difference from the photoelectric in-situ active pixel sensor according to the second embodiment of the present invention is that in the photoelectric in-situ active pixel sensor according to the fourth embodiment of the present invention, the back film layer 115a formed on the back surface of the back oxide layer 114 is back polysilicon or a back transparent electrode. The material of the back transparent electrode includes indium tin oxide (ITO).

[0113] like Figures 5A to 5K FIG2 is a schematic diagram of the device structure in each step of the method for manufacturing a photoelectric in-situ active pixel sensor according to an embodiment of the present invention. The method for manufacturing a photoelectric in-situ active pixel sensor according to an embodiment of the present invention is used to manufacture the photoelectric in-situ active pixel sensor according to each embodiment of the present invention. The following description will be made using the manufacturing method of the photoelectric in-situ active pixel sensor according to the first embodiment of the present invention as an example. The method for manufacturing a photoelectric in-situ active pixel sensor according to an embodiment of the present invention includes the following steps:

[0114] Step 1: providing a hybrid substrate, wherein the hybrid substrate is composed of an SOI substrate and a semiconductor substrate.

[0115] The SOI substrate includes a semiconductor main layer 101 , a dielectric buried layer 102 and a semiconductor top layer 103 . The dielectric buried layer 102 is formed on the surface of the semiconductor main layer 101 , and the semiconductor top layer 103 is formed on the surface of the dielectric buried layer 102 .

[0116] The semiconductor substrate includes the semiconductor main layer 101 and a semiconductor epitaxial layer 101 a formed on the surface of the semiconductor main layer 101 .

[0117] The semiconductor main layer 101 is lightly doped with the second conductivity type, and the semiconductor epitaxial layer 101 a is lightly doped with the second conductivity type.

[0118] In some embodiments, the material of the semiconductor body layer 101 includes silicon, germanium, silicon germanium, gallium nitride, or indium gallium arsenide.

[0119] The material of the semiconductor epitaxial layer 101a includes silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenide.

[0120] The material of the semiconductor top layer 103 includes silicon, germanium, germanium silicon, gallium nitride or indium gallium arsenide. The thickness of the semiconductor top layer 103 is between 5 nm and 500 nm.

[0121] The dielectric buried layer 102 is made of insulating materials such as silicon dioxide, aluminum oxide, and hafnium oxide, and has a thickness ranging from 10 nm to 1000 nm.

[0122] In some embodiment methods, the hybrid substrate can also be formed on the basis of the SOI substrate. In this case, step 1 includes the following sub-steps:

[0123] like Figure 5A As shown, an initial substrate is provided, which is a wafer of the SOI substrate.

[0124] like Figure 5B As shown, the semiconductor substrate is formed into a region Figure 1 The semiconductor top layer 103 and the dielectric buried layer 102 in the area corresponding to the middle bracket 202 are removed, and the surface of the semiconductor main layer 101 at the bottom is exposed. This sub-step includes: photolithography and opening the formation area of ​​the semiconductor substrate and forming a photoresist window. Then, the semiconductor top layer 103 and the dielectric buried layer 102 are etched to the semiconductor main layer 101 using the photoresist as a mask. Etching can be done by dry or wet methods: dry etching generally uses fluorine-based or halogen element gases, such as SF6, Cl2, etc.; while wet etching generally uses strong acid or strong base solutions such as HF, NH4HF2, KOH, etc.

[0125] Afterwards, epitaxial growth is performed to form the semiconductor epitaxial layer 101a on the exposed surface of the semiconductor main layer 101. In this way, the hybrid substrate is formed. Figure 5B In FIG, the semiconductor epitaxial layer 101 a is located in the region above the corresponding dotted line. The semiconductor epitaxial layer 101 a is in-situ doped during epitaxial growth, and the doping is the same as that of the semiconductor main layer 101 .

[0126] The method of the embodiment of the present invention further includes:

[0127] like Figure 5B As shown, a shallow trench isolation 104 is formed, and the bottom area of ​​the shallow trench isolation 104 enters the semiconductor body layer 101. The shallow trench isolation 104 is formed by a shallow trench isolation process, namely, an STI process.

[0128] The semiconductor top layer 103 in the area surrounded by the shallow trench isolation 104 serves as a first active area.

[0129] In some example methods, the STI process includes:

[0130] Photolithography and opening the STI window form a photoresist pattern that defines the formation area of ​​the shallow trench isolation 104. Then, the semiconductor top layer 103 and the dielectric buried layer 102 are etched to the semiconductor main layer 101 using the photoresist as a mask to form a groove structure, that is, a shallow trench. Then, silicon dioxide is deposited to fill the groove to form the shallow trench isolation 104. The silicon dioxide of the shallow trench isolation 104 is usually formed by chemical vapor deposition (CVD).

[0131] The method of the embodiment of the present invention further includes:

[0132] like Figure 5C As shown, deep trenches 205 are formed around the periphery of the device unit structure, and the deep trenches 205 are located in the semiconductor substrate. The deep trenches 205 are formed by photolithography definition and etching processes. Before the photolithography process, a hard mask layer 204 is formed. The material of the hard mask layer 204 is silicon nitride or silicon oxide.

[0133] A dielectric layer is filled in the deep trench 205 to form a deep trench isolation 105 .

[0134] After the deep trench 205 is formed and before the dielectric layer is filled in the deep trench 205, the method further includes:

[0135] like Figure 5D As shown, a first cladding layer 106 of a first conductivity type is formed on the side of the deep trench 205 of the deep trench isolation 105 .

[0136] In some embodiments, the first cladding layer 106 is formed by epitaxial growth and in-situ doping of the first conductivity type, with a doping concentration of 1E16 cm -3 ~1E18cm -3 .

[0137] In some embodiments, the first cladding layer 106 can be formed by ion implantation of the first conductivity type. The process conditions of the ion implantation include: arsenic is generally used as an impurity implantation with a dose of 1E10 cm -2 ~1E13cm -2 The energy is between 0.1keV and 1keV. After ion implantation, annealing is also performed. The ion activation annealing temperature is generally between 900 degrees and 1200 degrees, and the time is 1 microsecond to 10 seconds.

[0138] like Figure 5E As shown, after forming the first cladding layer 106, the hard mask layer 204 is removed. A dielectric layer, such as an oxide layer, is filled in the deep trench 205 to form the deep trench isolation 105. The oxide layer, such as silicon dioxide, of the deep trench isolation 105 can be formed by chemical vapor deposition (CVD).

[0139] Step 2: forming a MOS transistor 203 of a device unit structure on the semiconductor top layer 103 .

[0140] The MOS transistor 203 is formed in a first active region surrounded by the shallow trench isolation 104 .

[0141] The channel region of the MOS transistor 203 is formed by the semiconductor top layer 103 .

[0142] In the method of the embodiment of the present invention, the number of the MOS transistor 203 in the device unit structure is one, and the photoelectric in-situ active pixel sensor is a single-transistor active pixel sensor.

[0143] In the method of the embodiment of the present invention, step 2 includes the following sub-steps:

[0144] The gate structure of the MOS transistor 203 is formed. The gate structure is a planar gate. The gate structure is formed on the top surface of the semiconductor top layer 103. The semiconductor top layer 103 covered by the gate structure serves as the channel region. The steps of forming the gate structure include:

[0145] like Figure 5F As shown, a gate dielectric layer 108 and a gate conductive material layer 109 are formed. The gate dielectric layer 108 and the gate conductive material layer 109 are patterned and etched to form the gate structure. In some embodiments, the gate dielectric layer 108 is a gate oxide layer, and the gate conductive material layer 109 is a polysilicon gate.

[0146] In some embodiments, the gate dielectric layer 108 may be a high-k dielectric layer, and the gate conductive material layer 109 may be a metal gate.

[0147] When the gate dielectric layer 108 is a high dielectric constant layer, the material of the high dielectric constant layer includes hafnium oxide or aluminum oxide, etc., which is deposited by an atomic layer deposition system (ALD) and has a thickness generally between 1 nm and 30 nm.

[0148] In some embodiments, the gate conductive material layer 109 can also be a composite layer of a polysilicon layer and a metal. In some embodiments, the gate conductive material layer 109 can have a thickness of 10 nm to 500 nm.

[0149] The patterned etching of the gate structure includes the following steps:

[0150] Photolithography forms a photoresist pattern to open a gate window, that is, the formation area of ​​the gate structure will be covered with photoresist and the photoresist outside the formation area of ​​the gate structure will be removed to form a window. Thereafter, the gate conductive material layer 109 and the gate dielectric layer 108 are etched using the photoresist as a mask to form the pattern of the gate structure. Etching can be done by dry or wet methods; dry etching generally uses fluorine-based or halogen element gases, such as SF6, CHF3, HBr or Cl2; and wet etching generally uses TMAH, KOH and other solutions.

[0151] Then, a spacer 110 is formed on the side of the gate structure.

[0152] In some exemplary methods, the steps of forming the sidewall spacer 110 include:

[0153] Deposit a layer of spacer material, such as silicon nitride, silicon dioxide, or low-k dielectrics such as SiOCN and SiBCN. This deposition can be done using processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).

[0154] Then, etching is performed to form the sidewall spacer 110 . The etching generally uses reactive ion etching with vertical directionality. The dry etching can use fluorine-based gases such as SF 6 , CHF 3 or CH 3 F.

[0155] like Figure 5H As shown, heavily doped source regions 111 and drain regions 112 are simultaneously formed in the semiconductor top layer 103 on both sides of the gate structure. The doping type of the source region 111 is the same as that of the channel region and opposite to that of the channel region.

[0156] Since the MOS transistor 203 in the photoelectric in-situ active pixel sensor of the first embodiment of the present invention is a PMOS, the source region 111 and the drain region 112 are both heavily doped with P-type.

[0157] In the embodiment of the present invention, the first electrode region 107 described later is formed before the source region 111 and the drain region 112. Figure 5H As shown, the steps of forming the source region 111 and the drain region 112 include:

[0158] A photoresist pattern is formed by photolithography to open the formation area of ​​the MOS transistor 203, that is, the first active area.

[0159] Afterwards, the semiconductor top layer 103 located on both sides of the gate structure in the first active region is removed using the photoresist and the gate structure as masks.

[0160] Afterwards, epitaxial growth is performed and a second conductive type, ie, P-type, in-situ heavy doping is performed to form the source region 111 and the drain region 112. The doping concentration of the source region 111 and the drain region 112 is 1E19cm -3 to 1E21cm -3 Therefore, in the first embodiment of the present invention, the source region 111 and the drain region 112 are formed by removing the semiconductor top layer 103 and then growing it again. In some embodiment methods, the material of the source region 112 and the drain region 112 can be the same as the material of the semiconductor top layer 103. In some embodiment methods, the material of the source region 112 and the drain region 112 can be different from the material of the semiconductor top layer 103. For example, the material of the source region 112 and the drain region 112 can be a material that provides stress for the channel region. When the semiconductor top layer 103 is silicon, the material of the source region 112 and the drain region 112 can be SiGe, which can improve the mobility of the channel carriers of the PMOS.

[0161] In some embodiments, the source region 112 and the drain region 112 can also be formed in the semiconductor top layer 103 on both sides of the gate structure in a self-aligned manner by source-drain implantation.

[0162] In some embodiments, the first electrode region 107 may be formed after the source region 111 and the drain region 112 are placed.

[0163] When the photoelectric in-situ active pixel sensor according to the second embodiment of the present invention is manufactured, since the MOS transistor 203 is an NMOS, the doping types of the source region 112 and the drain region 112 need to be changed to N-type.

[0164] Step 3: Return Figure 5G As shown, a first electrode region 107 heavily doped with a first conductivity type of an embedded PN diode is formed in the surface region of the semiconductor epitaxial layer 101 a.

[0165] The semiconductor epitaxial layer 101 a and the semiconductor main layer 101 at the bottom of the first electrode region 107 constitute a second electrode region of the embedded PN diode.

[0166] The photosensitive structure of the device unit structure includes the embedded PN diode.

[0167] In some embodiments, the area covered by the first electrode region 107 accounts for 10% to 100% of the area of ​​the semiconductor substrate within the region surrounded by the deep trench isolation 105 .

[0168] In some exemplary methods, the process for forming the first electrode region 107 includes the following steps:

[0169] A photoresist pattern is formed by photolithography to open a formation area of ​​the first electrode region 107 , and the area covered by the first electrode region 107 is defined by the opened area by photolithography.

[0170] Afterwards, ion implantation is performed using the photoresist pattern as a mask to form the first electrode region 107. Arsenic can generally be used for the ion implantation of the first electrode region 107, with a dosage of 1E13 cm -2 to 1E16cm -2 , the energy is between 1keV and 10keV; then the injected ions need to be annealed and activated, the ion activation annealing temperature is generally between 900 degrees and 1200 degrees, and the time is 1 microsecond to 10 seconds.

[0171] Step 4: Figure 5I As shown, a contact hole 113 and an electrode composed of a front metal layer are formed, and the electrode includes a first electrode connected to the first electrode region 107 through the contact hole 113, and the first electrode is used to connect a reverse bias voltage.

[0172] The first interface between the dielectric buried layer 102 and the semiconductor main layer 101 at the bottom of the MOS transistor 203 serves as a collecting end for photogenerated carriers of the second conductivity type.

[0173] When the device unit structure is in a working state, the reverse bias voltage depletes the second electrode region of the embedded PN diode and forms a first depletion region for photosensitivity. The reverse bias voltage also transfers photogenerated carriers of the second conductivity type generated in the first depletion region to the first interface; the photogenerated carriers at the first interface change the threshold voltage of the MOS transistor 203 through an interface coupling effect.

[0174] In addition to the first electrode, the front metal layer is also patterned to form a gate, a source, and a drain.

[0175] Contact holes 113 are also formed on top of the gate structure, the source region 111 and the drain region 112 , respectively.

[0176] The top of the gate structure is connected to the gate composed of the front metal layer through the contact hole 113;

[0177] The top of the source region 111 is connected to the source electrode composed of the front metal layer through a contact hole 113;

[0178] The top of the drain region 112 is connected to the drain electrode formed by the front metal layer through a contact hole 113 .

[0179] In the front-side process of some embodiments, the metal interconnection process includes multiple front-side metal layers, and each of the front-side metal layers is isolated by an interlayer film.

[0180] Each of the contact holes 113 passes through the bottom interlayer film. The steps of forming the contact holes 113 include:

[0181] A photoresist pattern is formed by a photolithography process to open the formation area of ​​each contact hole 113.

[0182] Then the interlayer film is etched to form a contact hole opening.

[0183] The contact hole opening is filled with metal and annealed, and finally the metal filled in the contact hole opening forms the contact hole 113. Common metals for the contact hole 113 include aluminum, nickel, titanium, or metal silicides such as nickel silicon and titanium silicon, and the annealing temperature is between 300 degrees and 900 degrees.

[0184] Then, the first front metal layer is formed and patterned.

[0185] After completing the front side process, the following back side processes are also included:

[0186] like Figure 5J As shown, the semiconductor body layer 101 is thinned. After thinning, the deep trench isolation 105 passes through the semiconductor substrate.

[0187] In some embodiment methods, the wafer, ie, the hybrid substrate, is flipped over, and then chemical mechanical polishing (CMP) is used to thin the semiconductor body layer 101 .

[0188] like Figure 5K As shown, a back oxide layer 114 is formed on the back side of the semiconductor body layer 101. The back oxide layer 114 also covers the back side of the deep trench isolation 105. In some embodiments, the back oxide layer 114 is deposited using a CVD process.

[0189] like Figure 5K As shown, a back side silicon nitride 115 is formed on the back side of the back side oxide layer 114. In some embodiments, the back side silicon nitride 115 is deposited using a CVD process.

[0190] When it is necessary to form the photoelectric in-situ active pixel sensor of the third embodiment of the present invention or the photoelectric in-situ active pixel sensor of the fourth embodiment of the present invention, it is necessary to replace the back silicon nitride 115 with back polysilicon or a back film layer 115a corresponding to the back transparent electrode.

[0191] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A photoelectric in-situ active pixel sensor, characterized in that: The device unit structure is formed on a hybrid substrate, which is composed of an SOI substrate and a semiconductor substrate; The SOI substrate comprises a semiconductor main layer, a dielectric buried layer and a semiconductor top layer, wherein the dielectric buried layer is formed on the surface of the semiconductor main layer, and the semiconductor top layer is formed on the surface of the dielectric buried layer; The semiconductor substrate includes the semiconductor main layer and a semiconductor epitaxial layer formed on the surface of the semiconductor main layer; The semiconductor main layer is lightly doped with the second conductivity type, and the semiconductor epitaxial layer is lightly doped with the second conductivity type; The device unit structure includes a MOS transistor and a photosensitive structure; The MOS transistor is formed on the semiconductor top layer, and the channel region of the MOS transistor is composed of the semiconductor top layer; The photosensitive structure includes an embedded PN diode, wherein the embedded PN diode includes a first electrode region heavily doped with a first conductivity type formed in a surface region of the semiconductor epitaxial layer and a second electrode region consisting of the semiconductor epitaxial layer at the bottom of the first electrode region and the semiconductor top layer; A first interface between the dielectric buried layer and the semiconductor main layer at the bottom of the MOS transistor serves as a photogenerated carrier collection end of the second conductivity type; The first electrode region is connected to a first electrode composed of a front metal layer through a contact hole, and the first electrode is used to connect to a reverse bias voltage; When the device unit structure is in a working state, the reverse bias voltage depletes the second electrode region of the embedded PN diode and forms a first depletion region for photosensitivity. The reverse bias voltage also transfers photogenerated carriers of the second conductivity type generated in the first depletion region to the first interface; the photogenerated carriers at the first interface change the threshold voltage of the MOS transistor through an interface coupling effect.

2. The photoelectric in-situ active pixel sensor according to claim 1, wherein: The MOS transistor is formed in a first active area surrounded by shallow trench isolation, and the bottom area of ​​the shallow trench isolation enters the semiconductor body layer.

3. The photoelectric in-situ active pixel sensor according to claim 2, wherein: The gate structure of the MOS transistor is a planar gate, the gate structure is formed on the top surface of the semiconductor top layer, and the semiconductor top layer covered by the gate structure serves as the channel region; A heavily doped source region and a heavily doped drain region are respectively formed on both sides of the gate structure. The doping type of the source region and the drain region is the same and opposite to the doping type of the channel region.

4. The photoelectric in-situ active pixel sensor according to claim 3, wherein: The MOS transistor is an NMOS, and both the source region and the drain region are heavily N-type doped; Alternatively, the MOS transistor is a PMOS, and both the source region and the drain region are heavily P-type doped.

5. The photoelectric in-situ active pixel sensor according to claim 3, wherein: Deep trench isolation is formed on the peripheral side of the device unit structure; The deep trench isolation passes through the semiconductor substrate.

6. The photoelectric in-situ active pixel sensor according to claim 5, wherein: A first cladding layer of a first conductivity type is formed on a side surface of the deep trench of the deep trench isolation.

7. The photoelectric in-situ active pixel sensor according to claim 5, wherein: The area covered by the first electrode region accounts for 10% to 100% of the area of ​​the semiconductor substrate within the region surrounded by the deep trench isolation.

8. The photoelectric in-situ active pixel sensor according to claim 6, wherein: The device unit structure further includes: a back oxide layer formed on the back side of the semiconductor body layer; A back silicon nitride, a back polysilicon or a back transparent electrode is formed on the back side of the back oxide layer.

9. The photoelectric in-situ active pixel sensor according to claim 1, wherein: The number of the MOS transistor in the device unit structure is one.

10. The photoelectric in-situ active pixel sensor according to any one of claims 1 to 9, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

11. A method for manufacturing a photoelectric in-situ active pixel sensor, characterized in that: The steps include: Step 1: providing a hybrid substrate, wherein the hybrid substrate is composed of an SOI substrate and a semiconductor substrate; The SOI substrate comprises a semiconductor main layer, a dielectric buried layer and a semiconductor top layer, wherein the dielectric buried layer is formed on the surface of the semiconductor main layer, and the semiconductor top layer is formed on the surface of the dielectric buried layer; The semiconductor substrate includes the semiconductor main layer and a semiconductor epitaxial layer formed on the surface of the semiconductor main layer; The semiconductor main layer is lightly doped with the second conductivity type, and the semiconductor epitaxial layer is lightly doped with the second conductivity type; Step 2: forming a MOS transistor of a device unit structure on the top semiconductor layer; The channel region of the MOS transistor is composed of the semiconductor top layer; Step 3: forming a first electrode region heavily doped with a first conductivity type of an embedded PN diode in the surface region of the semiconductor epitaxial layer; The semiconductor epitaxial layer and the semiconductor top layer at the bottom of the first electrode region constitute a second electrode region of the embedded PN diode; The photosensitive structure of the device unit structure includes the embedded PN diode; Step 4: forming a contact hole and an electrode composed of the front metal layer, the electrode including a first electrode connected to the first electrode region through the contact hole, the first electrode being used to connect to a reverse bias voltage; A first interface between the dielectric buried layer and the semiconductor main layer at the bottom of the MOS transistor serves as a photogenerated carrier collection end of the second conductivity type; When the device unit structure is in a working state, the reverse bias voltage depletes the second electrode region of the embedded PN diode and forms a first depletion region for photosensitivity. The reverse bias voltage also transfers photogenerated carriers of the second conductivity type generated in the first depletion region to the first interface; the photogenerated carriers at the first interface change the threshold voltage of the MOS transistor through an interface coupling effect.

12. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 11, wherein: Before proceeding to step 2, it also includes: forming a shallow trench isolation, wherein a bottom region of the shallow trench isolation enters into the semiconductor main layer; The MOS transistor is formed in a first active region surrounded by the shallow trench isolation.

13. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 12, wherein: Step 2 includes the following sub-steps: forming a gate structure of the MOS transistor, wherein the gate structure is a planar gate and is formed on the top surface of the semiconductor top layer, with the semiconductor top layer covered by the gate structure serving as the channel region; Heavily doped source and drain regions are simultaneously formed on both sides of the gate structure. The doping type of the source region is the same as that of the channel region and is opposite to that of the channel region.

14. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 13, wherein: The MOS transistor is an NMOS, and both the source region and the drain region are heavily N-type doped; Alternatively, the MOS transistor is a PMOS, and both the source region and the drain region are heavily P-type doped.

15. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 13, wherein: Before step 2, it also includes: forming a deep trench on a peripheral side of the device unit structure, wherein the deep trench is located in the semiconductor substrate; A dielectric layer is filled in the deep trench to form deep trench isolation.

16. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 15, wherein: After the deep trench is formed and before the dielectric layer is filled in the deep trench, the method further includes: A first cladding layer of a first conductivity type is formed on a side surface of the deep trench of the deep trench isolation; The first cladding layer is formed by epitaxial growth and in-situ doping of the first conductivity type, or the first cladding layer is formed by ion implantation of the first conductivity type.

17. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 15, wherein: The area covered by the first electrode region accounts for 10% to 100% of the area of ​​the semiconductor substrate within the region surrounded by the deep trench isolation.

18. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 16, wherein: Also includes the following back-end processes: Thinning the semiconductor main layer, wherein after thinning, the deep trench isolation passes through the semiconductor substrate; forming a back oxide layer on the back side of the semiconductor body layer, wherein the back oxide layer also covers the back side of the deep trench isolation; A back silicon nitride, a back polysilicon or a back transparent electrode is formed on the back side of the back oxide layer.

19. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 11, wherein: The number of the MOS transistor in the device unit structure is one.

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