A dual parallel capture device for carrier pseudo-code of deep space broadband spread spectrum signal

Abstract

This invention proposes a dual-parallel carrier-pseudo-code capture device suitable for deep-space broadband spread-spectrum signals. According to the Nyquist theorem, as the pseudo-code length increases exponentially and the spectrum broadens, the required sampling rate also increases exponentially. To meet the requirements of broadband spread-spectrum sampling, a method using carrier parallel multipathing and reduced sampling rate is employed. This method enables dual-parallel carrier-pseudo-code capture of broadband spread-spectrum signals in deep space with low signal-to-noise ratios, while maintaining a relatively low clock rate and hardware resource overhead. The device comprises the following modules: a parallel downconversion module 1, a parallel despreading module 2, a data reassembly module 3, a phase rotation module 4, an FFT processing module 5, and a comparator module 6. The invention utilizes a parallel carrier capture method to reduce the operating clock, improve the timing stability of complex FPGA programs, and reduce FPGA internal resource usage. Furthermore, the parallel pseudo-code capture method addresses the issues of long deep-space broadband capture times and high hardware resource utilization. The device can be used in anti-interference applications, including space tracking and control, deep-space communications, and satellite communications.

Description

Technical Field

[0001] The present invention belongs to the field of aerospace measurement and control technology, and in particular refers to a dual-parallel capture device for deep space broadband spread spectrum signal carrier pseudo-code, which can be used in anti-interference fields including aerospace measurement and control, deep space communication and satellite communication. Background Art

[0002] In recent years, broadband spread spectrum modulation has been widely used in cutting-edge fields such as aerospace measurement and control, satellite remote sensing, and unmanned aerial vehicle data links. As the international environment changes, the requirements for signal concealment increase, and the pseudo-code length affects the number of compatible users, the demand for broadband spread spectrum modulation technology is more urgent.

[0003] According to the Nyquist theorem, as the pseudo-code length increases exponentially and the spectrum widens, the required sampling rate also increases exponentially. However, FPGA hardware wiring has reached 7nm technology, which is close to the Shannon limit. Therefore, the FPGA operation clock rate cannot meet the requirements of broadband spread spectrum sampling. The method of using carrier parallel multiplexing and reducing the sampling rate is used.

[0004] Traditional despreading uses serial pseudo code despreading algorithm. This algorithm has less hardware resources. However, due to serial despreading, the total despreading time is a multiple of the number of pseudo codes of a single despreading time. If the despreading time of each pseudo code chip is close to 500ms, and the pseudo code chip is at least thousands of pseudo code lengths of 2 11 For example, if the traditional serial despreading method takes 1000s to complete, it is not suitable for wideband pseudo-code despreading. Therefore, a multi-channel parallel chip despreading algorithm is required for the pseudo-code despreading process, and the carrier also uses a parallel algorithm. Summary of the Invention

[0005] In view of this, the present invention proposes a dual-parallel capture device for carrier pseudo-code of deep space broadband spread spectrum signals. This method can obtain dual-parallel capture of carrier pseudo-code of broadband spread spectrum signals under low signal-to-noise ratio in deep space at a lower clock rate and hardware resource overhead.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] A dual parallel capture device for deep space broadband spread spectrum signal carrier pseudo code, comprising: a parallel down-conversion module 1, a parallel despreading module 2, a data reassembly module 3, a phase rotation module 4, an FFT processing module 5 and a comparator module 6;

[0008] The parallel down-conversion module 1 is used to receive N external input parameters, each parameter including a sampling clock / N, a carrier frequency control word, and a carrier offset phase. Each parameter generates two waveforms, sin and cos, which are multiplied one-to-one with the N external input orthogonal data data to obtain a mixing result. The mixing result is filtered to remove the second harmonic component to obtain the down-conversion imaginary part and the down-conversion real part, which are output to the parallel despreading module 2; wherein N∈2, 4, 8, ..., N is an exponent of 2, and the carrier offset phase of each parameter is different;

[0009] The parallel despreading module 2 is used to receive the external input initial phase 0, initial phase 1, pseudo code polynomial 0 and pseudo code polynomial 1 to generate a pseudo code for storage; and receive the external input sampling clock / N, pseudo code frequency control word and pseudo code offset phase to generate a code clock address, use the code clock address to search for the corresponding pseudo code in the storage, and perform XOR with the down-converted real part and imaginary part and integrate and clean the result, and store the integrated cleaned result in the internal FIFO;

[0010] The data reassembly module 3 is used to read the results of the integral cleaning in the FIFO, put the integral cleaning results into the internal storage module in sequence, and output the stored data to the phase rotation module 4;

[0011] The phase rotation module 4 is used to perform Hilbert transform on the input data to generate the in-phase and quadrature data required for FFT operation, and output them to the FFT processing module 5;

[0012] The FFT processing module 5 is used to perform FFT operation on the in-phase and quadrature data to obtain the spectrum maximum, the corresponding position of the spectrum maximum and the offset address, and output them to the comparator module 6;

[0013] The comparator module 6 is used to compare the input data with the internally stored data. If the spectrum maximum value obtained by the FFT operation is greater than or equal to the stored spectrum maximum value, the stored spectrum maximum value, the corresponding position of the spectrum maximum value and the offset address are updated to the spectrum maximum value, the corresponding position of the spectrum maximum value and the offset address obtained by the FFT operation; otherwise, the stored value remains in the original state, and when the offset address is equal to the pseudo-code length, the final spectrum maximum value, the corresponding position of the spectrum maximum value and the offset address are output.

[0014] Furthermore, the parallel despreading module 2 includes a pseudo code generator, N pseudo code NCO modules, m*N pseudo code storage RAMs, 2m*N XOR modules, 2m integral cleaning modules and m FIFOs; wherein m∈1, 2, 3, ...≤pseudo code length, and m is a natural number;

[0015] The pseudocode generator is used to generate a pseudocode using the externally input initial phase 0, initial phase 1, pseudocode polynomial 0 and pseudocode polynomial 1, and store the generated pseudocode into m*N pseudocode storage RAMs;

[0016] Each pseudo code NCO module is used to generate a code clock address using the external input sampling clock / N, pseudo code frequency control word and pseudo code offset phase, and the N code clock addresses are output to the corresponding pseudo code storage RAM;

[0017] The pseudo code storage RAM is used to use the code clock address and the offset address of the external input to find the corresponding pseudo code, and output the found pseudo code to the corresponding XOR module;

[0018] The XOR module is used to perform XOR on the pseudo code found and the down-conversion imaginary part and the down-conversion real part output by the parallel down-conversion module 1, and output the XOR result to the integral cleaning module;

[0019] The integral cleaning module is used to perform integral cleaning on the input data and then store it in FIFO;

[0020] The FIFO write data clock is the integration cleaning clock, the write data enable clock is '1', the read data clock is the system clock, the read data enable controls the m FIFOs to work in serial order and the number of read data is the number of data processed by the FFT processing module 5 each time.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The present invention reduces the internal clock of the FPGA through parallel carrier capture, thereby avoiding the limitation of the internal resource usage of the FPGA due to timing problems caused by excessively high clock.

[0023] 2. Deep space wideband spread spectrum signals are extremely weak compared to other satellite spread spectrum signals, requiring a long energy accumulation time. Each pseudo-code chip takes nearly 1 second to capture, and there are at least thousands of pseudo-code chips. If traditional serial capture methods were used to complete capture in just 1000 seconds, the estimated frequency offset and pseudo-code phase would deviate significantly from the frequency offset and pseudo-code phase required for tracking, making it impossible to close the tracking loop. Therefore, a parallel approach is required to complete pseudo-code capture. If each pseudo-code chip were to form a pseudo-code capture module, the resource requirements would be enormous, far exceeding the resources of mainstream FPGAs. Analysis revealed that the clock rate of the pseudo-code despread integrated data is extremely low, while the processing clock rate of the FFT module in an FPGA can reach nearly 100 MHz. Therefore, by converting multiple channels of low-speed parallel pseudo-code despread integrated data into a single high-speed serial pseudo-code despread integrated data channel, followed by phase rotation and FFT processing, the parallelization requirement can be met without increasing hardware complexity.

[0024] In summary, the present invention utilizes a parallel carrier capture method to reduce the operating clock, improve the timing stability of complex FPGA programs, and improve the usage of FPGA internal resources. At the same time, the parallel pseudo-code capture method solves the problems of long deep-space broadband capture time and high hardware resource occupancy. It can be used in anti-interference fields including aerospace measurement and control, deep space communication, and satellite communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a block diagram of the device principle of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further explained below with reference to the accompanying drawings.

[0027] A dual parallel capture device for deep space broadband spread spectrum signal carrier pseudo code, comprising: a parallel down-conversion module 1, a parallel despreading module 2, a data reassembly module 3, a phase rotation module 4, an FFT processing module 5 and a comparator module 6;

[0028] The parallel down-conversion module 1 is used to receive N external input parameters, each parameter including a sampling clock / N, a carrier frequency control word, and a carrier offset phase. Each parameter generates two waveforms, sin and cos, which are multiplied one-to-one with the N external input orthogonal data data to obtain a mixing result. The mixing result is filtered to remove the second harmonic component to obtain the down-conversion imaginary part and the down-conversion real part, which are output to the parallel despreading module 2; wherein N∈2, 4, 8, ..., N is an exponent of 2, and the carrier offset phase of each parameter is different;

[0029] The parallel despreading module 2 is used to receive the external input initial phase 0, initial phase 1, pseudo code polynomial 0 and pseudo code polynomial 1 to generate a pseudo code for storage; and receive the external input sampling clock / N, pseudo code frequency control word and pseudo code offset phase to generate a code clock address, use the code clock address to search for the corresponding pseudo code in the storage, and perform XOR with the down-converted real part and imaginary part and integrate and clean the result, and store the integrated cleaned result in the internal FIFO;

[0030] The data reassembly module 3 is used to read the results of the integral cleaning in the FIFO, put the integral cleaning results into the internal storage module in sequence, and output the stored data to the phase rotation module 4;

[0031] The phase rotation module 4 is used to perform Hilbert transform on the input data to generate the in-phase and quadrature data required for FFT operation, and output them to the FFT processing module 5;

[0032] The FFT processing module 5 is used to perform FFT operation on the in-phase and quadrature data to obtain the spectrum maximum, the corresponding position of the spectrum maximum and the offset address, and output them to the comparator module 6;

[0033] The comparator module 6 is used to compare the input data with the internally stored data. If the spectrum maximum value obtained by the FFT operation is greater than or equal to the stored spectrum maximum value, the stored spectrum maximum value, the corresponding position of the spectrum maximum value and the offset address are updated to the spectrum maximum value, the corresponding position of the spectrum maximum value and the offset address obtained by the FFT operation; otherwise, the stored value remains in the original state, and when the offset address is equal to the pseudo-code length, the final spectrum maximum value, the corresponding position of the spectrum maximum value and the offset address are output.

[0034] The parallel despreading module 2 includes a pseudo code generator, N pseudo code NCO modules, m*N pseudo code storage RAMs, 2m*N XOR modules, 2m integral cleaning modules and m FIFOs; wherein, m∈1, 2, 3, ...≤ pseudo code length, m is a natural number, and the value of m is limited by the amount of FPGA resources and the capture time; with a pseudo code length of 2 11 Taking the FPGA chip xc7vx690tffg1927-2 as an example, suitable values ​​for m are 16 and 32, resulting in capture times of approximately 116.5087ms and 58.2544ms. The pseudocode query result is XORed with the down-converted real and imaginary parts, respectively. The XOR results are then accumulated in the integral cleaning module. The integral cleaning module accumulates the multiple XOR results and inputs the cleaned integral result into the FIFO. This represents the workflow of the parallel despreading module.

[0035] The pseudocode generator is used to generate a pseudocode using the externally input initial phase 0, initial phase 1, pseudocode generating polynomial 0 and pseudocode generating polynomial 1, and store the generated pseudocode into m*N pseudocode storage RAMs;

[0036] Each pseudo code NCO module is used to generate a code clock address using the external input sampling clock / N, pseudo code frequency control word and pseudo code offset phase, and the N code clock addresses are output to the corresponding pseudo code storage RAM;

[0037] The pseudo code storage RAM is used to use the code clock address and the offset address of the external input to find the corresponding pseudo code, and output the found pseudo code to the corresponding XOR module;

[0038] The XOR module is used to perform XOR on the pseudo code found and the down-conversion imaginary part and the down-conversion real part output by the parallel down-conversion module 1, and output the XOR result to the integral cleaning module;

[0039] The integral cleaning module is used to perform integral cleaning on the input data and then store it in FIFO;

[0040] The FIFO write data clock is the integration cleaning clock, the write data enable clock is '1', the read data clock is the system clock, the read data enable controls the m FIFOs to work in serial order and the number of read data is the number of data processed by the FFT processing module 5 each time.

Claims

1. A dual parallel capture device for deep space broadband spread spectrum signal carrier pseudo code, characterized in that: include: A parallel down-conversion module (1), a parallel despreading module (2), a data reassembly module (3), a phase rotation module (4), an FFT processing module (5) and a comparator module (6); The parallel down-conversion module (1) is used to receive N channels of external input parameters, each of which includes a sampling clock / N, a carrier frequency control word, and a carrier offset phase. Each channel of parameters generates two waveforms, sin and cos, which correspond to the N channels of external input orthogonal data data and are multiplied one by one to obtain a mixing result. The mixing result is filtered to remove the second harmonic component to obtain a down-conversion imaginary part and a down-conversion real part, which are output to the parallel despreading module (2); wherein N∈2, 4, 8, ..., N is an exponent of 2, and the carrier offset phase of each channel of parameters is different; The parallel despreading module (2) is used to receive external input initial phase 0, initial phase 1, pseudo code polynomial 0 and pseudo code polynomial 1 to generate pseudo code for storage; and receive external input sampling clock / N, pseudo code frequency control word and pseudo code offset phase to generate code clock address, use code clock address to search corresponding pseudo code in storage, and perform XOR with down-converted real part and imaginary part and integral cleaning, and store the result after integral cleaning into internal FIFO; The data reorganization module (3) is used to read the results of the integration cleaning in the FIFO, put the results of the integration cleaning into the internal storage module in sequence, and output the stored data to the phase rotation module (4); The phase rotation module (4) is used to perform Hilbert transform on the input data to generate in-phase and quadrature data required for FFT operation, and output the data to the FFT processing module (5); The FFT processing module (5) is used to perform FFT operation on the in-phase and quadrature data to obtain the maximum value of the spectrum, the corresponding position of the maximum value of the spectrum and the offset address, and output them to the comparator module (6); The comparator module (6) is used to compare the input data with the internally stored data. If the maximum spectrum value obtained by the FFT operation is greater than or equal to the stored maximum spectrum value, the stored maximum spectrum value, the corresponding position of the maximum spectrum value and the offset address are updated to the maximum spectrum value, the corresponding position of the maximum spectrum value and the offset address obtained by the FFT operation; otherwise, the stored value remains in its original state, and when the offset address is equal to the pseudo-code length, the final maximum spectrum value, the corresponding position of the maximum spectrum value and the offset address are output.

2. The dual parallel capture device for deep space broadband spread spectrum signal carrier pseudo-code according to claim 1, characterized in that: The parallel despreading module (2) includes a pseudo code generator, N pseudo code NCO modules, m*N pseudo code storage RAMs, 2m*N XOR modules, 2m integral cleaning modules and m FIFOs; wherein m∈1, 2, 3, ...≤ pseudo code length, and m is a natural number; The pseudocode generator is used to generate a pseudocode using the externally input initial phase 0, initial phase 1, pseudocode polynomial 0 and pseudocode polynomial 1, and store the generated pseudocode into m*N pseudocode storage RAMs; Each pseudo code NCO module is used to generate a code clock address using the external input sampling clock / N, pseudo code frequency control word and pseudo code offset phase, and the N code clock addresses are output to the corresponding pseudo code storage RAM; The pseudo code storage RAM is used to use the code clock address and the offset address of the external input to find the corresponding pseudo code, and output the found pseudo code to the corresponding XOR module; The XOR module is used to perform XOR on the pseudo code found and the down-conversion imaginary part and the down-conversion real part output by the parallel down-conversion module (1), and output the XOR result to the integral cleaning module; The integral cleaning module is used to perform integral cleaning on the input data and then store it in FIFO; The write data clock of FIFO is the integration cleaning clock, the write data enable clock is '1', the read data clock is the system clock, the read data enable controls the m FIFOs to work in serial order and the number of read data is the number of data processed each time by the FFT processing module (5).

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