Method for processing a modulus squared data generation task and related apparatus

Abstract

The application discloses a processing method of a modulo square data generation task and related devices, wherein a classical computing unit constructs a quantum circuit for calculating a modulo square operation result of input data in GF(2 k ) based on a preset irreducible polynomial and a LUP decomposition method, and sends the input data and the quantum circuit to a quantum computing unit; the quantum computing unit excites a quantum bit to an initial quantum state based on the input data, and drives the quantum bit to evolve from the initial quantum state based on the quantum circuit to obtain a measurement result of the quantum bit; the measurement result is sent to the classical computing unit; and the classical computing unit determines and outputs the modulo square operation result based on the measurement result, thereby realizing efficient generation of modulo square data in GF(2 k ), and further realizing acceleration of cracking of a classical encryption algorithm.

Description

Technical Field

[0001] The present invention belongs to the field of quantum computing technology, and in particular to a method for processing modular square data generation tasks and a related device. Background Art

[0002] A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, and to store and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is considered a quantum computer. Quantum computers are a key technology under research because they can handle mathematical problems more efficiently than conventional computers. For example, they can reduce the time required to crack RSA keys from hundreds of years to just hours.

[0003] Finite field, also known as Galois Field (GF), is a very important concept in many disciplines such as abstract algebra and cryptography. Taking cryptography as an example, the discrete logarithm problem over finite fields is one of the two core difficult problems in the classical public key cryptography system. GF(2 k ) occupies a special position among many finite fields. How to efficiently generate GF(2 k ) in order to accelerate the cracking of classic encryption algorithms. Summary of the Invention

[0004] The purpose of this invention is to provide a method and a related device for processing modular square data generation tasks, aiming to efficiently generate GF(2 k ) in order to accelerate the cracking of classic encryption algorithms.

[0005] An embodiment of the present invention provides a method for processing a modular square data generation task, which is applied to a classical computing unit. The modular square data generation task is used to calculate the finite field GF92. k ), the method comprising:

[0006] Based on the preset irreducible polynomial and LUP decomposition method, a method for calculating GF(2 k ) is a quantum circuit that generates the modular square operation result of the input data;

[0007] sending the input data and the quantum circuit to a quantum computing unit;

[0008] Receive the measurement result fed back by the quantum computing unit, and determine and output the modular square operation result based on the measurement result.

[0009] Optionally, the method for calculating GF(2 k) in the quantum circuit of the modular square operation result of the input data, including:

[0010] Converting a preset irreducible polynomial into a square matrix, and performing LUP decomposition on the square matrix to obtain L-type, U-type, and P-type matrices;

[0011] Constructing quantum circuits corresponding to the L-type and U-type matrices based on CNOT gates, and constructing quantum circuits corresponding to the P-type matrix based on SWAP gates;

[0012] The quantum circuits corresponding to the P-type, U-type and L-type matrices are spliced ​​together to obtain the quantum circuits for calculating GF(2 k ) is a quantum circuit that generates the result of modular square operation of the input polynomial.

[0013] Optionally, converting the preset irreducible polynomial into a square matrix includes:

[0014] Determine the degree corresponding to the highest term in the preset irreducible polynomial;

[0015] Determining the result of the modular square operation of each term with a lower degree than the highest term;

[0016] A square matrix corresponding to the irreducible polynomial is determined based on a modular square operation result of each term.

[0017] Optionally, constructing a quantum circuit corresponding to the L-type matrix based on a CNOT gate includes:

[0018] Determine the non-zero elements a in the L-type matrix except the diagonal ij , apply the CNOT gate to the i-th and j-th quantum bits to obtain the quantum circuit corresponding to the L-type matrix, the i-th quantum bit is the controlled bit, the j-th quantum bit is the control bit, and i and j are the number of rows and columns of the L-type matrix respectively.

[0019] Optionally, constructing a quantum circuit corresponding to the U-shaped matrix based on a CNOT gate includes:

[0020] Determine the non-zero elements a in the U-shaped matrix except the diagonal ij , apply the CNOT gate to the i-th and j-th quantum bits to obtain the quantum circuit corresponding to the U-shaped matrix, the j-th quantum bit is the controlled bit, the i-th quantum bit is the control bit, and i and j are the number of rows and columns of the U-shaped matrix respectively.

[0021] Optionally, the quantum circuit corresponding to the P-type matrix is ​​constructed based on the SWAP gate, and the dimension of the P-type matrix is ​​k×k, including:

[0022] Transfer the quantum state of k qubits corresponding to the number of rows to the quantum state of k qubits corresponding to the number of columns, and determine the non-zero elements a in the P-type matrix except the diagonal. mn , m and n are the number of rows and columns of the P-type matrix respectively;

[0023] A SWAP gate is applied to the m-th qubit among the k qubits corresponding to the number of rows and the n-th qubit among the k qubits corresponding to the number of columns to obtain a quantum circuit corresponding to the P-type matrix.

[0024] Another embodiment of the present invention provides a method for processing a modular square data generation task, which is applied to a quantum computing unit. The modular square data generation task is used to calculate a finite field GF(2 k ), the method comprising:

[0025] Receive the input data and quantum circuit sent by the classical computing unit, the quantum circuit is used to calculate GF(2 k ) The result of the modular square operation of the input data described in );

[0026] Exciting a quantum bit to an initial quantum state based on the input data, and driving the quantum bit to evolve from the initial quantum state based on the quantum circuit to obtain a measurement result of the quantum bit;

[0027] The measurement result is sent to the classical computing unit, so that the classical computing unit determines the modular square operation result based on the measurement result.

[0028] Yet another embodiment of the present invention provides a quantum computing system, the quantum computing system comprising a classical computing unit and a quantum computing unit;

[0029] The classical computing unit is used to perform the following steps:

[0030] Based on the preset irreducible polynomial and LUP decomposition method, a method for calculating GF(2 k ) is a quantum circuit that generates the modular square operation result of the input data;

[0031] sending the input data and the quantum circuit to a quantum computing unit;

[0032] receiving a measurement result fed back by a quantum computing unit, and determining and outputting the modular square operation result based on the measurement result;

[0033] The quantum computing unit is used to perform the following steps:

[0034] Receive the input data and quantum circuit sent by the classical computing unit, the quantum circuit is used to calculate GF(2k ) The result of the modular square operation of the input data described in );

[0035] Exciting a quantum bit to an initial quantum state based on the input data, and driving the quantum bit to evolve from the initial quantum state based on the quantum circuit to obtain a measurement result of the quantum bit;

[0036] The measurement result is sent to the classical computing unit, so that the classical computing unit determines the modular square operation result based on the measurement result.

[0037] Another embodiment of the present invention provides a processing device for a modular square data generation task, which is applied to a classical computing unit. The modular square data generation task is used to calculate a finite field GF(2 k ), the device comprising:

[0038] A processing unit for constructing a method for calculating GF(2 k ) is a quantum circuit that generates the modular square operation result of the input data;

[0039] a sending unit, configured to send the input data and the quantum circuit to a quantum computing unit;

[0040] A receiving unit is used to receive the measurement result fed back by the quantum computing unit, and determine and output the modular square operation result based on the measurement result.

[0041] Another embodiment of the present invention provides another processing device for generating modular square data, which is applied to a quantum computing unit. The modular square data generation task is used to calculate the finite field GF(2 k ), the device comprising:

[0042] A receiving unit is configured to receive the input data and quantum circuit sent by the classical computing unit, wherein the quantum circuit is configured to calculate GF(2 k ) The result of the modular square operation of the input data described in );

[0043] a computing unit, configured to excite the qubit to an initial quantum state based on the input data, and drive the qubit to evolve from the initial quantum state based on the quantum circuit, to obtain a measurement result of the qubit;

[0044] A sending unit is configured to send the measurement result to the classical computing unit, so that the classical computing unit determines the modular square operation result based on the measurement result.

[0045] Yet another embodiment of the present invention provides a storage medium storing a computer program, wherein the computer program is configured to execute any of the above methods when running.

[0046] Yet another embodiment of the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform any of the above methods.

[0047] Compared with the prior art, the present invention provides a method and related device for processing modular square data generation tasks. The classical calculation unit is constructed based on a preset irreducible polynomial and LUP decomposition method to calculate GF(2 k ) in the quantum circuit of the modular square operation result of the input data, and sending the input data and the quantum circuit to the quantum computing unit; the quantum computing unit excites the quantum bit to the initial quantum state based on the input data, and drives the quantum bit to evolve from the initial quantum state based on the quantum circuit to obtain the measurement result of the quantum bit; the measurement result is sent to the classical computing unit; the classical computing unit determines and outputs the modular square operation result based on the measurement result; and realizes the efficient generation of GF(2 k ) in order to accelerate the cracking of classic encryption algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A network block diagram of a processing system for modular square data generation tasks provided by an embodiment of the present invention;

[0049] Figure 2 A schematic flow chart of a method for processing a modular square data generation task provided by an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of the structure of a quantum circuit corresponding to an L-type matrix provided in an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of the structure of a quantum circuit corresponding to a P-type matrix provided in an embodiment of the present invention;

[0052] Figure 5 A structural diagram of a quantum circuit for modular square operations provided by an embodiment of the present invention;

[0053] Figure 6 A schematic flow chart of a method for processing a modular square data generation task provided by an embodiment of the present invention;

[0054] Figure 7A schematic structural diagram of a device for processing modular square data generation tasks provided by an embodiment of the present invention;

[0055] Figure 8 A schematic structural diagram of a device for processing modular square data generation tasks provided by an embodiment of the present invention;

[0056] Figure 9 A schematic structural diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention.

[0058] Figure 1 This is a network block diagram of a system for processing modular squared data generation tasks, provided by an embodiment of the present invention. The system may include a network 110, a server 120, a wireless device 130, a client 140, storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, classical processors, quantum processors, and other devices (not shown).

[0059] The network 110 is a medium for providing communication links between various devices and computers connected together within the processing system for the modular square data generation task, including but not limited to the Internet, corporate intranet, local area network, mobile communication network and their combinations. The connection method can be wired, wireless communication links or optical fiber cables, etc.

[0060] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and applications or software tools that perform conventional computing processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which may be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0061] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application 163 (application 173). The application 163 (application 173) may be used to implement a quantum algorithm compiled according to the modular square data generation task method provided in an embodiment of the present invention.

[0062] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0063] It should be noted that a real quantum computer is a hybrid structure, which at least includes Figure 1 two parts: the classical computing unit 160 responsible for performing classical computing and control; and the quantum computing unit 170 responsible for running quantum programs to implement quantum computing.

[0064] The classical computing unit 160 and the quantum computing unit 170 described above can be integrated in one device or distributed in two different devices. For example, the first device including the classical computing unit 160 runs a classical computer operating system, on which quantum application development tools and services are provided, and storage and network services required by quantum application programs are also provided. The user develops a quantum program through the quantum application development tools and services thereon, and sends the quantum program to the second device including the quantum computing unit 170 through the network service thereon. The second device runs a quantum computer operating system, which parses and compiles the code of the quantum program into instructions that can be recognized and executed by the quantum processor 170, and the quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0065] The computing unit of the classical processor 161 in the classical computing unit 160 is based on CMOS tubes of silicon chips, and such computing unit is not limited by time and coherence, i.e., such computing unit is not limited by the length of use and is available at any time. In addition, in silicon chips, the number of such computing units is also sufficient, and the number of computing units in a classical processor 161 is currently thousands or even tens of thousands. The number of computing units is sufficient and the computing logic of CMOS tubes is fixed, for example: AND logic. When operating with CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the effect of operation.

[0066] The basic computing unit of the quantum processor 171 in the quantum computing unit 170 is the qubit. The input of the qubit is limited by coherence and coherence time, that is, the qubit is limited by the length of use and is not available at any time. Making full use of the qubit within the available use time of the qubit is a key problem in quantum computing. In addition, the number of qubits in a quantum computer is one of the representative indicators of the performance of the quantum computer. Each qubit realizes the computing function through the logical function configured on demand. Given that the number of qubits is limited, and the logical functions in the field of quantum computing are diverse, such as: Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate) Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. During quantum computing, it is necessary to use limited qubits in combination with a variety of logical functions to achieve the computing effect.

[0067] Based on these differences, the application of classical logic functions to the design of CMOS tubes and the application of quantum logic functions to the design of quantum bits are significantly and essentially different. The application of classical logic functions to the design of CMOS tubes does not require consideration of the individuality of the CMOS tubes. For example, the representation of CMOS tubes in silicon chips is the individual identification, position, and usable life of each CMOS tube. Therefore, the classical algorithms composed of classical logic functions only express the operational relationships of the algorithms, and do not express the algorithm's dependence on the individual CMOS tubes.

[0068] Quantum logic functions acting on qubits must consider their individuality, such as their position within the quantum chip, their individual identifier, their location, their relationship to surrounding qubits, and the usable lifespan of each qubit. Therefore, quantum algorithms composed of quantum logic functions not only express the algorithm's operational relationships but also its dependence on individual qubits.

[0069] Exemplary:

[0070] Quantum Algorithm 1: H1, H2, CNOT(1,3), H3, CNOT(2,3);

[0071] Quantum Algorithm 2: H1, H2, CNOT(1,2), H3, CNOT(2,3);

[0072] Among them, 1 / 2 / 3 represent three sequentially connected quantum bits Q1, Q2, Q3 or mutually connected quantum bits Q1, Q2, Q3;

[0073] An example explanation of how quantum algorithms are affected by qubit coherence time is as follows:

[0074] Define a single quantum bit logic gate execution time as t, 1 acting on adjacent bits on two single quantum bit logic gate execution time is 2t;

[0075] When Q1, Q2, Q3 are connected with each other, the calculation of quantum algorithm one needs 6t, which is divided into four time periods, and the time required for each time period is t, 2t, t, 2t respectively, and the operation performed in each time period is: H1, H2; CNOT(1,3); H3; CNOT(2,3);

[0076] The calculation of quantum algorithm one needs 5t, which is divided into three time periods, and the time required for each time period is t, 2t, 2t respectively, and the operation performed in each time period is: H1, H2, H3; CNOT(1,2); CNOT(2,3);

[0077] When Q1, Q2, Q3 are connected with each other, the calculation of quantum algorithm one needs to be equivalent to: H1, H2; swap(1,2), CNOT(2,3), swap(1,2); H3; CNOT(2,3). The calculation of the equivalent quantum algorithm one needs 10t, which is divided into four time periods, and the time required for each time period is t, 6t, t, 2t respectively. The operation performed in each time period is: H1, H2; swap(1,2), CNOT(2,3), swap(1,2); H3; CNOT(2,3).

[0078] Therefore, the design of quantum logic function acting on quantum bits (including the design of whether to use quantum bits and the design of the efficiency of each quantum bit) is the key to improving the operation performance of quantum computers, and needs special design, which is the uniqueness of quantum algorithms based on quantum logic function implementation, and is significantly different from the essence of classical algorithms based on classical logic function implementation. The above design for quantum bits is a technical problem that ordinary computing devices do not need to consider and face. The present application provides a processing method for a modulus square data generation task and related devices, which aims to efficiently generate modulus square data in GF(2 k ) and further realize the acceleration of breaking classical encryption algorithms.

[0079] Referring to Figure 2 , Figure 2 A flowchart of a processing method for a modulus square data generation task provided by an embodiment of the present application is applied to a classical computing unit, and the modulus square data generation task is used to calculate the modulus square operation result of input data in a finite field GF(2 k ), and the method comprises the following steps:

[0080] Step 201: constructing a calculation method for GF(2 kA quantum circuit for calculating a modulus square operation result of input data in GF(2

[0081] Wherein, the decomposition of a square matrix A into the product of a lower triangular matrix L and an upper triangular matrix U is called LU decomposition. LUP decomposition is to add a permutation matrix P on the basis of LU decomposition. The square matrix A is first subjected to the action of the permutation matrix to obtain AP, and then the new matrix is subjected to LU decomposition, i.e. AP = LU.

[0082] Wherein, the elements in GF(2 k ) are polynomials whose coefficients are composed of 0 and 1, and more accurately, are the residue classes of polynomials, wherein the equivalence relation is characterized by a modulus of a k-th irreducible polynomial (so-called modulus reduction is to perform polynomial division and take the remainder). The so-called irreducible polynomial is a polynomial that has no other polynomial as a factor except 1 and the polynomial itself under the current number field.

[0083] For current binary system computers, GF(2 k ) is particularly important. Many encryption standard algorithms process bytes as units, for example, each byte can be regarded as an element in GF(2 8 ) (k = 8), which corresponds to a polynomial of degree not more than 7, a7x 7 +a6x 6 +a5x 5 +a4x 4 +a3x 3 +a2x 2 +a13 1 +a0.

[0084] Step 202: sending the input data and the quantum circuit to a quantum computing unit;

[0085] Step 203: receiving the measurement result fed back by the quantum computing unit, and determining and outputting the modulus square operation result based on the measurement result.

[0086] Wherein, the quantum computing unit can load the input data by exciting the quantum state of the quantum bit to the initial state based on the input data, for example, the input data is 1+x+x 3 , which corresponds to the vector form (1, 1, 0, 1), and the 0th, 1st and 3rd quantum bits are excited from the ground state |0> to the excited state |1>; then the quantum bit is driven to evolve from the initial quantum state based on the quantum circuit, and the measurement result of the quantum bit is obtained. The quantum computing unit executes the quantum circuit for a specified degree.

[0087] Wherein, the measurement result can be in the form of an array, for example, for two qubits and 1024 execution times, the measurement result can be "00": 251, "01": 213, "10": 260, "11": 300, wherein "00", "01", "10", "11" are the measured quantum states, and "251, 213, 260, 300" are the corresponding times of the measured quantum states.

[0088] Specifically, the quantum computing unit generates a first pulse modulation signal based on the input data, the first pulse modulation signal being used to drive the quantum bit to be excited to an initial quantum state, and generates a second pulse modulation signal based on the quantum circuit, the first pulse modulation signal being used to drive the quantum bit to evolve from the initial quantum state to a target state; the quantum computing unit generates a third pulse modulation signal, the third pulse modulation signal being used to measure the quantum bit to obtain a measurement result corresponding to the target state.

[0089] Compared with the prior art, the application provides a processing method for a modulus square data generation task and a related device, a classical computing unit constructs a quantum circuit for calculating the modulus square operation result of input data in GF(2 k ) based on a preset irreducible polynomial and a LUP decomposition method, and sends the input data and the quantum circuit to a quantum computing unit; the quantum computing unit excites a quantum bit to an initial quantum state based on the input data, and drives the quantum bit to evolve from the initial quantum state based on the quantum circuit to obtain a measurement result of the quantum bit; the measurement result is sent to the classical computing unit; the classical computing unit determines and outputs the modulus square operation result based on the measurement result; high-efficiency generation of modulus square data in GF(2 k ) is realized, and then the classical encryption algorithm is accelerated to be cracked.

[0090] Further, the quantum circuit for calculating the modulus square operation result of the input data in GF(2 k ) based on the preset irreducible polynomial and the LUP decomposition method comprises:

[0091] convert the preset irreducible polynomial into a square matrix, and perform LUP decomposition on the square matrix to obtain L-type, U-type and P-type matrices;

[0092] construct a quantum circuit corresponding to the L-type and U-type matrices based on a CNOT gate, and construct a quantum circuit corresponding to the P-type matrix based on a SWAP gate;

[0093] splice the quantum circuits corresponding to the P-type, U-type and L-type matrices to obtain a quantum circuit for calculating the modulus square operation result of the input polynomial in GF(2 k ).

[0094] Among them, the elements of the P-type, U-type, and L-type matrices are all taken from {0,1}, so the quantum circuit corresponding to the P-type matrix can be realized by the SWAP gate, and the quantum circuits corresponding to the U-type and L-type matrices can be realized by the CNOT gate.

[0095] Specifically, converting the preset irreducible polynomial into a square matrix includes:

[0096] Determine the degree corresponding to the highest term in the preset irreducible polynomial;

[0097] Determining the result of the modular square operation of each term with a lower degree than the highest term;

[0098] A square matrix corresponding to the irreducible polynomial is determined based on a modular square operation result of each term.

[0099] for Existence (x+y) 2 =x 2 +y 2 This is because 2xy=0 in the F2 field. This property makes the language of linear algebra able to complete the GF(2 k ) square operation.

[0100] For example, the preset irreducible polynomial is f=1+x+x 4 , the highest term x 4 The corresponding degree is 4, and each term lower than the highest term is x 3 、x 2 、x 1 , 1, the modular square operation results of each term are:

[0101] 1 2 mod f=1

[0102] x 2 mod f = x 2

[0103] (x 2 ) 2 mod f = x 4 mod f=1+x

[0104] (x 3 ) 2 mod f = x 6 mod f = x 2 ×(1+x)=x 2 +x 3

[0105] Convert the above expression into the language of linear algebra:

[0106] (1,0,0,0) 2 =(1,0,0,0)

[0107] (0,1,0,0) 2 =(0,0,1,0)

[0108] (0,0,1,0) 2 =(1,1,0,0)

[0109] (0,0,0,1) 2 =(0,0,1,1)

[0110] Since any element in the finite field generated by the above irreducible polynomials can be represented by 1, x, x 2 ,x 3 Linear expression, and because the square operation on the binary field is also linear, there should be a matrix such that

[0111]

[0112]

[0113]

[0114]

[0115] Putting the above four equations together we get:

[0116]

[0117] Thus, the matrix to be determined can be obtained as:

[0118]

[0119] Specifically, constructing a quantum circuit corresponding to the L-type matrix based on a CNOT gate includes:

[0120] Determine the non-zero elements a in the L-type matrix except the diagonal ij , apply the CNOT gate to the i-th and j-th quantum bits to obtain the quantum circuit corresponding to the L-type matrix, the i-th quantum bit is the controlled bit, the j-th quantum bit is the control bit, and i and j are the number of rows and columns of the L-type matrix respectively.

[0121] like Figure 3 As shown, Figure 3 A schematic diagram of the structure of a quantum circuit corresponding to an L-type matrix provided in an embodiment of the present invention. For example, the L-type matrix is:

[0122]

[0123] The non-zero elements of the L-type matrix except the diagonal are a 20 、a 21 、a 30 , then according to the order of the non-zero elements from small to large and then from small to large, the CNOT gate is applied to the 2nd and 0th qubits, the 2nd qubit is the controlled bit, and the 0th qubit is the control bit; the CNOT gate is applied to the 2nd and 1st qubits, the 2nd qubit is the controlled bit, and the 1st qubit is the control bit; the CNOT gate is applied to the 3rd and 0th qubits, the 3rd qubit is the controlled bit, and the 0th qubit is the control bit.

[0124] Specifically, the quantum circuit corresponding to the U-shaped matrix is ​​constructed based on the CNOT gate, including:

[0125] Determine the non-zero elements a in the U-shaped matrix except the diagonal ij , apply the CNOT gate to the i-th and j-th quantum bits to obtain the quantum circuit corresponding to the U-shaped matrix, the j-th quantum bit is the controlled bit, the i-th quantum bit is the control bit, and i and j are the number of rows and columns of the U-shaped matrix respectively.

[0126] The specific implementation process of the quantum circuit corresponding to the U-type matrix is ​​similar to the specific implementation process of the quantum circuit corresponding to the L-type matrix. Please refer to the specific implementation process of the quantum circuit corresponding to the above L-type matrix, and will not be repeated here.

[0127] Specifically, the quantum circuit corresponding to the P-type matrix is ​​constructed based on the SWAP gate, and the dimension of the P-type matrix is ​​k×k, including:

[0128] Transfer the quantum state of k qubits corresponding to the number of rows to the quantum state of k qubits corresponding to the number of columns, and determine the non-zero elements a in the P-type matrix except the diagonal. mn , m and n are the number of rows and columns of the P-type matrix respectively;

[0129] A SWAP gate is applied to the m-th qubit among the k qubits corresponding to the number of rows and the n-th qubit among the k qubits corresponding to the number of columns to obtain a quantum circuit corresponding to the P-type matrix.

[0130] Furthermore, transferring the quantum state of the k qubits corresponding to the number of rows to the quantum state of the k qubits corresponding to the number of columns includes:

[0131] The SWAP gate is applied to the qubits corresponding to the row number and the qubits corresponding to the column number with the same serial number, and there are k qubits corresponding to both the row number and the column number.

[0132] For example, Figure 4 As shown, Figure 4 A schematic diagram of the structure of a quantum circuit corresponding to a P-type matrix provided in an embodiment of the present invention. If k = 4, the quantum circuit includes four quantum bits corresponding to the number of rows: q Line0 ,q Line1 ,q Line2 ,q Line3 , the number of columns corresponds to the four quantum bits: q Row0 ,q Row1 ,q Row2 ,q Row3 . You can first use SWAP(q Line0 ,q Row0 )、SWAP(q Line1 ,q Row1 )、SWAP(q Line2 ,q Row2 )、SWAP(q Line3 ,q Row3 ) transfers the quantum state of the qubit corresponding to the row number to the quantum state of the qubit corresponding to the column number. Here, the four SWAP gates act on different qubits, so their action sequence is not affected. Figure 4 Just one example.

[0133] If the P-type matrix is:

[0134]

[0135] Then the non-zero elements are a 01 、a 12 、a 23 、a 30 , so there exists SWAP(q Line0 ,q Row1 )、SWAP(q Line1 ,q Row2 )、SWAP(q Line2 ,q Row3 )、SWAP(q Line3 ,q Row0 ). Similarly, the four SWAP gates act on different quantum bits, so it does not affect the timing of their action. Figure 4 Just one example.

[0136] Specifically, the quantum circuits corresponding to the P-type, U-type and L-type matrices are spliced ​​to obtain the quantum circuits for calculating GF(2 k) is a quantum circuit that uses the modular square operation result of the polynomial as input. The dimensions of the L-type and U-type matrices are also k×k. The k qubits corresponding to the number of rows of the P-type matrix can be cascaded with the k qubits included in the quantum circuits corresponding to the U-type and L-type to achieve splicing. Figure 5 , Figure 5 A structural diagram of a quantum circuit for modular square operations provided by an embodiment of the present invention.

[0137] See also Figure 6 , Figure 6 A schematic flow chart of a method for processing a modular square data generation task provided by an embodiment of the present invention, which is applied to a quantum computing unit, wherein the modular square data generation task is used to calculate a finite field GF(2 k ), the method comprising:

[0138] Step 601: Receive the input data and quantum circuit sent by the classical computing unit, the quantum circuit is used to calculate GF(2 k ) The result of the modular square operation of the input data described in );

[0139] Step 602: Exciting the qubit to an initial quantum state based on the input data, and driving the qubit to evolve from the initial quantum state based on the quantum circuit to obtain a measurement result of the qubit;

[0140] Step 603: Send the measurement result to the classical computing unit, so that the classical computing unit determines the modular square operation result based on the measurement result.

[0141] The specific implementation of this embodiment can be found in the application to the classic computing unit side. Figure 2 The embodiments shown are not described in detail here.

[0142] Yet another embodiment of the present invention provides a quantum computing system, the quantum computing system comprising a classical computing unit and a quantum computing unit;

[0143] The classical computing unit is used to perform the following steps:

[0144] Based on the preset irreducible polynomial and LUP decomposition method, a method for calculating GF(2 k ) is a quantum circuit that generates the modular square operation result of the input data;

[0145] sending the input data and the quantum circuit to a quantum computing unit;

[0146] receiving a measurement result fed back by a quantum computing unit, and determining and outputting the modular square operation result based on the measurement result;

[0147] The quantum computing unit is used to perform the following steps:

[0148] Receive the input data and quantum circuit sent by the classical computing unit, the quantum circuit is used to calculate GF(2 k ) The result of the modular square operation of the input data described in );

[0149] Exciting a quantum bit to an initial quantum state based on the input data, and driving the quantum bit to evolve from the initial quantum state based on the quantum circuit to obtain a measurement result of the quantum bit;

[0150] The measurement result is sent to the classical computing unit, so that the classical computing unit determines the modular square operation result based on the measurement result.

[0151] Furthermore, the method further comprises:

[0152] The obtained ciphertext is decrypted based on the modular square operation result.

[0153] See also Figure 7 , Figure 7 A schematic diagram of a processing device for a modular square data generation task provided by an embodiment of the present invention, which is applied to a classical computing unit, wherein the modular square data generation task is used to calculate a finite field GF(2 k ), the device comprising:

[0154] The processing unit 701 is used to construct a method for calculating GF(2 k ) is a quantum circuit that generates the modular square operation result of the input data;

[0155] A sending unit 702, configured to send the input data and the quantum circuit to a quantum computing unit;

[0156] The receiving unit 703 is configured to receive the measurement result fed back by the quantum computing unit, and determine and output the modular square operation result based on the measurement result.

[0157] See also Figure 8 , Figure 8 A schematic diagram of a processing device for a modular square data generation task provided by an embodiment of the present invention, which is applied to a quantum computing unit, wherein the modular square data generation task is used to calculate a finite field GF(2 k ), the device comprising:

[0158] The receiving unit 801 is used to receive the input data and quantum circuit sent by the classical computing unit, and the quantum circuit is used to calculate GF(2 k) The result of the modular square operation of the input data described in );

[0159] a computing unit 802 configured to excite a qubit to an initial quantum state based on the input data, and drive the qubit to evolve from the initial quantum state based on the quantum circuit to obtain a measurement result of the qubit;

[0160] The sending unit 803 is configured to send the measurement result to the classical computing unit, so that the classical computing unit determines the modular square operation result based on the measurement result.

[0161] Regarding the specific functions and effects achieved by the processing device for the modular square data generation task, please refer to other embodiments of this specification for reference and explanation, and will not be repeated here. The various modules in the processing device for the modular square data generation task can be implemented in whole or in part by software, hardware, or a combination thereof. The modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0162] See also Figure 9 The embodiment of this specification also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the processing method of the module square data generation task in any of the above embodiments when executing the computer program. Figure 9 The computer device may be a classical computer or a quantum computer.

[0163] The embodiments of this specification also provide a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, the computer executes the processing method for generating modular squared data in any of the above embodiments.

[0164] The embodiments of this specification also provide a computer program product including instructions, which, when executed by a computer, enables the computer to perform the processing method for generating modular squared data in any of the above embodiments.

[0165] It should be understood that the specific examples in this specification are only intended to help those skilled in the art better understand the implementation methods of this specification, rather than to limit the scope of the present invention.

[0166] It can be understood that in the various implementations of this specification, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of this specification.

[0167] It can be understood that the various embodiments described in the specification can be implemented alone or in combination, and the embodiments of the specification are not limited in this regard.

[0168] Unless otherwise defined, all technical and scientific terms used in the embodiments of the specification have the same meanings as commonly understood by one of ordinary skill in the art in the technical field of the specification. The terms used in the specification are only for the purpose of describing the specific embodiments and are not intended to limit the scope of the specification. The term "and / or" used in the embodiments of the specification includes any and all combinations of one or more of the related listed items. The singular forms "a", "an" and "the" used in the embodiments of the specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0169] It can be understood that the processor of the embodiments of the specification can be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above method embodiments can be completed by integrated logic circuits of hardware in the processor or instructions in the form of software. The processor described above can be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the specification can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the specification can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0170] It is appreciated that the memory in the embodiments of the present specification can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM). It should be noted that the memory of the system and method described herein is intended to include, but not limited to, these and any other suitable types of memory.

[0171] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be realized in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present specification.

[0172] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0173] In several embodiments provided in the present specification, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0174] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e. can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0175] In addition, each functional unit in each embodiment of the present specification can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit.

[0176] If the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present specification or the parts of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present specification. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0177] The above is only a specific embodiment of the present specification, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present specification, which should be covered within the protection scope of the present specification. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for processing a modular square data generation task, characterized in that: Applied to the classical computing unit, the modular square data generation task is used to calculate the finite field The method comprises: Based on the preset irreducible polynomial and LUP decomposition method, it is used to calculate The quantum circuit of the modular square operation result of the input data; The method based on the preset irreducible polynomial and LUP decomposition is used to calculate The quantum circuit for the modular square operation of the input data in , including: Convert the preset irreducible polynomial into a square matrix; The converting of the preset irreducible polynomial into a square matrix includes: Determine the degree corresponding to the highest term in the preset irreducible polynomial; Determining the result of the modular square operation of each term with a lower degree than the highest term; Determine the square matrix corresponding to the irreducible polynomial based on the modular square operation result of each term; sending the input data and the quantum circuit to a quantum computing unit; Receive the measurement result fed back by the quantum computing unit, and determine and output the modular square operation result based on the measurement result.

2. The method according to claim 1, wherein The method based on the preset irreducible polynomial and LUP decomposition is used to calculate The quantum circuit for the modular square operation of the input data in , including: Performing LUP decomposition on the square matrix to obtain L-type, U-type and P-type matrices; Constructing quantum circuits corresponding to the L-type and U-type matrices based on CNOT gates, and constructing quantum circuits corresponding to the P-type matrix based on SWAP gates; The quantum circuits corresponding to the P-type, U-type and L-type matrices are spliced ​​together to obtain the quantum circuits for computing A quantum circuit that computes the modular square operation result of the input polynomial.

3. The method according to claim 2, wherein The method of constructing a quantum circuit corresponding to the L-type matrix based on a CNOT gate includes: Determine the non-zero elements in the L-type matrix except the diagonal , apply the CNOT gate to the i-th and j-th quantum bits to obtain the quantum circuit corresponding to the L-type matrix, the i-th quantum bit is the controlled bit, the j-th quantum bit is the control bit, and i and j are the number of rows and columns of the L-type matrix respectively.

4. The method according to claim 2, wherein The method of constructing a quantum circuit corresponding to the U-shaped matrix based on a CNOT gate includes: Determine the non-zero elements in the U-shaped matrix except the diagonal , apply the CNOT gate to the i-th and j-th quantum bits to obtain the quantum circuit corresponding to the U-shaped matrix, the i-th quantum bit is the control bit, the j-th quantum bit is the controlled bit, and i and j are the number of rows and columns of the U-shaped matrix respectively.

5. The method according to claim 2, wherein The quantum circuit corresponding to the P-type matrix is ​​constructed based on the SWAP gate, and the dimension of the P-type matrix is ​​k×k, including: Transfer the quantum state of k qubits corresponding to the number of rows to the quantum state of k qubits corresponding to the number of columns, and determine the non-zero elements in the P-type matrix except the diagonal , m and n are the number of rows and columns of the P-type matrix respectively; A SWAP gate is applied to the m-th qubit among the k qubits corresponding to the number of rows and the n-th qubit among the k qubits corresponding to the number of columns to obtain a quantum circuit corresponding to the P-type matrix.

6. A method for processing a modular square data generation task, characterized in that: Applied to quantum computing units, the module square data generation task is used to calculate finite fields The method comprises: Receive the input data and quantum circuit sent by the classical computing unit, the quantum circuit is used to calculate The result of modular square operation of the input data described in ; Exciting a quantum bit to an initial quantum state based on the input data, and driving the quantum bit to evolve from the initial quantum state based on the quantum circuit to obtain a measurement result of the quantum bit; Sending the measurement result to the classical computing unit, so that the classical computing unit determines the modular square operation result based on the measurement result; The quantum circuit is constructed based on a preset irreducible polynomial and LUP decomposition method, including: Determine the degree corresponding to the highest term in the preset irreducible polynomial; Determining the result of the modular square operation of each term with a lower degree than the highest term; A square matrix corresponding to the irreducible polynomial is determined based on a modular square operation result of each term.

7. A quantum computing system, characterized in that The quantum computing system includes a classical computing unit and a quantum computing unit; The classical computing unit is used to perform the following steps: Based on the preset irreducible polynomial and LUP decomposition method, it is used to calculate The quantum circuit of the modular square operation result of the input data; The method based on the preset irreducible polynomial and LUP decomposition is used to calculate The quantum circuit for the modular square operation of the input data in , including: Convert the preset irreducible polynomial into a square matrix; The converting of the preset irreducible polynomial into a square matrix includes: Determine the degree corresponding to the highest term in the preset irreducible polynomial; Determining the result of the modular square operation of each term with a lower degree than the highest term; Determine the square matrix corresponding to the irreducible polynomial based on the modular square operation result of each term; sending the input data and the quantum circuit to a quantum computing unit; receiving a measurement result fed back by a quantum computing unit, and determining and outputting the modular square operation result based on the measurement result; The quantum computing unit is used to perform the following steps: Receive the input data and quantum circuit sent by the classical computing unit, the quantum circuit is used to calculate The result of modular square operation of the input data described in ; Exciting a quantum bit to an initial quantum state based on the input data, and driving the quantum bit to evolve from the initial quantum state based on the quantum circuit to obtain a measurement result of the quantum bit; The measurement result is sent to the classical computing unit, so that the classical computing unit determines the modular square operation result based on the measurement result.

8. A processing device for modular square data generation task, characterized in that: Applied to the classical computing unit, the modular square data generation task is used to calculate the finite field The modular square operation result of the input data is obtained, and the device comprises: A processing unit for constructing a method for calculating irreducible polynomials and LUP decomposition based on a preset method The quantum circuit of the modular square operation result of the input data; The method based on the preset irreducible polynomial and LUP decomposition is used to calculate The quantum circuit for the modular square operation of the input data in , including: Convert the preset irreducible polynomial into a square matrix; The converting of the preset irreducible polynomial into a square matrix includes: Determine the degree corresponding to the highest term in the preset irreducible polynomial; Determining the result of the modular square operation of each term with a lower degree than the highest term; Determine the square matrix corresponding to the irreducible polynomial based on the modular square operation result of each term; a sending unit, configured to send the input data and the quantum circuit to a quantum computing unit; A receiving unit is used to receive the measurement result fed back by the quantum computing unit, and determine and output the modular square operation result based on the measurement result.

9. A processing device for modular square data generation task, characterized in that: Applied to quantum computing units, the module square data generation task is used to calculate finite fields The modular square operation result of the input data is obtained, and the device comprises: A receiving unit is configured to receive the input data and quantum circuit sent by the classical computing unit, wherein the quantum circuit is used to compute The result of modular square operation of the input data described in ; a computing unit, configured to excite the qubit to an initial quantum state based on the input data, and drive the qubit to evolve from the initial quantum state based on the quantum circuit, to obtain a measurement result of the qubit; a sending unit, configured to send the measurement result to the classical computing unit, so that the classical computing unit determines the modular square operation result based on the measurement result; The quantum circuit is constructed based on a preset irreducible polynomial and LUP decomposition method, including: Determine the degree corresponding to the highest term in the preset irreducible polynomial; Determining the result of the modular square operation of each term with a lower degree than the highest term; A square matrix corresponding to the irreducible polynomial is determined based on a modular square operation result of each term.

10. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 6 when executed.

11. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 6.

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