A Bitmap-based FPGA on-orbit programming method for power-off and resumable data transmission

Abstract

The present invention provides a method for uploading data to FPGA on-orbit programming with power-off resumable transmission based on a bitmap. The method introduces the bitmap concept in the computer field into the field of on-board FPGA on-orbit programming, creates a storage area for storing bitmap information required to indicate the correctness of programming data frame transmission, and forms a mapping relationship between a frame sequence number in the programming data frame and a specific bit in the bitmap. The address of each bit in the bitmap represents the sequence number of a completely uploaded programming data frame, and the Boolean value of each bit in the bitmap indicates whether the specific uploaded programming data frame has been successfully transmitted and stored. As can be seen, the present invention can efficiently complete the reception, verification, and storage of uploaded programming data frames under limited satellite-to-ground link communication resources, accurately locate programming data frames that need to be reissued due to transmission errors, avoid resource waste caused by repeated erasing and writing, and efficiently implement the uploading and reception processing of programming data frames under limited communication resources.

Description

Technical Field

[0001] The present invention belongs to the technical field of on-orbit reconstruction, and in particular relates to a Bitmap-based FPGA on-orbit programming power-off and resumable data injection method. Background Art

[0002] On-orbit programming of SRAM (Static Random Access Memory) FPGAs (Field-Programmable Gate Arrays) is a technology that uses ground data upload to cache the compiled program bitstream files via the satellite platform and forward them to each unit, allowing on-orbit maintenance or software upgrades for spaceborne units using SRAM FPGAs. The technology in this area can currently be summarized as follows: First, a continuous address transmission method is used. If a data transmission error occurs during a long period of data uploading, all data can only be erased and re-uploaded. Therefore, it is more suitable for on-orbit programming of extremely small-scale software; Second, represented by the patent "A method for implementing on-orbit reconstruction breakpoint resumption based on anti-fuse FPGA" (CN112506527A) and the patent "A method for improving the effectiveness of on-orbit file uploading" (CN115567510A), this type of solution divides the programming data frame on the basis of the continuous address transmission method, adds data frame continuity check and single data frame correctness check, and once an abnormal situation occurs in the uploading, the subsequent uploading is interrupted and the ground is notified to ensure the continuity and correctness of the programming uploading data. However, when the satellite-to-ground link communication resources are limited, this solution will frequently interrupt the injection, wasting the programming data frames cached by the satellite platform, and the injection process cannot be restored after a power outage during programming; thirdly, taking the patent "A data injection method for satellite on-orbit software reconstruction" (CN112003643A) as an example, this solution is divided into two steps: satellite-to-ground injection and in-satellite injection. After channel coding is performed in the satellite-to-ground injection, the data frame division method is also adopted. The injection programming data is stored in the satellite platform's satellite service solid-state memory, and the satellite service computer controls the program loading of each unit (i.e., in-satellite injection). If the satellite carries a large number of programmable units, the storage resources and program loading complexity of the satellite platform will be greatly increased, and the injection process cannot be restored after a power outage during programming.

[0003] Currently, the efficiency of on-orbit programming of spaceborne FPGAs is primarily constrained by two factors: First, due to the limited satellite-to-ground link communication rate and the satellite platform's access time slots to each individual device, on-orbit programming of spaceborne single-device FPGAs is time-consuming. Second, with the trend toward smaller and lighter satellites and their placement in low-Earth orbits, satellite platforms will power on-board single-devices on a time-sharing basis or only be able to receive large-scale programming data during the tracking and control arc. Therefore, during long data transmission processes, on-orbit programming of spaceborne single-device FPGAs must also be able to resume transmission after a power outage and restart. Given the limited satellite-to-ground link communication resources and satellite energy consumption, improvements are needed in programming data upload and single-device reception methods to ensure efficient on-orbit programming of spaceborne FPGAs. Summary of the Invention

[0004] To solve the above problems, the present invention provides a Bitmap-based FPGA on-orbit programming power-off and resume data injection method, which adopts a non-continuous injection method based on programming data frames, avoids the waste of satellite-to-ground link communication resources caused by repeated sending of programming data frames, and realizes the function of resuming data injection after power failure.

[0005] A Bitmap-based FPGA on-orbit programming and power-off data injection method is provided. A control FPGA, a Flash chip, and a processing FPGA are provided on a satellite-borne standalone device. The method comprises the following steps:

[0006] Encapsulate the bitstream file to be uploaded into multiple fixed-length programming data frames, and each programming data frame includes a frame sequence number, CRC code information, on-track programming valid data, frame header and frame footer;

[0007] A storage area for bitmap information is created in the internal RAM and Flash chip of the onboard processing FPGA. Each bit of the bitmap corresponds one-to-one with the frame sequence number and storage address, and the Boolean value of each bit is used to indicate whether the programming data frame corresponding to each bit is successfully injected. The bitmap information stored in the internal RAM is cleared when power is lost, while the bitmap information stored in the Flash chip can still be saved after power loss.

[0008] When the injection process is carried out continuously, after the onboard single machine receives the programming data frame injected from the ground, the processing FPGA performs CRC check and repeatability check on the received current programming data frame. If both pass, the on-orbit programming valid data in the current programming data frame is stored in the corresponding sector of the Flash chip through the control FPGA. After the storage is completed, the bits at the storage address corresponding to the frame sequence number of the current programming data frame in the two bitmap storage areas are set to 1; if any check fails or the storage fails, the bits at the storage address corresponding to the frame sequence number of the current programming data frame in the two bitmap storage areas are set to 0;

[0009] When the injection process is interrupted and the onboard unit is powered off and restarted, the FPGA that is powered on again reads the bitmap information stored in the FLASH chip, rebuilds the bitmap information in the internal RAM, and returns the bitmap information to the ground measurement and control station through telemetry. The ground measurement and control station resends the programming data frame that has not passed the verification or has not been injected according to the frame sequence number corresponding to the 0 bit in the bitmap information, thereby realizing power-off transmission.

[0010] Furthermore, if the bitstream file to be uploaded exceeds the satellite single data upload limit or the upload time of the bitstream file exceeds the satellite arc time corresponding to the ground tracking and control station, all programming data frames are grouped and each programming data frame is uploaded in groups.

[0011] Furthermore, the grouped programming data frame consists of: a 2-byte frame header, a 1-byte type code, a 2-byte frame sequence number, on-track programming valid data, a 4-byte CRC check code, and a 1-byte cumulative sum check code as the frame tail. Among them, in the 2 bytes of the frame sequence number, the lower 11 bits are used to represent the frame sequence number in each group, and the upper 5 bits are used to represent the group number of each programming data frame.

[0012] Furthermore, the storage area in the Flash chip stores the bitmap information corresponding to all programming data frames in groups, one group of programming data frames corresponds to one group of bitmap information, and the storage area of ​​the internal RAM of the FPGA only stores the bitmap information corresponding to the current group of programming data frames currently being uploaded.

[0013] Furthermore, when the injection process is interrupted and the onboard unit is powered off and restarted, only the Bitmap information group corresponding to the interrupted programming data frame group is read back from the Flash chip to the processing FPGA through the control FPGA, thereby indicating the programming data frame that needs to be continued or reissued.

[0014] Furthermore, after the onboard single machine receives the programming data frame injected on the ground, the processing FPGA performs CRC check, repeatability check and group number check on the received current programming data frame. If all pass, the on-orbit programming valid data in the current programming data frame is stored in the corresponding sector of the Flash chip through the control FPGA.

[0015] Furthermore, when all programming data frames are successfully uploaded, the control FPGA performs an overall CRC check on all valid on-orbit programming data stored in the corresponding storage sector of the Flash chip. If the overall CRC check passes, the ground measurement and control station sends a loading source switching instruction or a single-machine reset instruction, and the control FPGA reads the valid on-orbit programming data from the Flash chip and loads it into the processing FPGA running area, thereby realizing on-orbit programming of the processing FPGA.

[0016] Beneficial effects:

[0017] 1. The present invention provides a bitmap-based data uploading method for on-orbit FPGA programming with power-off and resume transmission. This method introduces the bitmap concept from the computer field into the field of on-board FPGA on-orbit programming. A storage area is created to store bitmap information required to indicate the correct transmission of programming data frames. A mapping relationship is formed between the frame sequence number in the programming data frame and specific bits in the bitmap. The address of each bit in the bitmap represents the sequence number of a complete uploaded programming data frame, and the Boolean value of each bit in the bitmap indicates whether the specific uploaded programming data frame has been successfully transmitted and stored. As can be seen, the present invention eliminates the need for continuous transmission based on programming data frames, greatly increasing the flexibility of data uploading and providing a foundation for implementing power-off and resume transmission. Furthermore, compared to direct transmission and breakpoint-resume transmission, the present invention can efficiently complete the reception, verification, and storage of uploaded programming data frames even when satellite-to-ground link communication resources are limited. This method accurately locates programming data frames that need to be reissued due to transmission errors, avoids resource waste caused by repeated erasures, and efficiently implements the uploading and reception processing of programming data frames even when communication resources are limited.

[0018] 2. The present invention provides a Bitmap-based FPGA on-orbit programming power-off and resume data upload method. The Bitmap information is stored in a Flash chip, which can ensure that the Bitmap information is not lost after a power outage. After the onboard FPGA is powered on again, the telemetry information can be used to prompt the ground to resend the programming data frames that need to be reissued. In addition, the programming data frames that were successfully uploaded before the power outage have been stored in the Flash. The ground only needs to resend the programming data frames that failed to be uploaded or were not uploaded according to the current Bitmap information, thereby realizing the power-off and resume transmission function. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The Bitmap-based onboard FPGA programming data frame encapsulation diagram provided by the present invention;

[0020] Figure 2 A schematic diagram of Bitmap mapping for on-orbit programming of a spaceborne FPGA based on Bitmap provided by the present invention;

[0021] Figure 3 A schematic diagram of the Bitmap-based on-board FPGA on-orbit programming software flow provided by the present invention;

[0022] Figure 4 This is a schematic diagram of the Bitmap-based on-board FPGA on-orbit programming hardware structure provided by the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0024] The present invention introduces the bitmap concept from the computer field into the field of FPGA (Field-Programmable Gate Array) on-orbit programming, creating a storage area as bitmap information. The Boolean value of each bit in the storage area is used to indicate whether each programming data frame has been successfully uploaded and stored. Ultimately, this technology realizes on-orbit programming data upload technology that uses programming data frames as units and can be resumed after power is interrupted. First, using programming data frames as units, the Boolean value of each bit in the bitmap is used to mark programming data frames that have been successfully uploaded and programming data frames that have failed to be uploaded. In the case of discontinuous transmission of programming data frames, on-orbit programming data upload, verification, and storage are completed. Next, the bitmap information is stored in a Flash memory device. The bitmap information transmitted back by the ground after the onboard FPGA is powered on again can locate programming data frames that have failed to be uploaded or have not been uploaded, thereby realizing the power-off resume function.

[0025] Specifically, a Bitmap-based FPGA on-orbit programming and power-off data injection method is provided. A control FPGA, a Flash chip, and a processing FPGA are provided on a satellite-borne standalone device. The method includes the following steps:

[0026] Step 1: Encapsulate the on-orbit programming data frame, specifically: encapsulate the bitstream file generated by compiling the onboard FPGA program to be injected into multiple fixed-length programming data frames, and each programming data frame includes a frame sequence number, CRC code (Cyclic Redundancy Check, cyclic redundancy check code) information, on-orbit programming valid data, and frame headers and footers adapted to satellite platform communication;

[0027] Step 2: Establish a bitmap information storage area and mapping relationship. Specifically, a storage area for storing bitmap information is created in the internal RAM and Flash chip of the processing FPGA on the onboard stand-alone machine. Each bit of the bitmap corresponds to each frame sequence number and storage address, and the Boolean value of each bit is used to indicate whether the programming data frame corresponding to each bit is successfully recorded. The bitmap information stored in the internal RAM is cleared when the power is off, while the bitmap information stored in the Flash chip can still be saved after power off.

[0028] That is, step S2 aims to establish corresponding bitmap areas in the onboard stand-alone Flash chip and the onboard FPGA internal RAM respectively, keep the bitmap information of the two locations updated synchronously, and establish a mapping relationship with the frame sequence number in step 1.

[0029] It should be noted that the present invention establishes two Bitmap storage areas in the Flash chip and the internal RAM of the onboard FPGA according to the frame sequence number. Storing the Bitmap in the Flash chip is the key to ensuring the power-off resume function, that is, the current programming data frame injection status can still be restored after the single machine is powered on again, but the read and write speed of the Flash chip is difficult to ensure the timely return of the onboard single machine telemetry information. Therefore, the same Bitmap storage area needs to be established in the internal RAM of the onboard FPGA to ensure timely return. Keep the two information updated synchronously, that is, after power-on, read the Bitmap information in the Flash chip back to the internal RAM of the onboard FPGA. During the injection of the programming data frame, the onboard FPGA writes the Bitmap information being updated in the internal RAM into the Flash chip to ensure that the Bitmap information is not lost in the event of power failure and can be transmitted back in time.

[0030] Step 3: Programming data frame annotation and reception processing, specifically: when the annotation process is continuously carried out, after the onboard single unit receives the programming data frame annotated on the ground, the processing FPGA performs CRC check and repeatability check on the received current programming data frame. If both pass, the on-orbit programming valid data in the current programming data frame is stored in the corresponding sector of the Flash chip through the control FPGA; after the storage is completed, the bits at the storage address corresponding to the frame sequence number of the current programming data frame in the two bitmap storage areas are set to 1; if any check fails or the storage fails, the bits at the storage address corresponding to the frame sequence number of the current programming data frame in the two bitmap storage areas are set to 0;

[0031] That is, the ground tracking and control station annotates the programming data frame obtained in step 1; the onboard single machine verifies and stores the programming data frame after receiving it, and updates the Bitmap information.

[0032] Step 4: Resend the programming data frames that failed to be injected according to the Bitmap information. Specifically, when the injection process is interrupted and the onboard unit is powered off and restarted, the processing FPGA that is powered on again reads the Bitmap information stored in the Flash chip, rebuilds the Bitmap information in the internal RAM, and returns the Bitmap information to the ground measurement and control station through telemetry. The ground measurement and control station resends the programming data frames that failed to pass the verification or have not been injected according to the frame sequence number corresponding to the 0 bit in the Bitmap information, thereby realizing power-off and resuming transmission.

[0033] That is to say, when an error occurs in the satellite-ground injection link transmission or the onboard single machine is powered off and restarted, the Bitmap information described in step 2 is returned to the ground through telemetry. The ground identifies the programming data frame that failed to be injected through the Boolean value of each bit of the Bitmap and resends the programming data frame.

[0034] Furthermore, if the bitstream file to be uploaded exceeds the satellite single data upload limit or the upload time of the bitstream file exceeds the satellite arc time corresponding to the ground measurement and control station, all programming data frames are grouped and each programming data frame is uploaded in groups; at this time, the storage area in the Flash chip stores the bitmap information corresponding to all programming data frames by group, and the storage area of ​​the internal RAM of the FPGA only stores the bitmap information corresponding to the current group of programming data frames currently being uploaded.

[0035] Taking the injection of multiple groups of programming data frames as an example, the Bitmap-based FPGA on-track programming power-off and resumable data injection method provided by the present invention is described in detail below.

[0036] (1) Encapsulate on-orbit programming data frame

[0037] According to the satellite's single data upload capability and the target software's programming data volume, the complete bitstream data after the onboard FPGA program is compiled is encapsulated into several fixed-length programming data frames. Each programming data frame that needs to be uploaded is marked with a frame sequence number. In addition to the frame header and footer, each programming data frame also includes a frame sequence number, an on-orbit programming valid data field, and a CRC code (Cyclic Redundancy Check). Finally, all programming data frames are divided into groups. The programming data frame structure is as follows: Figure 1 As shown in the figure, after the frame header, each programming data frame is encapsulated with a frame sequence number from 0 to N-1, and before the frame tail, the CRC code corresponding to the on-track programming data field is encapsulated. At the same time, considering the data volume limit of a single injection, the on-track programming data frame is reasonably divided into M groups, and it is ensured that the number of programming data frames in each group, except the last one, is a power of 2, that is, After being divided into M groups, the high bits of the frame sequence number can be used as group numbers from 0 to M-1.

[0038] For example, taking the xq7k325trf900 FPGA as an example, the total amount of data required for chip program execution is 11.4M bytes. To adapt to the communication protocol, the programming data frame uses 480 bytes as the effective data field, which can be divided into a total of 23,841 programming data frames. Each programming data frame encapsulates a 2-byte frame header, a 1-byte type code, and a 2-byte frame sequence number before the effective data field. After the effective data field, a 4-byte CRC checksum and a 1-byte cumulative checksum are encapsulated as the frame trailer. All in-orbit programming data frames are reasonably divided into 12 groups, each with 2048 frames (the 12th group has 1313 frames). In this way, for the 2-byte frame sequence number, the lower 11 bits can be used as the sequence number within each group, and the upper 5 bits can be used as the group number.

[0039] (2) Establishing Bitmap information storage area and mapping relationship

[0040] First, the basic idea of ​​Bitmap is to use a bit of Boolean value to mark the correctness or existence of an element. The present invention uses the address of each bit in the Bitmap to represent the serial number of the complete programming data frame, and uses the Boolean value of each bit in the Bitmap to represent whether the specific programming data frame is successfully transmitted and stored. The mapping relationship between the frame serial number in the programming data frame and the specific bit in the Bitmap is the core part of this solution. Figure 2 As shown in the figure. Next, two bitmap storage areas are created in the Flash chip and the onboard FPGA's internal RAM based on the frame sequence number. The establishment of two bitmap storage areas is based on the following considerations: Storing the bitmap in the Flash chip is key to ensuring power-off resume, allowing the current programming data frame to be restored after a single unit is powered on again. However, the Flash chip's read and write speeds are insufficient to ensure timely transmission of telemetry information from the onboard single unit. Therefore, an identical bitmap storage area must also be created in the onboard FPGA's internal RAM to ensure timely transmission. A RAM with a width of 1 bit and a depth of P is instantiated inside the onboard FPGA, which contains the bitmap size of the current group. Accordingly, a storage sector of N storage units containing the entire bitmap size is set in the Flash chip, which is used as two copies of the bitmap information for uploading programming data frames. The two pieces of information are kept updated synchronously after power-on, that is, the bitmap information in the Flash chip is read back to the RAM inside the onboard FPGA core after power-on. During the uploading of programming data frames, the onboard FPGA writes the bitmap information being updated in the internal RAM into the Flash chip, to ensure that the bitmap information is not lost in the event of power failure and can be transmitted back in time.

[0041] For example, in terms of Bitmap information storage management, the Bitmap stored in the Flash chip indicates whether all 23,841 programming data frames have been successfully uploaded, and the information will not be lost after power failure, but it cannot meet the requirements of timely data transmission of satellite single-machine telemetry information; the Bitmap information stored in the RAM inside the processing FPGA is limited by storage capacity and power failure restrictions. It only retains the Bitmap information of the programming data frames in the current group, indicating whether the 2,048 programming data frames in the current group have been successfully uploaded. The data will be lost after power failure, but it can meet the requirements of timely data transmission of telemetry information.

[0042] The bitmaps stored in the two areas are maintained synchronously: on the one hand, during the execution of the on-orbit programming function, if the uploaded programming data frame passes the verification, the processing FPGA must not only update the bitmap information of the current group in the internal RAM according to the frame sequence number, but also update the overall bitmap stored in the Flash chip through the control FPGA; on the other hand, after the processing FPGA is powered on and reloaded, the bitmap data in the internal RAM is cleared. If the transmission of the i-th group of programming data frames is to be restored, the bitmap information of the m-th group in the Flash chip needs to be read back to the processing FPGA through the control FPGA according to the m-1th programming successful group number stored in the Flash chip, so as to indicate the on-orbit programming data frame that currently needs to be uploaded.

[0043] (3) Programming data frame annotation and reception processing

[0044] During the execution of the on-orbit programming task by the satellite-borne stand-alone machine, it is first necessary to send instructions from the ground to specify the programming object, so that the control FPGA points to the starting position of the corresponding storage sector of the Flash chip. Every time the satellite-borne stand-alone machine receives the programming data frame injected from the ground, it will perform CRC check, repeatability check and group number check in sequence in the processing FPGA, wherein the CRC check is to ensure the correct transmission of the valid data field of the programming data frame, the repeatability check is to check whether the Bitmap has been set to 1 according to the frame sequence number, and the group number check is to ensure batch transmission by group, that is, the repeatability check and group number check are both to check whether the current programming data frame has completed transmission, avoiding repeated writing of the Flash chip due to erroneous operations on the ground. After the three checks are passed, the satellite-borne FPGA stores the valid data field in the programming data frame into the corresponding sector of the Flash chip according to the address corresponding to the frame sequence number. After the storage is completed, the satellite-borne FPGA sets the corresponding addresses in the two Bitmap storage areas to 1 according to the received frame sequence number, thereby marking that the current injected programming data frame has passed the check and stored successfully.

[0045] It should be noted that this embodiment adopts a group-uploading method for programming data frames, that is, the ground measurement and control station uploads 2048 consecutive programming data frames in the same group within the satellite arc time. After the FPGA receives the programming data frames forwarded by the satellite platform cache, it loops to receive, verify, and store them until all 2048 programming data frames in the group are uploaded. The addresses of the programming data frames with verification errors are left vacant, that is, set to 0.

[0046] (4) Reissue programming data frames that failed to be added or were not added according to the Bitmap information

[0047] If the on-orbit programming data injection lasts for a long time, during which time the satellite platform needs to power off a single unit or the satellite orbit exceeds the tracking and control arc, causing the onboard FPGA to be temporarily unable to continue the on-orbit programming injection task, the onboard FPGA will enter re-issuance mode. After the on-board unit is powered on again, the on-orbit programming injection task will be resumed. The on-board FPGA will read the bitmap information stored in the Flash chip and remap it to the internal RAM. The bitmap information will be sent back to the ground tracking and control station via telemetry to mark the programming data frame that failed or was not completed. The ground station parses the bitmap information sent back by telemetry and finds the address of the bit with a Boolean value of 0. This is mapped to the frame sequence number of the programming data frame encapsulation within the current group, corresponding to the programming data frame that failed or was not completed.

[0048] At this point, the ground control station completes the transmission task for that group by resending all programming data frames that failed verification or have not yet been uploaded. After all programming data frames in that group are successfully stored, the FPGA writes the corresponding group number to the Flash chip, and the next group of programming data frames can be uploaded at the next power-up. This non-continuous uploading method, which uses programming data frames as units, avoids the waste of satellite-to-ground link communication resources caused by repeated transmission of programming data frames and enables data uploading to resume after a power outage.

[0049] For example, during the execution of the sixth group programming, if the single programming data injection time exceeds the current arc time, the satellite platform needs to stop powering the unit. After the satellite platform next powers on the unit, the onboard unit returns the current sixth group's bitmap information to the ground through burst telemetry, such as 0xFFFFFFFF...7FE0000, a total of 512 hexadecimal numbers. This bitmap information indicates that the 2020th programming data frame and the last 17 frames of the sixth group failed to be injected successfully. After the onboard unit is powered on again, the ground tracking and control station can resend these 18 programming data frames separately to complete the on-orbit programming of the sixth group of data. The processing FPGA then writes 0x06 (the number of the currently programmed group) to the group number storage sector of the Flash chip via the control FPGA.

[0050] (5) Complete all programming data frames and reload

[0051] Repeat steps (3) and (4) in groups until M groups are reached. If all 12 groups of on-track programming data frames are successfully written, the Bitmap storage area is fully filled. The overall operation process can be found in Figure 3 At this time, another anti-fuse structure control FPGA will perform an overall CRC check on all the valid on-orbit programming data (such as a total of 11.4M bytes) received in the corresponding storage sector of the Flash chip. This process takes about 6 seconds. If the overall CRC check passes, it means that the entire on-orbit programming data transmission part of the on-board FPGA has been completed correctly, and the program can be correctly loaded and updated for use. The ground measurement and control station sends a loading source switching instruction or a single-machine reset instruction to power on the single machine again. The anti-fuse structure control FPGA is responsible for reading the corresponding program (such as reading 11.4M bytes of program data) from the on-orbit programming sector of the Flash chip and loading it into the on-board FPGA running area, thereby realizing the on-orbit reconstruction of the FPGA. The hardware circuit structure block diagram corresponding to this process is shown as follows. Figure 4 shown.

[0052] It should be noted that in the entire hardware circuit structure, the control FPGA is directly connected to the Flash chip and provides an interface for operating the Flash to the onboard FPGA. The control FPGA uses an anti-fuse structure and is responsible for program loading and reading and writing the Flash chip. It does not perform on-orbit programming. The processing FPGA uses an SRAM structure to program the target chip (i.e., the onboard FPGA) on-orbit, receive the programming data, and complete on-orbit reconstruction. The processing FPGA in the onboard stand-alone unit obtains the on-orbit programming data through the communication protocol data line connected to the satellite platform. After internal verification, the processing FPGA writes valid data to the corresponding storage sector of the Flash chip through the read and write interface provided by the control FPGA. The Flash program storage area is divided into a backup program storage area and an on-orbit programming program storage area. After the stand-alone unit is powered on, the control FPGA loads the data in the corresponding storage area of ​​the Flash chip into the processing FPGA.

[0053] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may of course make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A Bitmap-based FPGA on-orbit programming and power-off data injection method, wherein a control FPGA, a Flash chip, and a processing FPGA are provided on a single satellite machine, characterized in that: The method comprises the following steps: Encapsulate the bitstream file to be uploaded into multiple fixed-length programming data frames, and each programming data frame includes a frame sequence number, CRC code information, on-track programming valid data, frame header and frame footer; A storage area for bitmap information is created in the internal RAM and Flash chip of the onboard processing FPGA. Each bit of the bitmap corresponds one-to-one with the frame sequence number and storage address, and the Boolean value of each bit is used to indicate whether the programming data frame corresponding to each bit is successfully injected. The bitmap information stored in the internal RAM is cleared when power is lost, while the bitmap information stored in the Flash chip can still be saved after power loss. When the injection process is carried out continuously, after the onboard single machine receives the programming data frame injected from the ground, the processing FPGA performs CRC check and repeatability check on the received current programming data frame. If both pass, the on-orbit programming valid data in the current programming data frame is stored in the corresponding sector of the Flash chip through the control FPGA. After the storage is completed, the bits at the storage address corresponding to the frame sequence number of the current programming data frame in the two bitmap storage areas are set to 1; if any check fails or the storage fails, the bits at the storage address corresponding to the frame sequence number of the current programming data frame in the two bitmap storage areas are set to 0; When the injection process is interrupted and the onboard unit is powered off and restarted, the FPGA that is powered on again reads the bitmap information stored in the FLASH chip, rebuilds the bitmap information in the internal RAM, and returns the bitmap information to the ground measurement and control station through telemetry. The ground measurement and control station resends the programming data frame that has not passed the verification or has not been injected according to the frame sequence number corresponding to the 0 bit in the bitmap information, thereby realizing power-off transmission.

2. A Bitmap-based FPGA on-track programming power-off data injection method as claimed in claim 1, characterized in that: If the bitstream file to be uploaded exceeds the satellite single data upload limit or the bitstream file upload time exceeds the satellite arc time corresponding to the ground tracking and control station, all programming data frames will be grouped and each programming data frame will be uploaded in groups.

3. A Bitmap-based FPGA on-track programming power-off data injection method as claimed in claim 2, characterized in that: The grouped programming data frame consists of: a 2-byte frame header, a 1-byte type code, a 2-byte frame sequence number, on-track programming valid data, a 4-byte CRC check code, and a 1-byte cumulative sum check code as the frame tail. Among them, in the 2 bytes of the frame sequence number, the lower 11 bits are used to represent the frame sequence number in each group, and the upper 5 bits are used to represent the group number of each programming data frame.

4. A Bitmap-based FPGA on-track programming power-off data injection method as claimed in claim 2, characterized in that: The storage area in the Flash chip stores the bitmap information corresponding to all programming data frames in groups. One group of programming data frames corresponds to one group of bitmap information. The storage area of ​​the internal RAM of the FPGA only stores the bitmap information corresponding to the current group of programming data frames being uploaded.

5. A Bitmap-based FPGA on-track programming power-off data injection method as claimed in claim 4, characterized in that: When the injection process is interrupted and the onboard unit is powered off and restarted, only the Bitmap information group corresponding to the interrupted programming data frame group is read back from the Flash chip to the processing FPGA through the control FPGA, thereby indicating the programming data frame that needs to be continued or reissued.

6. A Bitmap-based FPGA on-track programming power-off data injection method as claimed in claim 2, characterized in that: After the onboard single machine receives the programming data frame injected on the ground, the processing FPGA performs CRC check, repeatability check and group number check on the received current programming data frame. If all of them pass, the on-orbit programming valid data in the current programming data frame is stored in the corresponding sector of the Flash chip through the control FPGA.

7. A Bitmap-based FPGA on-track programming and power-off data injection method as claimed in claim 1, characterized in that: When all programming data frames are successfully uploaded, the control FPGA performs an overall CRC check on all valid on-orbit programming data stored in the corresponding storage sector of the Flash chip. If the overall CRC check passes, the ground measurement and control station sends a loading source switching instruction or a single-machine reset instruction, and the control FPGA reads the valid on-orbit programming data from the Flash chip and loads it into the processing FPGA running area, thereby realizing on-orbit programming of the processing FPGA.

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