RISC-V extended instruction set construction method and device supporting dynamic reconstruction

Abstract

A method and device for constructing a RISC‑V extended instruction set supporting dynamic reconstruction can use the RISC‑V instruction set to tightly couple dynamic reconstruction control with a processor, thereby solving the problem of high resource occupation of bus logic in the traditional processor instruction set structure. The method includes: (1) constructing an extended instruction set adapted to an on-chip dynamic reconstruction interface for interactive operations between registers and ICAP interface data; (2) DPRC connects the on-chip reconstruction interface to the processor data path, thereby coupling the dynamic reconstruction controller with the processor data path; (3) After the DPRC instruction is fetched by the instruction fetch unit IF, it is sent to the DPRC module for processing through the instruction decoding unit IDU and the pre-decoding unit PDU, and finally the read data is written back to the register through the write back unit WBU.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for constructing a RISC-V extended instruction set that supports dynamic reconstruction. Background Art

[0002] The instruction set is an interface stored inside the processor that connects hardware and software. The processor completes complex computing tasks by reading instructions from memory, decoding and executing operations. Each processor has a specific instruction set corresponding to it, and the design of the instruction set directly affects the performance of the processor. In addition to setting the instruction set that supports basic operations and control, the processor design also needs to design an extended instruction set for specific application areas. The instruction set extension for specific application areas can simplify the process, allowing the processor to execute directly according to the decoded information, avoiding the complex computing process generated by the basic instruction set and causing waste of resources.

[0003] The RISC-V instruction set is a completely open, standard, open-source reduced instruction set (RISC) architecture that can support a variety of applications. The instruction set adopts a modular design and provides a large amount of custom coding space to support the expansion of the instruction set, allowing developers to carry out refined device design based on some specific modules and extended instruction sets according to different requirements such as resources, energy consumption, permissions, and real-time performance. It can be found in everything from embedded devices to high-performance computing (HPC), reflecting the powerful device customization capabilities.

[0004] Through the open instruction set standard, RISC-V has spawned a large number of open source processors based on the RISC-V instruction set, such as Xiangshan, BOOM, Hummingbird, Rocket, and VexRiscv. The design process of these processors fully utilizes the extended features of the RISC-V instruction set to achieve optimization and customization for different application scenarios. RISC-V has integrated nearly 20 extended instruction sets, each of which has its own application field. For example, the h extended instruction set is used to implement hardware virtualization, the b instruction set extension can be used to accelerate bit-level operations, and the k extension is used to accelerate common encryption and decryption algorithm operations such as aes, sha2, sm3, and sm4.

[0005] At present, the optimization of traditional dynamic reconfiguration control in various application scenarios is mainly to improve the transmission from external memory to internal memory, and the part from internal memory to the reconfiguration controller buffer has not been effectively optimized. There is relatively little research on the improvement of the dynamic reconfiguration control scheme itself, resulting in the failure to effectively improve the overall performance and area optimization in essence. In addition, the existing research is only carried out on a single device, these schemes lack universality and are difficult to implement on other devices. At present, when the processor performs dynamic reconfiguration control, it mainly relies on device buses such as AXI. Such methods have high bus overhead and occupy a lot of resources, which increases the complexity and cost of the device to a certain extent. At the same time, these buses may also cause unnecessary occupation of the logic resources of the static part. Tightly coupling dynamic reconfiguration control with the processor to reduce the resources occupied by bus logic is a better solution. This tightly coupled structure is difficult to achieve with the traditional processor instruction set structure, and the RISC-V instruction set provides an innovative way to solve this problem, but there is currently no instruction set specifically for dynamic reconfigurable control, so the development of such an instruction set is crucial to the development of dynamic reconfigurable control. Summary of the invention

[0006] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a method for constructing a RISC-V extended instruction set that supports dynamic reconstruction, which can use the RISC-V instruction set to tightly couple the dynamic reconstruction control with the processor, and solve the problem of high resource occupation of bus logic in the traditional processor instruction set structure.

[0007] The technical solution of the present invention is: a method for constructing a RISC-V extended instruction set that supports dynamic reconstruction, wherein a dynamic reconstruction device comprises: a processor soft core for controlling dynamic reconstruction, a dynamic reconstruction controller for interacting with an internal configuration access interface ICAP interface, and a configuration controller module for writing configuration data into a configuration RAM, wherein the method comprises the following steps:

[0008] (1) Build an extended instruction set that is compatible with the on-chip dynamic reconfiguration interface for interactive operations between registers and ICAP interface data;

[0009] (2) The dynamic partial reconfiguration controller (DPRC) connects the on-chip reconfiguration interface to the processor data path, thereby coupling the dynamic reconfiguration controller soft core with the processor data path;

[0010] (3) DPRC After the instruction is fetched by the instruction fetch unit IF, it is sent to the DPRC for processing through the instruction decoding unit IDU and the pre-decoding unit PDU. Finally, the read data is written back to the register through the write back unit WBU.

[0011] The present invention reduces the overhead used for dynamic reconfiguration control and processor interaction in the traditional structure by designing a tightly coupled data path, thereby effectively reducing the logic resource area required for the dynamic reconfiguration control part. The finer-grained microinstructions of the present invention bring about a shorter pipeline beat, thereby achieving a higher clock frequency. The parameterized multi-cycle model proposed in the present invention achieves adaptation to different devices and different timing requirements, effectively increases the versatility of DPRC on various devices, and optimizes the timing characteristics, thereby increasing the clock frequency.

[0012] A RISC-V extended instruction set construction device supporting dynamic reconstruction is also provided, the dynamic reconstruction device comprising: a processor soft core for controlling dynamic reconstruction, a dynamic reconstruction controller for interacting with an ICAP interface, and a CFGC module for writing configuration data into a CRAM. The RISC-V extended instruction set construction device supporting dynamic reconstruction comprises:

[0013] An extension module configured to construct an extended instruction set compatible with the on-chip dynamic reconfiguration interface for interactive operations between registers and ICAP interface data;

[0014] A coupling module configured as a DPRC to connect an on-chip reconfiguration interface to a processor data path, thereby coupling a dynamic reconfiguration controller soft core to the processor data path;

[0015] The processing module is configured as follows: After the DPRC instruction is fetched by the instruction fetch unit IF, it is sent to the DPRC module for processing through the instruction decoding unit IDU and the pre-decoding unit PDU, and finally the read data is written back to the register through the write back unit WBU. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A system structure block diagram of a RISC-V extended instruction set construction device supporting dynamic reconstruction according to the present invention is shown.

[0017] Figure 2 An R-type instruction structure according to the present invention is shown.

[0018] Figure 3 The encoding format used by the DPRC extended instruction set according to the present invention is shown.

[0019] Figure 4 The structure of a processor supporting the DPRC extended instruction set according to the present invention is shown.

[0020] Figure 5 The microinstruction control flow according to the present invention is shown.

[0021] Figure 6The DPRC microinstruction definition according to the present invention is shown.

[0022] Figure 7 A flowchart of a method for constructing a RISC-V extended instruction set supporting dynamic reconstruction according to the present invention is shown. DETAILED DESCRIPTION

[0023] like Figure 1-4 As shown in , 7, the RISC-V extended instruction set construction method supporting dynamic reconstruction, the dynamic reconstruction device includes: a processor soft core for controlling dynamic reconstruction, a dynamic reconstruction controller for interacting with an ICAP (Internal Configuration Access Ports, internal configuration access interface) interface, and a CFGC (Configuration Controller) module for writing configuration data into a CRAM (Configuration RAM, configuration RAM), and the method includes the following steps:

[0024] (1) Build an extended instruction set that is compatible with the on-chip dynamic reconfiguration interface for interactive operations between registers and ICAP interface data;

[0025] (2) DPRC (Dynamic Partial Reconfiguration Controller) connects the on-chip reconfiguration interface to the processor data path, thereby coupling the dynamic reconfiguration controller soft core with the processor data path;

[0026] (3) After the DPRC instruction is fetched by the instruction fetch unit IF, it is sent to the DPRC module for processing through the instruction decoding unit IDU and the pre-decoding unit PDU. Finally, the read data is written back to the register through the write back unit WBU.

[0027] The present invention reduces the overhead used for dynamic reconfiguration control and processor interaction in the traditional structure by designing a tightly coupled data path, thereby effectively reducing the logic resource area required for the dynamic reconfiguration control part. The finer-grained microinstructions of the present invention bring about a shorter pipeline beat, thereby achieving a higher clock frequency. The parameterized multi-cycle model proposed in the present invention achieves adaptation to different devices and different timing requirements, effectively increases the versatility of DPRC on various devices, and optimizes the timing characteristics, thereby increasing the clock frequency.

[0028] Preferably, in step (2), DPRC uses a combination of a microinstruction sequence and a pipeline, and DPRC interacts with the ICAP interface to perform read and write operations on the ICAP interface, thereby achieving dynamic reconstruction.

[0029] Preferably, in step (3), the PDU translates the current state and the input instruction into a microinstruction address, the IDU sends the instruction to its corresponding instruction processing pipeline, the code stream write bsw, the dual code stream write bsdw and the code stream read bsr are the corresponding instruction processing pipelines, and the ICAP interface in a specific state is read and written; the RW Changer is a read-write conversion processing pipeline, which is used for logical processing during read-write and write-read switching; the WBU is used to write the data obtained by each pipeline back to the register; the split point of the pipeline level is set at bsw, bsdw, bsr and RW Changer, and the instruction processing flow is streamlined by inserting registers at the split point.

[0030] Preferably, in step (3), the microinstruction with address 0000 is used to process the bsw instruction, and outputs the data in rs1 to the ICAP interface before exiting the instruction execution; the microinstructions with addresses 0001 and 0010 are used to process the bsdw instruction, which outputs the data in rs1 to the ICAP interface at the address 0001 in the first clock cycle, and outputs the data in rs2 to the ICAP interface at the address 0010 in the second clock cycle, and then exits the execution.

[0031] Preferably, in step (3), the microinstruction at address 0011 is used to process the bsr instruction, write the output of the ICAP interface into the rd register, complete the write-back, and terminate the instruction execution.

[0032] Preferably, in step (3), the microinstruction with an address between 01xx and 11xx is used to complete the RW Changer instruction, and is executed when the PDU detects that the instruction is different from the current read-write state; wherein the address 01xx is the stage of pulling up the CSIB, then jumping to the address 10xx, flipping the RDWRB state, and finally jumping to the address 11xx, pulling down the CSIB to complete the change of the read-write state; then jumping to the address between 0000 and 0011, and executing the corresponding microinstruction.

[0033] Preferably, in step (3), the PDU's judgment of the current state enables the RW Changer pipeline to participate in the execution of the overall pipeline in a timely manner according to different situations, thereby realizing a variable pipeline level structure; at the same time, fine-grained microinstructions bring about a short pipeline beat and achieve a high clock frequency.

[0034] A person of ordinary skill in the art can understand that all or part of the steps in the above-mentioned embodiment method can be implemented by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps of the above-mentioned embodiment method, and the storage medium can be: ROM / RAM, disk, optical disk, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also includes a RISC-V extended instruction set construction device that supports dynamic reconstruction, and the device is usually represented in the form of functional modules corresponding to the steps of the method. The dynamic reconstruction device includes: a processor soft core for controlling dynamic reconstruction, a dynamic reconstruction controller for interacting with the ICAP interface, and a CFGC module for writing configuration data to CRAM. The RISC-V extended instruction set construction device that supports dynamic reconstruction includes:

[0035] An extension module configured to construct an extended instruction set compatible with the on-chip dynamic reconfiguration interface for interactive operations between registers and ICAP interface data;

[0036] A coupling module configured as a DPRC to connect an on-chip reconfiguration interface to a processor data path, thereby coupling a dynamic reconfiguration controller soft core to the processor data path;

[0037] The processing module is configured as follows: After the DPRC instruction is fetched by the instruction fetch unit IF, it is sent to the DPRC module for processing through the instruction decoding unit IDU and the pre-decoding unit PDU, and finally the read data is written back to the register through the write back unit WBU.

[0038] Preferably, in the coupling module, DPRC uses a combination of a microinstruction sequence and a pipeline, and DPRC performs read and write operations on the ICAP interface by interacting with the ICAP interface, thereby achieving dynamic reconstruction.

[0039] Preferably, in the processing module, the PDU translates the current state and input instructions into microinstruction addresses, the IDU sends the instructions to its corresponding instruction processing pipeline, the code stream write bsw, the dual code stream write bsdw and the code stream read bsr are the corresponding instruction processing pipelines, and read and write processing is performed on the ICAP interface in a specific state; the RW Changer is a read-write conversion processing pipeline, which is used for logical processing during read-write and write-read switching; the WBU is used to write the data obtained by each pipeline back to the register; the split points of the pipeline levels are set at bsw, bsdw, bsr and RW Changer, and the instruction processing flow is streamlined by inserting registers at the split points.

[0040] The present invention is described in more detail below.

[0041] The current dynamic reconfiguration system generally includes the following three main parts: a processor soft core for controlling dynamic reconfiguration, a dynamic reconfiguration controller for interacting with the ICAP interface, and a CFGC module responsible for writing configuration data into CRAM.

[0042] Figure 1 The DPRC dynamic reconfiguration system solution of the present invention is demonstrated, in which all parts except CFGC in the existing dynamic reconfiguration system are replaced with a structure combining a RISC-V soft core and a DPRC extended instruction set, thereby realizing a better dynamic reconfiguration control solution.

[0043] The present invention provides a RISC-V extended instruction set, which supports FPGA dynamic reconstruction.

[0044] Figure 2 The extended instruction set adapted to the on-chip dynamic reconfiguration interface is mainly used for interactive operations between registers and ICAP interface data. The functions of these instructions are similar to the R-type instruction set of the RISC-V architecture, and other components such as immediate values ​​are not required. Therefore, the decoding part of the instruction can be reused, simplifying the implementation and reducing resource (area) occupancy.

[0045] DPRC connects the on-chip reconfiguration interface to the processor data path, thereby achieving tight coupling between the dynamic reconfiguration control part and the processor data path. Figure 3 The encoding format used by the DPRC extended instruction set is demonstrated, in which the func3 segment can be used to directly control the read and write enable of the GPR, which can optimize the combinational logic delay caused by the decoding logic and increase the main frequency.

[0046] The location of the FPGA dynamic reconfiguration extension in the processor is as follows: Figure 4 As shown in the figure, the processor structure diagram shows the location of the DPRC extended instruction set in the data path, and interacts with other parts through GPR (General Propose Register). Similar to the processing process of other instructions, the DPRC instruction is taken out by the IF (Instruction Fetch Unit), and then sent to the DPRC module for processing through the IDU (Instruction Decode Unit) and PDU (PreDecodeUnit). Finally, the read data is written back to the register through the WBU (Write BackUnit).

[0047] Furthermore, in order to avoid the tight integration of DPRC and the processor from affecting the processor's main frequency and reducing the overall performance, DPRC adopts a design that combines microinstruction sequence with pipeline.

[0048] Specifically, DPRC mainly interacts with the ICAP interface to implement read and write operations on the ICAP interface, thereby achieving dynamic reconstruction.

[0049] Specifically, Figure 5 The main control flow of DPRC is described. In the figure, PDU is used to translate the current state and input instructions into microinstruction addresses. IDU is the DPRC instruction decoding module, which is used to send instructions to its corresponding instruction processing pipeline. bsw (bitstream write), bsdw (bitstream dual write) and bsr (bitstream read) are the corresponding instruction processing pipelines, which are used for read and write processing of the ICAP interface in a specific state. RW Changer is a read-write conversion processing pipeline, which is used for logical processing during read-write and write-read switching. WBU is used to write the data obtained by each pipeline back to the register. The vertical lines in the figure indicate the division points of the pipeline stage. The instruction processing flow is pipelined by inserting registers to achieve a higher main frequency.

[0050] Specifically, Figure 5 The microinstructions used to implement the structure in the block diagram are as follows Figure 6As shown in the figure, the microinstruction with address (addr) "0000" is used to process the bsw instruction, outputs the data in rs1 to the ICAP interface and then exits the instruction execution. The microinstructions with addresses "0001" and "0010" are used to process the bsdw instruction. At the first clock cycle, i.e., address "0001", the data in rs1 is output to the ICAP interface, and at the second clock cycle, i.e., address "0010", the data in rs2 is output to the ICAP interface, and then exits the execution. The microinstruction with address "0011" is used to process bsr, writes the output of the ICAP interface to the rd register, completes the write-back, and ends the instruction execution. The microinstructions with addresses between "01xx" and "11xx" are used to complete the RW Changer, i.e., read-write conversion function, and are executed when the PDU detects that this instruction is different from the current read-write state. The address "01xx" is the stage of pulling up CSIB, then jumping to the address "10xx", flipping the RDWRB state, and finally jumping to the address "11xx", pulling down CSIB to complete the change of read and write status. Then jump to the address between "0000" and "0011" to execute the corresponding microinstructions. The PDU's judgment of the current state enables the RW Changer pipeline to participate in the execution of the overall pipeline in a timely manner according to different situations, realizing a variable pipeline level structure. At the same time, finer-grained microinstructions bring shorter pipeline beats, thereby achieving higher clock frequencies.

[0051] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A method for constructing a RISC-V extended instruction set supporting dynamic reconstruction, wherein the dynamic reconstruction device comprises: A processor soft core for controlling dynamic reconfiguration, a dynamic reconfiguration controller for interacting with an internal configuration access interface ICAP interface, and a configuration controller module for writing configuration data into a configuration RAM, characterized in that it includes the following steps: (1) Build an extended instruction set that is compatible with the on-chip dynamic reconfiguration interface for interactive operations between registers and ICAP interface data; (2) The dynamic partial reconfiguration controller (DPRC) connects the on-chip reconfiguration interface to the processor data path, thereby coupling the dynamic reconfiguration controller soft core with the processor data path; (3) After the DPRC instruction is fetched by the instruction fetch unit IF, it is sent to the DPRC for processing through the instruction decoding unit IDU and the pre-decoding unit PDU. Finally, the read data is written back to the register through the write back unit WBU. In the step (2), DPRC uses a combination of a microinstruction sequence and a pipeline, and DPRC interacts with the ICAP interface to perform read and write operations on the ICAP interface, thereby achieving dynamic reconstruction.

2. The method for constructing a RISC-V extended instruction set supporting dynamic reconfiguration according to claim 1, characterized in that: In the step (3), the PDU translates the current state and the input instruction into a microinstruction address, and the IDU sends the instruction to its corresponding instruction processing pipeline. The code stream write bsw, the dual code stream write bsdw and the code stream read bsr are the corresponding instruction processing pipelines, which perform read and write processing on the ICAP interface in a specific state; RW Changer is a read-write conversion processing pipeline, which is used for logical processing during read-write and write-read switching; WBU is used to write the data obtained by each pipeline back to the register; the split points of the pipeline stages are set in bsw, bsdw, bsr, and RW Changer, and the instruction processing flow is pipelined by inserting registers at the split points.

3. The method for constructing a RISC-V extended instruction set supporting dynamic reconfiguration according to claim 2, characterized in that: In the step (3), the microinstruction with address 0000 is used to process the bsw instruction, outputs the data in rs1 to the ICAP interface and then exits the instruction execution; the microinstructions with addresses 0001 and 0010 are used to process the bsdw instruction, which outputs the data in rs1 to the ICAP interface at the address 0001 in the first clock cycle, and outputs the data in rs2 to the ICAP interface at the address 0010 in the second clock cycle, and then exits the execution.

4. The method for constructing a RISC-V extended instruction set supporting dynamic reconfiguration according to claim 3, characterized in that: In the step (3), the microinstruction at address 0011 is used to process the bsr instruction, write the output of the ICAP interface into the rd register, complete the write-back, and the instruction execution ends.

5. The method for constructing a RISC-V extended instruction set supporting dynamic reconfiguration according to claim 4, characterized in that: In the step (3), the microinstruction with the address between 01xx and 11xx is used to complete the RW Changer instruction, and is executed when the PDU detects that the instruction is different from the current read-write state; wherein the address 01xx is the stage of pulling up the CSIB, then jumping to the address 10xx, flipping the RDWRB state, and finally jumping to the address 11xx, pulling down the CSIB to complete the change of the read-write state; then jumping to the address between 0000 and 0011, and executing the corresponding microinstruction.

6. The method for constructing a RISC-V extended instruction set supporting dynamic reconfiguration according to claim 5, characterized in that: In the step (3), the PDU's judgment of the current state enables the RW Changer pipeline to participate in the execution of the overall pipeline in a timely manner according to different situations, thereby realizing a variable pipeline level structure; at the same time, fine-grained microinstructions bring about a short pipeline beat and achieve a high clock frequency.

7. A RISC-V extended instruction set construction device supporting dynamic reconstruction, the dynamic reconstruction device comprising: A processor soft core for controlling dynamic reconfiguration, a dynamic reconfiguration controller for interacting with an ICAP interface, and a CFGC module for writing configuration data into a CRAM, wherein the RISC-V extended instruction set construction device supporting dynamic reconfiguration comprises: An extension module configured to construct an extended instruction set compatible with the on-chip dynamic reconfiguration interface for interactive operations between registers and ICAP interface data; A coupling module configured as a DPRC to connect an on-chip reconfiguration interface to a processor data path, thereby coupling a dynamic reconfiguration controller soft core to the processor data path; The processing module is configured such that after the DPRC instruction is fetched by the instruction fetch unit IF, it is sent to the DPRC module for processing through the instruction decoding unit IDU and the pre-decoding unit PDU, and finally the read data is written back to the register through the write back unit WBU; In the coupling module, DPRC combines microinstruction sequence with pipeline, and DPRC performs read and write operations on the ICAP interface by interacting with the ICAP interface, thereby realizing dynamic reconstruction.

8. The RISC-V extended instruction set construction device supporting dynamic reconfiguration according to claim 7, characterized in that: In the processing module, PDU translates the current state and input instructions into microinstruction addresses, IDU sends instructions to its corresponding instruction processing pipeline, code stream write bsw, dual code stream write bsdw and code stream read bsr are corresponding instruction processing pipelines, which perform read and write processing on the ICAP interface in a specific state; RW Changer is a read-write conversion processing pipeline, which is used for logical processing during read-write and write-read switching; WBU is used to write the data obtained by each pipeline back to the register; the split points of the pipeline stages are set in bsw, bsdw, bsr, and RW Changer, and the instruction processing flow is pipelined by inserting registers at the split points.

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