Current accumulator, data transmission circuit, and semiconductor device

Abstract

The embodiment of the present disclosure provides a current accumulator, a data transmission circuit and a semiconductor device. The current accumulator comprises: a switch tube connected between a feedback node and a ground terminal; and an inverter, an input end of the inverter receiving a feedback signal, and an output end of the inverter being connected to a control end of the switch tube, the switch tube being turned on or turned off in response to a level of the control end, so as to turn on or turn off between the feedback node and the ground terminal, thereby adjusting the level of the feedback node. The embodiment of the present disclosure is beneficial to improving the response rate of the current accumulator.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a current accumulator, a data transmission circuit and a semiconductor device. BACKGROUND

[0002] In memory applications, as the signal transmission rate is getting faster and the clock frequency is increasing, the input data channel loss has a greater impact on the signal quality, which easily leads to intersymbol interference (ISI). ISI refers to a phenomenon that the transmission of the current input data is affected by the previously transmitted input data due to the limitation of the bandwidth of the input data channel. At present, the FFE (Continuous Time Linear Equalizer) or DFE (Decision Feedback Equalizer) is usually used to correct or adjust the current transmission data signal to reduce the interference of the previously transmitted data signal on the current transmission data signal.

[0003] However, the response rate of the previously transmitted data signal to correct the current transmission data signal in the current data transmission circuit still needs to be improved. SUMMARY

[0004] Embodiments of the present disclosure provide a current accumulator, a data transmission circuit and a semiconductor device, which can at least improve the response rate of the current accumulator, thereby improving the response rate of the previously transmitted data signal to correct the current transmission data signal.

[0005] According to some embodiments of the present disclosure, in one aspect, a current accumulator is provided, which is applied to a data transmission circuit, and the data transmission circuit is used to output a feedback signal, and the feedback signal is obtained by sampling a previously transmitted data signal; the current accumulator comprises: a switch tube connected between a feedback node and a ground end, wherein the level of the feedback node is controlled by a current transmission data signal of the data transmission circuit; and an inverter, wherein an input end of the inverter receives the feedback signal, and an output end of the inverter is connected to a control end of the switch tube, and the switch tube is turned on or turned off in response to the level of the control end, so as to turn on or turn off between the feedback node and the ground end, thereby adjusting the level of the feedback node.

[0006] In some embodiments, the switch tube is a first NMOS tube; the inverter comprises a first PMOS tube and a second NMOS tube, a source of the first PMOS tube is connected to a working power supply, a drain of the first PMOS tube is connected to a drain of the second NMOS tube and serves as an output terminal of the inverter, a source of the second NMOS tube is connected to the ground terminal, and a gate of the first PMOS tube is connected to a gate of the second NMOS tube and serves as an input terminal of the inverter.

[0007] In some embodiments, the feedback signal comprises a first feedback signal and a first differential feedback signal which are differential to each other; the feedback node comprises a first feedback node and a second feedback node; the number of switch tubes is two, one of the switch tubes is connected between the first feedback node and the ground terminal, and the other switch tube is connected between the second feedback node and the ground terminal; the inverter corresponds to the switch tube; the current accumulator further comprises a gating circuit configured to receive the first feedback signal and the first differential feedback signal, and in response to a control signal, select one of the first feedback signal or the first differential feedback signal to be transmitted to an input terminal of one of the inverters, and select the other of the first feedback signal or the first differential feedback signal to be transmitted to an input terminal of the other inverter.

[0008] In some embodiments, the gating circuit comprises a first selector, an output terminal of the first selector is connected to an input terminal of the inverter corresponding to one of the switch tubes, the first selector receives the first feedback signal and the first differential feedback signal, and in response to the control signal, outputs one of the first feedback signal or the first differential feedback signal; and a second selector, an output terminal of the second selector is connected to an input terminal of the inverter corresponding to the other of the switch tubes, the second selector receives the first feedback signal and the first differential feedback signal, and in response to the control signal, outputs the other of the first feedback signal or the first differential feedback signal.

[0009] In some embodiments, the control signal comprises a first control signal and a second control signal which are opposite to each other; the first selector comprises: a first transmission gate having a first positive control end and a first negative control end, an input end receiving the first feedback signal, and an output end connected to an input end of a corresponding inverter, the first positive control end receiving the first control signal, and the first negative control end receiving the second control signal; a second transmission gate having a second positive control end and a second negative control end, an input end receiving the first differential feedback signal, and an output end connected to an input end of a corresponding inverter, the second positive control end receiving the second control signal, and the second negative control end receiving the first control signal, wherein the output end of the first transmission gate and the output end of the second transmission gate are connected to an input end of the same inverter; the second selector comprises: a third transmission gate having a third positive control end and a third negative control end, an input end receiving the first feedback signal, and an output end connected to an input end of a corresponding inverter, the third positive control end receiving the second control signal, and the third negative control end receiving the first control signal; a fourth transmission gate having a fourth positive control end and a fourth negative control end, an input end receiving the first differential feedback signal, and an output end connected to an input end of a corresponding inverter, the fourth positive control end receiving the first control signal, and the fourth negative control end receiving the second control signal, wherein the output end of the third transmission gate and the output end of the fourth transmission gate are connected to an input end of the same inverter.

[0010] In some embodiments, the first transmission gate, the second transmission gate, the third transmission gate, and the fourth transmission gate are CMOS transmission gates.

[0011] In some embodiments, the current accumulator further comprises: a load connected between the switch tube and the ground terminal.

[0012] In some embodiments, the load is configured to be adjusted in response to a tap adjustment signal so that an equivalent resistance of the load is adjustable.

[0013] In some embodiments, the tap adjustment signal comprises a plurality of sub-signals; the load comprises: a plurality of third NMOS tubes connected in parallel between the switch tube and the ground terminal; wherein a gate of each third NMOS tube receives a corresponding sub-signal, and the third NMOS tube is controlled to be turned on or turned off by the sub-signal.

[0014] In some embodiments, an odd number of the inverters are connected in sequence, and an output end of the last-stage inverter is connected to a control terminal of the switch tube.

[0015] In some embodiments, the number of inverters is even, and the output of the last inverter is connected to the control terminal of the switch tube. According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a data transmission circuit, comprising: a transmitter having a first input terminal and a first output terminal, configured to output a data signal via the first output terminal in response to a clock signal; a transmission channel connected to the first output terminal, configured to transmit the data signal output by the transmitter; a receiver having a second input terminal and a second output terminal, configured to receive the data signal transmitted by the transmission channel at the second input terminal, and output the data signal via the second output terminal in response to the clock signal; and the current accumulator provided by any of the above embodiments, wherein the feedback node is the first output terminal or the second input terminal.

[0016] According to some embodiments of the present disclosure, still another aspect of the embodiments of the present disclosure further provides a data transmission circuit, comprising: M data paths, each of which receives a data signal and a sampling clock, and outputs a target data and a feedback signal, and the phase of the sampling clock received by each of the data paths is different from each other, and the i-th data path is any of the data paths in the M data paths, 1≤i≤M, and M≥2; the i-th data path comprises: an amplification circuit configured to amplify the voltage difference between the data signal and a reference voltage and output a differential signal pair; a sampling circuit configured to receive a corresponding sampling clock, sample the differential signal pair and output; and at least one current accumulator provided by any of the above embodiments, wherein the output terminal of the amplification circuit is the feedback node, and the input terminal of the inverter of each current accumulator receives the feedback signal output by the sampling circuit of a corresponding data path.

[0017] According to some embodiments of the present disclosure, still another aspect of the embodiments of the present disclosure further provides a semiconductor device comprising the data transmission circuit provided by any of the above embodiments.

[0018] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0019] The embodiments of the present disclosure provide a current accumulator, an inverter is added before the control terminal of the switch tube of the current accumulator, in this way, the rising edge or the falling edge of the feedback signal received by the control terminal of the switch tube is reduced, so that the time required for the switch tube to reach the maximum on state is shortened, thereby improving the response rate of the current accumulator, shortening the response time of the current accumulator, and enabling the current accumulator to adjust the level of the feedback node based on the received feedback signal faster. In this way, the response rate of the current accumulator adjusting the level of the feedback node, i.e., the response rate of the previously transmitted data signal correcting the currently transmitted data signal, can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A data transmission circuit in the related art;

[0022] Figure 2 A block diagram of a current accumulator provided in an embodiment of the present disclosure;

[0023] Figure 3 Waveform diagrams of data signals received by the control end of the switch tube in the embodiment of the present disclosure and data signals received by the control end of the switch tube in the related art;

[0024] Figure 4 1 is a circuit structure diagram of a current accumulator;

[0025] Figure 5 Schematic diagram of another circuit structure of the current accumulator;

[0026] Figure 6 Schematic diagram of another circuit structure of the current accumulator;

[0027] Figure 7 Schematic diagram of another circuit structure of the current accumulator;

[0028] Figure 8 A schematic diagram of a circuit structure of a gating circuit in a current accumulator;

[0029] Figure 9 A schematic diagram of a circuit structure of a CMOS transmission gate;

[0030] Figure 10 is another block diagram of the current accumulator;

[0031] Figure 11 A circuit structure diagram of a load;

[0032] Figure 12 Schematic diagram of another circuit structure of the current accumulator;

[0033] Figure 13 and Figure 14 Two block diagrams of data transmission circuit provided by embodiments of the present disclosure;

[0034] Figure 15 and Figure 16 Two other block diagrams of data transmission circuit;

[0035] Figure 17 An architectural diagram of data transmission circuit provided by embodiments of the present disclosure;

[0036] Figure 18 A circuit structure diagram of current summer in a data path. DETAILED DESCRIPTION

[0037] Taking the application of current summer in DFE (Decision Feedback Equalizer) as an example, Figure 1 A data transmission circuit in the related art. The data transmission circuit includes an amplifier 10, a sampler 11, and at least one current summer 12. The amplifier 10 receives input data, and outputs an internal signal to a first node n1 and an internal differential signal to a second node n2. The sampler 11 is connected to the first node n1 and the second node n2, and samples the signals of the first node n1 and the second node n2 in response to a sampling clock signal dqs to output a sampling signal. The current summer 12 is connected to the first node n1 and the second node n2, and includes a first switch tube m1 and a second switch tube m2. One end of the first switch tube m1 and one end of the second switch tube m2 are connected to the first node n1 and the second node n2, respectively. The other end of the first switch tube m1 and the other end of the second switch tube m2 are connected to a bias circuit 13.

[0038] According to the number of bits of the input data participating in DFE in the previously transmitted input data, the feedback equalization adjustment circuit in the data receiving circuit can be divided into 1-tap, 2-tap, 3-tap, and 4-tap equalization circuits. The feedback equalization adjustment circuit can even have more taps (i.e., the number of taps can be greater than 4). A tap can be understood as a tap adjustment circuit. Each tap adjustment circuit corresponds to a tap signal, and the tap signal corresponds to a bit of data. The current transmitted input data is adjusted according to the tap signal. Among them, 1-tap means that 1 bit of data in the previously transmitted data participates in DFE; 2-tap means that 2 bits of data in the previously transmitted data participate in DFE; 3-tap means that 3 bits of data in the previously transmitted data participate in DFE; and 4-tap means that 4 bits of data in the previously transmitted data participate in DFE.

[0039] It should be noted that, if specified, in the embodiments of the present disclosure, n-tap refers to n bits of previously transmitted data participating in DFE, and Tap-n refers to the nth bit of previously transmitted data participating in DFE. For example, Tap-1 refers to the first bit of previously transmitted data participating in DFE, and Tap-2 refers to the second bit of previously transmitted data participating in DFE.

[0040] Specifically, the sampling signal output by the sampler 11 can be used as a feedback signal participating in DFE to adjust the level of the signal of the input data currently transmitted, wherein the feedback signal is based on sampling the input data previously transmitted. The transmission path of the feedback signal output by the sampler 11 to the current accumulator 12 is a feedback path.

[0041] Among them, the feedback signal is usually a differential signal. For a current accumulator 12, the gate of the first switch tube m1 and the gate of the second switch tube m2 respectively receive one of the differential signals, which is denoted as fb1_p, and the other signal is denoted as fb1_n. Among them, each current accumulator 12 receives a feedback signal based on sampling one bit of input data previously transmitted. Taking the number of current accumulators 12 as n for example, the two differential signals received by the nth current accumulator 12 are denoted as fbn_p and fbn_n, and n can be any natural number greater than or equal to 1.

[0042] It can be understood that the differential signals fb1_p and fb1_n correspond to the feedback signal of the first bit of previously transmitted data participating in DFE described above, and the differential signals fbn_p and fbn_n correspond to the feedback signal of the nth bit of previously transmitted data participating in DFE described above.

[0043] By the two differential signals in the feedback signal, the first switch tube m1 or the second switch tube m2 is controlled to reach the maximum on state, thereby adjusting the level of the first node n1 or the second node n2 to improve the problem of inter-symbol interference.

[0044] However, in the above-mentioned circuit, for the transmission path of the feedback signal to the current accumulator 12, there is usually a large load and a long path, which results in that the rising edge time and the falling edge time of the two differential signals in the feedback signal are large during the transmission of the two signals to the gate of the first switch tube m1 and the gate of the second switch tube m2. This results in that the first switch tube m1 and the second switch tube m2 reach the maximum on state for a long time, thereby causing the response rate of the current accumulator 12 to slow down, that is, affecting the feedback time required for the current accumulator 12 to adjust the level of the first node n1 and the second node n2.

[0045] Therefore, there is still room for improvement in the response rate of the previously transmitted data signal to correct or adjust the currently transmitted data signal.

[0046] Based on this, the current accumulator provided by the embodiments of the present disclosure adds an inverter before the control end of the switch tube of the current accumulator, in this way, the rising edge time or the falling edge time of the feedback signal received by the control end of the switch tube is reduced, so that the time required for the switch tube to reach the maximum on state is shortened, thereby improving the response rate of the current accumulator and shortening the response time of the current accumulator, so that the current accumulator can adjust the level of the feedback node based on the received feedback signal faster.

[0047] The current accumulator provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are presented in order to make the reader better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by the embodiments of the present disclosure can still be implemented.

[0048] Figure 2 A block diagram of the current accumulator provided by the embodiments of the present disclosure.

[0049] Reference Figure 2 The current accumulator 101 is applied to a data transmission circuit, the data transmission circuit is used to output a feedback signal FB, and the feedback signal is based on sampling a previously transmitted data signal. The current accumulator 101 includes a switch tube 111 and an inverter Inv. The switch tube 111 is connected between the feedback node NET and the ground end GND, and the level of the feedback node NET is controlled by the currently transmitted data signal of the data transmission circuit. The input end of the inverter Inv receives the feedback signal FB, and the output end is connected to the control end of the switch tube 111. Wherein, the switch tube 111 is turned on or turned off in response to the level of the control end, so as to turn on or turn off between the feedback node NET and the ground end GND, thereby adjusting the level of the feedback node NET.

[0050] The level of the feedback node NET corresponds to the level of the data signal currently transmitted by the data transmission circuit. In other words, the level of the feedback node NET reflects the level of the data signal currently transmitted, and the level of the feedback node NET is determined by the level of the data signal currently transmitted. When the current bit of the data signal (i.e., the voltage of the data signal currently transmitted) is to be corrected, the current bit of the data signal is corrected by using the level of the feedback signal FB based on the data signal sample of the previous bit or the previous n bits to correct the level of the feedback node NET, and then to correct the level of the current bit of the data signal. It can be understood that the current bit of the data signal is the data signal currently transmitted, and the level of the feedback node NET is mainly controlled by the level of the data signal currently transmitted, and the level of the feedback node NET is fine-tuned based on the feedback signal FB.

[0051] Compared with the rising edge and the falling edge of the feedback signal FB received by the input end of the inverter Inv, the rising edge time and the falling edge time of the signal output by the feedback signal FB after passing through the inverter Inv can be reduced, that is, the signal can reach the maximum voltage level or the minimum voltage level in a shorter time, so that the switch tube 111 can be turned on faster, and correspondingly, the time required for the switch tube 111 to reach the maximum on state is shortened, thereby shortening the response time of the current accumulator 101, so that the current accumulator 101 can correct the level of the feedback node NET based on the feedback signal FB faster. It can be understood that if the feedback signal FB received by the input end of the inverter Inv has a rising edge, the feedback signal FB output by the output end of the inverter Inv has a corresponding falling edge; if the feedback signal FB received by the input end of the inverter Inv has a falling edge, the feedback signal FB output by the output end of the inverter Inv has a corresponding rising edge.

[0052] In some examples, the current accumulator 101 can be applied to a data transmission circuit that can implement FFE (Feed-Forward Equalization). Specifically, the current accumulator 101 can be connected to the output stage of the transmitting end (or transmitter) of the data transmission circuit, and the current accumulator 101 can increase or decrease the current of the node (i.e., the feedback node NET) corresponding to the output stage to change the signal level of the feedback node NET, thereby completing the pre-distortion of the signal of the transmitting end. Because the response time of the current accumulator 101 is shortened, the rate of increasing or decreasing the current of the node corresponding to the output stage is increased, that is, the correction of the level of the signal of the transmitting end is completed. In other words, the rate of the data transmission circuit for feed-forward equalization can be improved.

[0053] In some examples, the current accumulator 101 can be applied to a data transmission circuit which can implement DFE. Specifically, the current accumulator can be connected to the accumulation stage (i.e. feedback node NET) of the receiving end (or receiver) of the data transmission circuit, and by increasing or decreasing the current sent to the receiving end by the accumulation stage, the signal level of the feedback node NET can be changed, so as to cancel the intersymbol interference input to the receiving end. Since the response time of the current accumulator 101 is shortened, the rate of increasing or decreasing the current sent to the receiving end by the accumulation stage, i.e. the rate of improving the intersymbol interference, is also improved. In other words, the rate of decision feedback equalization of the data transmission circuit can be improved.

[0054] Figure 3 A waveform diagram of the feedback signal received by the control end of the switch tube in the embodiment of the present disclosure and the feedback signal received by the control end of the switch tube in the related art.

[0055] Reference Figure 3 The solid line 1 is a waveform diagram of the feedback signal received by the control end of the switch tube 111 in the embodiment of the present disclosure, and the dashed line 2 is a waveform diagram of the feedback signal received by the control end of the switch tube in the related art, i.e. the scheme in which the control end of the switch tube is not connected to the inverter. For example, in the case of turning on the control end of the switch tube 111 by receiving a high-level signal, the position corresponding to the arrow of the solid line 1 is the time when the switch tube 111 is in the maximum on state, and the position corresponding to the arrow of the dashed line 2 is the time when the switch tube is in the maximum on state.

[0056] It can be found that, compared with the related art, in the embodiment of the present disclosure, if the feedback signal is a high-level signal, the feedback signal reaches the maximum level faster, and if the feedback signal is a low-level signal, the feedback signal reaches the minimum level faster.

[0057] In the related art, the time required for the feedback signal to reach the maximum level is defined as t1, i.e. the rising edge time of the feedback signal in the related art is t1; in the embodiment of the present disclosure, the time required for the feedback signal to reach the maximum level is t2, i.e. the rising edge time of the feedback signal is t2, and the delay caused by the inverter itself is t3. Then, compared with the related art, the response time of the current accumulator as a whole is reduced by△t in the embodiment of the present disclosure, and△t is as follows:

[0058] △t = t1-t2-t3 (1)

[0059] Figure 4 A circuit structure diagram of the current accumulator. Reference Figure 4The switch tube 111 can be a first NMOS tube MN1, and the gate of the first NMOS tube MN1 is the control terminal of the switch tube 111. The inverter Inv can include a first PMOS tube MP1 and a second NMOS tube MN2, the source of the first PMOS tube MP1 is connected to the working voltage VDD, the drain of the first PMOS tube MP1 is connected to the drain of the second NMOS tube MN2 and serves as the output terminal of the inverter Inv, the source of the second NMOS tube MN2 is connected to the ground terminal, and the gate of the first PMOS tube MP1 is connected to the gate of the second NMOS tube MN2 and serves as the input terminal of the inverter Inv.

[0060] In order to minimize the area of the circuit occupied by the inverter Inv, the first PMOS tube MP1 and the second NMOS tube MN2 can be as small as possible. In addition, for a small size inverter, the RC delay of the inverter itself is relatively small, which is beneficial to reduce the influence of the RC delay of the inverter itself on the rate of adjusting the level of the feedback node NET.

[0061] In some examples, the size of the first NMOS tube MN1 can be the same as the size of the second NMOS tube MN2, and the size of the first NMOS tube MN1 can be the same as the size of the first PMOS tube MP1.

[0062] It can be understood that the feedback signal can be a differential signal, including a first feedback signal and a first differential feedback signal which are differential to each other.

[0063] With reference to Figure 3 and Figure 4 The same current accumulator 101 can be connected to one feedback node NET. The number of inverters Inv connected to the control terminal of the switch tube 111 can be an odd number, for example, 1, 3 or 5, and so on. The odd number of inverters Inv are connected in sequence, and the output terminal of the last inverter Inv is connected to the control terminal of the switch tube 111. On the one hand, in order to minimize the circuit area occupied by the inverter Inv, on the other hand, in order to reduce the delay caused by the inverter Inv itself, one inverter Inv can be connected to the control terminal of the switch tube 111. Figure 4 In the example where the number of inverters Inv is 1, it can be understood that in other examples, the number of inverters connected to the control terminal of the same switch tube can also be 3, 5 or more.

[0064] With reference to Figure 3 and Figure 4As the control end of the switch tube 111 is connected with an odd number of inverters Inv, in order to ensure that the feedback signal FB participates in adjusting the level of the feedback node NET, the correspondence between the first feedback signal and the first differential feedback signal in the feedback signal FB and the feedback node NET can be reasonably selected. For example, if the control end of the switch tube in the related art is not connected with an inverter, and the control end of the switch tube receives the first feedback signal, that is, the feedback node corresponds to the first feedback signal; then in the embodiment of the present disclosure, the control end of the switch tube 111 receives the first differential feedback signal, so that the feedback node NET corresponds to the first differential feedback signal. If the control end of the switch tube 111 in the related art is not connected with an inverter, and the control end of the switch tube 111 receives the first differential feedback signal, that is, the feedback node NET corresponds to the first differential feedback signal; then in the embodiment of the present disclosure, the control end of the switch tube 111 receives the first feedback signal, so that the feedback node NET corresponds to the first feedback signal.

[0065] In this way, although the control end of the switch tube 111 is connected with an inverter Inv, the correct feedback signal FB can still participate in adjusting the level of the feedback node NET. For example, taking the first feedback signal as 1 and the first differential feedback signal as 0 as an example: if the current accumulator 101 should receive “0” to adjust the level of the feedback node NET, the first feedback signal is sent to the input end of the inverter of the current accumulator 101; if the current accumulator 101 should receive “1” to adjust the level of the feedback node NET, the first differential feedback signal is sent to the input end of the inverter of the current accumulator 101.

[0066] It should be noted that, unless otherwise specified, in the embodiments of the present disclosure, a signal of 1 means that the signal is a high-level signal, and a signal of 0 means that the signal is a low-level signal.

[0067] Figure 5 Another circuit structure diagram of the current accumulator.

[0068] Reference Figure 5 The same current accumulator 101 can be connected with one feedback node. The number of inverters Inv connected to the control end of the switch tube 111 can be even, for example, can be 2, 4 or 6, and the even number of inverters Inv are connected in turn, and the output end of the last inverter Inv is connected to the control end of the switch tube 111. Similarly, on the one hand, in order to minimize the circuit area occupied by the inverter Inv, on the other hand, in order to reduce the delay caused by the inverter Inv itself, 2 inverters Inv can be connected to the control end of the switch tube 111. It can be understood that in other examples, the number of inverters Inv connected to the control end of the same switch tube 111 can also be 4, 6 or more.

[0069] It can be understood that, for the scheme that the control end of the switch tube 111 is connected with an even number of inverters Inv, better tr / tf characteristics can be achieved while the circuit logic used in the original circuit scheme (i.e., the control end of the switch tube is not connected with an inverter) is not changed. tr refers to the falling edge time, and tf refers to the rising edge time. The shorter the time of each of the rising edge time and the falling edge time, the better the tr / tf characteristics.

[0070] With reference to the foregoing Figure 5 , since the control end of the switch tube 111 is connected with an even number of inverters Inv, in order to ensure that the feedback signal FB participates in adjusting the logic level of the feedback node NET, the correspondence between the first feedback signal and the first differential feedback signal in the feedback signal FB and the feedback node NET can be reasonably selected. For example, if the control end of the switch tube in the related art is not connected with an inverter, and the control end of the switch tube receives the first feedback signal, that is, the feedback node corresponds to the first feedback signal; then, in the embodiment of the present disclosure, the control end of the switch tube 111 also receives the first feedback signal, so that the feedback node NET corresponds to the first feedback signal. If the control end of the switch tube in the related art is not connected with an inverter, and the control end of the switch tube receives the first differential feedback signal, that is, the feedback node corresponds to the first differential feedback signal; then, in the embodiment of the present disclosure, the control end of the switch tube 111 receives the first differential feedback signal, so that the feedback node NET corresponds to the first differential feedback signal.

[0071] Figure 6 Another circuit structure diagram of the current accumulator.

[0072] With reference to the foregoing Figure 6 , the feedback signal FB (with reference to Figure 2 ) includes a first feedback signal FB_P and a first differential feedback signal FB_N that are differentially connected with each other, the number of feedback nodes NET (with reference to Figure 2 ) of the same current accumulator 101 is two, and the feedback nodes NET include a first feedback node NET1 and a second feedback node NET2, that is, the two feedback nodes NET are the first feedback node NET1 and the second feedback node NET2. Correspondingly, the number of switch tubes 111 and the number of inverters Inv of the same current accumulator 101 are both two. One of the switch tubes 111 is connected between the first feedback node NET1 and the ground end, and the other switch tube 111 is connected between the second feedback node NET2 and the ground end GND, and the inverters Inv correspond to the switch tubes 111.

[0073] With reference to the foregoing Figure 6The current accumulator 101 can further include a gating circuit 121. The gating circuit 121 is configured to receive the first feedback signal FB P and the first differential feedback signal FB N, and select one of the first feedback signal FB P or the first differential feedback signal FB N to be transmitted to the input end of one inverter Inv and select the other of the first feedback signal FB P or the first differential feedback signal FB N to be transmitted to the input end of the other inverter Inv in response to a control signal T.

[0074] The inverter Inv and the switch tube 111 can be one-to-one corresponding, that is, the control end of one switch tube 111 is connected to one inverter Inv, and the input end of the inverter Inv receives one of the first feedback signal FB P or the first differential feedback signal FB N. As known from the foregoing analysis, the control end of one switch tube 111 can also be connected to an odd number of inverters Inv greater than or equal to 3, and the odd number of inverters Inv are connected in sequence.

[0075] The gating circuit 121 selects the signal in the data signal for adjusting the level of the first feedback node NET1 and the signal in the data signal for adjusting the level of the second feedback node NET2.

[0076] Continuing to refer to Figure 6 Since the control end of the switch tube 111 is connected to the inverter Inv, in order to ensure that the feedback signal participates in the logic of adjusting the level of the feedback node, the corresponding relationship between the first feedback signal FB P and the first differential feedback signal FB N and the feedback node can be reasonably selected. For example, if the control end of the switch tube in the related art is not connected to the inverter, and the level of the first feedback node is controlled by the first feedback signal, and the level of the second feedback node is controlled by the first differential feedback signal, that is, the first feedback node corresponds to the first feedback signal, and the second feedback node corresponds to the first differential feedback signal; then in the embodiment of the present disclosure, the level of the first feedback node NET1 is controlled by the first differential feedback signal FB N, and the level of the second feedback node NET2 is controlled by the first feedback signal FB P, the gating circuit 121 selects the first differential feedback signal to be transmitted to the input end of the inverter Inv corresponding to the switch tube 111 connected to the first feedback node NET1, and selects the first feedback signal FB P to be transmitted to the input end of the inverter Inv corresponding to the switch tube 111 connected to the second feedback node NET2.

[0077] Figure 7 Another circuit structure diagram of the current accumulator.

[0078] Figure 7 The corresponding current accumulator and Figure 6 The corresponding current accumulator is substantially the same, and the main difference is that Figure 7The number of inverters Inv connected to the control end of the same switch tube 111 is even, and the even number of inverters Inv are connected in sequence.

[0079] Figure 8 A circuit structure diagram of a gating circuit in a current accumulator.

[0080] Reference Figure 8 The gating circuit 121 includes a first selector 1221 and a second selector 1222. The output end of the first selector is connected to the input end of the inverter Inv corresponding to a switch tube 111, and the first selector 1221 receives the first feedback signal FB_P and the first differential feedback signal FB_N, and outputs one of the first feedback signal FB_P or the first differential feedback signal FB_N in response to the control signal. The output end of the second selector 1222 is connected to the input end of the inverter Inv corresponding to another switch tube 111, and the second selector 1222 receives the first feedback signal FB_P and the first differential feedback signal FB_N, and outputs the other one of the first feedback signal FB_P or the first differential feedback signal FB_N in response to the control signal.

[0081] The gating logic of the first selector 1221 and the second selector 1222 can refer to the above-mentioned corresponding relationship between the first feedback signal FB_P and the first differential feedback signal FB_N participating in adjusting the level of the first feedback node NET1 and the second feedback node NET2.

[0082] Continuing to refer to Figure 8 The control signal includes first and second control signals T1T and T1B that are inversely related to each other; the first selector 1221 includes a first transmission gate TG1 and a second transmission gate TG2.

[0083] The first transmission gate TG1 has a first positive control end and a first negative control end, receives the first feedback signal FB_P at the input end, and is connected to the input end of the corresponding inverter Inv at the output end. The first positive control end receives the first control signal T1T, and the first negative control end receives the second control signal T1B.

[0084] The second transmission gate TG2 has a second positive control end and a second negative control end, receives the first differential feedback signal FB_N at the input end, and is connected to the input end of the corresponding inverter Inv at the output end. The second positive control end receives the second control signal T1B, and the second negative control end receives the first control signal T1T.

[0085] The output end of the first transmission gate TG1 and the output end of the second transmission gate TG2 are connected to the input end of the same inverter Inv.

[0086] The second selector 1222 includes a third transmission gate TG3 and a fourth transmission gate TG4.

[0087] The third transmission gate TG3 has a third positive control end and a third negative control end, the input end receives the first feedback signal FB_P, the output end is connected to the input end of the corresponding inverter Inv, the third positive control end receives the second control signal T1B, and the third negative control end receives the first control signal T1T.

[0088] The fourth transmission gate TG4 has a fourth positive control end and a fourth negative control end, the input end receives the first differential feedback signal FB_N, the output end is connected to the input end of the corresponding inverter Inv, the fourth positive control end receives the first control signal T1T, and the fourth negative control end receives the second control signal T1B.

[0089] The output end of the third transmission gate TG3 and the output end of the fourth transmission gate TG4 are connected to the input end of the same inverter Inv.

[0090] For any of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4, the positive control end and the negative control end are provided, if the control signal received by the positive control end is a high level signal and the control signal received by the negative control end is a low level signal, the input end and the output end of the transmission gate are conducted, that is, the transmission gate is turned on, if the control signal received by the positive control end is a low level signal and the control signal received by the negative control end is a high level signal, the input end and the output end of the transmission gate are cut off, that is, the transmission gate is cut off.

[0091] In some examples, the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 can all be CMOS transmission gates TG. Figure 9 A circuit structure diagram of a CMOS transmission gate is shown in FIG. 2. Figure 9 The CMOS transmission gate TG can include a PMOS tube MP and an NMOS tube MN. The gate of the PMOS tube MP is the negative control end, the gate of the NMOS tube is the positive control end, the source of the PMOS tube MP and the source of the NMOS tube MN are connected and serve as the input end INPUT_1 of the transmission gate, and the drain of the PMOS tube MP and the drain of the NMOS tube MN are connected and serve as the output end OUTPUT_1 of the transmission gate TG.

[0092] It should be noted that, Figure 8 and Figure 9 are only specific circuit structures for implementing the first selector and the second selector, and the specific circuit structure of the gating circuit is not limited in the embodiments of the present disclosure. Other circuits that can realize the function of selecting the first feedback signal or the first differential signal to be transmitted to the corresponding inverter are also applicable to the embodiments of the present disclosure.

[0093] Figure 10 Another block diagram of the current accumulator.

[0094] refer to Figure 10 The current accumulator 101 may further include a load 131 connected between the switch 111 and the ground terminal GND. Since the load 131 is located between the switch 111 and the ground terminal GND, when the switch 111 is turned on, the load 131 can act as a voltage divider to prevent excessive current between the feedback node NET and the ground terminal GND, thereby preventing the voltage level of the feedback node NET from changing too quickly.

[0095] In some examples, the equivalent resistance of the load 131 may be a fixed value.

[0096] In some examples, the load 131 can also be configured to adjust the equivalent resistance of the load 131 in response to the tap adjustment signal CODE. Since the equivalent resistance of the load 131 is adjustable, the voltage division capability of the load 131 is adjustable. When the switch 111 is turned on, the current accumulator 101's ability to adjust the voltage level of the feedback node NET is also correspondingly adjustable.

[0097] The tap adjustment signal CODE may be provided by a mode register.

[0098] Figure 11 A circuit diagram of a load.

[0099] refer to Figure 11 The tap adjustment signal CODE may include multiple sub-signals. The load 131 may include multiple third NMOS transistors MN3 connected in parallel between the switch 111 and the ground terminal GND. The gate of each third NMOS transistor MN3 receives a corresponding sub-signal, and the third NMOS transistor MN3 is turned on or off under the control of the sub-signal. Different sub-signals may be identified as code_1, code_2, ..., code_m.

[0100] The load 131 may include 2, 3, 4 or any number of third NMOS transistors MN3 connected in parallel, and the channel width-to-length ratios of different third NMOS transistors MN3 may be the same or the channel width-to-length ratios of at least two third NMOS transistors MN3 may be different.

[0101] In some examples, the switch transistor 111 is the first NMOS transistor MN1 , and the drain of each third NMOS transistor MN3 is connected to the source of the first NMOS transistor MN1 .

[0102] By controlling the number of the turned-on third NMOS transistors MN3 , the equivalent resistance of the load 131 can be adjusted.

[0103] It should be noted that in other embodiments, the current accumulator can also not be provided with the load, and the switch tube can be connected between the ground terminal.

[0104] Figure 12 A schematic diagram of another circuit structure of the current accumulator.

[0105] Reference Figure 12 In the same current accumulator 101, different switch tubes 111 can be connected to the ground terminal GND via the same load 131. Compared with the scheme in which each switch tube 111 is connected with a load 131, the shared load 131 can reduce power consumption and parasitic resistance, and can also save the circuit area of the current accumulator 101.

[0106] The embodiments of the present disclosure also provide a data transmission circuit, which includes the current accumulator provided by any of the above embodiments. The data transmission circuit provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the description of the above embodiments can be applied to the embodiments of the data transmission circuit. In order to avoid redundancy, the same or corresponding parts of the foregoing embodiments can refer to the detailed description of the foregoing embodiments, which will not be repeated hereinafter.

[0107] Figure 13 And Figure 14 Two block diagrams of the data transmission circuit provided by the embodiments of the present disclosure.

[0108] Reference Figure 13 The data transmission circuit can be a circuit that can realize the FFE function. Specifically, the data transmission circuit includes a transmitter (TX) 201, a transmission channel 202, a receiver (RX) 203, and the current accumulator 204 provided by any of the above embodiments. The transmitter 201 has a first input end and a first output end, and outputs a data signal via the first output end in response to a clock signal (not shown). The transmission channel 202 is connected to the first output end and is configured to transmit the data signal output by the transmitter 201. The receiver 203 has a second input end and a second output end. The receiver 203 is configured to receive the data signal from the transmission channel 202 at the second input end, and output the data signal via the second output end in response to the clock signal. The feedback node of the current accumulator 204 is the first output end.

[0109] Reference Figure 14The data transmission circuit can be a circuit capable of implementing the DFE function. Specifically, the data transmission circuit includes a transmitter (TX) 201, a transmission channel 202, a receiver (RX) 203, and the current accumulator 204 provided in any of the above embodiments. The transmitter 201 has a first input end and a first output end, and outputs a data signal via the first output end in response to a clock signal (not shown). The transmission channel 202 is connected to the first output end and is configured to transmit the data signal output by the transmitter 201. The receiver 203 has a second input end and a second output end. The receiver 203 is configured to receive the data signal from the transmission channel 202 at the second input end, and output a data signal via the second output end in response to the clock signal. The feedback node of the current accumulator 204 is the second input end.

[0110] It should be noted that the transmitter 201 receives a data signal, and the current accumulator 204 receives a feedback signal based on sampling of a previously transmitted n-bit data signal.

[0111] It can be understood that when n is 1, i.e., a previously transmitted 1-bit data signal participates in adjusting the level of the feedback node, and accordingly, the number of current accumulators 204 is 1. When n is 2, i.e., two previously transmitted 1-bit data signals jointly participate in adjusting the level of the feedback node, and accordingly, the number of current accumulators 204 is 2, one current accumulator 204 receives a first previously transmitted 1-bit data signal, and the other current accumulator 204 receives a second previously transmitted 1-bit data signal. By analogy, when n is 3, 4, or other values, the corresponding relationship between the current accumulators 204 and the previously transmitted data signals can be known, which will not be described herein.

[0112] Figure 15 and Figure 16 are two other block diagrams of the data transmission circuit.

[0113] Figure 15 and Figure 13 The corresponding solutions are basically the same, and the main difference is that Figure 15 in which the number of the transmission channel 202 and the feedback node is two, and the transmitter 201 transmits signals in the form of a differential signal pair.

[0114] Figure 16 and Figure 14 The corresponding solutions are basically the same, and the main difference is that Figure 16 in which the number of the transmission channel 202 and the feedback node is two, and the transmitter 201 transmits signals in the form of a differential signal pair.

[0115] The data transmission circuit provided by the above embodiments has improved response rate of the current accumulator, so that the rate of adjusting the level of the feedback node by the previously transmitted data signal is improved, thereby improving the accuracy of data signal transmission.

[0116] The data transmission circuit provided by the above embodiments has improved response rate of the current accumulator, so that the rate of adjusting the level of the feedback node by the previously transmitted data signal is improved, thereby improving the accuracy of data signal transmission.

[0117] Figure 17 An architecture diagram of the data transmission circuit provided by the above embodiments.

[0118] Reference Figure 17 The data transmission circuit includes M data paths 300, each of which receives a data signal IN and a sampling clock CLK, and the phases of the sampling clocks CLK received by each of the data paths 300 are different from each other, the i-th data path is any one of the M data paths 300, 1≤i≤M, and M≥2; wherein the i-th data path 300 includes:

[0119] The amplification circuit 301 is configured to amplify the voltage difference between the data signal IN and the reference voltage VERF and output a differential signal pair.

[0120] The sampling circuit 302 is configured to receive the corresponding sampling clock CLK, sample the differential signal pair and output; wherein the signal participating in DFE output by the sampling circuit 302 is called feedback signal FB.

[0121] At least one current accumulator 303, the output end of the amplification circuit 301 is the feedback node (not marked), and the input end of the inverter of each current accumulator 303 receives the feedback signal FB output by the sampling circuit 302 of the corresponding data path 300.

[0122] Among the M data paths 300, the first data path to the Mth data path can be numbered in natural number in ascending order, and the phase difference between the sampling clocks CLK received by any two consecutive data paths 300 in the first data path to the Mth data path can be the same.

[0123] The data transmission circuit described above is a circuit capable of implementing the DFE function. The number of current accumulators 303 in each data path 300 is the same as the number of bit positions participating in the DFE feedback signal FB. If 1-bit data signals participating in the DFE are transmitted previously, the number of current accumulators in each data path 300 is 1; if 2-bit data signals participating in the DFE are transmitted previously, the number of current accumulators in each data path 300 is 2.

[0124] For example, the level of the feedback node participating in the i-th data path of the previously transmitted 4-bit data signal is 4. According to the number of bits of the data participating in the DFE in the previously transmitted data signal, the current accumulators 303 of the i-th data path can be divided into 1-tap, 2-tap, 3-tap and 4-tap current accumulators. Tap means tap, which can be understood as that each data path can include 4 current accumulators 303, each current accumulator 303 corresponds to a tap signal, and a tap signal corresponds to a bit of data. The level of the feedback node is adjusted according to the tap signal. Among them, 1-tap means that 1-bit data participating in the DFE is transmitted previously; 2-tap means that 2-bit data participating in the DFE is transmitted previously; 3-tap means that 3-bit data participating in the DFE is transmitted previously; 4-tap means that 4-bit data participating in the DFE is transmitted previously. It can be understood that the number of taps can be any number greater than or equal to.

[0125] The amplification circuit 301 is used to compare and amplify the voltage difference between the received data signal IN and the reference voltage VREF to obtain a differential signal pair, which includes a first signal output via a first feedback node and a first differential signal output via a second feedback node. The sampling circuit 302 is used to further amplify the voltage difference between the first signal and the first differential signal in the differential signal pair to sample the differential signal and output a sampling signal.

[0126] In some examples, M can be 4, and each data path can include 4 current accumulators. The sampling clock received by each of the 4 data paths can be CLK_0, CLK_90, CLK_180 and CLK_270, respectively, and the phase of the sampling clock can be 0°, 90°, 180° and 270°, respectively.

[0127] Figure 18 The circuit structure of the current accumulator in a data path.

[0128] Reference Figure 18 For example, the level of the feedback node participating in the i-th data path of the previously transmitted 4-bit data signal is 4. According to the number of bits of the data participating in the DFE in the previously transmitted data signal, the current accumulators 303 of the i-th data path can be divided into 1-tap, 2-tap, 3-tap and 4-tap current accumulators. Tap means tap, which can be understood as that each data path can include 4 current accumulators 303, each current accumulator 303 corresponds to a tap signal, and a tap signal corresponds to a bit of data. The level of the feedback node is adjusted according to the tap signal. Among them, 1-tap means that 1-bit data participating in the DFE is transmitted previously; 2-tap means that 2-bit data participating in the DFE is transmitted previously; 3-tap means that 3-bit data participating in the DFE is transmitted previously; 4-tap means that 4-bit data participating in the DFE is transmitted previously. It can be understood that the number of taps can be any number greater than or equal to. Figure 18 ​

[0129] With reference to Figure 18 The feedback nodes include a first feedback node NET1 and a second feedback node NET2. Each data path includes n current accumulators 303 corresponding to 1-bit data signals transmitted previously, where the n current accumulators 303 are respectively identified as Tap 1, Tap 2, …, Tap n-1 and Tap n, where Tap n represents that the feedback signal received by the corresponding current accumulator 303 is based on sampling of the nth-bit data signal transmitted previously. The first feedback signal and the first differential feedback signal received by the current accumulator 303 identified as Tap n are respectively identified as FBn_P and FBn_N, and the feedback signal received by the current accumulator 303 corresponding to Tap 1 is FB1_P and FB1_N, and the feedback signal received by the current accumulator 303 identified as Tap 2 is FB2_P and FB2_N. The control signal received by the current accumulator 303 identified as Tap n includes TnT and TnB, and the control signal received by the current accumulator 303 corresponding to Tap 1 is T1T and T1B, and the control signal received by the current accumulator 303 identified as Tap 2 is T2T and T2B.

[0130] In the above data transmission circuit, the previous-bit data signal participating in the feedback equalization adjustment can be in a direct feedback manner, that is, the n-bit data transmitted previously is directly fed back to the feedback node for operation, so as to offset the influence of the inter-symbol interference on the next-bit data (or current-bit data).

[0131] Since the response rate of the current accumulator is improved, the delay of each tap is shortened, and accordingly, the equalization effect of the DFE is better, that is, the effect of eliminating the inter-symbol interference is better. In this way, even if the feedback signal experiences a long feedback path to return to the feedback node, the delay caused by the long feedback path is long and accordingly has a large load, but since the inverter in the current accumulator can shorten the rising edge or the falling edge of the data signal reaching the control end of the switch tube, the feedback rate / response rate of the feedback signal participating in the DFE is improved, which makes the negative influence caused by the long feedback path or the large load can be weakened or even offset, so as to improve the effect of eliminating the inter-symbol interference.

[0132] Correspondingly, the embodiment of the present disclosure also provides a semiconductor device including the data transmission circuit provided by any of the above embodiments. It can be understood that the description of the current accumulator and the description of the data transmission circuit in the foregoing embodiments are also applicable to the embodiment of the semiconductor device, and to avoid redundancy, the following will not be described in detail.

[0133] The semiconductor device can be a DRAM or an SRAM. The DRAM can be an SDRAM, and the SDRAM can be a DDR SDRAM, such as a DDR4, a DDR5, a DDR6, a LPDDR4, a LPDDR5, or a LPDDR6. In some embodiments, the semiconductor device can be a memory chip, and the memory chip can be a DRAM chip or an SRAM chip. In addition, the input data can be DQ input data.

[0134] It is to be understood that the above-described embodiments are merely illustrative of examples of implementing the present disclosure and that various modifications can be introduced without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art, without departing from the spirit and scope of the embodiments of the present disclosure, can make various modifications and changes, and therefore the scope of protection of the embodiments of the present disclosure should be limited by the scope defined by the claims.

Claims

1. A current accumulator, applied to a data transmission circuit, the data transmission circuit being configured to output a feedback signal, the feedback signal being obtained based on sampling a previously transmitted data signal, the current accumulator comprising: a switch tube, the switch tube being connected between a feedback node and a ground terminal, wherein a level of the feedback node is controlled by a data signal currently transmitted by the data transmission circuit; an inverter, wherein an input end receives the feedback signal and an output end is connected to a control end of the switch tube, wherein the switch tube is turned on or off in response to the electrical level of the control end, so as to connect or disconnect the feedback node and the ground end, thereby adjusting the electrical level of the feedback node; The feedback signal includes a first feedback signal and a first differential feedback signal that are differential with each other; the feedback node includes a first feedback node and a second feedback node; there are two switching tubes, one of which is connected between the first feedback node and the ground terminal, and the other is connected between the second feedback node and the ground terminal, and the inverter corresponds to the switching tube; The current accumulator further includes: The gating circuit is configured to receive the first feedback signal and the first differential feedback signal, and in response to a control signal, select one of the first feedback signal or the first differential feedback signal to be transmitted to the input terminal of one of the inverters, and select the other of the first feedback signal or the first differential feedback signal to be transmitted to the input terminal of the other inverter.

2. The current accumulator according to claim 1, characterized in that The switch tube is a first NMOS tube; the inverter includes: A first PMOS transistor and a second NMOS transistor, wherein the source of the first PMOS transistor is connected to a working power supply, the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor and serves as the output end of the inverter, the source of the second NMOS transistor is connected to the ground end, and the gate of the first PMOS transistor is connected to the gate of the second NMOS transistor and serves as the input end of the inverter.

3. The current accumulator according to claim 1, characterized in that The gating circuit comprises: a first selector, wherein an output terminal of the first selector is connected to an input terminal of the inverter corresponding to one of the switching tubes, the first selector receives the first feedback signal and the first differential feedback signal, and outputs one of the first feedback signal or the first differential feedback signal in response to the control signal; a second selector, wherein the output end of the second selector is connected to the input end of the inverter corresponding to the other switching tube, the second selector receives the first feedback signal and the first differential feedback signal, and outputs the other of the first feedback signal or the first differential feedback signal in response to the control signal.

4. The current accumulator according to claim 3, characterized in that: The control signal includes a first control signal and a second control signal that are inverted to each other; the first selector includes: a first transmission gate having a first positive control terminal and a first negative control terminal, an input terminal receiving the first feedback signal, an output terminal connected to the input terminal of the corresponding inverter, the first positive control terminal receiving the first control signal, and the first negative control terminal receiving the second control signal; a second transmission gate having a second positive control terminal and a second negative control terminal, an input terminal receiving the first differential feedback signal, an output terminal connected to the input terminal of the corresponding inverter, the second positive control terminal receiving the second control signal, and the second negative control terminal receiving the first control signal, wherein the output terminal of the first transmission gate and the output terminal of the second transmission gate are connected to the input terminal of the same inverter; The second selector includes: a third transmission gate having a third positive control terminal and a third negative control terminal, an input terminal receiving the first feedback signal, an output terminal connected to the input terminal of the corresponding inverter, the third positive control terminal receiving the second control signal, and the third negative control terminal receiving the first control signal; a fourth transmission gate having a fourth positive control terminal and a fourth negative control terminal, an input terminal receiving the first differential feedback signal, and an output terminal connected to the input terminal of the corresponding inverter, the fourth positive control terminal receiving the first control signal, and the fourth negative control terminal receiving the second control signal, wherein the output terminal of the third transmission gate and the output terminal of the fourth transmission gate are connected to the input terminal of the same inverter.

5. The current accumulator according to claim 4, characterized in that: The first transmission gate, the second transmission gate, the third transmission gate, and the fourth transmission gate are all CMOS transmission gates.

6. The current accumulator according to claim 1, characterized in that: The current accumulator further includes: A load is connected between the switch tube and the ground terminal.

7. The current accumulator according to claim 6, characterized in that: The load is configured to respond to a tap adjustment signal so that an equivalent resistance of the load is adjustable.

8. The current accumulator according to claim 7, characterized in that: The tap adjustment signal includes a plurality of sub-signals; the load includes: a plurality of third NMOS transistors connected in parallel between the switch transistor and the ground terminal; The gate of each of the third NMOS transistors receives a corresponding sub-signal, and the third NMOS transistor is turned on or off under the control of the sub-signal.

9. The current accumulator according to any one of claims 1 to 8, characterized in that: It comprises an odd number of inverters connected in sequence, and the output end of the inverter at the last stage is connected to the control end of the switch tube.

10. The current accumulator according to any one of claims 1 to 8, characterized in that: It comprises an even number of inverters connected in sequence, and the output end of the inverter at the last stage is connected to the control end of the switch tube.

11. A data transmission circuit, characterized in that: include: a transmitter having a first input terminal and a first output terminal, configured to output the data signal via the first output terminal in response to a clock signal; a transmission channel connected to the first output end and configured to transmit the data signal output by the transmitter; a receiver having a second input terminal and a second output terminal, configured to receive the data signal transmitted from the transmission channel at the second input terminal and output the data signal via the second output terminal in response to the clock signal; According to the current accumulator according to any one of claims 1 to 10, the feedback node is the first output terminal or the second input terminal.

12. A data transmission circuit, characterized in that: include: M data paths, each data path receives a data signal and a sampling clock, and outputs target data and a feedback signal, and the sampling clocks received by each data path have different phases, the i-th data path is any one of the M data paths, 1≤i≤M, M≥2; wherein the i-th data path includes: an amplifier circuit configured to amplify a voltage difference between a voltage of the data signal and a reference voltage and output a differential signal pair; a sampling circuit configured to receive the corresponding sampling clock, sample the differential signal pair, and output the sampled signal; At least one current accumulator according to any one of claims 1 to 10, wherein the output end of the amplifier circuit serves as the feedback node, and the input end of the inverter of each current accumulator receives the feedback signal output by the sampling circuit of a corresponding data path.

13. The data transmission circuit according to claim 12, wherein: The M is 4, and each of the data paths includes 4 current accumulators.

14. A semiconductor device, characterized in that: The method comprises the data transmission circuit according to claim 11, or comprises the data transmission circuit according to claim 12 or 13.

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