Cache resource configuration device, memory access control device and chip

Abstract

The invention relates to a Cache resource configuration device, a memory access control device and a chip, and the device comprises an access monitoring module which is used for receiving an access request transmitted by a peripheral, obtaining a device ID and virtual address data according to the access request, carrying out the statistics of the access flow of a cache partition corresponding to the device ID in a current period according to the virtual address data, and sending the access flow to a memory access control module; sending the virtual address data to a full association Cache, and sending the access traffic to a capacity adjustment module; wherein the full associative Cache comprises a plurality of cache partitions, each cache partition corresponds to a device ID, and each peripheral is endowed with a unique device ID; and the partition capacity adjusting module is used for dynamically adjusting the distribution capacity of the cache partitions periodically according to the access traffic of the current period. According to the method and the device, the effective utilization rate of full-associative Cache resources can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit development, and in particular to a cache resource configuration device, a memory access control device and a chip. Background Art

[0002] In a system that supports the Input / Output Memory Management Unit (IOMMU) or the System Memory Management Unit (SMMU), the IOMMU or SMMU provides address services to each peripheral (external device). When the peripheral accesses memory, it provides a virtual address. After the virtual address is translated into a physical address by the IOMMU or SMMU, the memory is accessed. In this process, the IOMMU or SMMU performs address translation.

[0003] In order to improve the efficiency of peripheral memory access, a commonly used processing technology is to set up an address translation cache unit (Translation Local Buffer, TLB) inside the IOMMU or SMMU. After the IOMMU or SMMU performs an address translation, the information related to this address translation will be cached in the TLB. The next time the address translation of the same page is performed, if the relevant entry in the TLB is hit, the physical address can be obtained directly and the address translation process can be skipped, reducing the memory access delay introduced by the peripheral due to address translation.

[0004] In order to improve the hit rate, TLB is generally set to a fully associative structure. When in use, all peripherals connected to the IOMMU or SMMU can use the TLB, and the density of each peripheral sending to the transmission stream is different and not balanced. There is uncertainty in time and space. If a less important peripheral suddenly performs a large DMA operation in a certain period of time, it is possible that the entire TLB cache will be occupied by the peripheral, which will affect the address translation performance of other peripherals that need it later. Summary of the invention

[0005] The purpose of this application is to provide a cache resource configuration device, a memory access control device and a chip to improve the effective utilization rate of fully associative cache resources.

[0006] To achieve the above-mentioned purpose, according to a first aspect of the present application, a Cache resource configuration device is provided, comprising:

[0007] A receiving module, used for receiving an access request transmitted by a peripheral device, obtaining a device ID and virtual address data according to the access request, obtaining a DEVID according to the device ID, and sending the DEVID and virtual address data to an access monitoring module;

[0008] An access monitoring module, configured to receive the DEVID and virtual address data, count the access traffic of the cache partition corresponding to the DEVID in the current cycle according to the virtual address data, send the virtual address data to the fully associative Cache, and send the access traffic to the capacity adjustment module; wherein the fully associative Cache includes a plurality of cache partitions;

[0009] The partition capacity adjustment module is used to periodically and dynamically adjust the allocated capacity of the multiple cache partitions according to the access traffic of the multiple cache partitions in the current cycle.

[0010] According to a second aspect of the present application, a memory access control device is provided, comprising an address translation unit, a fully associative cache, and a cache resource configuration device according to the first aspect of the present application;

[0011] The address translation unit is used to receive the access request transmitted by the peripheral device and forward the access request to the Cache resource configuration device;

[0012] The fully associative Cache includes a Cache controller and a Cache memory;

[0013] The cache controller is used to determine the physical address data corresponding to the virtual address data in the fully associative cache according to the virtual address data, and if yes, take out the hit physical address data from the cacheline of the corresponding group and send it to the memory controller to access the memory, and if no, return a miss result to the address translation unit;

[0014] The address translation unit is further used to obtain virtual address data according to the access request based on the miss result, translate the virtual address data into physical address data, send the currently translated physical address data to the memory controller to access the memory, and send the currently translated physical address data to the cache controller;

[0015] The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it.

[0016] According to the third aspect of the present application, a chip is provided, comprising the cache resource configuration device according to the first aspect of the present application, or comprising the memory access control device according to the second aspect of the present application.

[0017] Implementing the above-mentioned cache resource configuration device, memory access control device and chip has the following beneficial effects:

[0018] The access monitoring module counts the access traffic of each peripheral to each cache partition of the fully associative cache, and periodically adjusts the allocated capacity of the cache partition corresponding to each peripheral according to the access traffic of each cache partition in the current cycle, thereby realizing dynamic adjustment of the fully associative cache resources according to the actual access needs of multiple peripherals, so that the fully associative cache resources can be more reasonably allocated to each peripheral, and can adapt to the situation where multiple peripherals share one IOMMU or SMMU, solving the problem that the entire TLB cache is occupied by a less important peripheral due to a sudden large-scale DMA operation, affecting the subsequent address translation performance of other peripherals. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 A schematic diagram of the framework structure of a Cache resource configuration device in an embodiment of the present application.

[0021] Figure 2 This is a flowchart of the first step of adjusting the cache partition allocation capacity in one embodiment of the present application.

[0022] Figure 3 This is a flowchart of the second step of adjusting the cache partition allocation capacity in one embodiment of the present application.

[0023] Figure 4 A schematic diagram of the framework structure of a memory access control device in one embodiment of the present application.

[0024] Figure 5 A schematic diagram of the circuit structure of a memory access control device in one embodiment of the present application.

[0025] Figure 6 A schematic diagram of the structure of a cache memory in one embodiment of the present application. DETAILED DESCRIPTION

[0026] The detailed description of the drawings is intended as an illustration of some embodiments of the present application, and is not intended to represent the only form in which the present application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included in the spirit and scope of the present application.

[0027] See also Figure 1 , an embodiment of the present application provides a Cache resource configuration device, including an access monitoring module and a partition capacity adjustment module;

[0028] The access monitoring module is used to receive an access request transmitted by a peripheral device, obtain a device ID and virtual address data according to the access request, count the access traffic of the cache partition corresponding to the device ID in the current cycle according to the virtual address data, send the virtual address data to the fully associative cache, and send the access traffic to the capacity adjustment module; wherein the fully associative cache includes multiple cache partitions, each cache partition corresponds to a device ID, and each peripheral device is assigned a unique device ID.

[0029] Specifically, the number of cache partitions in the fully associative cache is 2 n , correspondingly, the number of device IDs is also 2 n The access monitoring module is used to monitor the virtual address data of each peripheral sent by the receiving module and perform periodic access traffic statistics. It includes multiple counters, each device ID of each peripheral corresponds to a counter, and each counter is used to count the access traffic of the cache partition corresponding to the corresponding device ID in the current cycle, and then the statistical results (access traffic) of each counter are sent to the partition capacity adjustment module.

[0030] The partition capacity adjustment module is used to periodically and dynamically adjust the allocated capacity of the multiple cache partitions according to the access traffic of multiple peripheral devices in the current cycle.

[0031] Specifically, the cache resource configuration device may also include a timer, and when the count of the timer is greater than the time threshold ADJUST_TIME_TH configured by software, it triggers dynamic adjustment of the allocated capacity of the multiple cache partitions according to the statistical results of each counter. The allocated capacity of the cache partition refers to the number of cachelines allocated to the cache partition, and a cacheline is a storage unit of the cache.

[0032] For example, if the access traffic of a cache partition is very high, it indicates that the peripherals associated with it need more cache resources to improve access efficiency. Therefore, the partition capacity adjustment module may increase the number of cachelines of the cache partition. On the contrary, if the access traffic of a cache partition is very low, it indicates that the currently allocated cache resources may be too many. The number of cachelines of the cache partition can be reduced to allocate the excess resources to other partitions that need them more. This dynamic adjustment can be implemented based on various strategies, including but not limited to most frequently used first (MRU), least recently used (LRU) or other custom algorithms.

[0033] In some specific embodiments, the partition capacity adjustment module is further used to:

[0034] Acquire access traffic rates of the multiple cache partitions in the current cycle according to the access traffic of the multiple cache partitions in the current cycle;

[0035] If the access flow rate of any cache partition in the current cycle is greater than its access flow rate in the previous cycle, the flow rate increment ΔV of any cache partition is obtained. If ΔV>ΔV max , then any cache partition needs to be increased in capacity and its capacity increment is determined; if ΔV<ΔV min , then any cache partition needs to be reduced in capacity, and its capacity reduction is determined; where ΔV max and ΔV min is the preset threshold;

[0036] If the access traffic rate of any cache partition in the current cycle is less than the access traffic rate in the previous cycle, the capacity of any cache partition needs to be reduced, and the capacity reduction is determined;

[0037] The allocated capacities of the plurality of cache partitions are adjusted according to the capacity increment and the capacity decrement.

[0038] Specifically, when the dynamic adjustment of the allocated capacity of the multiple cache partitions is triggered according to the statistical results of each counter, the partition capacity adjustment module calculates the real-time rate corresponding to each device ID. The rate calculation method is: divide the real-time access traffic value of the cache partition corresponding to the device ID in the current cycle by the time threshold ADJUST_TIME_TH to obtain the real-time access traffic rate corresponding to the device ID; ADJUST_TIME_TH can be understood as the adjustment cycle time.

[0039] Furthermore, based on the calculated real-time access traffic rate, for the i-th device ID, V n Indicates the access traffic rate of the cache partition corresponding to the device ID calculated in real time in the current cycle, denoted by Vf Indicates the access traffic rate of the cache partition corresponding to the device ID calculated in the previous cycle, ΔV i V represents the ID of the ith device n -V f Value, using ΔV max Indicates the threshold of the difference in access traffic rate before and after the capacity needs to be increased, ΔV min Indicates the threshold of the difference in access traffic rate before and after the capacity needs to be reduced, which is:

[0040] When V f <V n Calculate ΔV i =V n -V f ; When ΔV i >ΔV max When , it means that the allocated capacity of the cache partition corresponding to the i-th device ID should be increased;

[0041] When ΔV min <=ΔV<=ΔV max , it means that the allocated capacity of the cache partition corresponding to the i-th device ID does not need to be adjusted;

[0042] When V f >V n Or (V f <V n )&&(ΔV i <ΔV min ), it means that the allocated capacity of the cache partition corresponding to the i-th device ID should be reduced.

[0043] It should be noted that the increment and decrement of the allocated capacity can be customized, for example, increasing or decreasing the capacity by a fixed value each time, or obtaining the increment or decrement based on multiplying the current allocated capacity by a preset coefficient. The above is only an example and this embodiment is not limited to this.

[0044] In some specific embodiments, the partition capacity adjustment module is further used to:

[0045] Obtain the allocated capacity of the cache partition corresponding to the preset device ID, determine the allocatable capacity according to the sum of the allocated capacity of the cache partition corresponding to the preset device ID and the capacity reduction of the cache partition to be reduced, and determine the sum of the capacity increment according to the capacity increment of the cache partition to be increased;

[0046] When the allocatable capacity is greater than or equal to the sum of the capacity increments, the allocated capacity of the corresponding cache partition is increased according to the capacity increment of the cache partition to be increased, and the allocated capacity of the corresponding cache partition is decreased according to the capacity reduction of the cache partition to be reduced, and the allocated capacity of the cache partition corresponding to the preset device ID is updated;

[0047] When the allocatable capacity is less than the sum of the capacity increments, the allocated capacity of the corresponding cache partition is reduced according to the capacity reduction of the cache partition that needs to be reduced, the allocated capacity of the cache partition that needs to be increased remains unchanged, and the allocated capacity of the cache partition corresponding to the preset device ID is updated.

[0048] Specifically, in this embodiment, a preset device ID is set, and the preset device ID is represented by DEV_LAST_ID. DEV_LAST_ID corresponds to a cache partition, but DEV_LAST_ID has no corresponding peripheral. The cache partition corresponding to DEV_LAST_ID is reserved for assisting in dynamically regulating the allocated capacity of the cache partitions corresponding to other device IDs. In other words, the cacheline of the cache partition corresponding to DEV_LAST_ID can be used to increase the capacity of other cache partitions.

[0049] Specifically, at the beginning of each adjustment cycle, the partition capacity adjustment module first determines the allocated capacity of the cache partition corresponding to the current DEV_LAST_ID, that is, the number of cachelines contained in the cache partition corresponding to the DEV_LAST_ID. For the convenience of description, it is defined as DEV_LAST_ID_t; further, the partition capacity adjustment module obtains the allocatable capacity by adding DEV_LAST_ID_t to the sum of the capacity reductions of all cache partitions that need to be reduced. The cache partitions that need to be reduced refer to those with low access traffic and the number of cachelines that need to be reduced in allocated capacity. At the same time, the partition capacity adjustment module calculates the sum of the capacity increments of all cache partitions that need to be increased in capacity. The cache partitions that need to be increased in capacity refer to those with high access traffic and the number of cachelines that need to be increased in allocated capacity.

[0050] The partition capacity adjustment module compares the allocatable capacity with the sum of the capacity increments of the cache partitions to be increased. There are two possible situations:

[0051] Case 1: The allocatable capacity is greater than or equal to the sum of the capacity increments. If the allocatable capacity is sufficient, the capacity adjustment can be performed normally. The partition capacity adjustment module will increase the allocated capacity according to the capacity increment of each cache partition that needs to be increased. At the same time, the partition capacity adjustment module will also reduce the allocated capacity according to the capacity reduction of each cache partition that needs to be reduced. After these adjustments, the partition capacity adjustment module will update DEV_LAST_ID_t to reflect the new allocation situation.

[0052] Case 2: The allocatable capacity is less than the sum of the capacity increments. If the allocatable capacity is insufficient to meet the needs of all cache partitions that need to be increased, the partition capacity adjustment module will not increase the allocated capacity of any cache partition that needs to be increased, but the partition capacity adjustment module will still reduce the allocated capacity of the cache partition that needs to be reduced according to the capacity reduction of the cache partition that needs to be reduced, thereby releasing some capacity. After these adjustments, the partition capacity adjustment module will also update DEV_LAST_ID_t.

[0053] In this way, the partition capacity adjustment module can ensure that the allocation of cache resources is balanced, and during the operation of the entire system, cache resources can be dynamically adjusted according to actual needs. This mechanism helps to maximize the utilization efficiency of the cache while avoiding resource waste.

[0054] In some specific embodiments, the capacity increase and capacity decrease of any cache partition in each cycle are both ΔP; wherein ΔP is a preset integer value, representing the number of cachelines increased or decreased, and the allocated capacity of the cache partition represents the number of cachelines contained in the cache partition.

[0055] Specifically, in order to facilitate fast calculation, two parameters ADD_NUM and DEC_NUM are defined in this embodiment. ADD_NUM*ΔP means that after adjustment, the number of cachelines can be increased in the cache that has not been allocated in the next time period; DEC_NUM*ΔP means that after adjustment, the number of cachelines in the cache that has not been allocated in the next time period will be reduced; in each adjustment, the initial values ​​of ADD_NUM and DEC_NUM are 0; based on the above parameter definitions, the functions of the partition capacity adjustment module are described in detail below. When performing capacity adjustment, it can be performed in two beats (one beat is one clock cycle).

[0056] The first step is to preliminarily determine whether the cache partition corresponding to each device ID is increased, unchanged, or reduced. The determination process of increasing, unchanged, or reducing the cache partition corresponding to each device ID can be found in Figure 2 ,include:

[0057] Step 1.1, determine V n and V f If V f >V n， This means that the allocated capacity of the cache partition corresponding to the i-th device ID needs to be reduced by ΔP. At the same time, ADD_NUM is increased by 1, and DEV_NUM_MAX_N_t = DEV_NUM_MAX_N-ΔP. Otherwise, proceed to step 1.2.

[0058] Step 1.2, get the ΔV corresponding to each device ID i =V n -V f and determine the value of ΔV i Is it less than ΔV? min If yes, the allocated capacity of the cache partition corresponding to the device ID is reduced by ΔP, and ADD_NUM is increased by 1, DEV_NUM_MAX_N_t = DEV_NUM_MAX_N-ΔP; otherwise, proceed to step 1.3;

[0059] step1.3 When ΔV min <=ΔV i <=ΔV max When , the allocated capacity of the cache partition corresponding to the device ID remains unchanged, and ADD_NUM remains unchanged;

[0060] When ΔV i >ΔV max When , it indicates that the allocated capacity of the cache partition corresponding to the device ID increases by ΔP, and DEC_NUM is increased by 1, DEV_NUM_MAX_N_t = DEV_NUM_MAX_N + ΔP;

[0061] Among them, DEV_NUM_MAX_N represents the current allocated capacity of the cache partition with device ID N, and DEV_NUM_MAX_N_t represents the allocated capacity of the cache partition with device ID N after adjustment.

[0062] The second step is to further determine whether the cache partition corresponding to each device ID is increased, unchanged, or decreased. The determination process can be found in Figure 3 ,include:

[0063] Step 2.1, determine whether DEV_LAST_ID_t+ADD_NUM is greater than DEC_NUM;

[0064] Step 2.2: When DEV_LAST_ID_t + ADD_NUM >= DEC_NUM, it indicates that there are sufficient unallocated cachelines for the DEVs that need to be added. When configuring software parameters using registers, the value of DEV_NUM_MAX_N_t can be updated to the corresponding register at this time.

[0065] In DEV_NUM_MAX_N, at the same time, the allocated capacity of the cache partition corresponding to DEV_LAST_ID is updated to DEV_LAST_ID_t + ADD_NUM - DEC_NUM, and this round of adjustment ends.

[0066] Step 2.3: When DEV_LAST_ID_t + ADD_NUM < DEC_NUM, it indicates that there are not enough remaining cachelines for the cache partitions that need to be added. At this time,

[0067] the value of DEV_NUM_MAX_N_t < DEV_NUM_MAX_N is updated to the corresponding register DEV_NUM_MAX_N, that is, the reduction adjustment of the cache partition is normally executed. At the same time, the value of the allocated capacity of the cache partition corresponding to DEV_LAST_ID is updated to

[0068] DEV_LAST_ID_t + ADD_NUM; the number of cachelines corresponding to the cache partitions that need to be increased in capacity remains unchanged, and this round of adjustment ends.

[0069] Based on the description of the above embodiments, the Cache resource configuration device of this embodiment counts the access traffic of each peripheral to each cache partition of the fully associative cache through the access monitoring module, and periodically adjusts the allocated capacity of the cache partitions corresponding to each peripheral according to the access traffic of each cache partition in the current period, realizing the dynamic adjustment of the fully associative cache resources according to the actual access requirements of multiple peripherals, enabling the fully associative cache resources to be more reasonably allocated to each peripheral, being able to adapt to the situation where multiple peripherals share one IOMMU or SMMU, and solving the problem that the entire cache of the TLB is occupied by a less important peripheral due to a large DMA operation of the peripheral, affecting the address translation performance of the subsequent remaining peripherals.

[0070] Refer to Figure 4 , another embodiment of the present application further provides a memory access control device, including an address translation unit, a fully associative cache, and the Cache resource configuration device according to the foregoing embodiment;

[0071] The fully associative Cache includes a Cache controller and a Cache memory; the fully associative Cache is the adjustment object targeted by the Cache resource configuration device of the above embodiment, which includes multiple cache partitions, each cache partition includes multiple cache lines, and each cache partition corresponds to a device ID.

[0072] The cache controller is used to determine the physical address data corresponding to the virtual address data in the fully associative cache based on the virtual address data. If yes, the hit physical address data is taken out from the cacheline of the corresponding group and sent to the memory controller to access the memory. If no, a miss result is output to the address translation unit. Specifically, when the cache controller receives the virtual address data, the cache controller checks whether the physical address data corresponding to the virtual address data exists in the corresponding cache partition of the cache memory. This process is called a cache hit check. If the physical address data corresponding to the virtual address data is found in the corresponding cache partition (i.e., a cache hit), the cache controller will take out the hit physical address data from the cacheline of the cache partition. Then, the cache controller sends this physical address data to the memory controller, and the memory controller uses this physical address data to access the data in the memory. If the physical address data corresponding to the virtual address data is not found in the corresponding cache partition (i.e., a cache miss), the cache controller will return a miss result to the address translation unit. This miss result tells the address translation unit that the physical address data corresponding to the requested virtual address data is not stored in the cache, so the access request needs to be further processed, that is, translated into physical address data, which is the address translation function performed by, for example, IOMMU or SMMU in the background technology.

[0073] The address translation unit is used to obtain virtual address data according to the miss result and the access request, translate the virtual address data into physical address data, send the currently translated physical address data to the memory controller to access the memory, and send the currently translated physical address data to the cache controller.

[0074] Specifically, when the cache controller notifies the address translation unit of a cache miss, the address translation unit will take action to handle the missed access request. The address translation unit obtains the virtual address data, which is the address that the peripheral originally requested to access. The address translation unit translates this virtual address data into physical address data. Address translation is an important function of memory management. It converts the virtual address (the address used by the peripheral) into a physical address (the address in the actual memory). The address translation unit sends the translated physical address data to the memory controller, which is the component responsible for actually accessing the physical memory hardware. It uses this physical address to read or write data in the memory. At the same time, the address translation unit also sends the translated physical address data to the cache controller. This is to allow the cache controller to store this address in the cache memory after the memory access is completed, so that the same virtual address request in the future can directly find the corresponding physical address in the cache memory, thereby improving access efficiency.

[0075] The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it.

[0076] Specifically, when the address translation unit completes the translation from the virtual address to the physical address and sends the physical address data to the cache controller, the cache controller needs to decide whether to store (or fill) this physical address data in a cacheline in the fully associative cache. If it is decided to store, this cacheline will record the current translated physical address data so that when the peripheral accesses the same virtual address again in the future, the cache can provide fast access. In some cases, the cache controller may decide not to store this physical address data, for example, due to limited cache space, and the current cache policy (such as least recently used (LRU) or random replacement) indicates that the existing data should be replaced; for example, the access pattern of the data indicates that it is unlikely to be accessed again, so storing it in the cache may not bring performance benefits; for example, in order to maintain cache consistency, it may be necessary to discard certain data according to specific cache policies or system requirements.

[0077] It should be noted that the memory access control device described in this embodiment can be regarded as a device similar to an input / output address translation unit (IOMMU) or a system address translation unit (SMMU). Both IOMMU and SMMU are hardware components for performing address translation and access control between a device (such as a peripheral) and a system memory. However, the memory access control device of this embodiment has the following improvements compared to a traditional IOMMU or SMMU:

[0078] (1) The memory access control device in this embodiment includes a cache resource configuration device, which allows the allocation of fully associative cache resources to be adjusted dynamically. This means that the resource allocation of the fully associative cache can be optimized based on the actual usage of the peripherals, rather than statically configured. This dynamism can improve the cache utilization and overall system performance.

[0079] (2) By dynamically adjusting cache resources, the cache hit rate can be optimized according to the actual access traffic of the peripherals, reducing cache misses, thereby reducing the number of memory accesses and latency. Dynamic cache resource configuration allows the system to better adapt to different workloads and access patterns, and also facilitates expansion in the future when more peripherals or more complex access patterns need to be supported.

[0080] The above improvements make the memory access control device more efficient and flexible in processing memory access requests of peripherals, especially in scenarios with multiple peripherals and high concurrent access, which can significantly improve the performance and scalability of the system.

[0081] In some specific embodiments, see Figure 5 , the memory access control device also includes a scheduling control module;

[0082] The cache controller is further used to obtain the device ID corresponding to the access request and the device ID corresponding to each cacheline in the corresponding cache partition, further obtain the priority corresponding to the device ID corresponding to the access request and the priority corresponding to the device ID corresponding to each cacheline, and output them to the scheduling control module; wherein the device ID corresponding to the cacheline is the device ID corresponding to the storage data of the cacheline.

[0083] Specifically, the cache controller obtains the device ID corresponding to the access request (i.e., the device ID corresponding to the peripheral id) and the device ID corresponding to each cacheline in the corresponding cache partition (i.e., the device ID corresponding to the storage data of the cacheline). Next, the cache controller further obtains the priority corresponding to the device ID corresponding to the access request and the priority corresponding to the device ID corresponding to each cacheline. These priority information are used to determine which data should be stored in the cache and which data should be replaced when the cache memory space is insufficient. After obtaining the above information, the cache controller outputs this information to the scheduling control module, and the scheduling control module decides whether to store the physical address data in the cache memory based on this information.

[0084] The scheduling control module is used to determine whether to store the currently translated physical address data in a cacheline of the corresponding group according to the priority corresponding to the device ID corresponding to the access request and the priority corresponding to the device ID corresponding to each cacheline, and return the determination result to the cache controller;

[0085] Specifically, the scheduling control module decides whether to store the physical address data in the cache according to the priority of the device ID corresponding to the access request and the priority of the device ID corresponding to each cacheline. This decision is made based on the cache storage strategy, such as but not limited to the least frequently used (LFU), most frequently used (LFU) or partition priority strategy, etc., according to the determination result of the scheduling control module.

[0086] The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it according to the determination result.

[0087] Specifically, the cache controller decides whether to store the currently translated physical address data in a cacheline of the corresponding group or discard the data.

[0088] In summary, in this embodiment, when the cache controller decides to store new data in the cache memory, it determines how to handle the acquisition of free cachelines and priority information, and how to cooperate with the scheduling control module to determine the data storage strategy. This strategy can optimize the utilization efficiency of the fully associative cache and reduce the latency of memory access.

[0089] In some specific embodiments, the scheduling control module is further used to determine whether there is at least one free cacheline in the corresponding cache partition. If so, the currently translated physical address data is stored in any free cacheline; if not, when the priority corresponding to the device ID corresponding to the access request is lower than the priority corresponding to the device ID corresponding to any cacheline in the corresponding cache partition, it is determined to discard the currently translated physical address data.

[0090] Specifically, the scheduling control module first checks whether there is at least one free cacheline (i.e., a cacheline that is not occupied) in the corresponding cache partition. If there is a free cacheline, it means that this cacheline currently does not store any valid data and can be used to store new physical address data. The scheduling control module will determine to store the currently translated physical address data in the free cacheline. In this way, when the same virtual address request is requested again, the cache can quickly provide the physical address data and reduce the number of memory accesses. If there is no free cacheline, then further, when the scheduling control module receives the device ID and its priority corresponding to the access request provided by the cache controller, as well as the device ID and its priority corresponding to each cacheline in the corresponding group, it will compare these priorities. If the priority of the device ID corresponding to the access request is lower than the priority of the device ID corresponding to any cacheline in the corresponding group, this means that the priority of the physical address data of the access request is low and is not the data that is most needed to be retained in the cache at present. In this case, the scheduling control module will decide to discard the currently translated physical address data, which means that this data will not be stored in the cache. This decision can avoid storing low-priority data in the cache, so that the data in the cache is the most needed high-priority data at the moment, which ensures that cache resources are used most effectively while reducing cache misses caused by storing low-priority data. With this strategy, the system can process access requests more efficiently because the data in the cache is the data most likely to be accessed, which helps improve the overall performance and response speed of the system.

[0091] In some specific embodiments, the scheduling control module is further used to select at least one cacheline with the lowest priority from the at least one cacheline when the priority corresponding to the device ID corresponding to the access request is higher than or equal to the priority corresponding to the device ID corresponding to at least one cacheline in the corresponding cache partition, and select a cacheline with the least number of uses within a recent preset time from the at least one cacheline with the lowest priority to store the currently translated physical address data.

[0092] Specifically, when the scheduling control module receives the device ID and its priority corresponding to the access request provided by the cache controller, as well as the device ID and its priority corresponding to each cacheline in the corresponding group, it will compare these priorities. If the priority of the device ID corresponding to the access request is higher than or equal to the priority of the device ID corresponding to at least one cacheline in the corresponding group, this means that the data priority of the access request is higher and needs to be retained in the cache first. In this case, the scheduling control module will select the cacheline with the lowest priority from the at least one cacheline. The cacheline with the lowest priority means that the data stored in it is not the data that is most needed to be retained in the cache. At this time, there may be one or at least two cachelines with the lowest priority. If there is only one Cacheline with the lowest priority, this Cacheline with the lowest priority is determined to be used to store the currently translated physical address data. If there are at least two Cachelines with the lowest priority, the scheduling control module will select the Cacheline with the least number of uses in the recent preset time from the at least two Cachelines with the lowest priority, that is, determine the Cacheline to be replaced based on the least used (LRU) strategy. Finally, the scheduling control module returns the information of the selected Cacheline to the Cache controller to tell the Cache controller to store the currently translated physical address data in this Cacheline with the least number of uses. In the above manner, it can be ensured that the data in the Cache is the data that is most likely to be accessed, while following the cache replacement strategy to maintain the efficiency and performance of the Cache.

[0093] In some specific embodiments, the cache memory further includes a priority data module and an LRU module, wherein the priority data module is used to store priority information corresponding to each device ID, and the LRU module is used to store the number of times each cacheline has been used within a recent preset time.

[0094] Specifically, if Figure 6 A fully associative cache is shown, where each cacheline includes a tag, data, and a device ID. The tag is used to store all the information that can uniquely identify each peripheral transmission stream (i.e. Figure 6 Each cacheline corresponds to a tag, and Data is used to store valid data in the data stream, that is, the translated physical address data (that is, Figure 6 Data 0 to Data n in the cache), the device ID is used to save the device ID corresponding to the cache data of each cacheline (i.e. Figure 6 The LRU module is used to record the number of times each cacheline has been used recently M. When a cacheline needs to be replaced, the cacheline with the least number of times M will be replaced first according to the records in the LRU. The priority data module is used to store the priority information corresponding to each device ID. The priority data module can be formed by a RAM, and the depth of the RAM is the maximum number of supported device IDs. The cache controller can read the priority information of the corresponding device ID from the priority data module and the cacheline usage count record from the LRU module, and then send them to the scheduling control module for cacheline replacement storage decision.

[0095] In some specific embodiments, the scheduling control module is further used to determine the priority corresponding to each device ID according to the allocated capacity and the actually used capacity of the storage partition corresponding to each device ID, and the unallocated capacity.

[0096] Specifically, in this embodiment, a parameter DEV_NUM_N is further set, where DEV_NUM_N represents the number of cachelines actually occupied by the cache partition with device ID N; the scheduling control module counts the value of DEV_NUM_N in real time, and sets the priority DEV_PRI_N corresponding to each device ID according to the size relationship between the value in DEV_NUM_MAX_N and DEV_NUM_N. The value of the priority will be cached in the priority data module (DEV PRI RAM) of the corresponding cacheline along with the data when performing cache allocation. The priority setting method is shown in Table 1 below:

[0097] Table 1

[0098]

[0099] In order to configure the parameters of the hardware circuit, the device of this embodiment also includes a status register module (CSR) for storing the status values ​​of various parameters of the hardware circuit, which includes

[0100] DEV_NUM_MAX_(N), ADJUST_TIME_TH, DEV_NUM_(N), DEV_PRI_(N) and other status registers, as shown in Table 2 below:

[0101] Table 2

[0102]

[0103] The timer counts the time and then compares it with the ADJUST_TIME_TH set in the status register module. When it is greater than ADJUST_TIME_TH, a pulse signal is sent to the allocation capacity adjustment module to trigger the adjustment of the capacity allocation of each cache partition, and then the timer starts a new round of counting from 0.

[0104] Based on the priorities defined in Table 2 and the status registers defined in Table 1, the workflow of the cache controller and the scheduling control module of this embodiment is further described, which specifically includes the following steps:

[0105] Step 3.1, when there is an unoccupied cacheline in the corresponding cache partition of the cache, directly allocate the currently translated physical address data to the unoccupied cacheline, and at the same time increase the corresponding DEV_NUM_N value by 1, and the allocation of the currently translated physical address data ends; otherwise, proceed to step 3.2;

[0106] The step 3.2 includes:

[0107] When all cachelines in the cache are occupied, the device ID corresponding to the data stored in each cacheline in the cache is read to obtain the priority DEV_PRI of each cacheline. At the same time, the device ID of the newly received access request (assuming it is N) can also be used to obtain its own DEV_PRI_N from the status register module, and then the following judgment is made:

[0108] (a) When DEV_PRI_N=1, read out the statistical count M of the LRU modules corresponding to all cachelines in the cache with the same device ID as the access request, and replace the currently translated physical address data into the cacheline with the smallest M value according to the LRU algorithm, and all status registers do not need to be changed;

[0109] (b) When DEV_PRI_N=2, check whether there is a cacheline with DEV_PRI_i=1 in the cache. If so, read out the statistical count M of the LRU module corresponding to the cacheline with DEV_PRI_i=1, replace the currently translated physical address data into the cacheline with the smallest M value according to the LRU algorithm, increase the DEV_NUM_N value corresponding to the device ID of the access request by 1, and reduce the DEV_NUM_i value corresponding to the replaced cacheline by 1;

[0110] (c) When DEV_PRI_N=2 and there is no cacheline with DEV_PRI_i=1 in the cache, the statistical count M of the LRU modules corresponding to all cachelines in the cache is read out, and the currently translated physical address data is replaced into the cacheline with the smallest M value according to the LRU algorithm. The DEV_NUM_N value corresponding to the device ID of the access request is increased by 1, and the DEV_NUM_i value corresponding to the replaced cacheline is decreased by 1.

[0111] Another embodiment of the present application further provides a chip, comprising the cache resource configuration device according to the above embodiment.

[0112] Another embodiment of the present application further provides a chip, comprising the memory access control device according to the above embodiment.

[0113] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A Cache resource configuration device, characterized in that: include: An access monitoring module is used to receive an access request transmitted by a peripheral device, obtain a device ID and virtual address data according to the access request, count the access traffic of the cache partition corresponding to the device ID in the current cycle according to the virtual address data, send the virtual address data to the fully associative cache, and send the access traffic to the capacity adjustment module; wherein the fully associative cache includes multiple cache partitions, each cache partition corresponds to a device ID, and each peripheral device is assigned a unique device ID; The partition capacity adjustment module is used to periodically and dynamically adjust the allocated capacity of the multiple cache partitions according to the access traffic of multiple peripherals in the current cycle.

2. The Cache resource configuration device according to claim 1, characterized in that: The partition capacity adjustment module is further used to: Acquire access traffic rates of the multiple cache partitions in the current cycle according to the access traffic of the multiple cache partitions in the current cycle; If the access flow rate of any cache partition in the current cycle is greater than its access flow rate in the previous cycle, the flow rate increment ΔV of any cache partition is obtained. If ΔV>ΔV max , then any cache partition needs to be increased in capacity and its capacity increment is determined; if ΔV<ΔV min , then any cache partition needs to be reduced in capacity, and its capacity reduction is determined; where ΔV max and ΔV min is the preset threshold; If the access traffic rate of any cache partition in the current cycle is less than the access traffic rate in the previous cycle, the capacity of any cache partition needs to be reduced, and the capacity reduction is determined; The allocated capacities of the plurality of cache partitions are adjusted according to the capacity increment and the capacity decrement.

3. The Cache resource configuration device according to claim 2, characterized in that: The partition capacity adjustment module is further used to: Obtain the allocated capacity of the cache partition corresponding to the preset device ID, determine the allocatable capacity according to the sum of the allocated capacity of the cache partition corresponding to the preset device ID and the capacity reduction of the cache partition to be reduced, and determine the sum of the capacity increment according to the capacity increment of the cache partition to be increased; When the allocatable capacity is greater than or equal to the sum of the capacity increments, the allocated capacity of the corresponding cache partition is increased according to the capacity increment of the cache partition to be increased, and the allocated capacity of the corresponding cache partition is decreased according to the capacity reduction of the cache partition to be reduced, and the allocated capacity of the cache partition corresponding to the preset device ID is updated; When the allocatable capacity is less than the sum of the capacity increments, the allocated capacity of the corresponding cache partition is reduced according to the capacity reduction of the cache partition that needs to be reduced, the allocated capacity of the cache partition that needs to be increased remains unchanged, and the allocated capacity of the cache partition corresponding to the preset device ID is updated.

4. The Cache resource configuration device according to claim 3, characterized in that: The capacity increment and capacity decrement of any cache partition in each cycle are both ΔP; wherein ΔP is a preset integer value, indicating the number of cachelines increased or decreased, and the allocated capacity of the cache partition indicates the number of cachelines contained in the cache partition.

5. A memory access control device, characterized in that: It comprises an address translation unit, a fully associative Cache and a Cache resource configuration device according to any one of claims 1 to 4; The fully associative Cache includes a Cache controller and a Cache memory; The cache controller is used to determine the physical address data corresponding to the virtual address data in the fully associative cache according to the virtual address data, and if yes, take out the hit physical address data from the cacheline of the corresponding group and send it to the memory controller to access the memory, and if no, output a miss result to the address translation unit; The address translation unit is used to obtain virtual address data according to the access request based on the miss result, translate the virtual address data into physical address data, send the currently translated physical address data to the memory controller to access the memory, and send the currently translated physical address data to the cache controller; The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it.

6. The memory access control device according to claim 5, characterized in that: The memory access control device also includes a scheduling control module; The cache controller is further used to obtain the device ID corresponding to the access request and the device ID corresponding to each cacheline in the corresponding cache partition, further obtain the priority corresponding to the device ID corresponding to the access request and the priority corresponding to the device ID corresponding to each cacheline, and output them to the scheduling control module; wherein the device ID corresponding to the cacheline is the device ID corresponding to the storage data of the cacheline; The scheduling control module is used to determine whether to store the currently translated physical address data in a cacheline of the corresponding group according to the priority corresponding to the device ID corresponding to the access request and the priority corresponding to the device ID corresponding to each cacheline, and return the determination result to the cache controller; The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it according to the determination result.

7. The memory access control device according to claim 6, characterized in that: The scheduling control module is further used to determine whether there is at least one free cacheline in the corresponding cache partition. If so, the currently translated physical address data is stored in any free cacheline; if not, when the priority corresponding to the device ID corresponding to the access request is lower than the priority corresponding to the device ID corresponding to any cacheline in the corresponding cache partition, it is determined to discard the currently translated physical address data.

8. The memory access control device according to claim 6, characterized in that: The scheduling control module is further used to select at least one cacheline with the lowest priority from the at least one cacheline when the priority corresponding to the device ID corresponding to the access request is higher than or equal to the priority corresponding to the device ID corresponding to at least one cacheline in the corresponding cache partition, and select a cacheline with the least number of uses within a recent preset time from the at least one cacheline with the lowest priority to store the currently translated physical address data.

9. The memory access control device according to claim 8, characterized in that: The cache memory further includes a priority data module and an LRU module. The priority data module is used to store priority information corresponding to each device ID, and the LRU module is used to store the number of times each cacheline is used within a recent preset time.

10. The memory access control device according to any one of claims 6 to 9, characterized in that: The scheduling control module is further used to determine the priority corresponding to each device ID according to the allocated capacity and the actually used capacity of the storage partition corresponding to each device ID, and the unallocated capacity.

11. A chip, comprising the cache resource configuration device according to any one of claims 1 to 4, or comprising the memory access control device according to any one of claims 5 to 10.

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