Complementary field effect transistor, manufacturing method thereof and static random access memory

Abstract

The invention provides a complementary field effect transistor and a manufacturing method thereof, and a static random access memory, and the method comprises the steps: providing a substrate, forming a laminated structure, forming a second type work function layer in a plurality of to-be-filled gaps, filling a protection material to form a protection layer, and etching the protection layer with a first thickness through employing an anisotropic technology, the isotropic process is continuously utilized to etch the protective layer with the second thickness, and the difference value between the second thickness and 1 / 2 of the width of the gap to be filled is smaller than the target threshold value, that is, the anisotropic process is utilized to etch the protective layer with the first thickness, and then the isotropic process is continuously utilized to etch the protective layer with the second thickness; therefore, accurate etching of the protection layer is realized. Therefore, the anisotropic etching is combined with the isotropic etching, so that the accurate etching of the protective layer can be realized, the accurate control of the position of the protective layer is realized, the work function layer is prevented from covering wrong transistors, and the risk of confusion of transistor types is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a complementary field effect transistor and a manufacturing method thereof, and a static random access memory. Background Art

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. The traditional three-gate or double-gate Fin Field-Effect Transistor (FinFET) is limited to nodes below 3 nanometers (nm). Nanosheet-Gate all round Fin Field-Effect Transistor (Nanosheet-GAAFET) has been developed that is not limited by the 3nm node. Furthermore, the Complementary Field-Effect Transistor (CFET) has received widespread attention and research because it has broken through the 1nm node limitation.

[0003] Currently, complementary field effect transistors can be used to form static random access memory (SRAM) memory cells, thereby significantly reducing the area of ​​the static random access memory. Figure 1 FIG. 1 is a schematic diagram of a circuit of a storage unit of a static random access memory, referring to FIG. Figure 2 and Figure 3 The following are the structural layouts corresponding to the memory cells of two types of static random access memory. That is to say, by adjusting the design of the memory cell from planar transistors to complementary field effect transistors, the length of the memory cell is shortened from 240nm to 156nm, which has greatly reduced the area of ​​the memory cell of the static random access memory.

[0004] Current complementary field-effect transistors include different types of transistors stacked up and down. When manufacturing different types of transistors, a protective layer is used to wrap one type of transistor to facilitate the manufacture of another type of high-k dielectric layer or work function layer. However, the position of the protective layer cannot be precisely controlled, resulting in the risk of transistor type confusion. Summary of the invention

[0005] In view of this, the purpose of the present application is to provide a complementary field effect transistor and a manufacturing method thereof, and a static random access memory, which can accurately control the position of the protective layer through the process, thereby reducing the risk of transistor type confusion.

[0006] The present application provides a method for manufacturing a complementary field effect transistor, the method comprising:

[0007] Providing a substrate, forming a plurality of stacked structures consisting of alternately stacked first semiconductor layers and second semiconductor layers on one side of the substrate, wherein the stacked structures include a buffer layer located in a middle region along a direction perpendicular to a plane where the substrate is located;

[0008] Etching the stacked structure and a partially thick substrate to form a fin structure, wherein the fin structure includes a top structure, a bottom structure and a substrate structure, wherein the top structure and the bottom structure are separated by the buffer layer, and an embedded power line is formed between the two substrate structures;

[0009] Etching the top structure, the buffer layer and the bottom structure to form a top source region, a top drain region, a bottom source region and a bottom drain region, wherein the top source region and the top drain region are located between the top channel region and the bottom drain region are located between the bottom source region and the bottom drain region; forming inner sidewalls on the sidewalls of the top structure and the sidewalls of the bottom structure;

[0010] forming a bottom source and a bottom drain in the bottom source region and the bottom drain region;

[0011] Forming a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain, wherein the buried power connection layer is electrically connected to the buried power line;

[0012] forming a top source and a top drain on the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode and the second storage bottom electrode;

[0013] The first semiconductor layer in the top channel region and the bottom channel region is removed to form a plurality of gaps to be filled between the second semiconductor layers, and a second type work function layer is formed in the plurality of gaps to be filled;

[0014] Filling a plurality of the gaps to be filled with a protective material to form a protective layer, etching the protective layer of a first thickness using an anisotropic process, and continuing to etch the protective layer of a second thickness using an isotropic process, along a plane direction perpendicular to a line connecting the bottom source electrode and the bottom drain electrode, a difference between the second thickness and 1 / 2 of a width of the gap to be filled is less than a target threshold;

[0015] Removing the second type work function layer in the gap to be filled that is not covered by the protective layer, and forming the first type work function layer in the gap to be filled that is not covered by the protective layer;

[0016] removing the protective layer;

[0017] Filling gates in the plurality of gaps to be filled, the gates surrounding the second semiconductor layer, and the stacked layers formed by the plurality of second semiconductor layers respectively forming a top channel structure and a bottom channel structure;

[0018] A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode and a second storage top electrode are formed on the top source and the top drain, respectively, and the top ground connection layer is connected to the bottom ground connection layer.

[0019] Optionally, forming an inner side wall on a side wall of the top structure and a side wall of the bottom structure comprises:

[0020] Etching and removing a portion of the first semiconductor layer on the sidewalls of the top structure and the sidewalls of the bottom structure, and etching and removing the buffer layer, to form a concave structure and a buffer isolation structure, respectively;

[0021] An inner sidewall is formed in the concave structure, and an isolation layer is formed in the buffer isolation structure.

[0022] Optionally, etching the protective layer having a first thickness by using an anisotropic process, and continuing to etch the protective layer having a second thickness by using an isotropic process comprises:

[0023] Etching the protective layer to a thickness of 1 / 2 of the width of the gap to be filled by using an anisotropic process;

[0024] The protection layer having a second thickness is continuously etched to a position of 1 / 2 of the isolation layer using an isotropic process.

[0025] Optionally, before forming a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain, the method further comprises:

[0026] forming a target side wall, wherein the target side wall covers the side wall of the inner side wall;

[0027] forming a first dielectric layer, wherein the first dielectric layer covers the top structure and the target sidewall;

[0028] Etching the first dielectric layer on both sides of the top structure to form a first groove, wherein the first groove exposes the bottom source and the bottom drain;

[0029] The forming of a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain comprises:

[0030] forming a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain exposed by the first groove;

[0031] The method further comprises:

[0032] forming a second dielectric layer in the first groove;

[0033] Etching the first dielectric layer and the second dielectric layer to a surface of the isolation layer that is away from the substrate;

[0034] Etching the target sidewall to a surface of the isolation layer that is away from the substrate;

[0035] The forming of a top source and a top drain on the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode and the second storage bottom electrode comprises:

[0036] A top source and a top drain are formed on the first dielectric layer and the second dielectric layer, and the first dielectric layer and the second dielectric layer cover the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode and the second storage bottom electrode.

[0037] Optionally, before forming a top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode and a second storage top electrode on the top source and the top drain respectively, the method further comprises:

[0038] forming a third dielectric layer on the top source and the top drain;

[0039] Etching the third dielectric layer on both sides of the top structure to form a second groove, wherein the second groove exposes the top source and the top drain;

[0040] A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode and a second storage top electrode are respectively formed on the top source and the top drain, comprising:

[0041] A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode are respectively formed on the top source and the top drain exposed by the second groove.

[0042] The present application provides a complementary field effect transistor, the complementary field effect transistor comprising:

[0043] substrate;

[0044] A top source, a top drain, a top channel structure, a bottom source, a bottom drain and a bottom channel structure are arranged on one side of the substrate, wherein in a direction perpendicular to the plane where the substrate is located, the top source overlaps with the bottom source, the top drain overlaps with the bottom drain, and the top channel structure overlaps with the bottom channel structure; the top channel structure is located between the top source and the top drain, the bottom channel structure is located between the bottom source and the bottom drain, and the top channel structure and the bottom channel structure include a stack formed by a plurality of nanosheets;

[0045] a gate, the gate surrounding the nanosheet;

[0046] The nanosheet of the top channel structure is surrounded by a first type work function layer, and the nanosheet of the bottom channel structure is surrounded by a second type work function layer;

[0047] The top ground connection layer contacts the top source, the bottom ground connection layer contacts the bottom source, and the top ground connection layer is connected to the bottom ground connection layer.

[0048] Optionally, an isolation layer is provided between the top channel structure and the bottom channel structure.

[0049] Optionally, a target sidewall is provided on a sidewall of the isolation layer.

[0050] Optionally, along a direction perpendicular to the plane where the substrate is located, 1 / 2 of the side wall of the isolation layer is the junction of the first type work function layer and the second type work function layer.

[0051] The present application provides a static random access memory, comprising a plurality of storage units, wherein the storage units include any one of the complementary field effect transistors described above.

[0052] The present application provides a method for manufacturing a complementary field effect transistor, the method comprising: providing a substrate, forming a plurality of stacked structures consisting of a first semiconductor layer and a second semiconductor layer alternately stacked on one side of the substrate, along a direction perpendicular to the plane where the substrate is located, the stacked structure includes a buffer layer located in a middle area, etching the stacked structure and a partial thickness of the substrate to form a fin structure, the fin structure includes a top structure, a bottom structure and a substrate structure, the top structure and the bottom structure are separated by a buffer layer, and an embedded power line is formed between the two substrate structures. The top structure, the buffer layer and the bottom structure are etched to form a top source region, a top drain region, a bottom source region and a bottom drain region, the top source region and the top drain region are between the top channel region, and the bottom source region and the bottom drain region are between the bottom channel region; inner sidewalls are formed on the sidewalls of the top structure and the sidewalls of the bottom structure, a bottom source and a bottom drain are formed in the bottom source region and the bottom drain region, a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode and a second storage bottom electrode are formed on the bottom source and the bottom drain, the buried power connection layer and the buried power line are electrically connected, and the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode are formed on the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode A top source and a top drain are formed on the bottom electrode and the second storage bottom electrode, the first semiconductor layer in the top channel region and the bottom channel region is removed, a plurality of gaps to be filled are formed between the second semiconductor layers, a second type work function layer is formed in the plurality of gaps to be filled, a protective material is filled in the plurality of gaps to be filled to form a protective layer, the protective layer of a first thickness is etched using an anisotropic process, and the protective layer of a second thickness is continuously etched using an isotropic process, along a plane direction perpendicular to a line connecting the bottom source and the bottom drain, a difference between the second thickness and 1 / 2 of a width of the gap to be filled is less than a target threshold, that is, by first etching the protective layer of a first thickness using an anisotropic process and then etching the protective layer of a second thickness using an isotropic process, precise etching of the protective layer is achieved. The second type of work function layer in the gap to be filled that is not covered by the protective layer is removed, and the first type of work function layer is formed in the gap to be filled that is not covered by the protective layer. The protective layer is removed, and the gate is filled in multiple gaps to be filled. The gate surrounds the second semiconductor layer, and the stack composed of multiple second semiconductor layers respectively forms a top channel structure and a bottom channel structure, and a top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode are formed on the top source and the top drain, respectively, and the top ground connection layer is connected to the bottom ground connection layer. It can be seen that the present application can achieve precise etching of the protective layer by combining anisotropic etching with isotropic etching, and accurately control the position of the protective layer, thereby avoiding the work function layer covering the wrong transistor and reducing the risk of transistor type confusion. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0054] Figure 1 A circuit diagram of a storage unit of a static random access memory is shown;

[0055] Figure 2 A structural layout corresponding to a storage unit of a static random access memory is shown;

[0056] Figure 3 Another structural layout corresponding to a storage unit of a static random access memory is shown;

[0057] Figure 4 A schematic flow chart of a method for manufacturing a complementary field effect transistor provided in an embodiment of the present application is shown;

[0058] Figure 5 The structure layout corresponding to a storage unit of a static random access memory provided by an embodiment of the present application is shown;

[0059] Figure 6 Shows Figure 5 A top-level schematic diagram of the provided structural layout;

[0060] Figure 7 Shows Figure 5 The underlying schematic diagram of the provided structural layout;

[0061] Figure 8 A schematic diagram of a three-dimensional structure of a complementary field effect transistor provided in an embodiment of the present application is shown;

[0062] 9-40 show schematic structural diagrams of complementary field effect transistors manufactured according to the method for manufacturing complementary field effect transistors provided in an embodiment of the present application. DETAILED DESCRIPTION

[0063] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0064] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0065] Secondly, the present application is described in detail with reference to the schematic diagram. When describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0066] refer to Figure 1 , which is a circuit diagram of a storage unit of a static random access memory. The storage unit of SRAM is called a byte (bit), which can only store a signal 0 or 1. Such a bit is composed of 6 transistors, which are divided into 2 P-type metal oxide semiconductor field effect transistors (P Metal-Oxide-Semiconductor Field-Effect Transistor, PMOS) and 4 N-type metal oxide semiconductor field effect transistors (N Metal-Oxide-Semiconductor Field-Effect Transistor, NMOS), among which PMOS is Figure 1 PU1 and PU2 in the NMOS are Figure 1 PD1, PD2, AC1 and AC2, Q and QB represent storage bits, Figure 1 VDD represents the power supply terminal, VSS represents the ground terminal, WL represents the word line, and BL represents the bit line.

[0067] refer to Figure 2 and Figure 3 As shown, the structural layout corresponding to the storage units of two types of static random access memories. Figure 2 The middle one is a planar transistor with only one-tier structure. Figure 3 The two-tier structure is a complementary field effect transistor, with NMOS (Top-tier: NMOS) on the top layer and PMOS (Bottom-tier: PMOS) on the bottom layer. In other words, by adjusting the design of the memory cell from a planar transistor to a complementary field effect transistor, the length of the memory cell has been shortened from 240nm to 156nm, which has greatly reduced the area of ​​the memory cell of the static random access memory.

[0068] The current complementary field effect transistor includes different types of transistors stacked up and down. When manufacturing different types of transistors, a protective layer is used to wrap one type of transistor so as to manufacture another type of high-k dielectric layer or work function layer. Currently, the protective layer is etched to a fixed position using an isotropic etching process, but the position of the protective layer cannot be precisely controlled, resulting in the risk of transistor type confusion.

[0069] Based on this, the present application provides a method for manufacturing a complementary field effect transistor, the method comprising: providing a substrate, forming a plurality of stacked structures consisting of alternating first semiconductor layers and second semiconductor layers on one side of the substrate, along a direction perpendicular to the plane where the substrate is located, the stacked structure includes a buffer layer located in a middle area, the stacked structure and a partial thickness of the substrate are etched to form a fin structure, the fin structure includes a top structure, a bottom structure and a substrate structure, the top structure and the bottom structure are separated by a buffer layer, and an embedded power line is formed between the two substrate structures. The top structure, the buffer layer and the bottom structure are etched to form a top source region, a top drain region, a bottom source region and a bottom drain region, the top source region and the top drain region are between the top channel region, and the bottom source region and the bottom drain region are between the bottom channel region; inner sidewalls are formed on the sidewalls of the top structure and the sidewalls of the bottom structure, a bottom source and a bottom drain are formed in the bottom source region and the bottom drain region, a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode and a second storage bottom electrode are formed on the bottom source and the bottom drain, the buried power connection layer and the buried power line are electrically connected, and the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode are formed on the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode A top source and a top drain are formed on the bottom electrode and the second storage bottom electrode, the first semiconductor layer in the top channel region and the bottom channel region is removed, a plurality of gaps to be filled are formed between the second semiconductor layers, a second type work function layer is formed in the plurality of gaps to be filled, a protective material is filled in the plurality of gaps to be filled to form a protective layer, the protective layer of a first thickness is etched using an anisotropic process, and the protective layer of a second thickness is continuously etched using an isotropic process, along a plane direction perpendicular to a line connecting the bottom source and the bottom drain, a difference between the second thickness and 1 / 2 of a width of the gap to be filled is less than a target threshold, that is, by first etching the protective layer of a first thickness using an anisotropic process and then etching the protective layer of a second thickness using an isotropic process, precise etching of the protective layer is achieved. The second type of work function layer in the gap to be filled that is not covered by the protective layer is removed, and the first type of work function layer is formed in the gap to be filled that is not covered by the protective layer. The protective layer is removed, and the gate is filled in multiple gaps to be filled. The gate surrounds the second semiconductor layer, and the stack composed of multiple second semiconductor layers respectively forms a top channel structure and a bottom channel structure, and a top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode are formed on the top source and the top drain, respectively, and the top ground connection layer is connected to the bottom ground connection layer. It can be seen that the present application can achieve precise etching of the protective layer by combining anisotropic etching with isotropic etching, and accurately control the position of the protective layer, thereby avoiding the work function layer covering the wrong transistor and reducing the risk of transistor type confusion.

[0070] In order to better understand the technical solution and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0071] See also Figure 4 , which is a schematic flow chart of a method for manufacturing a complementary field effect transistor provided in an embodiment of the present application.

[0072] The present application embodiment is according to Figure 5 The structure layout corresponding to the storage unit of the static random access memory shown is used to manufacture complementary field effect transistors, Figure 5 The structure of the storage cell in the example consists of two layers, the top layer is NMOS, and the reference Figure 6 As shown, the bottom layer is PMOS, reference Figure 7 As shown. Figure 7 It can be seen that a buried power line (Buried VDD) can be designed to achieve power connection of complementary field effect transistors.

[0073] Figure 8 Shown is a three-dimensional structural schematic diagram of a complementary field effect transistor provided in an embodiment of the present application. By performing cross-sections on the three-dimensional structural schematic diagram in the XX', YY', Y1-Y1', Y2-Y2' and Y3-Y3' directions, cross-sectional structural schematic diagrams of complementary field effect transistors of A, B, C, D and E are obtained respectively. Fig. 24B , Fig.25C , Fig.27C and Fig.40C is the cross section in the Y2-Y2' direction corresponding to D, Fig.25B , Fig.26B , Fig.27B and Fig.40B is the cross section in the Y1-Y1' direction corresponding to C, Fig.25D , Fig.27D , Fig.39B and Fig.40D It is the cross section in the Y3-Y3' direction corresponding to E.

[0074] The method for manufacturing a complementary field effect transistor provided in the embodiment of the present application comprises the following steps:

[0075] S101, providing a substrate, forming a stacked structure consisting of a first semiconductor layer and a second semiconductor layer alternately stacked on one side of the substrate, wherein the stacked structure includes a buffer layer located in a middle region along a direction perpendicular to a plane where the substrate is located, and referring to Fig.9A and Fig. 9B shown.

[0076] In an embodiment of the present application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, and the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0077] As an example, impurities may be injected into the bulk silicon substrate, and a highly doped well region may be formed after annealing to achieve the desired well depth. For different device types, the doping type of the substrate 110 is different, wherein for a P-type semiconductor device, the highly doped well region is an N-well, and the injected impurities are n-type impurity ions, such as phosphorus (P) ions, wherein for an N-type semiconductor device, the highly doped well region is a p-well, and the injected impurities are p-type impurity ions, such as boron (B) ions.

[0078] In the embodiment of the present application, a stacked structure in which the first semiconductor layer 121 and the second semiconductor layer 122 are alternately stacked may be formed on one side of the substrate 110. Fig.9A and Fig. 9B shown.

[0079] Specifically, for different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 may be the same, for example, the material of the first semiconductor layer 121 may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon or germanium. For different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 may be different, for example, for a P-type semiconductor device, the material of the first semiconductor layer 121 may be silicon, and the material of the second semiconductor layer 122 may be silicon germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon.

[0080] Considering that the stacked structure can be used to form two transistors with different doping types stacked up and down, when the material is silicon, silicon of different doping types can also be used. For example, the material of the second semiconductor layer 122 located at the top is P-type doped silicon, and the material of the second semiconductor layer 122 located at the bottom can be N-type doped silicon.

[0081] Along the direction perpendicular to the plane where the substrate 110 is located, the stacked structure includes a buffer layer 123 located in the middle region, and the buffer layer 123 is used to separate two transistors of different doping types stacked up and down to be formed later. The material of the buffer layer 123 can be the same as that of the first semiconductor layer 121, and both sides of the surface of the buffer layer 123 are the first semiconductor layer 121.

[0082] As a possible implementation, along the direction perpendicular to the plane where the substrate 110 is located, if the material of the first semiconductor layer 121 is silicon germanium, the proportion of Ge in the first semiconductor layer 121 in the stacked structure gradually increases and then decreases, wherein the proportion of Ge in the buffer layer 123 is the highest. As an example, the proportion of Ge increases from 30% to 60% and then decreases to 30%.

[0083] In practical applications, silicon oxide may be formed on the substrate 110 . The stacked structure may be formed after the silicon oxide on the substrate 110 is removed and the substrate 110 is cleaned.

[0084] S102, etching the stacked structure and a partial thickness of the substrate to form a fin structure, the fin structure includes a top structure, a bottom structure and a substrate structure, the top structure and the bottom structure are separated by a buffer layer, and an embedded power line is formed between the two substrate structures, referring to Fig. 10A and FIG. 10B to FIG. 16A and Fig. 16B shown.

[0085] In an embodiment of the present application, the stacked structure and the partially thick substrate 100 may be etched to form two fin structures, the fin structure including a top structure 510, a bottom structure 520 and a substrate structure 530, wherein the top structure 510 and the bottom structure 520 are separated by a buffer layer 123. After the fin structure is formed, an embedded power line 310 may be formed between the substrate structure 530 included in the two fin structures, and an embedded ground line is not formed while the embedded power line 310 is formed. The process flow of forming the fin structure and the embedded power line 310 is specifically introduced below.

[0086] S1021, sidewall transfer process, reference Fig. 10A and Fig. 10B shown.

[0087] In an embodiment of the present application, a self-aligned sidewall transfer process is used to form a first sidewall 201. The material of the first sidewall 201 is silicon nitride. The specific formation process is: a sacrificial layer 202 is covered on the stacked structure. The material of the sacrificial layer 202 can be polycrystalline silicon or amorphous silicon. Photolithography is used to perform patterning and etching of part of the sacrificial layer 202, and silicon nitride material is deposited. Anisotropic etching is then used to etch away the remaining sacrificial layer 202, so that only the first sidewall 201 on the stacked structure is retained. The first sidewall 201 acts as a hard mask in the subsequent photolithography for forming the fin.

[0088] S1022, forming a fin structure, reference Fig.11A and Fig. 11B shown.

[0089] In the embodiment of the present application, the stacked structure and a partial thickness of the substrate can be etched by an etching process to form a plurality of periodically distributed fins, as shown in FIG. Fig.11A and Fig. 11BAs shown. The first sidewall 201 is used as a mask for etching to form a fin with a stacked structure. The top of the fin is a top structure 510 and a bottom structure 520 formed by the stacked structure. The top structure 510 and the bottom structure 520 are separated by a buffer layer 123. The top structure 510 and the bottom structure 520 are channel regions. The bottom of the fin is a substrate 110, forming a fin as shown in FIG. Fig. 11B The fin shown in FIG. The fin includes not only a stacked structure but also a single crystal silicon structure that penetrates into the substrate 110. The etching process can be dry etching or wet etching, and in one embodiment, reactive ion etching can be used. The fin structure will be used to form a nanosheet of a complementary field effect transistor. Although Fig. 11B While two fins are shown, it should be understood that any suitable number and configuration of fins may be used in practical applications.

[0090] In practical applications, after the fin structure is formed, the first sidewall 201 may be removed.

[0091] S1023, forming an embedded power line 310, referring to Fig. 12A and FIG. 12B to FIG. 15A and Fig. 15B shown.

[0092] In the embodiment of the present application, a buried power line 310 may be formed between the substrate structure 530 of the two fin structures. Specifically, a dielectric insulating material may be deposited first, and then a planarization process, such as a CMP process, may be performed to form an insulating layer 410. Fig. 12A and Fig. 12B , the insulating layer 410 between the two fin structures is etched to the depth of the area where the substrate structure 530 is located, forming a recess, referring to Fig.13A and Fig. 13B , a metal material, such as tungsten (W), is filled in the recess formed by etching, and then a planarization process and an etch-back process are performed to form a buried power line 310, referring to Fig.14A and Fig. 14B Finally, the dielectric insulating material is deposited, followed by a planarization process to fill the recesses. Fig.15A and Fig. 15B shown.

[0093] In practical applications, the buried power line 310 may also be a ground line (VSS) or another power voltage plane (VCC).

[0094] S1024, forming shallow trench isolation 203 (STI), reference Fig.16A and Fig. 16B shown.

[0095] In an embodiment of the present application, a shallow trench isolation 203 may be formed between different fins. Specifically, a selective back etching process is performed on the insulating layer 410 formed in S1023 to expose the three-dimensional fins, specifically exposing the top structure 510 and the bottom structure 520, thereby forming a shallow trench isolation 203 adjacent to the fin structure. The surface of the shallow trench isolation 203 on one side away from the substrate 110 may be flush with the surface of the side of the stacked structure in the fin structure close to the substrate 110, or may be higher or lower than the surface. The shallow trench isolation 203 may be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fin structures.

[0096] S103, etching the top structure, the buffer layer and the bottom structure to form a top source region, a top drain region, a bottom source region and a bottom drain region, the top source region and the top drain region are between the top channel region, the bottom source region and the bottom drain region are between the bottom channel region, and inner sidewalls are formed on the sidewalls of the top structure and the sidewalls of the bottom structure, referring to Fig.17A and FIG. 17B to FIG. 20A and Fig. 20B shown.

[0097] In the embodiments of the present application, considering that two transistors of different doping types need to be stacked up and down subsequently, the source and drain of the two transistors need to be formed separately. First, the source and drain regions of the two transistors need to be formed, and then the inner sidewalls need to be formed. The specific process is described in detail below.

[0098] S1031, forming a dummy gate 204 and a second spacer 205, referring to Fig.17A and Fig. 17B shown.

[0099] In an embodiment of the present application, a dummy gate stack is formed on the exposed fin structure and in a direction perpendicular to the fin line, i.e., in the XX direction. The dummy gate stack is a multi-layer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204 and a hard mask layer (not shown). The dummy gate stack can be formed by processes such as thermal oxidation, chemical vapor deposition, and sputtering. The dummy gate stack spans the stacked structure on the upper part of the fin structure, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 204 can be polysilicon or amorphous silicon. The material of the hard mask layer can be oxide, carbide, organic matter, etc.

[0100] In the embodiment of the present application, second spacers 205 can be respectively provided on both sides of the dummy gate stack along the fin line direction, i.e., the YY direction, and the second spacers 205 on both sides have the same thickness. The material of the second spacers 205 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0101] S1032, etching the top structure 510, the buffer layer 123 and the bottom structure 520 to form a top source region 1101, a top drain region 1102, a bottom source region 1201 and a bottom drain region 1202, refer to Fig.18A shown.

[0102] In the embodiment of the present application, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source and drain etching on the stacked structure through an etching process, specifically, the top structure 510, the buffer layer 123 and the bottom structure 520 are etched to form a top source region 1101, a top drain region 1102, a bottom source region 1201 and a bottom drain region 1202, a top channel region 1103 is between the top source region 1101 and the top drain region 1102, and a bottom channel region 1203 is between the bottom source region 1201 and the bottom drain region 1202. Among them, the top source region 1101, the top drain region 1102, the bottom source region 1201 and the bottom drain region 1202 no longer have a stacked structure after being etched, refer to Fig.18A shown.

[0103] S1033, forming a concave structure, reference Fig.19A and Fig.19B shown.

[0104] In an embodiment of the present application, the first semiconductor layer 121 located in the top structure 510 and the bottom structure 520 is selectively etched along the YY direction, that is, part of the first semiconductor layer 121 on the side walls of the top structure 510 and the side walls of the bottom structure 520 is etched away, and the second semiconductor layer 122 is not damaged. Along the YY direction, a concave structure is formed in the missing part of the first semiconductor layer 121 than the second semiconductor layer 122, that is, pull-back etching is performed, and part of the first semiconductor layer 121 is etched away from the bottom source region 1201 and the bottom drain region 1202 to the bottom channel region 1203, and part of the first semiconductor layer 121 is etched away from the top source region 1101 and the top drain region 1102 to the top channel region 1103.

[0105] While the first semiconductor layer 121 in the top structure 510 and the bottom structure 520 is selectively etched, the buffer layer 123 is also etched away to form a buffer isolation structure. Fig.19A shown.

[0106] S1034, forming inner wall 206, reference Fig. 20A and Fig. 20B shown.

[0107] In the embodiment of the present application, after the first semiconductor layer 121 is etched, a dielectric material is deposited on the bottom structure 520 located in the bottom channel region 1203 and the top structure 510 in the top channel region 1103, i.e., the periphery of the fin, and the dielectric material is etched to form an inner sidewall 206, and the inner sidewall 206 is flush with the second semiconductor layer 122 in a direction perpendicular to the plane where the substrate 110 is located. In other words, the concave structure caused by etching S1033 is filled by the inner sidewall 206, and the material of the inner sidewall 206 can be silicon nitride or silicon oxide.

[0108] In addition to filling the concave structure, the dielectric material also fills the buffer isolation structure, thereby forming an isolation layer 200 .

[0109] S104, forming a bottom source and a bottom drain in the bottom source region and the bottom drain region, referring to Fig.21A Show.

[0110] In the embodiment of the present application, after etching the stacked structure to form the bottom source region 1201 and the bottom drain region 1202, a bottom source 131 and a bottom drain 132 may be formed in the bottom source region 1201 and the bottom drain region 1202, respectively. Fig.21A The surface of the bottom source 131 and the bottom drain 132 away from the substrate 110 may be flush with the surface of the isolation layer 200 close to the substrate 110 .

[0111] Specifically, for different types of semiconductor devices, the source material and the drain material may be different. For P-type semiconductor devices, the source and drain materials are boron-doped silicon germanium, i.e., SiGe:B; for N-type semiconductor devices, the source and drain materials are carbon-doped silicon, i.e., Si:C.

[0112] S105, forming a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain, and the buried power connection layer and the buried power line are electrically connected, referring to FIG. 22A to FIG. 28A , Fig.27B , Fig.27C and Fig.27D shown.

[0113] In the embodiment of the present application, considering that the two transistors stacked up and down need to be electrically led out later, after forming the bottom source 131 and the bottom drain 132, a buried power connection layer 320, a bottom ground connection layer 331, a bottom word line connection layer, a bottom bit line connection layer 351, a first storage bottom electrode 361, and a second storage bottom electrode 371 may be formed on the bottom source 131 and the bottom drain 132, and the buried power connection layer 320 is electrically connected to the buried power line 310. The specific formation process is described in detail below.

[0114] S1051, forming a target sidewall 300, referring to Fig.22A shown.

[0115] In the embodiment of the present application, after forming the bottom source 131 and the bottom drain 132, a target sidewall 300 may be formed, and the target sidewall 300 covers the sidewall of the inner sidewall 206, that is, the target sidewall 300 is respectively arranged on both sides of the inner sidewall 206 along the fin line direction, that is, the YY direction, and the target sidewalls 300 on both sides have the same thickness. The material of the target sidewall 300 may be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0116] S1052, forming a first dielectric layer 420, the first dielectric layer 420 covers the top structure 510 and the target sidewall 300, referring to Fig.23A and Fig. 23B .

[0117] In the embodiment of the present application, after forming the target sidewall 300, a dielectric material may be deposited and a planarization process may be performed to form a first dielectric layer 420, the first dielectric layer 420 covering the top structure 510 and the target sidewall 300, as shown in FIG. Fig.23A and Fig. 23B .

[0118] S1053, etching the first dielectric layer 420 on both sides of the top structure 510 to form a first groove 610, the first groove 610 exposes the bottom source 131 and the bottom drain 132, refer to Fig.24A and Fig. 24B .

[0119] In the embodiment of the present application, after forming the first dielectric layer 420, the first dielectric layer 420 on both sides of the top structure 510 can be etched to the bottom source 131 and the bottom drain 132 to form a first groove 610, and the first groove 610 exposes the bottom source 131 and the bottom drain 132. Fig.24A The first groove 610 also exposes the buried power line 310, referring to Fig. 24B shown.

[0120] S1054, forming a buried power connection layer 320, a bottom ground connection layer 331, a bottom word line connection layer, a bottom bit line connection layer 351, a first storage bottom electrode 361, and a second storage bottom electrode 371 on the bottom source 131 and the bottom drain 132 exposed by the first groove 610, referring to Fig.25A , Fig.25B , Fig.25C and Fig.25D shown.

[0121] In the embodiment of the present application, after forming the first groove 610 exposing the bottom source 131 and the bottom drain 132, a bottom ground connection layer 331, a first storage bottom electrode 361 and a bottom bit line connection layer 351 may be formed on the bottom source 131 and the bottom drain 132 exposed by the first groove 610. Fig.25A A first storage bottom electrode 361 and a second storage bottom electrode 371 are formed on the bottom source 131 and the bottom drain 132 exposed by the first groove 610, referring to Fig.25D A buried power connection layer 320 and a bottom ground connection layer 331 are formed on the bottom source 131 and the bottom drain 132 exposed by the first groove 610, and the buried power connection layer 320 is electrically connected to the buried power line 310, referring to Fig.25B and Fig.25C At the same time, a bottom word line connection layer is formed on the bottom source 131 and the bottom drain 132 exposed by the first groove 610 .

[0122] S1055, forming a second dielectric layer 430 in the first groove 610, referring to Fig.26A and Fig.26B shown.

[0123] In the embodiment of the present application, after forming the buried power connection layer 320, the bottom ground connection layer 331, the bottom word line connection layer, the bottom bit line connection layer 351, the first storage bottom electrode 361 and the second storage bottom electrode 371, a dielectric material can be deposited in the first groove 610, and then a planarization process is performed to form a second dielectric layer 430, referring to Fig.26A and Fig.26B The materials of the first dielectric layer 420 and the second dielectric layer 430 can be the same.

[0124] S1056, etching the first dielectric layer 420 and the second dielectric layer 430 to the side surface of the buffer layer 123 away from the substrate 110, refer to Fig.27A , Fig.27B , Fig.27C and Fig.27D shown.

[0125] In the embodiment of the present application, after forming the second dielectric layer 430, the first dielectric layer 420 and the second dielectric layer 430 can be etched back to the surface of the side of the buffer layer 123 away from the substrate 110, and the etched first dielectric layer 420 and the second dielectric layer 430 cover the buried power connection layer 320, the bottom ground connection layer 331, the bottom word line connection layer, the bottom bit line connection layer 351, the first storage bottom electrode 361 and the second storage bottom electrode 371, refer to Fig.27A , Fig.27B , Fig.27C and Fig.27D shown.

[0126] S1057, etching the target sidewall 300 to the side surface of the isolation layer 200 away from the substrate 110, refer to Fig.28A shown.

[0127] In an embodiment of the present application, after forming the buried power connection layer 320, the bottom ground connection layer 331, the bottom word line connection layer, the bottom bit line connection layer 351, the first storage bottom electrode 361 and the second storage bottom electrode 371, the target sidewall 300 can also be etched to the surface of the side of the isolation layer 200 away from the substrate 110, that is, the target sidewall 300 is only set on the side wall of the isolation layer 200.

[0128] S106, forming a top source and a top drain on the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode and the second storage bottom electrode, referring to Fig.29A shown.

[0129] In the embodiment of the present application, after forming the buried power connection layer 320, the bottom ground connection layer 331, the bottom word line connection layer, the bottom bit line connection layer 351, the first storage bottom electrode 361 and the second storage bottom electrode 371, the top source 133 and the top drain 134 can be further formed on the buried power connection layer 320, the bottom ground connection layer 331, the bottom word line connection layer, the bottom bit line connection layer 351, the first storage bottom electrode 361 and the second storage bottom electrode 371, so as to form the source and drain of the transistor located at the upper part of the two transistors stacked up and down, with reference to FIG. Fig.29A The top source 133 and the top drain 134 may be located on the first dielectric layer 420 and the second dielectric layer 430 .

[0130] Specifically, for different types of semiconductor devices, the source material and the drain material may be different. For P-type semiconductor devices, the source and drain materials are boron-doped silicon germanium, i.e., SiGe:B; for N-type semiconductor devices, the source and drain materials are carbon-doped silicon, i.e., Si:C.

[0131] S107, removing the first semiconductor layer in the top channel region and the bottom channel region, forming a plurality of gaps to be filled between the second semiconductor layers, and forming a second type work function layer in the plurality of gaps to be filled, referring to Fig. 30A and FIG. 30B to FIG. 32A and Fig.32B shown.

[0132] In the embodiment of the present application, the first semiconductor layer 121 in the top channel region 1103 and the bottom channel region 1203 may be removed, that is, a nanosheet channel release process may be performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layers 122, as shown in FIG. Fig.31A and Fig.31B Then, a second type work function layer 710 is formed in the plurality of gaps 402 to be filled, referring to Fig.32A and Fig.32B shown.

[0133] Specifically, the first semiconductor layer 121 in the stacked structure located in the top channel region 1103 and the bottom channel region 1203 can be selectively etched to release the nanosheet channel. In other words, the stacked structure exposed by the fin is processed to remove the first semiconductor layer 121 of each layer, which is a sacrificial layer, and release the nanosheet formed by the second semiconductor layer 122.

[0134] In the embodiments of the present application, there are several possible implementation methods for performing nanosheet channel release for different types of devices:

[0135] In a first possible implementation, for P-type and N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon germanium, and the silicon germanium is selectively removed, and the second semiconductor layer 122, i.e., silicon, is retained to form a silicon stack nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon germanium at a faster rate than silicon can be used.

[0136] In a second possible implementation, for a P-type semiconductor device, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon, and the silicon is selectively removed, and the second semiconductor layer 122, i.e., silicon germanium, is retained to form a silicon germanium stacked nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon at a faster rate than silicon germanium can be used.

[0137] In a third possible implementation, for an N-type semiconductor device, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon germanium, and the silicon germanium is selectively removed, and the second semiconductor layer 122, i.e., silicon, is retained to form a silicon stack nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon germanium at a faster rate than silicon can be used.

[0138] In the embodiment of the present application, before removing the first semiconductor layer 121 in the top channel region 1103 and the bottom channel region 1203 , the dummy gate 204 may be removed first. The specific process flow is as follows.

[0139] S1071, remove the false gate 204, refer to Fig. 30A and Fig. 30B shown.

[0140] In the embodiment of the present application, a spacer layer 207 may be deposited on the surface of the dummy gate 204, the top source 133 and the top drain 134 to prevent the interconnection short circuit between the dummy gate 204 and the top source 133 or the top drain 1342 in the subsequent steps, and the spacer layer 207 may be subjected to a chemical mechanical polishing process to make it flat. Fig. 30A and Fig. 30B As shown, the dummy gate 204 formed of the polysilicon or amorphous silicon is etched or corroded by a selective etching or corrosion process, that is, the dummy gate 204 is removed.

[0141] In the embodiment of the present application, after forming a plurality of gaps 402 to be filled, an interface layer may be formed on the surface of the second semiconductor layer 122 and the interface between the interface layer and the second semiconductor layer 122 may be passivated. Specifically, the material of the interface layer may be silicon oxide.

[0142] In the embodiment of the present application, after the interface layer is formed, a high-k dielectric layer may be formed on the surface of the interface layer, and the high-k dielectric layer surrounds the surface of the interface layer. Specifically, the material of the high-k dielectric layer may be HfO2, HfSiO x , HfON, HfSiON, HfAlOx, HfLaO x 、Al2O3、ZrO2、ZrSiO x , Ta2O5 or La2O3 or a combination of them.

[0143] Taking into account the formation of different types of transistors above and below, it is necessary to use isolation layers to isolate different types of transistors and different types of work function layers to realize different types of transistors. The specific process flow is introduced below.

[0144] S1072, forming a second type work function layer 710 in all the gaps 402 to be filled, referring to Fig.32A and Fig.32B shown.

[0145] In the embodiment of the present application, a second type work function layer 710 may be formed in all the gaps 402 to be filled, and the second type work function layer 710 surrounds the surface of the high-k dielectric layer. Specifically, the second type work function layer 710 is a P-type work function layer (P-WFL).

[0146] S108, filling a plurality of gaps to be filled with a protective material to form a protective layer, etching the protective layer of a first thickness using an anisotropic process, and continuing to etch the protective layer of a second thickness using an isotropic etching process, along a plane direction perpendicular to a line connecting the bottom source and the bottom drain, the difference between the second thickness and 1 / 2 of the width of the gap to be filled is less than a target threshold, reference Fig.33A and FIG. 33B to FIG. 35A and Fig.35Bshown.

[0147] In an embodiment of the present application, a protective material can be filled in a plurality of gaps 402 to be filled to form a protective layer 730, an anisotropic process is used to etch the protective layer 730 of a first thickness, and an isotropic etching process is continued to be used to etch the protective layer 730 of a second thickness, wherein, along a plane direction perpendicular to a line connecting the bottom source 131 and the bottom drain 134, a difference between the second thickness and 1 / 2 of the width of the gap 402 to be filled is less than a target threshold, that is, the first thickness of the protective layer 730 is precisely etched using an anisotropic process, so that the second thickness of the protective layer 730 can be subsequently etched using an isotropic etching process, so that the protective layer 730 is etched to a position of 1 / 2 of the isolation layer 200, thereby achieving precise etching of the protective layer 730 and reducing the risk of subsequently forming the same work function layer covering different transistors.

[0148] S1081, using an anisotropic process to etch the protective layer 730 to a thickness of 1 / 2 of the width of the gap 402 to be filled, refer to Fig.34A and Fig.34B shown.

[0149] In the embodiment of the present application, the first thickness may be 1 / 2 of the width of the gap 402 to be filled, and the protective layer 730 having a thickness of 1 / 2 of the width of the gap 402 to be filled may be etched using an anisotropic process, that is, the protective layer 730 having a thickness of 1 / 2 of the width of the gap 402 to be filled is etched from the surface of the protective layer 730 on one side away from the substrate 110. The etching speed of the anisotropic process in the direction perpendicular to the surface of the substrate 110 is greater than the etching speed in the direction parallel to the surface of the substrate 110, so when the protective layer 730 is etched using the anisotropic process, the protective layer 730 between adjacent second semiconductor layers 120 may not be completely etched away.

[0150] As an example, the anisotropic etching process may be a reactive ion etching (RIE) process, a remote plasma source (RPS) process, an atomic layer etching (ALE) process or a physical milling process.

[0151] S1082, continue to etch the second thickness of the protection layer 730 to the half position of the isolation layer 200 using the isotropic etching process, refer to Fig.35A and Fig.35B shown.

[0152] In the embodiment of the present application, since the use of anisotropic etching processes is prone to the problem that the protective layer 730 between adjacent second semiconductor layers 120 is not completely etched away, the isotropic process is continued to be used to continue etching the protective layer 730 to the 1 / 2 position of the isolation layer 200, wherein the 1 / 2 position of the isolation layer 200 is the 1 / 2 position in the direction perpendicular to the plane where the substrate 110 is located. Since the etching speed of the isotropic process is the same in all directions, it is possible to etch not only the protective layer 730 in the direction perpendicular to the surface of the substrate 110, but also the protective layer 730 between adjacent second semiconductor layers 120.

[0153] Considering that the difference between the second thickness and 1 / 2 of the width of the gap 402 to be filled is less than the target threshold, the target threshold can be 0. In this way, when the protective layer 730 is etched using an isotropic process, the protective layer 730 can be etched to 1 / 2 of the isolation layer 200, and the protective layer 730 between adjacent second semiconductor layers 120 can also be removed. That is, the etching position of the protective layer 730 can be accurately controlled, and the protective layer 730 between the nanosheets can also be effectively removed to avoid residual protective layer 730.

[0154] refer to Fig.35A and Fig.35B As shown, the protection layer 730 fills the gap 402 to be filled in the bottom structure 520 .

[0155] As an example, the isotropic etching process may be a wet etching process, an RPS process, a chemical dry etching process or an ALE process.

[0156] S109, removing the second type work function layer in the gap to be filled that is not covered by the protective layer, and forming a first type work function layer in the gap to be filled that is not covered by the protective layer, referring to Fig.36A and Fig.36B To reference Fig.37A and Fig.37B shown.

[0157] In the embodiment of the present application, the protective layer 730 is used as a mask to remove the second type work function layer 710 in the gap 402 to be filled that is not covered by the protective layer 730, and the first type work function layer 720 is formed in the gap 402 to be filled that is not covered by the protective layer 730, that is, the second type work function layer 710 in the gap 402 to be filled located in the top structure 510 is removed, and the first type work function layer 720 is formed in the gap 402 to be filled located in the top structure 510, thereby forming the first type work function layer 720 in the top structure 510 and the second type work function layer 710 in the bottom structure 520, refer to Fig.36A and Fig.36BSpecifically, the first type work function layer 720 is an N-type work function layer (N-WFL). The second type work function layer 710 located in the gap 402 to be filled in the top structure 510 can be removed by an etching process.

[0158] S1091, remove the protective layer 730, refer to Fig.37A and Fig.37B shown.

[0159] In the embodiment of the present application, after the first type work function layer 720 and the second type work function layer 710 are formed, the protection layer 730 may be removed.

[0160] In practical applications, the protective layer 730 may be removed first, and then the first type work function layer 720 may be formed in all the gaps 402 to be filled. That is, the second type work function layer 710 may be formed first in the gaps 402 to be filled in the bottom structure 520, and then the first type work function layer 720 may be formed.

[0161] S110, filling gates in the plurality of gaps to be filled, the gates surrounding the second semiconductor layer, and the stacked layers formed by the plurality of second semiconductor layers respectively forming a top channel structure and a bottom channel structure, referring to Fig.38A and Fig.38B shown.

[0162] In the embodiment of the present application, after the nanosheet channel is released, there are multiple gaps 402 to be filled between the multiple second semiconductor layers 122, and the gate 160 can be filled in the multiple gaps 402 to be filled. The gate 160 surrounds the second semiconductor layer 122 to form a ring gate structure. Specifically, the gate 160 surrounds the first type work function layer 720 and the second type work function layer 710. The stack composed of the multiple second semiconductor layers 122 forms a top channel structure and a bottom channel structure, that is, a nanosheet channel of a complementary field effect transistor is formed, refer to Fig.38A and Fig.38B shown.

[0163] In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 also covers the space after the spacer layer 207 and the dummy gate 204 are removed. The gate 160 covering the spacer layer 207 can be chemically mechanically polished for planarization.

[0164] S120, forming a top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode and a second storage top electrode on the top source and the top drain, respectively, the top ground connection layer is connected to the bottom ground connection layer, and the reference Fig.39A and FIG. 39B to FIG. 40A , Fig.40B , Fig.40C and Fig.40D shown.

[0165] In the embodiment of the present application, after the gate 160 is formed, a top ground connection layer 332, a top word line connection layer, a top bit line connection layer 352, a first storage top electrode 362 and a second storage top electrode 372 may be formed on the top source 133 and the top drain 134, respectively. The top ground connection layer 332 is connected to the bottom ground connection layer 331. Fig.40A , Fig.40B , Fig.40C and Fig.40D The specific formation process is described in detail below.

[0166] S121 , forming a third dielectric layer 440 on the top source 133 and the top drain 134 .

[0167] In the embodiment of the present application, after forming the top source 133 and the top drain 134 , a dielectric material may be deposited and a planarization process may be performed to form a third dielectric layer 440 , and the third dielectric layer 440 covers the top source 133 and the top drain 134 .

[0168] S122, etching the third dielectric layer 440 on both sides of the top structure 510 to form a second groove 620, the second groove 620 exposes the top source 133 and the top drain 134, refer to Fig.39A and Fig.39B shown.

[0169] In the embodiment of the present application, after forming the third dielectric layer 440, the third dielectric layer 440 on both sides of the top structure 510 can be etched to the top source 133 and the top drain 134 to form a second groove 620, and the second groove 620 exposes the top source 133 and the top drain 134. Fig.39A The second groove 620 also exposes the first storage bottom electrode 361 and the second storage bottom electrode 371, referring to Fig.39B shown.

[0170] S123, forming a top ground connection layer 332, a top word line connection layer, a top bit line connection layer 352, a first storage top electrode 362 and a second storage top electrode 372 on the top source 133 and the top drain 134 exposed by the second groove 620, respectively, Fig.40A , Fig.40B , Fig.40C and Fig.40D shown.

[0171] In the embodiment of the present application, after forming the second groove 620 exposing the top source 133 and the top drain 134, a top ground connection layer 332, a first storage top electrode 362 and a top bit line connection layer 352 may be formed on the top source 133 and the top drain 134 exposed by the second groove 620, referring to Fig.40A A first storage top electrode 362 and a second storage top electrode 372 are formed on the top source 133 and the top drain 134 exposed by the second groove 620, referring to Fig.40D A top ground connection layer 332 and a top bit line connection layer 352 are formed on the top source 133 and the top drain 134 exposed by the second groove 620. The top ground connection layer 332 and the bottom ground connection layer 331 are electrically connected. Fig.40B and Fig.40C At the same time, a top word line connection layer is formed on the top source 133 and the top drain 134 exposed by the second groove 620 .

[0172] In practical applications, the first storage electrode includes a first storage top electrode 362 and a first storage bottom electrode 361, and the first storage electrode may be a Q storage electrode. The second storage electrode includes a second storage top electrode 372 and a second storage bottom electrode 371, and the second storage electrode may be a QB storage electrode.

[0173] The use of anisotropic etching combined with isotropic etching provided in the embodiment of the present application can not only realize the layering process of the work function layer using a precisely positioned protective layer, but also can realize the layering process of the gate or high-k dielectric layer using a precisely positioned protective layer, thereby also realizing the upper and lower layering of gates or high-k dielectric layers of different types and thicknesses of transistors stacked up and down. It can be seen that the present application can realize precise etching of the protective layer by using anisotropic etching combined with isotropic etching, avoid longitudinal position passing, and realize precise control of the position of the protective layer, thereby avoiding transistors with different types of work function layers, high-k dielectric layers and gate coverage errors, and reducing the risk of confusion of transistor types. The present application can also effectively remove the protective layer between nanosheet layers by using anisotropic etching combined with isotropic etching, thereby avoiding the residue of the protective layer.

[0174] Based on the method for manufacturing a complementary field effect transistor provided in the above embodiment, the embodiment of the present application further provides a complementary field effect transistor, and its working principle is described in detail below in conjunction with the accompanying drawings.

[0175] See also Fig.40A , Fig.40B , Fig.40C and Fig.40D As shown, this figure is a schematic diagram of the cross-sectional structure of the complementary field effect transistor provided in an embodiment of the present application.

[0176] The complementary field effect transistor provided in this embodiment includes:

[0177] Substrate 110;

[0178] A top source 133, a top drain 134, a top channel structure, a bottom source 131, a bottom drain 132 and a bottom channel structure are arranged on one side of the substrate, wherein in a direction perpendicular to the plane where the substrate is located, the top source 133 overlaps with the bottom source 131, the top drain 134 overlaps with the bottom drain 132, and the top channel structure overlaps with the bottom channel structure; the top channel structure is located between the top source 133 and the top drain 134, the bottom channel structure is located between the bottom source 131 and the bottom drain 132, and the top channel structure and the bottom channel structure include a stack formed by a plurality of nanosheets;

[0179] A gate 160, wherein the gate 160 surrounds the nanosheet;

[0180] The nanosheet of the top channel structure is surrounded by a first type work function layer 720, and the nanosheet of the bottom channel structure is surrounded by a second type work function layer 710;

[0181] The top ground connection layer 332 is in contact with the top source 133 , the bottom ground connection layer 331 is in contact with the bottom source 131 , and the top ground connection layer 332 is connected to the bottom ground connection layer 331 .

[0182] As a possible implementation manner, an isolation layer 200 is disposed between the top channel structure and the bottom channel structure.

[0183] As a possible implementation manner, a target sidewall 300 is disposed on the sidewall of the isolation layer 200 .

[0184] As a possible implementation, along a direction perpendicular to the plane where the substrate 110 is located, 1 / 2 of the sidewall of the isolation layer 200 is the boundary between the first type work function layer 720 and the second type work function layer 710 .

[0185] Based on a complementary field effect transistor provided in the above embodiment, an embodiment of the present application further provides a static random access memory, the static random access memory includes a plurality of storage units, and the storage unit includes the complementary field effect transistor described in any one of the above embodiments.

[0186] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the structural embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the structural embodiment. The structural embodiment described above is only illustrative, and ordinary technicians in this field can understand and implement it without creative work.

[0187] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A method for manufacturing a complementary field effect transistor, characterized in that: The method comprises: Providing a substrate, forming a plurality of stacked structures consisting of alternately stacked first semiconductor layers and second semiconductor layers on one side of the substrate, wherein the stacked structures include a buffer layer located in a middle region along a direction perpendicular to a plane where the substrate is located; Etching the stacked structure and a partially thick substrate to form a fin structure, wherein the fin structure includes a top structure, a bottom structure and a substrate structure, wherein the top structure and the bottom structure are separated by the buffer layer, and an embedded power line is formed between the two substrate structures; Etching the top structure, the buffer layer and the bottom structure to form a top source region, a top drain region, a bottom source region and a bottom drain region, wherein the top source region and the top drain region are located between the top channel region and the bottom source region and the bottom drain region are located between the bottom channel region; forming inner sidewalls on the sidewalls of the top structure and the sidewalls of the bottom structure; forming a bottom source and a bottom drain in the bottom source region and the bottom drain region; Forming a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain, wherein the buried power connection layer is electrically connected to the buried power line; forming a top source and a top drain on the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode and the second storage bottom electrode; The first semiconductor layer in the top channel region and the bottom channel region is removed to form a plurality of gaps to be filled between the second semiconductor layers, and a second type work function layer is formed in the plurality of gaps to be filled; Filling a plurality of the gaps to be filled with a protective material to form a protective layer, etching the protective layer of a first thickness using an anisotropic process, and continuing to etch the protective layer of a second thickness using an isotropic process, along a plane direction perpendicular to a line connecting the bottom source electrode and the bottom drain electrode, a difference between the second thickness and 1 / 2 of a width of the gap to be filled is less than a target threshold; Removing the second type work function layer in the gap to be filled that is not covered by the protective layer, and forming the first type work function layer in the gap to be filled that is not covered by the protective layer; removing the protective layer; Filling gates in the plurality of gaps to be filled, the gates surrounding the second semiconductor layer, and the stacked layers formed by the plurality of second semiconductor layers respectively forming a top channel structure and a bottom channel structure; A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode and a second storage top electrode are formed on the top source and the top drain, respectively, and the top ground connection layer is connected to the bottom ground connection layer.

2. The manufacturing method according to claim 1, characterized in that: The forming of the inner side wall on the side wall of the top structure and the side wall of the bottom structure comprises: Etching and removing a portion of the first semiconductor layer on the sidewalls of the top structure and the sidewalls of the bottom structure, and etching and removing the buffer layer, to form a concave structure and a buffer isolation structure, respectively; An inner sidewall is formed in the concave structure, and an isolation layer is formed in the buffer isolation structure.

3. The manufacturing method according to claim 2, characterized in that: The etching of the protective layer having a first thickness by using an anisotropic process and continuing to etch the protective layer having a second thickness by using an isotropic process comprises: Etching the protective layer to a thickness of 1 / 2 of the width of the gap to be filled by using an anisotropic process; The protection layer having a second thickness is continuously etched to a position of 1 / 2 of the isolation layer using an isotropic process.

4. The manufacturing method according to claim 3, characterized in that: Before forming a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain, the method further includes: forming a target side wall, wherein the target side wall covers the side wall of the inner side wall; forming a first dielectric layer, wherein the first dielectric layer covers the top structure and the target sidewall; Etching the first dielectric layer on both sides of the top structure to form a first groove, wherein the first groove exposes the bottom source and the bottom drain; The forming of a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain comprises: forming a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain exposed by the first groove; The method further comprises: forming a second dielectric layer in the first groove; Etching the first dielectric layer and the second dielectric layer to a surface of the isolation layer that is away from the substrate; Etching the target sidewall to a surface of the isolation layer that is away from the substrate; The forming of a top source and a top drain on the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode and the second storage bottom electrode comprises: A top source and a top drain are formed on the first dielectric layer and the second dielectric layer, and the first dielectric layer and the second dielectric layer cover the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode and the second storage bottom electrode.

5. The manufacturing method according to claim 1, characterized in that: Before forming a top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode and a second storage top electrode on the top source and the top drain, respectively, the method further includes: forming a third dielectric layer on the top source and the top drain; Etching the third dielectric layer on both sides of the top structure to form a second groove, wherein the second groove exposes the top source and the top drain; A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode and a second storage top electrode are respectively formed on the top source and the top drain, comprising: A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode are respectively formed on the top source and the top drain exposed by the second groove.

6. A complementary field effect transistor, characterized in that: The complementary field effect transistor comprises: substrate; A top source, a top drain, a top channel structure, a bottom source, a bottom drain and a bottom channel structure are arranged on one side of the substrate, wherein in a direction perpendicular to the plane where the substrate is located, the top source overlaps with the bottom source, the top drain overlaps with the bottom drain, and the top channel structure overlaps with the bottom channel structure; the top channel structure is located between the top source and the top drain, the bottom channel structure is located between the bottom source and the bottom drain, and the top channel structure and the bottom channel structure include a stack formed by a plurality of nanosheets; a gate, the gate surrounding the nanosheet; The nanosheet of the top channel structure is surrounded by a first type work function layer, and the nanosheet of the bottom channel structure is surrounded by a second type work function layer; The top ground connection layer contacts the top source, the bottom ground connection layer contacts the bottom source, and the top ground connection layer is connected to the bottom ground connection layer.

7. The complementary field effect transistor according to claim 6, characterized in that: An isolation layer is disposed between the top channel structure and the bottom channel structure.

8. The complementary field effect transistor according to claim 7, characterized in that: The sidewall of the isolation layer is provided with a target sidewall.

9. The complementary field effect transistor according to claim 7, characterized in that: Along a direction perpendicular to the plane where the substrate is located, 1 / 2 of the side wall of the isolation layer is the junction of the first type work function layer and the second type work function layer.

10. A static random access memory, characterized in that: It comprises a plurality of memory cells, each of which comprises a complementary field effect transistor as claimed in any one of claims 6 to 9.

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