Multi-layer ion trap on shaped glass or dielectric substrate

Abstract

Aspects of the present disclosure describe trapping devices for quantum information processing (QIP) architectures, and more particularly, to the use and manufacture of multi-layer ion traps on shaped glass or dielectric substrates (100). A method of fabricating an ion trap is described that includes processing a back side of a substrate, constructing a multilayer stack on a top side of the substrate, completing a back etch to penetrate the substrate, and etching through a metal (140) and a dielectric (150) in the multilayer stack to complete formation of the ion trap. Shaping of the ion trap may also include trap narrowing features, wings, and / or undercuts. Ion traps fabricated using this method can be used in QIP systems to trap atomic species provided through pores in the back side of the substrate as qubits in quantum operations and calculations.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 333,781, filed on April 22, 2022, entitled “Multi-Layer Ion Trap on Shaped Glass or Dielectric Substrate,” and U.S. Non-Provisional Patent Application No. 18 / 302,572, filed on April 18, 2023, entitled “Multi-Layer Ion Trap on Shaped Glass or Dielectric Substrate,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of the present disclosure relate generally to trapped devices for quantum information processing (QIP) architectures and, more particularly, to the use and fabrication of multi-layer ion traps on shaped glass or dielectric substrates. Background Art

[0004] Trapped atoms are one of the main implementations of quantum information processing or quantum computing. Atom-based qubits can be used as quantum memories, as quantum gates in quantum computers and simulators, and as nodes in quantum communication networks. Qubits based on trapped atomic ions have a rare combination of properties. For example, qubits based on trapped atomic ions have very good coherence, can be prepared and measured with an efficiency close to 100%, and can be easily entangled with each other by modulating their Coulomb interactions with suitable external control fields (such as light fields or microwave fields). These properties make atom-based qubits attractive for extended quantum operations such as quantum computing or quantum simulation.

[0005] It is therefore important to improve the design and fabrication of wells for handling atom-based qubits. Summary of the invention

[0006] The following is a simplified summary of one or more aspects to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify key or essential elements of all aspects, nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that is presented later.

[0007] One aspect of the present disclosure describes techniques for making multilayer traps on a shaped glass or dielectric substrate. The types of traps made using these techniques include ion traps, but are not necessarily so limited. The term shaping can refer to various processes or techniques that physically modify or change at least a portion of a substrate to produce a substrate of a desired form. Shaping may involve forming holes through the substrate and / or more substantial shaping, such as trap wings, narrowing of the middle portion of the trap, and / or undercutting. The method includes preparing a glass or dielectric substrate, building a multilayer stack on the top surface of the glass or dielectric substrate, and etching from the back to completely etch through the glass or dielectric substrate and / or a portion of the multilayer stack and complete the ion trap.

[0008] One aspect of the present disclosure describes a method for manufacturing a well, the method comprising: processing the back side of a substrate for subsequent processing; after processing the back side of the substrate, building a multilayer stack on the top surface of the substrate, the multilayer stack including at least one metal layer for wiring and at least one metal layer for a top electrode; and after building the multilayer stack on the top surface of the substrate, shaping the substrate by processing the back side of the substrate.

[0009] Another aspect of the present disclosure describes a QIP system that uses multi-layer ion traps on a shaped glass or dielectric substrate.

[0010] One aspect of the present disclosure describes a QIP system, the QIP system including an ion trap having a substrate made of a glass material or a dielectric material, and a multilayer stack disposed on the substrate and including at least one metal layer for wiring, at least one dielectric layer, and at least one metal layer for a top electrode, wherein the substrate and the multilayer stack are shaped to form a hole extending through the substrate and through the multilayer stack. The QIP system also includes a source configured to provide atomic species from the back side of the ion trap, the atomic species passing through the holes in the substrate and the multilayer stack of the ion trap to the top surface of the ion trap.

[0011] One aspect of the present disclosure describes an ion trap having a substrate made of a glass material or a dielectric material; and a multilayer stack, which is arranged on the substrate and includes at least one metal layer for wiring, at least one dielectric layer and at least one metal layer for a top electrode, and the substrate and the multilayer stack are formed to form a hole extending through the substrate and the multilayer stack.

[0012] To achieve the above and related purposes, the one or more aspects include the features fully described and particularly pointed out in the appended claims. The following description and the accompanying drawings set forth in detail certain illustrative features of the one or more aspects. However, these features are only indicative of some of the various ways in which the principles of the various aspects can be employed, and the present description is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The disclosed aspects will hereinafter be described in conjunction with the accompanying drawings, which are provided to illustrate and not to limit the disclosed aspects, wherein like reference numerals represent like elements, and wherein:

[0014] Figure 1A-1H An example of a fabrication process for fabricating a well with metallization on a shaped glass substrate or a shaped dielectric substrate according to aspects of the present disclosure is shown.

[0015] Figure 2A and Figure 2B An example of using dams to limit the deleterious effects of etching on a device according to aspects of the present disclosure is shown.

[0016] Figure 3A and Figure 3B Examples of other shaping of glass substrates or dielectric substrates according to aspects of the present disclosure are shown.

[0017] Figure 4 A flow chart of a method of fabricating a well with metallization on a shaped glass substrate or a shaped dielectric substrate according to aspects of the present disclosure is shown.

[0018] Figure 5 An example of a quantum information processing (QIP) system in accordance with aspects of the present disclosure is shown in which an ion trap having the features described herein may be used.

[0019] Figure 6 An example of a computer device according to aspects of the present disclosure is shown in which an ion trap having the features described herein can be used for quantum information processing. DETAILED DESCRIPTION

[0020] The detailed description given below in conjunction with the accompanying drawings is intended as a description of various configurations, rather than being intended to represent the only configurations in which the concepts described herein can be practiced. This detailed description includes specific details for providing a comprehensive understanding of the various concepts. However, it is apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known components are shown in block diagram form to avoid blurring these concepts.

[0021] Figure 1A-1HExamples of fabrication processes for fabricating wells with metallization on shaped glass substrates or shaped dielectric substrates in accordance with various aspects of the present disclosure are shown. These figures provide schematic diagrams of the fabrication process, and the sizes and thicknesses shown are for illustration purposes only and are not intended to accurately represent the actual sizes and thicknesses of the well features.

[0022] The type of metallization process used can be an electroplating process, similar to the electroplating process used in the manufacture of microelectromechanical systems (MEMS). It should be understood that, where appropriate, techniques other than electroplating processes can be used for metallization. For example, for at least some of the metallization steps required as part of the present disclosure, techniques such as sputtering and / or physical vapor deposition (PVD) or other similar techniques can be used instead of electroplating processes. Although the processes or methods described herein are applicable to wells with multiple metallization layers (e.g., wells that allow one or more metal layers to be used for wiring and one metal layer to be used for the top electrode), they can also be applied in whole or in part to wells using a single metallization layer.

[0023] Figure 1A A substrate 100 made of glass or dielectric material, also referred to as a wafer or die, is shown. One example of a material that can be used for the substrate 100 is fused silica (FuSi). Also shown are alignment patterns or marks 110 formed on the top surface of the substrate 100 using standard manufacturing processes. These alignment marks 110 can be used to align subsequent processes performed on the surface of the substrate 100.

[0024] Next, if Figure 1B As shown, the back side of the substrate 100 is processed by laser writing or similar process to prepare a wafer for selective etching. Figure 1B As shown, a local etch 120 may be performed to form a hole from the back side of the substrate 100 to the front side of the substrate 100. Examples of selective etching types include Andrius The technique is described by Saulius Juodkazis, Mitsuru Watanabe, Masafumi Miwa, Shigeki Matsuo, Hiroaki Misawa, and Junji Nishii in "Femtosecond laser-assisted three-dimensional microfabrication insilica," Opt. Lett. 26, 277-279 (2001). Example manufacturing sources for this process are Translume (www.transume.com) and Femtoprint (www.Femtoprint.ch). The local etch 120 may include one or more write and etch steps.

[0025] If local etching is included (such as Figure 1B 120 ). If the local etching is performed on the top surface of the substrate 100, the local etching may produce a meniscus or thin layer 130. The meniscus 130 can be left to provide mechanical support for subsequent processes performed on the top surface of the substrate 100. The thickness of the meniscus 130 can depend on how many local etchings 120 (if any) are performed. In addition or alternatively, the meniscus 130 can be retained to reduce the topology of high aspect ratio (HAR) lithography used with the electroplating process. Having a flat surface by leaving the meniscus 130 can allow better photoresist deposition and development. The meniscus 130 can also be prepared by a laser writing process for selective etching in subsequent steps. When the top surface processing has been completed, the meniscus 130 can be etched at a later stage to complete the hole through the substrate 100.

[0026] Figure 1C The next steps performed on the top surface of the substrate 100 are shown. These steps may include depositing or forming a patterned or unpatterned metallization layer 140 on the top surface of the substrate 100, and then depositing or forming a dielectric layer 150. The metallization layer 140 provides a protective etch barrier for subsequent processing steps and may also be used as an electrical wiring layer. The metallization layer 140 may be referred to as a first metallization layer. Examples of metals for the metallization layer 140 are chromium or titanium tungsten (Ti-tungsten or TiW). The layer may be a multi-metal stack to improve conductivity or provide further protection benefits; for example, chromium or titanium tungsten metallization may be covered with copper metallization to improve conductivity. The dielectric layer 150 may be patterned and filled with metal or other conductive materials to form electrical vias 155 through the dielectric layer 150. Both the dielectric layer 150 and the vias 155 may be planarized using chemical mechanical polishing or other processes to provide a flat or nearly flat surface for further process steps. Since multiple layers of different materials are deposited or formed on a glass (or dielectric) substrate, the wells described herein may be referred to as multilayer wells on glass. In addition, since the glass is formed by, for example, local etching 120 (and subsequent full etching, and possibly etching in other portions of the substrate 100), the wells described herein may be referred to as multilayer wells on formed glass. When the substrate is a dielectric substrate or a glass-ceramic substrate, the wells may be referred to as multilayer wells on formed dielectrics or formed glass-ceramic, respectively.

[0027] Then, if Figure 1DAs shown, metallization 160 is applied on the top of dielectric layer 150 to form the top electrode and / or wiring connection of the well. As described above, the process for metallization, such as the process for manufacturing metallization 160, can be a plating process similar to that used in MEMS manufacturing. In addition, an example of a metal for metallization 160 is gold (Au), but other metals or combinations of metals can also be used. When metallization 160 is a top metal layer of a multi-layer stack or multi-layer structure built on the top surface of substrate 100, it can be referred to as a top metallization or a top electroplated metallization (if made with such a process). In an exemplary aspect, metallization 160 can include a metallization layer (not shown) located between the top metallization and dielectric layer 150, which can be patterned or not. An example of the metallization layer is a plating seed layer used when metallization 160 is formed by electroplating metal. The intermediate layer can be etched before the following steps, or it can be left to be removed in the later stage of the process.

[0028] Figure 1E A temporary protective layer 170 is shown deposited on the metallization 160. The temporary protective layer 170 covers the structure formed by the metallization 160, but not under the structure. The temporary protective layer 170 can be formed of one or more protective layers. The temporary protective layer 170 allows subsequent etching processes to be performed on the back side of the substrate 100 without affecting the multilayer stack on the top surface.

[0029] Figure 1F The process of obtaining a local etch 120 and performing further etching (e.g., by placing the entire substrate 100 in an acid bath) to break through the meniscus 130 and produce a complete etch 120' on the back side of the substrate 100 is shown. If the earlier local etch is not performed, the etch will provide a complete etch through the substrate 110. The metallization layer 140, also referred to as the protective metallization layer 140, can be used primarily for routing, however, the metallization layer 40 can also be used to prevent the backside etch from penetrating and reaching the dielectric layer 150. As a variation, the metallization layer 140 can be patterned to allow the etchant to reach the dielectric layer 150 in a specified area above the etch 120'. If the meniscus 130 or other areas of the substrate have been processed for selective etching during earlier processing, the shape of the final etch can be controlled. If the meniscus 130 has not been processed in this way, the etch may be isotropic. The etchant or etching process used for this manufacturing stage can be the same as the earlier etchant or etching process used for early selective substrate shaping, or it can be different.

[0030] Optionally, the metallization layer 140 may then be etched from the back side to expose the dielectric layer 150. The dielectric layer 150 may then be etched to complete the hole 120 through the entire substrate and the deposited layers, such as Figure 1G Thus, there is a hole connecting the back surface to the top surface, and by using the alignment mark 110 (see Figure 1A ) to properly align the hole. An example of such a hole is a hole used to load atomic species from the back side of the substrate 100 to the top surface of the well to trap and use them for quantum bits in quantum operations and computations.

[0031] Once breakthrough is achieved, the temporary protective layer 170 can be removed, e.g. Figure 1H At this point, additional protective layers and etching from the front side can be used to cut holes in the dielectric layer 150 and the metallization layer 140. For example, if the optional backside etch through the metallization layer 140 and the dielectric layer 150 is not performed, the frontside etch can be completed to completely etch through the device, including a patterned protective layer to limit the etch to specific areas.

[0032] The above-described manufacturing techniques address some incompatibilities of using glass forming or etching processes with processes used in MEMS manufacturing. In order to be able to create a multilayer stack, it is helpful, but not always necessary, for the top surface of substrate 100 to remain pristine and free of holes, and if an etching process is applied entirely to the top surface, holes created in the surface by such an etching process may not be handled well. In addition, after building a multilayer stack on the top surface of substrate 100, a back etching process cannot be fully performed because the laser writing process may damage or destroy the multilayer stack. Therefore, the techniques described herein involve processing of the substrate (which may include local etching), building a multilayer stack on the top surface, and final etching from the back to the front, while protecting the front from the acid (or other process) used to form the substrate by removing the laser writing area of ​​the substrate or the untreated substrate (e.g., the meniscus 130), or a combination of both.

[0033] Figure 2A An example of using dams or vias 200 through dielectric layer 150 to limit the extent of the etch through dielectric layer 150 to region 210 is shown. The dams or vias 200 may surround the top extent of etch 120", or may only encompass a portion of the etch. Without these protective dams or vias 200, the etch through dielectric layer 150 may be limited only by the etch time if an acid is used. This may impose design constraints to prevent excessive undercutting of metallization 160 while still completing the etch through dielectric layer 150.

[0034] Figure 2B Shows Figure 2A The temporary protective layer of the well structure (e.g., temporary protective layer 170) is removed. The figure also shows a complete etch through the device (e.g., see Figure 1H ).

[0035] Although Figure 1A-Figure 2B Examples are shown of providing holes in a glass or dielectric substrate (or glass ceramic substrate) using substrate shaping, but the techniques described above can be applied to multi-layer wells in glass involving additional or alternative shaping. Figure 3A and Figure 3B Examples of other shaping of glass substrates or dielectric substrates according to aspects of the present disclosure are shown.

[0036] For example, Figure 3A A substrate 100 is shown in which glass forming is used to produce narrowing and / or wings 310 of a well 300. The well 300 is shown as being narrow in the middle, and wings 310 are formed at both ends of the well 300. These features enable the well to provide improved optical compatibility and system integration. Thus, the process involving backside processing, top multilayer stack construction, and final backside etching as described herein can be used to produce a well 300 such as a substrate 100. Figure 3A The shaped well shown.

[0037] In another example, Figure 3B A substrate 100 is shown in which glass forming results in narrowing of the well 300, wings 310 and / or undercuts 320. Figure 3B As shown, the well 300 is shown as being narrow in the middle, with wings 310 formed at both ends of the well, and undercuts 320 added on both sides of the middle portion of the well 300. The shape or geometry of the undercut 320 is provided by way of illustration and not limitation, and other shapes or geometries may also be used. These features enable the well to provide improved optical compatibility (e.g., compatibility with the beam waist) and system integration. Therefore, the process described herein involving backside processing, top multilayer stacking construction, and final backside etching can be used to produce a well such as Figure 3B The shaped well shown.

[0038] Figure 4 A flow chart of a method 400 for fabricating a well with metallization on a shaped glass substrate or a shaped dielectric substrate is shown in accordance with aspects of the present disclosure.

[0039] After providing a glass or dielectric substrate, method 400 may include processing a body of the glass or dielectric substrate (eg, substrate 100) at 410. The processing may include the above combined Figure 1A and Figure 1B One or more of the steps described.

[0040] Method 400 may include building (eg, disposing or depositing) a multilayer stack on a top surface of a glass or dielectric substrate at 420. The building may include combining the above Figure 1C-1E One or more of the various steps described.

[0041] Method 400 may include performing or completing etching through the glass or dielectric substrate from the back side and completing the ion trap at 430. This may include etching through a portion of the multilayer stack from the back side to form a hole through the entire thickness of the substrate 100 and the multilayer stack. Completion of the etching may include the above in combination with Figure 1F and Figure 1G Describe the steps.

[0042] In addition, method 400 may include: Figure 1H and Figure 2B The temporary protective layer (eg, temporary protective layer 170 ) is shown removed, and / or additional etching through the metallization layer 140 and the dielectric layer 150 is performed.

[0043] Additionally, method 400 may include forming a dam or via (eg, dam 200 ) in the dielectric layer to limit the extent of etching through the dielectric layer.

[0044] One aspect of the present disclosure describes a method for manufacturing a well (e.g., method 400), which includes processing the back side of a substrate for subsequent processing; after processing the back side of the substrate, building a multilayer stack on the top surface of the substrate, the multilayer stack including at least one metal layer for wiring and at least one metal layer for a top electrode; and after building the multilayer stack on the top surface of the substrate, shaping the substrate by processing the back side of the substrate.

[0045] For this method, the substrate may be made of a glass material or a dielectric material.

[0046] For this method, the substrate can be made of fused silica.

[0047] For this method, processing the back side of the substrate includes applying at least one laser writing step to process the back side of the substrate for selective etching.

[0048] For this method, processing the back side of the substrate includes locally shaping the substrate by removing a portion of the substrate from the back side of the substrate. In addition, removing a portion of the substrate includes applying one or more laser writing steps and one or more etching steps. Additionally or alternatively, removing a portion of the substrate leaves a meniscus near the top surface of the substrate. Additionally or alternatively, processing the back side of the substrate includes applying one or more laser writing steps to the meniscus, which may process the entire thickness of the meniscus for later selective etching, or may only process a portion of the thickness for later selective etching. In addition, the method includes removing the meniscus at a later stage. For example, constructing a multilayer stack includes providing a protective layer on the multilayer stack, and removing the meniscus after providing the protective layer on the multilayer stack.

[0049] For this method, constructing a multilayer stack includes disposing a first metallization on a top surface of a substrate, disposing a dielectric layer on the first metallization, and disposing a second metallization on the dielectric layer, the first metallization being part of the at least one metal layer for wiring, and the second metallization being part of the at least one metal layer for a top electrode. Disposing the dielectric layer includes forming a through hole in the dielectric layer to enable a connection between the first metallization and the second metallization. Disposing the first metallization includes patterning the first metallization to provide wiring. Disposing the second metallization includes patterning the second metallization to provide a top electrode. Disposing the first metallization, disposing the second metallization, or both include an electroplating process. In addition, the second metallization can be made of gold. Disposing the second metallization includes patterning the second metallization to provide a top electrode.

[0050] For this method, building a multilayer stack includes providing a dielectric layer and providing two or more metallization layers on the dielectric layer.

[0051] For this method, building a multilayer stack includes providing more than two metallization layers.

[0052] For this method, constructing the multilayer stack includes disposing a protective layer on the multilayer stack, and shaping the substrate by processing the back side of the substrate includes removing a portion of the substrate from the back side of the substrate to form a hole through the thickness of the substrate. In addition, shaping the multilayer stack by removing a portion of the multilayer stack is used to extend the hole through the substrate through the multilayer stack. The multilayer stack includes a dielectric layer having a plurality of dams, and the hole extending through the multilayer stack extends between the dams in the dielectric layer. The method also includes removing the protective layer.

[0053] Figure 5 A block diagram of an example of a QIP system 500 in which the multi-layer ion traps on shaped glass or dielectric substrates described herein may be implemented according to aspects of the present disclosure is shown. QIP system 500 may also be referred to as a quantum computing system, a computer device, a trapped ion system, etc.

[0054] The QIP system 500 may include a source 560 that provides atomic species (e.g., a plume or flux of neutral atoms) to a chamber 550 having an ion trap 570 that traps the atomic species after ionization (e.g., photoionization). The source 560 may be implemented separately from the chamber 550. The ion trap 570 may be part of a processor or processing portion of the QIP system 500. The ion trap 570 may be an example of a multilayer ion trap on a shaped glass or dielectric substrate as described herein. For example, the ion trap 570 may be configured as described above in conjunction with Figure 1A-Figure 2B In addition, the ion trap 570 can be formed to include the above combined Figure 3A and Figure 3BSome or all of the features described, such as well 300.

[0055] Imaging system 530 may include a high-resolution imager (e.g., a CCD camera) for monitoring atomic ions while they are provided to the ion trap or after they are provided to ion trap 570. In one aspect, imaging system 530 may be implemented separately from optics and trap controller 520, however, using fluorescence to detect, identify, and label atomic ions through the use of image processing algorithms may require coordination with optics and trap controller 520.

[0056] The QIP system 500 may also include an algorithm component 510 that may operate with other portions of the QIP system 500 (not shown) to perform quantum algorithms or quantum operations, including combined stacks or sequences of single-qubit operations and / or multi-qubit operations (e.g., two-qubit operations) and extended quantum computations. Thus, the algorithm component 510 may provide instructions to various components of the QIP system 500 (e.g., to the optics and trap controller 520) to enable implementation of the quantum algorithm or quantum operation.

[0057] Reference now Figure 6 , shows an example of a computer system or device 600 according to various aspects of the present disclosure. Computer device 600 may, for example, represent a single computing device, a plurality of computing devices, or a distributed computing system. Computer device 600 may be configured as a quantum computer (e.g., a QIP system), a classical computer, or a combination of quantum and classical computing functions. For example, computer device 600 may be used to process information using quantum algorithms based on trapped ion technology, and thus may implement the multi-layer ion traps on a shaped glass or dielectric substrate described herein. Figure 5 A general example of a computer device 600 as a QIP system is shown in QIP system 500 shown in FIG.

[0058] The computer device 600 may include a processor 610 for performing processing functions associated with one or more features described herein. The processor 610 may include a single group or multiple groups of processors or a multi-core processor. In addition, the processor 610 may be implemented as an integrated processing system and / or a distributed processing system. The processor 610 may include one or more central processing units (CPUs) 610a, one or more graphics processing units (GPUs) 610b, one or more quantum processing units (QPUs) 610c, one or more intelligent processing units (IPUs) 610d (e.g., artificial intelligence or AI processors), or a combination of some or all of these types of processors. In one aspect, the processor 610 may refer to a general-purpose processor of the computer device 300, which may also include an additional processor 610 for performing more specific functions (e.g., including functions for controlling the operation of the computer device 600). The processor 610 may include an ion trap, such as a multilayer ion trap on a shaped glass or dielectric substrate as described herein. For example, an ion trap may be used in one or more QPUs 610c.

[0059] In one example, the computer device 600 may include a memory 620 for storing instructions executable by the processor 610 for performing the functions described herein. In one embodiment, for example, the memory 620 may correspond to a computer-readable storage medium storing code or instructions for performing one or more functions or operations described herein. As with the processor 610, the memory 620 may refer to a general memory of the computer device 600, which may also include additional memory 620 for storing instructions and / or data for more specific functions, such as instructions and / or data for individual beam control.

[0060] In addition, the computer device 600 may include a communication component 630 for establishing and maintaining communications with one or more parties using the hardware, software, and services described herein. The communication component 630 may host communications between components on the computer device 600, as well as communications between the computer device 600 and external devices (such as devices located on a communication network and / or devices connected serially or locally to the computer device 600). For example, the communication component 630 may include one or more buses, and may also include a transmit chain component and a receive chain component associated with a transmitter and a receiver, respectively, operable to interface with external devices.

[0061] In addition, computer device 600 may include data storage 640, which may be any suitable combination of hardware and / or software that provides mass storage of information, databases, and programs employed in conjunction with the embodiments described herein. For example, data storage 640 may be a data repository for operating system 660 (e.g., a classical OS or a quantum OS). In one embodiment, data storage 640 may include memory 620.

[0062] Computer device 600 may also include user interface component 650, which is operable to receive input from the user of computer device 600, and is also operable to generate output for presenting to the user or providing to different systems (directly or indirectly). User interface component 650 may include one or more input devices, including but not limited to keyboard, numeric keypad, mouse, touch-sensitive display, digitizer, navigation key, function key, microphone, voice recognition component, any other mechanism or any combination thereof that can receive input from the user. In addition, user interface component 650 may include one or more output devices, including but not limited to display, loudspeaker, tactile feedback mechanism, printer, any other mechanism or any combination thereof that can present output to the user.

[0063] In one implementation, the user interface component 650 may send and / or receive messages corresponding to the operation of the operating system 660. In addition, the processor 610 may execute the operating system 660 and / or applications or programs, and the memory 620 or data storage 640 may store them.

[0064] When the computer device 600 is implemented as part of a cloud-based infrastructure solution, the user interface component 650 may be used to allow a user of the cloud-based infrastructure solution to interact with the computer device 600 remotely.

[0065] One aspect of the present disclosure describes a QIP system (e.g., QIP system 500) that includes an ion trap having a substrate made of a glass material or a dielectric material, and a multilayer stack disposed on the substrate and including at least one metal layer for wiring, at least one dielectric layer, and at least one metal layer for a top electrode, wherein the substrate and the multilayer stack are shaped to form a hole extending through the substrate and through the multilayer stack. The QIP system also includes a source configured to provide atomic species from the back side of the ion trap, the atomic species passing through the substrate of the ion trap and the hole in the multilayer stack to reach the top surface of the ion trap.

[0066] One aspect of the present disclosure describes an ion trap having a substrate made of a glass material or a dielectric material; and a multilayer stack, which is arranged on the substrate and includes at least one metal layer for wiring, at least one dielectric layer and at least one metal layer for a top electrode, and the substrate and the multilayer stack are formed to form a hole extending through the substrate and through the multilayer stack.

[0067] The above description of the present disclosure is provided to enable those skilled in the art to implement or use the present disclosure. It will be apparent to those skilled in the art that various modifications to the present disclosure will be apparent, and the common principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. In addition, although the elements of the various aspects described may be described or claimed in the singular, plural forms may be considered unless expressly stated to be limited to the singular. In addition, unless otherwise stated, all or a portion of any aspect may be used together with all or a portion of any other aspect. Therefore, the present disclosure is not limited to the examples and designs described herein, but should conform to the widest scope of the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a well, comprising: Processing the back side of the substrate for subsequent processing; After processing the back side of the substrate, building a multilayer stack on the top side of the substrate, the multilayer stack comprising at least one metal layer for wiring and at least one metal layer for a top electrode; as well as After building the multilayer stack on the top surface of the substrate, the substrate is shaped by processing the back side of the substrate. 2 . The method according to claim 1 , wherein the substrate is made of a glass material or a dielectric material. The method of claim 1 , wherein the substrate is made of fused silica.

4. The method of claim 1, wherein processing the back side of the substrate comprises applying at least one laser writing step to process the back side of the substrate for selective etching. 5 . The method of claim 1 , wherein processing the back side of the substrate comprises locally shaping the substrate by removing a portion of the substrate from the back side of the substrate.

6. The method of claim 5, wherein removing a portion of the substrate comprises applying one or more laser writing steps and one or more etching steps.

7. The method of claim 5, wherein removing a portion of the substrate leaves a meniscus adjacent a top surface of the substrate. The method of claim 7 , further comprising removing the meniscus.

9. The method according to claim 8, wherein: constructing the multilayer stack includes providing a protective layer on the multilayer stack, and After disposing the protective layer on the multilayer stack, the meniscus is removed.

10. The method of claim 1, wherein constructing the multi-layer stack comprises: Disposing a first metallization on the top surface of the substrate, providing a dielectric layer on the first metallization, and providing a second metallization on the dielectric layer, The first metallization is a part of the at least one metal layer for wiring, and the second metallization is a part of the at least one metal layer for a top electrode.

11. The method of claim 10, wherein providing the dielectric layer comprises forming a via in the dielectric layer to enable connection between the first metallization and the second metallization. 12 . The method of claim 10 , wherein providing the first metallization comprises patterning the first metallization to provide the wiring.

13. The method of claim 10, wherein providing the second metallization comprises patterning the second metallization to provide the top electrode.

14. The method of claim 10, wherein providing the first metallization, providing the second metallization, or both comprises an electroplating process.

15. The method of claim 1, wherein: constructing the multilayer stack includes providing a protective layer on the multilayer stack; and Shaping the substrate by processing the back side of the substrate includes removing a portion of the substrate from the back side of the substrate to form a hole through the thickness of the substrate. 16 . The method of claim 15 , further comprising shaping the multilayer stack by removing a portion of the multilayer stack such that the hole through the substrate extends through the multilayer stack.

17. The method of claim 16, wherein the multilayer stack comprises a dielectric layer having a plurality of dams, and the holes extending through the multilayer stack extend between dams in the dielectric layer. The method of claim 16 , further comprising removing the protective layer.

19. An ion trap, comprising: A substrate made of a glass material or a dielectric material; as well as a multilayer stack disposed on the substrate and comprising at least one metal layer for wiring, at least one dielectric layer and at least one metal layer for a top electrode, Wherein the substrate and the multi-layer stack are shaped to form a hole extending through the substrate and through the multi-layer stack.

20. A quantum information processing system, comprising: An ion trap, the ion trap comprising: a substrate made of a glass material or a dielectric material, and a multilayer stack disposed on the substrate and comprising at least one metal layer for wiring, at least one dielectric layer and at least one metal layer for a top electrode, wherein the substrate and the multi-layer stack are shaped to form a hole extending through the substrate and through the multi-layer stack; and A source is configured to provide atomic species from a back side of the ion trap, the atomic species passing through holes in a substrate of the ion trap and a multilayer stack to a top surface of the ion trap.

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