Test equipment, test system, test method and test device

Abstract

The invention discloses test equipment, a test system, a test method and a test device.The test equipment provided by the invention is internally provided with an FPGA chip capable of controlling a target power supply for supplying power to a to-be-tested MCU, and in practical application, different test logic programs can be configured in the FPGA chip according to practical requirements, so that the test efficiency is improved; according to the technical scheme, the FPGA chip in the test equipment can generate the high-frequency clock signal, so that the time accuracy during voltage burr fault injection of the to-be-tested MCU can be ensured, and the test effect of the to-be-tested MCU can be further ensured.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a testing device, a testing system, a testing method and a testing apparatus. Background Art

[0002] At present, personal consumer electronic products have developed rapidly, enabling them to provide users with many functions such as artificial intelligence, data analysis, online shopping, personal information protection, etc., providing great convenience for users' daily lives.

[0003] Most personal consumer electronic products are equipped with microcontroller units (MCU) chips, which can realize various functions of personal consumer electronic products. However, these MCU chips may have certain loopholes in design and manufacturing process. If these loopholes cannot be detected in time through effective means, it will not only affect users when using personal consumer electronic products, but also may leak users' personal privacy data, making users face the risk of personal information leakage.

[0004] Therefore, how to effectively detect the vulnerabilities in MCU chips is a technical problem that needs to be solved urgently. Summary of the invention

[0005] This specification implements a test device, a test system, a test method and a test apparatus to partially solve the problem that the prior art cannot effectively test whether a microcontroller unit MCU has a vulnerability.

[0006] The embodiments of this specification adopt the following technical solutions:

[0007] The present invention provides a test device, wherein the test device is provided with a field programmable gate array (FPGA) chip and a power supply:

[0008] The power supply is used to supply power to the test equipment;

[0009] The FPGA chip is used to receive a test instruction, generate a control signal according to the test instruction, and control a target power supply that supplies power to a microcontroller unit MCU to be tested to generate a voltage glitch through the control signal, so as to test the MCU to be tested.

[0010] Furthermore, in some implementations, the test device is also provided with a programmable power supply, and the programmable power supply is used to supply power to the MCU to be tested.

[0011] Furthermore, in some implementations, the FPGA chip is used to control the programmable power supply to generate voltage glitches through the control signal.

[0012] Furthermore, in some implementations, the test device is also provided with an MCU interface;

[0013] The FPGA chip is used to send a target signal to the MCU under test through the MCU interface, and the target signal includes: at least one of a restart signal for restarting the MCU under test and a reset signal for resetting the MCU under test.

[0014] Furthermore, in some implementations, the FPGA chip is used to generate a control signal through the MCU interface, so as to control the target power supply to generate voltage glitches through the control signal.

[0015] Furthermore, in some implementations, the test device is also provided with a transmission interface;

[0016] The FPGA chip is used to receive a test instruction sent by a preset host computer through the transmission interface.

[0017] Furthermore, in some embodiments, the test device is further provided with a data transmission unit;

[0018] The FPGA chip is used to obtain response data generated by the MCU under test under the influence of the voltage glitch generated on the target power supply from the MCU under test through the data transmission unit, and send the response data to the host computer through the data transmission unit.

[0019] Furthermore, in some embodiments, the test device is also provided with a storage unit;

[0020] The storage unit is used to store at least part of the response data when the data amount of the response data exceeds a set data amount;

[0021] The FPGA chip is used to read the data stored in the storage unit and send the read data to the host computer through the transmission interface.

[0022] The embodiment of this specification provides a test system, including: a host computer, a test device and a microcontroller unit MCU to be tested, wherein the test device is provided with a field programmable gate array FPGA chip, a power supply and a transmission interface, and the power supply is used to power the test device;

[0023] The host computer is used to send a test instruction to the FPGA chip in the test device through the transmission interface;

[0024] The test device is used to receive the test instruction, generate a control signal through the FPGA chip based on the test instruction, and control the target power supply that supplies power to the microcontroller unit MCU under test to generate voltage glitches through the control signal, so as to test the MCU under test.

[0025] Furthermore, in some embodiments, the test device is further provided with a data transmission unit;

[0026] The test device is used to obtain response data generated by the MCU under test under the influence of the voltage glitch generated by the target power supply from the MCU under test through the data transmission unit, and send the response data to the host computer through the FPGA chip through the data transmission unit.

[0027] Furthermore, in some embodiments, the test device is also provided with a storage unit;

[0028] The storage unit is used to store at least part of the response data when the data amount of the response data exceeds a set data amount;

[0029] The FPGA chip is used to read the data stored in the storage unit through the FPGA chip, and send the read data to the host computer through the transmission interface.

[0030] Further, in some implementations, the host computer is used to send a pre-saved test logic program to the test device through the transmission interface before sending the test instruction;

[0031] The test device stores the test logic program in the FPGA chip so that when receiving the test instruction, the test task for the MCU to be tested is executed through the test logic program.

[0032] The present specification provides a testing method, which is applied to a field programmable gate array (FPGA) chip provided in a testing device, and includes:

[0033] Receive test instructions;

[0034] Generate a control signal according to the test instruction;

[0035] The control signal is used to control a target power supply that supplies power to a microcontroller unit MCU to be tested to generate a voltage glitch, so as to test the MCU to be tested.

[0036] The present specification provides a testing device, which is arranged in a testing device and includes:

[0037] A receiving module, used for receiving a test instruction;

[0038] A generating module, used for generating a control signal according to the test instruction;

[0039] The control module is used to control the target power supply that supplies power to the microcontroller unit MCU to be tested to generate voltage glitches through the control signal, so as to test the MCU to be tested.

[0040] An embodiment of the present specification provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned test method is implemented.

[0041] At least one of the above technical solutions adopted in this specification can achieve the following beneficial effects:

[0042] In the test device provided in the embodiment of the present specification, a field programmable gate array FPGA chip and a power supply are provided in the test device. The power supply is used to power the test device, and the FPGA chip can generate a corresponding control signal according to the test instruction after receiving the test instruction, and through the control signal, control the target power supply that supplies power to the microcontroller unit MCU to generate voltage glitches, so as to test the MCU to be tested.

[0043] It can be seen from the above-mentioned test equipment that the test equipment provided in this specification is provided with an FPGA chip that can control the target power supply to the MCU under test. In practical applications, different test logic programs can be configured in the FPGA chip according to actual needs to achieve the needs of flexible testing of different types of MCUs under test. Moreover, a high-frequency clock signal can be generated by the FPGA chip in the test equipment, thereby ensuring the time accuracy when injecting voltage glitch faults into the MCU under test, so as to further ensure the test effect of the MCU under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of a test device provided for this specification;

[0045] Figure 2 A schematic diagram of a test device with an MCU interface in this specification;

[0046] Figure 3 A schematic diagram of a test device provided with user buttons in this specification;

[0047] Figure 4 A schematic diagram of a test device provided with a transmission interface provided in this specification;

[0048] Figure 5A schematic diagram of a test device provided with a data transmission unit for this specification;

[0049] Figure 6 A schematic diagram of a test device provided with a storage unit for the purpose of this specification;

[0050] Figure 7 A schematic diagram of a test device provided with a clock function device for this specification;

[0051] Figure 8 A flow chart of a test method provided in this specification;

[0052] Fig. 9 A schematic diagram of a test device provided in this specification. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of them. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0054] At present, in order to prevent the adverse effects caused by the vulnerabilities in the microcontroller unit (MCU) chips in personal consumer electronic products, it is usually necessary to test the MCU chips in personal consumer electronic products, and then repair the vulnerabilities in the MCU chips based on the test results. The specific testing method is usually voltage glitch fault injection, which is to observe the behavioral response of the device under test by deliberately introducing a short voltage fluctuation (i.e. "glitch") on the power line of the device under test.

[0055] Among them, voltage glitch refers to a sudden and short-term abnormality in a signal, which may be a spike or a dip. In the case of voltage glitch, this usually means a momentary increase or decrease in the power supply voltage, which can last from nanoseconds to microseconds.

[0056] Once the device under test is affected by voltage glitches, some abnormal conditions may occur. For example, the MCU under test may be affected by voltage glitches, which may make the encrypted firmware or code stored in the MCU under test readable or accessible. For another example, if the MCU under test stores the key required for encrypting data, the MCU under test may be affected by voltage glitches, which may cause part or all of the stored key to be leaked. For another example, the MCU under test may be affected by voltage glitches, which may cause errors in the execution of key calculations.

[0057] Therefore, by injecting voltage glitch faults, we can test whether the MCU under test will have abnormal conditions under the influence of voltage glitches, and then test whether the MCU under test has vulnerabilities. Once the vulnerabilities are determined, we can repair the vulnerabilities of the MCU under test according to the characteristics of each vulnerability, so that the MCU under test can still maintain security and reliability under the influence of voltage glitches. Taking the abnormal state in the above example as an example, by repairing the vulnerabilities, we expect that the MCU under test will not leak the keys required for encrypted data, the encrypted firmware or code will still be unreadable or inaccessible, and no errors will occur during the execution of key calculations, etc. under the influence of voltage glitches.

[0058] However, the current voltage glitch fault injection method has many problems. For example, when using an Atmel microcontroller to implement voltage glitch fault injection, the core frequency of the Atmel microcontroller is too low to achieve accurate delay, and thus the time accuracy of the voltage glitch fault injection cannot be guaranteed, thereby affecting the final test effect. For another example, when injecting voltage glitch faults into the MCU to be tested, the current method does not have the characteristics of high sampling rate and high resolution, so that when collecting the voltage waveform, it is necessary to use equipment such as an oscilloscope to determine the specific voltage glitch fault injection point. The entire fault injection process is cumbersome and inefficient. Since additional equipment (such as an oscilloscope) is also required, the cost required for the entire fault injection process is also significantly increased.

[0059] To this end, this specification provides a test device, which is provided with an FPGA chip that can control the target power supply to the MCU under test. In practical applications, different test logic programs can be configured in the FPGA chip according to actual needs to achieve the need for flexible testing of different types of MCUs under test. Moreover, a high-frequency clock signal can be generated by the FPGA chip in the test device, thereby ensuring the time accuracy when voltage glitch faults are injected into the MCU under test, so as to further ensure the test effect of the MCU under test.

[0060] Next, a test device provided in this specification will be introduced in detail.

[0061] Figure 1 A schematic diagram of a test device provided for this specification.

[0062] exist Figure 1 The test equipment shown includes a power supply and a Field-Programmable Gate Array (FPGA) chip, wherein the power supply is mainly used to power the test equipment, and the FPGA chip is used to receive test instructions and generate corresponding control signals according to the test instructions, so as to control the target power supply that supplies power to the MCU to be tested to generate voltage glitches through the control signal, so as to test the MCU to be tested.

[0063] In this process, the target power supply used to supply power to the MCU under test may be an external power supply provided outside the test equipment. In this case, a line may be provided between the FPGA chip and the external power supply. The FPGA chip controls the external power supply to generate voltage glitches based on the generated control signal and the line, thereby attempting to induce an abnormal condition in the MCU under test.

[0064] Of course, a target power supply dedicated to the MCU under test can also be provided in the test equipment, and the target power supply can be Figure 1 The programmable power supply shown.

[0065] A programmable power supply is a power supply device that can control its output voltage and current through external signals or commands. The programmable power supply can provide high-precision voltage and current regulation, as well as stable output performance. Therefore, in this specification, the FPGA chip can control the programmable power supply to generate voltage glitches through control signals to achieve testing of the MCU to be tested.

[0066] In addition to the above-mentioned methods, other methods can actually be used to achieve voltage glitches on the target power supply. Specifically, the test device provided in this specification can also be provided with an MCU interface, and the FPGA chip in the test device can output a control signal through the MCU interface to control the target power supply, such as Figure 2 shown.

[0067] Figure 2 Schematic diagram of the test equipment with MCU interface in this manual.

[0068] FPGA chip through Figure 2 The process in which the MCU interface generates a control signal may specifically be that the FPGA chip transmits the parameters used to generate the control signal to the MCU interface, and the MCU interface may generate a corresponding control signal based on the acquired parameters.

[0069] The MCU interface can further transmit the control signal to the target power supply that supplies power to the MCU to be tested, so as to inject a voltage glitch fault into the MCU to be tested. If the target power supply is the programmable power supply mentioned above (except that the programmable power supply this time can be an external power supply set outside the test equipment), after the MCU interface sends the control signal to the programmable power supply, the programmable power supply will be controlled to generate voltage glitches. If the target power supply is an ordinary power supply set outside the test equipment, the control signal generated by the MCU interface can be regarded as a level signal that can cause the target power supply to generate voltage glitches.

[0070] In addition to generating the above control signals, the above MCU interface can also generate target signals for controlling the MCU under test. The target signals mentioned here may be signals such as: a restart signal for restarting the MCU under test, a reset signal for resetting the MCU interface under test, and the like.

[0071] The restart signal mentioned here is used to restore the MCU under test to a known initial state. For example, the internal registers in the MCU under test will be set to default values ​​after restarting. For another example, the clock source of the MCU under test can be switched back to the default setting by restarting to ensure that the MCU under test runs with the correct clock frequency.

[0072] The reset signal is mainly used to reset the state of the MCU under test, for example, to initialize the internal registers in the MCU under test, that is, to reset the internal registers in the MCU under test to the default state or the predefined state, so that the processor in the MCU under test will execute the code from the starting address of the program; for another example, to clear the status flag, that is, to clear all flags in the status register of the MCU under test to zero, to ensure that the processor in the MCU under test is in a known initial state; for another example, to initialize the I / O port of the MCU under test, that is, to reset the I / O port of the MCU under test to the default state or the predefined state.

[0073] The signals listed above can be used in the test process of the MCU under test. For example, after a voltage glitch fault is injected into the MCU under test, the state of the MCU under test can be restored to the initial state through a restart signal, and then the next voltage glitch fault is injected into the MCU under test.

[0074] It should be pointed out that the above only lists two signals with different functions. In actual applications, there may be other signals for controlling the MCU under test, which will not be explained in detail here.

[0075] In this specification, the test instructions received by the FPGA chip can be generated in a variety of ways. For example, a user button can be provided in the test device, and the user button can be used to generate the test instructions, such as Figure 3 shown.

[0076] Figure 3 A schematic diagram of a test device provided in this specification with user buttons.

[0077] exist Figure 3 In the test device shown, when the user touches the user button, the test device can generate a test instruction and transmit the test instruction to the FPGA chip through the internal circuit in the test device. In this case, the test instruction generated by touching the user button can be regarded as a trigger signal for the FPGA chip to perform voltage glitch fault injection, that is, after receiving the test instruction, the FPGA chip can perform voltage glitch fault injection according to the test logic program stored inside the FPGA chip. In the case where multiple test logic programs suitable for different MCUs are stored inside the FPGA chip, different MCUs can still be tested in this way.

[0078] It should be pointed out that in this specification, a plurality of pins are provided on the printed circuit board (PCB) in the test equipment (pins are metal contacts on the PCB that connect components). Therefore, a plurality of buttons can be provided on the PCB in the test equipment according to actual needs. Different buttons can realize different functions. Therefore, the above-mentioned user button is one of the many buttons provided in the PCB of the test equipment, which is used to trigger the FPGA chip to realize voltage glitch fault injection.

[0079] In addition to the above-mentioned method of triggering the FPGA chip to perform voltage glitch fault injection, other methods can also be used to achieve it. Specifically, the test device provided in this specification can also be provided with a transmission interface, which can receive test instructions sent from the host computer, such as Figure 4 shown.

[0080] Figure 4 This is a schematic diagram of a test device provided with a transmission interface in this specification.

[0081] Figure 4The upper computer is also shown in the figure. The upper computer usually refers to a computer system with higher-level control and management functions. It is mainly responsible for monitoring, coordinating and managing the workflow of the entire system, and can perform data processing, analysis, decision-making, and send control instructions to the lower computer (slave device or subsystem). In this specification, the specific form of the upper computer can be various, such as hardware devices such as desktop computers and servers, or software such as clients and applications installed in hardware devices.

[0082] Furthermore, the host computer can generate a test instruction, and send the test instruction to the FPGA chip through the transmission interface to trigger the FPGA chip to perform voltage glitch fault injection. There are many ways for the host computer to trigger the generation of test instructions. For example, when the host computer detects that the user performs a test operation on the MCU to be tested, it can generate a test instruction for the MCU to be tested; for another example, the host computer can first send a detection signal to the test device to detect whether the MCU to be tested has been connected to the test device. When it is determined that the MCU to be tested has been connected to the test device, a test instruction can be generated.

[0083] During the process of voltage glitch fault injection, the MCU under test is affected by the voltage glitch and will generate corresponding response data. The response data mentioned here can be understood as data that can be obtained from the MCU under test, such as the power supply voltage waveform (the power supply voltage waveform can reflect the change of the power supply voltage before and after the voltage glitch is injected, so as to understand the amplitude and duration of the voltage glitch), the output signal of the MCU under test (mainly used to detect whether the MCU under test has abnormal behavior or information leakage after being affected by the voltage glitch), the data read from the storage unit in the MCU under test (mainly used to check the data content stored in non-volatile memory such as Flash or EEPROM, so as to determine whether the data will be modified or erased after the MCU under test is affected by the voltage glitch), etc.

[0084] Therefore, the above response data can be used to analyze whether the MCU under test has vulnerabilities. Therefore, the response data can be sent to the host computer to analyze the vulnerabilities in the MCU under test through the host computer.

[0085] To this end, the test device provided in this specification is also provided with a data transmission unit, which is mainly used to transmit the response data generated by the MCU under test affected by the voltage burr to the host computer via the test device, such as Figure 5 shown.

[0086] Figure 5 Schematic diagram of a test device provided with a data transmission unit for this specification.

[0087] from Figure 5It can be seen that the response data generated by the voltage glitch of the MCU under test is sent to the FPGA chip in the test equipment via the data transmission unit, and then sent to the host computer through the transmission interface by the FPGA chip.

[0088] The data transmission unit mentioned in this specification may be an analog-to-digital converter (ADC), which is a hardware device that can convert continuously changing analog signals into discrete digital signals. Of course, the data transmission unit may also be in other forms, and the main function is to obtain response data from the MCU to be tested and send it to the FPGA chip.

[0089] In addition, the specific forms of the transmission interface mentioned above can also be various, for example, the transmission interface can be an interface using the Universal Serial Bus (USB) 2.0 protocol, an interface using the USB 3.0 protocol, etc. Among them, the interface using the USB 3.0 protocol can be preferably used, so that the host computer can quickly send test instructions to the FPGA chip, and can quickly send the response data obtained by the FPGA chip to the host computer for analysis and processing, thereby further improving the test efficiency for the MCU to be tested.

[0090] It should be pointed out that in actual applications, the MCU under test may generate a large amount of response data under the influence of voltage glitches. The so-called large amount of data can be understood as exceeding the maximum amount of data that the FPGA chip can send when completing a data transmission. In this case, the test equipment needs to store part of the response data first, and then perform data transmission multiple times to send all the response data generated by the MCU under test under the influence of voltage glitches to the host computer, such as Figure 6 shown.

[0091] Figure 6 Schematic diagram of a test device provided with a storage unit for the purpose of this specification.

[0092] Figure 6 The test device shown in the figure is provided with a storage unit, which can store at least part of the response data when the amount of response data exceeds the set amount of data. Then, when the FPGA chip sends the response data, it can read the data from the storage unit and store the read data through Figure 6 The transmission interface in is sent to the host computer.

[0093] The storage unit may be in various specific forms. For example, the storage unit may be a memory such as DDR3 or DDR4, and the specific form may be determined according to actual needs.

[0094] It can be seen from the above-mentioned test equipment that the test equipment provided in this specification is equipped with an FPGA chip that can control the target power supply to the MCU under test. In practical applications, different test logic programs can be configured in the FPGA chip according to actual needs to achieve the needs of flexible testing of different types of MCUs under test.

[0095] Moreover, the FPGA chip in the test equipment (in conjunction with the internal phase-locked loop in the FPGA chip) can generate a high-frequency clock signal (such as a clock signal with a maximum frequency of 400M and a minimum clock period of 2.5ns), thereby ensuring the timing accuracy when injecting voltage glitch faults into the MCU under test, thereby further ensuring the test effect of the MCU under test.

[0096] Furthermore, through the above-mentioned data transmission unit, the sampling rate and resolution of the data can be improved, so that the fault injection point of the voltage glitch can be quickly determined through the collected data. For example, when the data transmission unit is an ADC, it can achieve a sampling rate of 500M to collect data and obtain data with a resolution of 12 bits, thereby quickly determining the fault injection point.

[0097] Therefore, in addition to transmitting the response data generated when the MCU under test is affected by the voltage glitch, the data transmission unit can also collect the power supply voltage signal of the MCU under test before the MCU under test is affected by the voltage glitch to determine the specific voltage glitch fault injection point.

[0098] It should be pointed out that the internal phase-locked loop mentioned above is actually an important circuit for frequency synthesis and clock management. The internal phase-locked loop can achieve functions such as increasing the frequency of the clock signal (actually it can achieve the effect of signal amplification), clock source switching (it can smoothly switch between different clock sources, such as switching from a low-frequency RC oscillator to a high-frequency crystal oscillator), and frequency stability (it can maintain the stability of the clock signal frequency. Even if the frequency of the external clock source fluctuates, the internal phase-locked loop can keep the output frequency consistent through feedback control). Therefore, it can be seen from here that the internal phase-locked loop can achieve the effect of clock signal amplification, so it can make the FPGA chip generate a high-frequency clock signal.

[0099] In addition, in this specification, the test equipment may also be provided with a device that implements a clock function, such as Figure 7 shown.

[0100] Figure 7 Schematic diagram of the test equipment provided for this specification with a clock function device.

[0101] Figure 7The clock shown is mainly used to implement functions such as synchronous operation (the clock signal provides the necessary timing reference for all synchronous logic circuits (such as triggers and registers) in the FPGA chip. These circuits perform status updates on the rising or falling edge of the clock to ensure the correct transfer and storage of data in the circuit), timing control (the clock signal determines the rate of data processing inside the FPGA chip. All sequential logic operations, including data reading, processing and writing, need to be completed within the clock cycle), and clock distribution network (there is a special clock distribution network inside the FPGA chip to efficiently and evenly distribute the clock signal to each required logic unit to ensure signal integrity and reduce clock skew). It can be understood as mainly maintaining the normal operation of the FPGA chip.

[0102] In addition to the test equipment shown in one or more of the above-mentioned embodiments, this specification also provides a test system, which includes a host computer, a test equipment and an MCU to be tested. The test equipment may be provided with an FPGA chip, a power supply and a transmission interface, and the power supply is used to power the test equipment.

[0103] The host computer in the test system can send test instructions to the FPGA chip in the test device through the transmission interface in the test device, and the FPGA chip in the test device can generate corresponding control signals based on the received test instructions, and control the target power supply to the MCU under test to generate voltage glitches through the control signal, so as to test the MCU under test. The basic process of implementing voltage glitch fault injection through the test system has been introduced in detail above, so it will not be repeated here.

[0104] Since there are various models and types of MCUs in actual applications, the voltage glitches that need to be generated when voltage glitch faults are injected into different MCUs are also different. Therefore, in this manual, different test logic programs can be burned in the FPGA chip according to actual needs, and the burned test logic program needs to be compatible with the MCU to be tested.

[0105] What needs to be emphasized is that the test logic program stored in the FPGA chip in the test equipment can be burned into the FPGA chip by the host computer before executing the test task for the MCU to be tested. In other words, the test equipment does not need to store the test logic program when it does not execute the test task, but before executing the test task, the test logic program required to execute the test task is stored in the FPGA chip by the host computer.

[0106] Therefore, the host computer can store test logic programs applicable to a variety of different MCUs, and these test logic programs can be configured by users on the host computer according to actual needs. In this way, the management of the test logic program in the host computer is actually realized, and there is no need to program the FPGA chip specifically. After the host computer is connected to the test equipment, it only needs simple operations to synchronize the required test logic program to the FPGA chip to perform voltage glitch fault injection.

[0107] In addition, as mentioned above, the PCB board in the test equipment is provided with multiple pins for executing function expansion, which enables the test equipment to connect some external trigger sources, such as oscilloscopes, logic analyzers, digital signal generators, etc. Figure 7 These devices can collect data from the MCU under test, and then transmit the collected data to Figure 7 The MCU interface in the chip is sent to the FPGA chip to perform operations such as determining the voltage glitch fault injection point.

[0108] In this specification, in order to further improve the test efficiency, when executing the test task for testing whether the data stored in the MCU to be tested (the stored data may be encrypted private data or firmware, where firmware refers to the program stored in the memory of the MCU to be tested) may be leaked due to the existing vulnerabilities, the host computer may save the space information of the storage space occupied by the data stored in the MCU to be tested, and this space information may reflect the size and storage location of the storage space occupied by the data stored in the MCU to be tested, such as, when the data stored in the MCU to be tested is firmware, the space information here may be the firmware length. And this space information may be based on the device information of the MCU to be tested, and pre-entered in the host computer.

[0109] On this basis, the host computer can send the spatial information to the FPGA chip through the above transmission interface, and the FPGA chip can perform voltage glitch fault injection for the data stored in the MCU under test based on the spatial information. This can avoid the FPGA chip from performing voltage fault injection on the empty sectors of the memory in the MCU under test, thereby effectively improving the test efficiency for the MCU under test.

[0110] In addition, it should be pointed out that since the FPGA chip in the test equipment itself has a high security, the data stored in the FPGA chip is unlikely to be leaked. Therefore, the test equipment or test system provided in this specification can ensure data security when executing test tasks for the MCU to be tested.

[0111] This specification also provides a test method, which is mainly applied to the FPGA chip in the above test equipment, such as Figure 8 shown.

[0112] Figure 8 A flow chart of a test method provided in this specification specifically includes the following steps:

[0113] S800: Receive a test instruction.

[0114] S802: Generate a control signal according to the test instruction.

[0115] S804: Controlling a target power supply that supplies power to a microcontroller unit MCU under test to generate a voltage glitch through the control signal, so as to test the MCU under test.

[0116] The above method can be implemented by a program deployed in an FPGA chip. Since the process of the test equipment performing voltage glitch fault injection through the FPGA chip has been described in detail in the above content, it will not be repeated in detail again.

[0117] The above is a test method provided in one or more embodiments of this specification. Based on the same idea, this specification also provides a corresponding test device, such as Fig. 9 shown.

[0118] Fig. 9 A schematic diagram of a test device provided for this specification includes:

[0119] Receiving module 901, used for receiving a test instruction;

[0120] A generating module 902, configured to generate a control signal according to the test instruction;

[0121] The control module 903 is used to control the target power supply that supplies power to the microcontroller unit MCU under test to generate voltage glitches through the control signal, so as to test the MCU under test.

[0122] The above device embodiments correspond to the method embodiments. For specific descriptions, please refer to the description of the method embodiments, which will not be repeated here. The device embodiments are obtained based on the corresponding method embodiments and have the same technical effects as the corresponding method embodiments. For specific descriptions, please refer to the corresponding method embodiments.

[0123] The present specification also provides a computer storage medium, which can store multiple instructions, and the instructions are suitable for being loaded and executed by a processor as described above. Figure 8 The method of the embodiment shown in the figure can be specifically executed by referring to Figure 8The specific description of the illustrated embodiment will not be repeated here.

[0124] The present specification also provides a computer program product, which stores at least one instruction, and the at least one instruction is loaded and executed by the processor as described above. Figure 8 The method of the embodiment shown in the figure can be specifically executed by referring to Figure 8 The specific description of the illustrated embodiment will not be repeated here.

[0125] Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc., that is to say, the executor of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0126] In the 1990s, improvements to a technology could be clearly distinguished as hardware improvements (for example, improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the method flow). However, with the development of technology, many improvements to the method flow today can be regarded as direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement in a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and produce a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0127] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0128] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0129] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0130] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0131] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0132] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0133] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0134] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0135] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0136] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0137] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0138] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0139] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0140] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0141] The above description is only an embodiment of the present specification and is not intended to limit the present specification. For those skilled in the art, the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of the claims of the present specification.

Claims

1. A test device, wherein the test device is provided with a field programmable gate array (FPGA) chip and a power supply: The power supply is used to supply power to the test equipment; The FPGA chip is used to receive a test instruction, generate a control signal according to the test instruction, and control a target power supply that supplies power to a microcontroller unit MCU to be tested to generate a voltage glitch through the control signal, so as to test the MCU to be tested.

2. The test device as claimed in claim 1, further comprising a programmable power supply, wherein the programmable power supply is used to supply power to the MCU to be tested.

3. The test equipment as described in claim 2, wherein the FPGA chip is used to control the programmable power supply to generate voltage glitches through the control signal.

4. The test device according to claim 1, further comprising an MCU interface; The FPGA chip is used to send a target signal to the MCU to be tested through the MCU interface, and the target signal includes: At least one of a restart signal for restarting the MCU under test and a reset signal for resetting the MCU under test.

5. The test equipment as described in claim 4, wherein the FPGA chip is used to generate a control signal through the MCU interface, so as to control the target power supply to generate voltage glitches through the control signal.

6. The test device according to claim 1, further comprising a transmission interface; The FPGA chip is used to receive a test instruction sent by a preset host computer through the transmission interface.

7. The test device according to claim 6, further comprising a data transmission unit; The FPGA chip is used to obtain response data generated by the MCU under test under the influence of the voltage glitch generated on the target power supply from the MCU under test through the data transmission unit, and send the response data to the host computer through the data transmission unit.

8. The test device according to claim 7, further comprising a storage unit; The storage unit is used to store at least part of the response data when the data amount of the response data exceeds a set data amount; The FPGA chip is used to read the data stored in the storage unit and send the read data to the host computer through the transmission interface.

9. A testing system comprising: A host computer, a test device and a microcontroller unit MCU to be tested, wherein the test device is provided with a field programmable gate array FPGA chip, a power supply and a transmission interface, and the power supply is used to power the test device; The host computer is used to send a test instruction to the FPGA chip in the test device through the transmission interface; The test device is used to receive the test instruction, generate a control signal through the FPGA chip based on the test instruction, and control the target power supply that supplies power to the microcontroller unit MCU under test to generate voltage glitches through the control signal, so as to test the MCU under test.

10. The test system according to claim 9, wherein the test device is further provided with a data transmission unit; The test device is used to obtain response data generated by the MCU under test under the influence of the voltage glitch generated by the target power supply from the MCU under test through the data transmission unit, and send the response data to the host computer through the FPGA chip through the data transmission unit.

11. The test system according to claim 10, wherein the test device is further provided with a storage unit; The storage unit is used to store at least part of the response data when the data amount of the response data exceeds a set data amount; The FPGA chip is used to read the data stored in the storage unit through the FPGA chip, and send the read data to the host computer through the transmission interface.

12. The test system according to claim 9, wherein the host computer is used to send the pre-saved test logic program to the test device through the transmission interface before sending the test instruction; The test device stores the test logic program in the FPGA chip so that when receiving the test instruction, the test task for the MCU to be tested is executed through the test logic program.

13. A testing method, the method being applied to a field programmable gate array (FPGA) chip provided in a testing device, comprising: Receive test instructions; Generate a control signal according to the test instruction; The control signal is used to control a target power supply that supplies power to a microcontroller unit MCU to be tested to generate a voltage glitch, so as to test the MCU to be tested.

14. A testing device, the device being arranged in a testing device, comprising: A receiving module, used for receiving a test instruction; A generating module, used for generating a control signal according to the test instruction; The control module is used to control the target power supply that supplies power to the microcontroller unit MCU to be tested to generate voltage glitches through the control signal, so as to test the MCU to be tested.

15. A computer-readable storage medium storing a computer program, wherein the computer program implements the method of claim 13 when executed by a processor.

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