Data processing method and device of magnetic random access memory, chip and electronic equipment
By dividing the data into multiple sets and writing and reading in batches, the problem of inability to read when MRAM writes data is solved, the data reading efficiency is improved, and the total operation time is reduced.
Patent Information
- Application Number
- CN202411274783.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2024-12-27
AI Technical Summary
Existing magnetic random memory (MRAM) cannot read simultaneously when writing data, resulting in a serious impact on the efficiency of reading data.
By dividing the data to be written into multiple data sets and reading the data in the magnetic random memory immediately after writing each data set, the current direction of the magnetic tunnel collection is controlled to realize data writing, and it is carried out in batches Write and read operations improve the efficiency of data reading.
It effectively improves the data reading efficiency of MRAM, reduces the impact on read operations when writing data, and reduces the total operation time.
Smart Images
Figure CN119207504A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of storage technology, and in particular to a data processing method, device, chip and electronic device for a magnetic random access memory. Background Art
[0002] Non-volatile magnetic random access memory (MRAM) has the characteristics of fast data transmission speed, non-volatility, high integration, and stable and reliable performance in extreme temperature ranges. Therefore, MRAM is often used as embedded on-chip memory, and applications run directly on MRAM. In this scenario, data reading and writing operations will be quite frequent; because MRAM does not support writing and reading data at the same time, when writing data to MRAM, the efficiency of MRAM reading data will be seriously affected. Summary of the invention
[0003] The embodiments of the present application provide a data processing method, device, chip and electronic device for a magnetic random access memory, which can improve the efficiency of MRAM in reading data.
[0004] The technical solution of the embodiment of the present application is implemented as follows:
[0005] In a first aspect, an embodiment of the present application provides a data processing method for a magnetic random access memory, the method comprising: obtaining data to be written and a write address of the data to be written in the magnetic random access memory;
[0006] Comparing the original data in the write address with the data to be written to obtain a comparison result;
[0007] Determine the bit unit of the value to be changed based on the comparison result;
[0008] Dividing the data to be written into a plurality of first data sets to be written and a plurality of second data sets to be written;
[0009] Controlling the current direction of the first magnetic tunnel junction set corresponding to the bit unit to implement writing of at least one data in the first data set to be written;
[0010] Reading data in the magnetic random access memory;
[0011] The current direction of the second magnetic tunnel junction set corresponding to the bit cell is controlled to achieve writing of data in at least one of the second data sets to be written.
[0012] In some optional embodiments, controlling the current direction of the first magnetic tunnel junction set corresponding to the bit unit to implement writing of at least one data in the first to-be-written data set includes:
[0013] Controlling the current direction of a first magnetic tunnel junction set in the first magnetic tunnel junction sets to be a first direction, so as to implement writing of data in a first data set to be written in the first data set to be written;
[0014] After a first time interval, controlling the current direction of a second magnetic tunnel junction set in the first magnetic tunnel junction set to be a first current direction, so as to implement writing of data in the second data set to be written in the first data set to be written;
[0015] And so on, until the current direction of the last magnetic tunnel junction set in the first magnetic tunnel junction set is controlled to be the first current direction, so as to implement the writing of data in the last data set to be written in the first data set to be written;
[0016] Wherein, the number of magnetic tunnel junctions included in each of the magnetic tunnel junction sets is less than a first number threshold.
[0017] In some optional embodiments, the method further comprises:
[0018] Within any one or more of the first time intervals, data in the magnetic random access memory is read.
[0019] In some optional embodiments, controlling the current direction of the second magnetic tunnel junction set corresponding to the bit unit to implement writing of at least one data in the second to-be-written data set includes:
[0020] Controlling the current direction of the first magnetic tunnel junction set in the second magnetic tunnel junction set to be a second direction, so as to implement writing of data in the first data set to be written in the second data set to be written;
[0021] After a second time interval, controlling the current direction of a second magnetic tunnel junction set in the second magnetic tunnel junction set to be a second current direction, so as to implement writing of data in the second data set to be written in the second data set to be written;
[0022] And so on, until the current direction of the last magnetic tunnel junction set in the second magnetic tunnel junction set is controlled to be the second current direction, so as to achieve the writing of data in the last data set to be written in the second data set to be written;
[0023] Wherein, the number of magnetic tunnel junctions included in each of the second magnetic tunnel junction sets is less than a second number threshold.
[0024] In some optional embodiments, the method further comprises:
[0025] Within any one or more of the second time intervals, data in the magnetic random access memory is read.
[0026] In some optional embodiments, the first time interval is the same as the second time interval;
[0027] Alternatively, the first time interval is different from the second time interval.
[0028] In a second aspect, an embodiment of the present application provides a data processing device of a magnetic random access memory, the device comprising:
[0029] An acquisition module, used for acquiring data to be written and a write address of the data to be written in the magnetic random access memory;
[0030] A comparison module, used for comparing the original data in the write address with the data to be written to obtain a comparison result;
[0031] A determination module, used for determining a bit address of a value to be changed based on the comparison result;
[0032] A division module, used for dividing the data to be written into multiple data sets to be written;
[0033] a first control module, configured to control a current direction of a first magnetic tunnel junction set corresponding to the bit unit, so as to implement writing of data in at least one of the first data sets to be written;
[0034] A reading module, used for reading data in the magnetic random access memory;
[0035] The second control module is used to control the current direction of the second magnetic tunnel junction set corresponding to the bit unit to achieve the writing of data in at least one of the second data sets to be written.
[0036] In some optional embodiments, the first control module is used to control the current direction of the first magnetic tunnel junction set in the first magnetic tunnel junction set to be a first direction, so as to implement the writing of data in the first data set to be written in the first data set to be written;
[0037] After a first time interval, controlling the current direction of a second magnetic tunnel junction set in the first magnetic tunnel junction set to be a first current direction, so as to implement writing of data in the second data set to be written in the first data set to be written;
[0038] And so on, until the current direction of the last magnetic tunnel junction set in the first magnetic tunnel junction set is controlled to be the first current direction, so as to implement the writing of data in the last data set to be written in the first data set to be written;
[0039] Wherein, the number of magnetic tunnel junctions included in each of the first magnetic tunnel junction sets is less than a first number threshold.
[0040] In some optional embodiments, the reading module is further used to read data in the magnetic random access memory within any one or more of the first time intervals.
[0041] In some optional embodiments, the second control module is used to control the current direction of the first magnetic tunnel junction set in the second magnetic tunnel junction set to be the second direction, so as to implement the writing of data in the first data set to be written in the second data set to be written;
[0042] After a second time interval, controlling the current direction of a second magnetic tunnel junction set in the second magnetic tunnel junction set to be a second current direction, so as to implement writing of data in the second data set to be written in the second data set to be written;
[0043] And so on, until the current direction of the last magnetic tunnel junction set in the second magnetic tunnel junction set is controlled to be the second current direction, so as to achieve the writing of data in the last data set to be written in the second data set to be written;
[0044] Wherein, the number of magnetic tunnel junctions included in each of the second magnetic tunnel junction sets is less than a second number threshold.
[0045] In some optional embodiments, the reading module is further used to read data in the magnetic random access memory within any one or more of the second time intervals.
[0046] In some optional embodiments, the first time interval is the same as the second time interval;
[0047] Alternatively, the first time interval is different from the second time interval.
[0048] In a third aspect, an embodiment of the present application provides a chip, the chip comprising:
[0049] processor, memory, and bus;
[0050] The memory stores executable instructions;
[0051] The processor communicates with the memory via the bus, and when the processor executes the executable instructions stored in the memory, the data processing method of the magnetic random access memory is implemented.
[0052] In a fourth aspect, an embodiment of the present application provides a component on a transportation device, wherein the component includes a chip, and the chip can implement the above-mentioned data processing method of the magnetic random access memory.
[0053] In a fifth aspect, an embodiment of the present application provides an electronic device, which includes a chip, and the chip can implement the above-mentioned magnetic random access memory data processing method.
[0054] The data processing method of the magnetic random access memory provided in the embodiment of the present application includes: obtaining the data to be written and the write address of the data to be written in the magnetic random access memory; comparing the original data in the write address with the data to be written to obtain a comparison result; determining the bit unit of the value to be changed based on the comparison result; dividing the data to be written into multiple first data sets to be written and multiple second data sets to be written; controlling the current direction of the first magnetic tunnel junction set corresponding to the bit unit to achieve the writing of data in at least one of the first data sets to be written; reading the data in the magnetic random access memory; controlling the current direction of the second magnetic tunnel junction set corresponding to the bit unit to achieve the writing of data in at least one of the second data sets to be written. In the embodiment of the present application, when writing data to the magnetic random access memory, the data to be written is divided into multiple data sets, and after writing the data in one data set to the magnetic random access memory, the data is read from the magnetic random access memory; and then, the data in another data set is written to the magnetic random access memory. In this way, by dividing the data to be written into the magnetic random access memory into multiple data sets, the data in one data set is controlled to be written into the magnetic random access memory each time; within the time interval when the data in two data sets are written into the magnetic random access memory, the data in the magnetic random access memory can be read, thereby improving the efficiency of MRAM in reading data. BRIEF DESCRIPTION OF THE DRAWINGS
[0055] Figure 1 It is a processing flow diagram of a data processing method of a magnetic random access memory provided by an embodiment of the present application;
[0056] Figure 2 The present invention provides a method for processing data in a magnetic random access memory.
[0057] Figure 3 This is an optional schematic diagram of reading data from an MRAM provided in an embodiment of the present application;
[0058] Figure 4This is another optional schematic diagram of reading data from an MRAM provided in an embodiment of the present application;
[0059] Figure 5 This is another optional schematic diagram of reading data from an MRAM provided in an embodiment of the present application;
[0060] Figure 6 It is a schematic diagram of the composition structure of a data processing device of a magnetic random access memory provided in an embodiment of the present application;
[0061] Figure 7 It is a schematic diagram of the structure of the chip provided in the embodiment of the present application. DETAILED DESCRIPTION
[0062] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.
[0063] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0064] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.
[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0066] It should be understood that in the various embodiments of the present application, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
[0067] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.
[0068] Magnetic random access memory is a memory that uses the magnetoresistance effect to store data. Unlike traditional semiconductor random access memory (RAM), MRAM uses magnetic tunnel junctions (MTJs) as storage units to record binary data by changing the magnetization direction. By changing the direction of the current flowing through the MTJ of the MRAM bit cell, the tunnel resistance changes, completing the storage of "0" and "1". Before starting the write "0" or write "1" operation, you need to wait for the write "0" or write "1" setup time to change the current direction of the MTJ. After writing "0", you need to wait for the write "0" or write "0" hold time to wait for the write operation to stabilize.
[0069] MRAM has a very high integration and read speed, and is often used as an embedded on-chip memory; MRAM can be placed on the chip or outside the chip. The chip can be a multi-core heterogeneous chip. Multi-core heterogeneous chips can be used in transportation equipment, including but not limited to balance cars, cars, buses, subways, trains, and airplanes.
[0070] In the related art, during the process of writing data into the MRAM, data cannot be read from the MRAM, and the total operation time required to write 128 bits of data into the MRAM at one time is about 30 microseconds, which seriously affects the efficiency of reading data from the MRAM.
[0071] The data processing method of the magnetic random access memory provided in the embodiment of the present application can at least solve the above problems and improve the real-time performance of reading data from the MRAM.
[0072] A processing flow diagram of a data processing method of a magnetic random access memory provided in an embodiment of the present application is as follows: Figure 1 As shown, at least the following steps are included:
[0073] Step S101, obtaining data to be written and a write address of the data to be written in a magnetic random access memory.
[0074] In some embodiments, a central processing unit (CPU) sends a write address and data to be written to the MRAM controller, wherein the data to be written may be 128-bit word write data.
[0075] Step S102: compare the original data in the write address with the data to be written to obtain a comparison result.
[0076] In some embodiments, the MRAM controller reads original data from the write address sent by the CPU; wherein the original data is data already stored in the write address corresponding to the data to be written.
[0077] In a specific implementation, if the original data of a bit cell in the MRAM is "1" and the data to be written to the bit cell is "0", the comparison result between the original data and the data to be written in the bit cell is inconsistent, and the value of the bit cell needs to be changed. If the original data of a bit cell in the MRAM is "1" and the data to be written to the bit cell is "1", the comparison result between the original data and the data to be written in the bit cell is consistent, and the value of the bit cell does not need to be changed.
[0078] Each bit cell in the MRAM corresponds to a magnetic tunnel junction (MTJ).
[0079] Step S103, determining the bit unit of the value to be changed based on the comparison result.
[0080] In some embodiments, the MRAM controller identifies the bit cells whose comparison results are inconsistent as the bit cells whose values are to be changed.
[0081] Step S104: dividing the data to be written into a plurality of first data sets to be written and a plurality of second data sets to be written.
[0082] In some embodiments, the data in the first data set to be written is "0", and the data in the second data set to be written is "1". Alternatively, the data in the first data set to be written is "1", and the data in the second data set to be written is "0".
[0083] In some embodiments, there are multiple first data sets to be written, and the number in each first data set to be written is less than the first number threshold. As an example, if the first number threshold is 9, the number in each first data set to be written is less than 9.
[0084] Step S105 , controlling the current direction of the first magnetic tunnel junction set corresponding to the bit cell to implement writing of at least one data in the first to-be-written data set.
[0085] In some embodiments, the current direction of the first magnetic tunnel junction set in the first magnetic tunnel junction set is controlled to be a first direction to achieve writing of data in the first data set to be written in the first data set to be written; after a first time interval, the current direction of the second magnetic tunnel junction set in the first magnetic tunnel junction set is controlled to be the first current direction to achieve writing of data in the second data set to be written in the first data set to be written; and so on, until the current direction of the last magnetic tunnel junction set in the first magnetic tunnel junction set is controlled to be the first current direction to achieve writing of data in the last data set to be written in the first data set to be written; wherein, the number of magnetic tunnel junctions included in each of the first magnetic tunnel junction sets is less than a first number threshold.
[0086] As an example, there are X first data sets to be written, corresponding to X magnetic tunnel junction sets, and each first data set to be written corresponds to a magnetic tunnel junction set. First, the current direction of the first magnetic tunnel junction set in the X magnetic tunnel junction sets is controlled to be the first direction, so as to achieve the writing of data in the first data set to be written in the X first data sets to be written. After the first time interval, the current direction of the second magnetic tunnel junction set in the X magnetic tunnel junction sets is controlled to be the first direction, so as to achieve the writing of data in the second data set to be written in the X first data sets to be written. After the first time interval, the current direction of the third magnetic tunnel junction set in the X magnetic tunnel junction sets is controlled to be the first direction, so as to achieve the writing of data in the third data set to be written in the X first data sets to be written. And so on, until the current direction of the last magnetic tunnel junction set in the first magnetic tunnel junction set is controlled to be the first current direction, so as to achieve the writing of data in the Xth data set to be written in the X first data sets to be written.
[0087] In an embodiment of the present application, data can be read from the MRAM within a first time interval. The size of the first time interval can be flexibly configured according to the actual application scenario. If the data to be read from the MRAM is small, the first time interval can be set to a smaller value; if the data to be read from the MRAM is large, the first time interval can be set to a larger value. In this way, when the data to be read from the MRAM is small, the data can be quickly read in a smaller first time interval, and the efficiency of writing data to the MRAM is less affected. When the data to be read from the MRAM is large, the data can be read in a larger first time interval, thereby improving the efficiency of reading data from the MRAM.
[0088] In a specific implementation, all data in the multiple first data sets to be written are written into the bit cells corresponding to the first magnetic tunnel junction set. For example, if there are X first data sets to be written, then there are X magnetic tunnel junction sets, and each first data set to be written corresponds to one magnetic tunnel junction set. If the data in the first data set to be written is "0", the direction of the word line current on the MTJ is controlled to be positive (the direction of the current is from inside to outside); at the same time, the current size is controlled so that when the circular magnetic field formed around the wire exceeds the coercive force of the antiferromagnetic layer, "0" is written or recorded on the bit cell.
[0089] Step S106, reading the data in the magnetic random access memory.
[0090] In some embodiments, if all the data in the first set of data to be written in step S105 has been written, the data can be read from the magnetic random access memory. As an example, the data in the magnetic random access memory can be read within a preset third time interval; wherein the third time interval can be flexibly set according to the actual application scenario. The third time interval is the time gap between writing the first set of data to be written and writing the second set of data to be written.
[0091] Step S107 , controlling the current direction of the second magnetic tunnel junction set corresponding to the bit cell to implement writing of at least one data in the second to-be-written data set.
[0092] In some embodiments, the current direction of the first magnetic tunnel junction set in the second magnetic tunnel junction set is controlled to be the second direction to implement the writing of data in the first data set to be written in the second data set to be written; after the second time interval, the current direction of the second magnetic tunnel junction set in the second magnetic tunnel junction set is controlled to be the second current direction to implement the writing of data in the second data set to be written; and so on, until the current direction of the last magnetic tunnel junction set in the second magnetic tunnel junction set is controlled to be the second current direction to implement the writing of data in the last data set to be written in the second data set to be written. Wherein, the number of magnetic tunnel junctions included in each of the second magnetic tunnel junction sets is less than the second number threshold. The number of second data sets to be written is multiple, and the number in each second data set to be written is less than the second number threshold. As an example, if the second number threshold is 8, the number in each first data set to be written is less than 7.
[0093] As an example, there are Y second data sets to be written, corresponding to Y magnetic tunnel junction sets, and each second data set to be written corresponds to a magnetic tunnel junction set. First, the current direction of the first magnetic tunnel junction set in the Y magnetic tunnel junction sets is controlled to be the second direction to achieve the writing of data in the first data set to be written in the Y second data sets to be written. After the second time interval, the current direction of the second magnetic tunnel junction set in the Y magnetic tunnel junction sets is controlled to be the second direction to achieve the writing of data in the second data set to be written in the Y second data sets to be written. After the second time interval, the current direction of the third magnetic tunnel junction set in the Y magnetic tunnel junction sets is controlled to be the second direction to achieve the writing of data in the third data set to be written in the Y second data sets to be written. And so on, until the current direction of the last magnetic tunnel junction set in the second magnetic tunnel junction set is controlled to be the first current direction to achieve the writing of data in the Yth data set to be written in the Y second data sets to be written.
[0094] In an embodiment of the present application, data can be read from the MRAM within a second time interval. The size of the second time interval can be flexibly configured according to the actual application scenario. If the data to be read from the MRAM is small, the second time interval can be set to a smaller value; if the data to be read from the MRAM is large, the second time interval can be set to a larger value. In this way, when the data to be read from the MRAM is small, the data can be quickly read in a smaller second time interval, and the efficiency of writing data to the MRAM is less affected. When the data to be read from the MRAM is large, the data can be read in a larger second time interval, thereby improving the efficiency of reading data from the MRAM.
[0095] In a specific implementation, all data in the plurality of second data sets to be written are written into the bit cells corresponding to the second magnetic tunnel junction set. For example, if there are Y first data sets to be written, then there are Y magnetic tunnel junction sets, and each second data set to be written corresponds to one magnetic tunnel junction set. If the data in the second data set to be written is "1", the direction of the word line current on the MTJ is controlled to be negative (the direction of the current is from outside to inside); at the same time, the current size is controlled so that when the circular magnetic field formed around the wire exceeds the coercive force of the antiferromagnetic layer, "1" is written or recorded on the bit cell.
[0096] In some embodiments, the first time interval is the same as the second time interval; or, the first time interval is different from the second time interval.
[0097] In the embodiment of the present application, data can be written to the MRAM in two times, first writing data "0" to the MRAM, and then writing data "1" to the MRAM after a third time interval. Alternatively, data "1" is written to the MRAM first, and then writing data "0" to the MRAM after a third time interval. When writing data "0" to the MRAM, data "0" can also be written in multiple times; the time interval between each two writing of data "0" is the first time interval. When writing data "1" to the MRAM, data "1" can also be written in multiple times; the time interval between each two writing of data "1" is the second time interval.
[0098] A detailed processing flow diagram of a data processing method of a magnetic random access memory provided in an embodiment of the present application is as follows: Figure 2 As shown, at least the following steps are included:
[0099] Step S201: The CPU sends a write address and data to be written to the MRAM controller.
[0100] The data to be written may be 128-bit word write data.
[0101] Step S202: The MRAM controller compares the original data in the write address with the data to be written to obtain a comparison result.
[0102] In some embodiments, the MRAM controller reads original data from the write address sent by the CPU; wherein the original data is data already stored in the write address corresponding to the data to be written.
[0103] In a specific implementation, if the original data of a bit cell in the MRAM is "1" and the data to be written to the bit cell is "0", the comparison result between the original data and the data to be written in the bit cell is inconsistent, and the value of the bit cell needs to be changed. If the original data of a bit cell in the MRAM is "1" and the data to be written to the bit cell is "1", the comparison result between the original data and the data to be written in the bit cell is consistent, and the value of the bit cell does not need to be changed.
[0104] Among them, each bit cell in the MRAM corresponds to an MTJ.
[0105] Step S203 : The MRAM controller determines the bit unit whose value is to be changed based on the comparison result.
[0106] In some embodiments, the MRAM controller identifies the bit cells whose comparison results are inconsistent as the bit cells whose values are to be changed.
[0107] Step S204, writing data "0" into the MRAM in P times.
[0108] In some embodiments, during the process of writing data "0" to the MRAM from the first time to the P-1th time, N "0"s are written to the MRAM each time; the number of data "0"s written to the MRAM for the Pth time is less than or equal to N, and the number N can be flexibly set according to the actual scenario.
[0109] After writing data "0" to the MRAM for the first time, the MRAM controller determines whether all data "0" have been written to the MRAM; if the judgment result is no, then write data "0" to the MRAM for the second time, and then the MRAM controller determines whether all data "0" have been written to the MRAM; if the judgment result is no, then write data "0" to the MRAM for the third time, if the judgment result is yes, execute step S205; if the judgment result is no, then continue to write data "0" to the MRAM for the fourth time. And so on, until all data "0" have been written to the MRAM.
[0110] In specific implementation, the time required to write data "0" to MRAM each time includes: write "0" setup time, single bit write time and write "0" hold time. The single bit write time is the time to write a "0" in a bit.
[0111] Step S205 , reading data from the MRAM.
[0112] Step S206, writing data "1" into the MRAM in Q times.
[0113] In some embodiments, during the process of writing data "1" to the MRAM from the first time to the Q-1th time, M "0"s are written to the MRAM each time; the number of data "1"s written to the MRAM for the Qth time is less than or equal to M, and the number M can be flexibly set according to the actual scenario.
[0114] After writing data "1" to the MRAM for the first time, the MRAM controller determines whether all data "1" have been written to the MRAM; if the judgment result is no, then write data "1" to the MRAM for the second time, and then the MRAM controller determines whether all data "1" have been written to the MRAM; if the judgment result is no, then write data "1" to the MRAM for the third time, if the judgment result is yes, then the data can be read from the MRAM; if the judgment result is no, then continue to write data "1" to the MRAM for the fourth time. And so on, until all data "1" have been written to the MRAM.
[0115] In specific implementation, the time required to write data "1" to MRAM each time includes: write "1" setup time, single bit write time and write "1" hold time. Among them, the single bit write time is the time to write a "1" in a bit.
[0116] Step S207: the MARM controller sends a notification to the CPU.
[0117] In some embodiments, the notification is used to indicate that writing data to the MRAM is finished.
[0118] In the data processing method of the magnetic random access memory provided in the embodiment of the present application, an optional schematic diagram of reading data from the MRAM is as follows: Figure 3 As shown, data can be read from the MRAM once (also referred to as a read operation) in the time interval between the operation of writing a "0" to the MRAM and the operation of writing a "1" to the MRAM. In the data processing method of the magnetic random access memory provided in the embodiment of the present application, another optional schematic diagram of reading data from the MRAM is as follows: Figure 4 As shown, data may be read from the MRAM twice or more in a time interval between an operation of writing a "0" to the MRAM and an operation of writing a "1" to the MRAM.
[0119] In the data processing method of the magnetic random access memory provided in the embodiment of the present application, another optional schematic diagram of reading data from the MRAM is as follows: Figure 5 As shown, write "0" to MRAM twice or more times, and read data from MRAM once or multiple times in the time interval between writing "0" to MRAM twice. Write "1" to MRAM twice or more times, and read data from MRAM once or multiple times in the time interval between writing "1" to MRAM twice. In the time interval between the operation of writing "0" to MRAM and the operation of writing "1" to MRAM, read data from MRAM once or multiple times. In the embodiment of the present application, the number of operations of writing "0" to MRAM and the number of operations of writing "1" to MRAM can be flexibly set as needed. In the time interval of writing "0" to MRAM, the number of data read from MRAM can be flexibly set as needed. In the time interval of writing "1" to MRAM, the number of data read from MRAM can be flexibly set as needed.
[0120] In the prior art, when writing data to MRAM, there is no time interval between writing "0" to MRAM and writing "1" to MRAM. Taking the scenario of writing 128 bits of data at a time as an example, the total operation time of an MRAM write operation in the prior art is:
[0121] Ttotal=Tread+2*(Twrs+Twrh)+(N+M)*Twrite;
[0122] Where N is the number of "0"s written, M is the number of "1"s written, Twrs is the setup time for writing "0", Twrite is the time required to write "0" or write "1", Twrh is the hold time for writing "0", and Twrs is the hold time for writing "1".
[0123] In the prior art, when 128 bits of data are written at a time, Tread=20ns, Twrs=3us, Twrh=1.7us, Twrite=300ns, and 50% of the 128 bits of data need to be rewritten, half of which is written from "1" to "0" and the other half is written from "0" to "1".
[0124] Then Ttotal=0.02+2*(3+1.7)+64*0.3=28.62us.
[0125] In the embodiment of the present application, when writing data to the MRAM, the number of bits written "0" or "1" each time is 8. Then the time for one MRAM write operation is:
[0126] t=Tread+(Twrs+Twrh)+N / 8*Twrite or Tread+(Twrs+Twrh)+M / 8*Twrite. Where N is the number of "0"s written, M is the number of "1"s written, Twrs is the setup time for writing "0", Twrite is the time required for writing "0" or writing "1", Twrh is the hold time for writing "0", and Twrs is the hold time for writing "1".
[0127] When writing 128 bits of data at a time, Tread = 20ns, Twrs = 3us, Twrh = 1.7us, Twrite = 300ns, 50% of the 128 bits of data need to be rewritten, half from "1" to "0", and the other half from "0" to "1".
[0128] Each write operation then takes t=0.02+(3+1.7)+32 / 8*0.3=5.92us.
[0129] Since in the embodiment of the present application, data can be read from the MRAM after any MRAM write operation is completed. In the embodiment of the present application, the time for a write operation is 5.92us, which is about 22.7us less than the time for a write operation in the prior art of 28.62us. Since in the embodiment of the present application, data can be read from the MRAM after any MRAM write operation is completed; therefore, in the embodiment of the present application, the MRAM write operation has little effect on the MRAM read operation; when writing data to the MRAM, the efficiency of reading data from the MRAM is less affected.
[0130] The present application embodiment provides a data processing device for a magnetic random access memory, and a schematic diagram of the structure of the data processing device for a magnetic random access memory is shown in FIG. Figure 6 As shown, including:
[0131] An acquisition module 301 is used to acquire data to be written and a write address of the data to be written in a magnetic random access memory;
[0132] A comparison module 302, used to compare the original data in the write address with the data to be written to obtain a comparison result;
[0133] A determination module 303, configured to determine a bit address of a value to be changed based on the comparison result;
[0134] A division module 304, configured to divide the data to be written into a plurality of data sets to be written;
[0135] A first control module 305, used to control the current direction of the first magnetic tunnel junction set corresponding to the bit unit to achieve writing of at least one data in the first to-be-written data set;
[0136] A reading module 306, used for reading data in the magnetic random access memory;
[0137] The second control module 307 is used to control the current direction of the second magnetic tunnel junction set corresponding to the bit unit to achieve the writing of data in at least one of the second data sets to be written.
[0138] In some optional embodiments, the first control module 305 is used to control the current direction of the first magnetic tunnel junction set in the first magnetic tunnel junction set to be a first direction, so as to implement the writing of data in the first data set to be written in the first data set to be written;
[0139] After a first time interval, controlling the current direction of a second magnetic tunnel junction set in the first magnetic tunnel junction set to be a first current direction, so as to implement writing of data in the second data set to be written in the first data set to be written;
[0140] And so on, until the current direction of the last magnetic tunnel junction set in the first magnetic tunnel junction set is controlled to be the first current direction, so as to implement the writing of data in the last data set to be written in the first data set to be written;
[0141] Wherein, the number of magnetic tunnel junctions included in each of the first magnetic tunnel junction sets is less than a first number threshold.
[0142] In some optional embodiments, the reading module is further used to read data in the magnetic random access memory within any one or more of the first time intervals.
[0143] In some optional embodiments, the second control module 307 is used to control the current direction of the first magnetic tunnel junction set in the second magnetic tunnel junction set to be the second direction, so as to implement the writing of data in the first data set to be written in the second data set to be written;
[0144] After a second time interval, controlling the current direction of a second magnetic tunnel junction set in the second magnetic tunnel junction set to be a second current direction, so as to implement writing of data in the second data set to be written in the second data set to be written;
[0145] And so on, until the current direction of the last magnetic tunnel junction set in the second magnetic tunnel junction set is controlled to be the second current direction, so as to achieve the writing of data in the last data set to be written in the second data set to be written;
[0146] Wherein, the number of magnetic tunnel junctions included in each of the second magnetic tunnel junction sets is less than a second number threshold.
[0147] In some optional embodiments, the reading module 306 is further configured to read data in the magnetic random access memory within any one or more of the second time intervals.
[0148] In some optional embodiments, the first time interval is the same as the second time interval; or, the first time interval is different from the second time interval.
[0149] The present application also provides a chip, a schematic diagram of the structure of the chip, such as Figure 7 As shown, the chip includes: a processor 410, a memory 450 and a bus 440; the various modules in the chip are coupled together through the bus 440. It can be understood that the bus 440 is used to realize the connection and communication between these modules. In addition to the data bus, the bus 440 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 7 Various buses are labeled as bus 440.
[0150] The processor 410 has signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware models, etc., where the general-purpose processor can be a microprocessor or any conventional processor, etc.
[0151] The memory 450 stores executable instructions for implementing the data processing method of the magnetic random access memory provided in the embodiment of the present application. The data processing method of the magnetic random access memory can be performed by Figure 6 The acquisition module 301, the comparison module 302, the determination module 303, the division module 304, the first control module 305, the reading module 306 and the second control module 307 in the data processing method device of the magnetic random access memory shown in the figure are implemented; the memory 450 can be removable, non-removable or a combination thereof. Exemplary hardware devices include solid-state memory, hard disk drive, optical disk drive, etc. The memory 450 optionally includes one or more storage devices that are physically far away from the processor 410.
[0152] In some embodiments, memory 450 is capable of storing data to support various operations, examples of which include programs, modules, and data structures, or a subset or superset thereof.
[0153] In some embodiments, the chip may further include:
[0154] Operating system 451, including system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks;
[0155] The network communication module 452 is used to reach other computing devices via one or more (wired or wireless) network interfaces 420. Exemplary network interfaces 420 include: Bluetooth, Wireless Authentication (WiFi), and Universal Serial Bus (USB).
[0156] An embodiment of the present application also provides a component on a transportation device, wherein the component includes a chip, and the chip can execute the data processing method of the magnetic random access memory.
[0157] In some optional embodiments, the components may be components at the circuit board level, components at the automotive electrical system level, or components of an automotive assembly. As an example, the components may be the engine, chassis, body, and electrical and electronic equipment of the vehicle. The electrical and electronic equipment of the vehicle may include headlights for lighting, management equipment for controlling the engine, central control equipment for receiving broadcasts, navigation, listening to music, entertainment, etc.
[0158] The embodiment of the present application also provides an electronic device, the electronic device includes a chip, the chip can execute the data processing method of the magnetic random access memory, wherein the chip can be a multi-core heterogeneous chip, and the electronic device can be a transportation device, the transportation device includes but is not limited to a balance car, a car, a bus, a train or an airplane, etc.
[0159] The present application embodiment provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored. When the executable instructions are executed by a processor, the processor will be triggered to execute the data processing method of the magnetic random access memory provided in the present application embodiment, for example, Figures 1 to 5 The data processing method of the magnetic random access memory is shown.
[0160] In some embodiments, the computer-readable storage medium may be a ferroelectric random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disk, or a CD-ROM; it may also be various devices including one or any combination of the above memories.
[0161] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, model, subroutine or other unit suitable for use in a computing environment.
[0162] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.
[0163] An embodiment of the present application provides a computer program product, which includes a computer program / instructions. When the computer program / instructions are executed by a processor, the data processing method of the magnetic random access memory described in the present application is implemented.
[0164] The above are only embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present application are included in the protection scope of the present application.
Claims
1. A data processing method for a magnetic random access memory, characterized in that: The method comprises: Acquire data to be written and a write address of the data to be written in a magnetic random access memory; Comparing the original data in the write address with the data to be written to obtain a comparison result; Determine the bit unit of the value to be changed based on the comparison result; Dividing the data to be written into a plurality of first data sets to be written and a plurality of second data sets to be written; Controlling the current direction of the first magnetic tunnel junction set corresponding to the bit unit to implement writing of at least one data in the first data set to be written; Reading data in the magnetic random access memory; The current direction of the second magnetic tunnel junction set corresponding to the bit cell is controlled to achieve writing of data in at least one of the second data sets to be written.
2. The method according to claim 1, characterized in that The controlling the current direction of the first magnetic tunnel junction set corresponding to the bit unit to implement the writing of at least one data in the first to-be-written data set comprises: Controlling the current direction of a first magnetic tunnel junction set in the first magnetic tunnel junction sets to be a first direction, so as to implement writing of data in a first data set to be written in the first data set to be written; After a first time interval, controlling the current direction of a second magnetic tunnel junction set in the first magnetic tunnel junction set to be a first current direction, so as to implement writing of data in the second data set to be written in the first data set to be written; And so on, until the current direction of the last magnetic tunnel junction set in the first magnetic tunnel junction set is controlled to be the first current direction, so as to implement the writing of data in the last data set to be written in the first data set to be written; Wherein, the number of magnetic tunnel junctions included in each of the first magnetic tunnel junction sets is less than a first number threshold.
3. The method according to claim 2, characterized in that The method further comprises: Within any one or more of the first time intervals, data in the magnetic random access memory is read.
4. The method according to claim 1, characterized in that: The controlling the current direction of the second magnetic tunnel junction set corresponding to the bit unit to implement the writing of at least one data in the second to-be-written data set comprises: Controlling the current direction of the first magnetic tunnel junction set in the second magnetic tunnel junction set to be a second direction, so as to implement writing of data in the first data set to be written in the second data set to be written; After a second time interval, controlling the current direction of a second magnetic tunnel junction set in the second magnetic tunnel junction set to be a second current direction, so as to implement writing of data in the second data set to be written in the second data set to be written; And so on, until the current direction of the last magnetic tunnel junction set in the second magnetic tunnel junction set is controlled to be the second current direction, so as to achieve the writing of data in the last data set to be written in the second data set to be written; Wherein, the number of magnetic tunnel junctions included in each of the second magnetic tunnel junction sets is less than a second number threshold.
5. The method according to claim 4, characterized in that The method further comprises: Within any one or more of the second time intervals, data in the magnetic random access memory is read.
6. The method according to any one of claims 2 to 5, characterized in that: The first time interval is the same as the second time interval; Alternatively, the first time interval is different from the second time interval.
7. A data processing device for a magnetic random access memory, characterized in that: The device comprises: An acquisition module, used for acquiring data to be written and a write address of the data to be written in the magnetic random access memory; A comparison module, used for comparing the original data in the write address with the data to be written to obtain a comparison result; A determination module, used for determining a bit address of a value to be changed based on the comparison result; A division module, used for dividing the data to be written into multiple data sets to be written; a first control module, configured to control a current direction of a first magnetic tunnel junction set corresponding to the bit unit, so as to implement writing of data in at least one of the first data sets to be written; A reading module, used for reading data in the magnetic random access memory; The second control module is used to control the current direction of the second magnetic tunnel junction set corresponding to the bit unit to achieve the writing of data in at least one of the second data sets to be written.
8. A chip, characterized in that: The chip includes: a processor, a memory and a bus; The memory stores executable instructions; The processor communicates with the memory via the bus, and when the processor executes the executable instructions stored in the memory, the data processing method of the magnetic random access memory according to any one of claims 1 to 6 is implemented.
9. A component on a traffic device, characterized in that: The component includes a chip, and the chip can implement the data processing method of the magnetic random access memory as described in any one of claims 1 to 6.
10. An electronic device, characterized in that: The electronic device comprises a chip, and the chip can implement the data processing method of the magnetic random access memory as claimed in any one of claims 1 to 6.