CMOS zero intermediate frequency mixer adopting second-order cross modulation calibration

Abstract

The invention belongs to the technical field of radio frequency integrated circuits and mixers, and relates to a CMOS zero intermediate frequency mixer adopting second-order cross modulation calibration. The structure of a Gilbert unit of the mixer is improved, and the mixer comprises the Gilbert unit, a pair of PMOS (P-channel Metal Oxide Semiconductor) tubes and a calibration circuit, the pair of PMOS transistors are used for reducing flicker distortion, the calibration circuit is located at the load and output end of the Gilbert unit, second-order intermodulation is calibrated by modulating the size of load resistance, various factors influencing second-order intermodulation distortion are equivalently replaced by modulating the load resistance, the load resistance on one side is replaced by a k-bit resistance modulation module, and the number of the k-bit resistance modulation module is smaller than that of the k-bit resistance modulation module. K is between 3 and 10. According to the mixer, the problem of mismatching of a double-balanced mixer circuit caused by multiple factors is solved, and second-order intermodulation distortion is effectively reduced; flicker noise is reduced, isolation between a radio frequency end and a local oscillator end is improved, local oscillator leakage and direct current offset are reduced, circuit operation difficulty is simplified, and circuit performance is effectively improved.

Description

Technical Field

[0001] The invention belongs to the technical field of radio frequency integrated circuits and mixers, and relates to a CMOS zero intermediate frequency mixer using second-order intermodulation calibration. Background Art

[0002] With the development of mobile communication technology, high-speed, high-efficiency, and low-loss mobile communications have always been the focus of research. As this research focus continues to deepen, it has promoted the pursuit of higher-performance communication systems. In modern communication systems, RF receivers receive and process signals from transmitters or the environment for application, and their performance plays a vital role in the entire communication system. Therefore, the requirements for receivers with higher efficiency, working in higher frequency bands, and lower losses are getting higher and higher.

[0003] In current receivers, the superheterodyne structure is the most widely used, but due to the large intermediate frequency, it will bring problems such as difficulty in integration and high noise. The corresponding zero intermediate frequency structure is characterized by directly down-converting the RF signal to the baseband, omitting the intermediate frequency part, which can solve many problems of the superheterodyne structure and also has some other unique advantages, including: the circuit does not require high-Q high-frequency or intermediate frequency bandpass filters that are difficult to integrate, and each module on the receiving link does not need to drive an external low-impedance load, which reduces the difficulty of integrated circuit implementation; the baseband filtering of the receiver is achieved through a high-order active low-pass filter, and its bandwidth can be adjusted; the intermediate frequency module is omitted, the overall area and power consumption of the chip will be reduced, and the verification time of the chip design will be short. Based on the various advantages of zero intermediate frequency receivers, more and more receivers are beginning to adopt zero intermediate frequency structures.

[0004] The front end of the RF receiver is mainly composed of modules such as a low noise amplifier, a variable gain amplifier and a mixer. The mixer is responsible for down-converting the RF signal to baseband, so the quality of its design is crucial to the performance of the entire receiver. However, there are many design difficulties in the zero intermediate frequency mixer, including second-order intermodulation distortion caused by factors such as device mismatch and temperature drift, and DC offset with a large impact of flicker noise in the low frequency band. These problems need to be focused on in the zero intermediate frequency structure. The present invention is committed to designing a zero intermediate frequency mixer, which reduces the second-order intermodulation distortion of the mixer and improves the circuit performance of the zero intermediate frequency mixer through technologies such as second-order intermodulation calibration, which can make up for the relatively weak research on high-performance zero intermediate frequency mixers in China.

[0005] The present invention reduces the mismatch problem of the mixer as much as possible by modulating the load resistance of the mixer, and can greatly reduce the influence of the second-order intermodulation distortion on the mixer. The flicker noise of the circuit is reduced by changing the circuit structure, and the DC offset problem of the circuit is reduced to a certain extent, which simplifies the operation difficulty, improves the integration of the circuit, and makes up for the current domestic lack and deficiency in the design of zero intermediate frequency mixers to a certain extent. Summary of the invention

[0006] The purpose of the present invention is to reduce the influence of second-order intermodulation distortion on the mixer and improve the performance of the circuit by adopting second-order intermodulation calibration and a new circuit structure. A CMOS zero intermediate frequency mixer adopting second-order intermodulation calibration is proposed. The structure is innovated on the basis of the basic Gilbert unit composed of a pair of input transistors and two groups of switch pair transistors. The mixer has the advantages of high gain, low noise and high linearity, and at the same time has a small chip area, high integration and low cost.

[0007] In order to achieve the above object, the present invention adopts the following technical scheme.

[0008] The zero intermediate frequency mixer comprises a Gilbert unit, a pair of PMOS tubes and a calibration circuit;

[0009] The Gilbert unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; the pair of PMOS tubes includes a first PMOS tube and a second PMOS tube;

[0010] The first NMOS transistor and the second NMOS transistor are of differential input structure, that is, the gates of the two transistors are respectively connected to the differential inputs RF+ and RF- of the radio frequency signal, and the sources of the two transistors are connected and connected to the ground terminal GND;

[0011] The 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube are two groups of switch pair transistors and are arranged from left to right in sequence. The source of the 3rd NMOS tube is connected to the 4th NMOS tube and is connected to the drain of the 1st NMOS tube. The source of the 5th NMOS tube is connected to the 6th NMOS tube and is connected to the drain of the 2nd NMOS tube. The gate of the 3rd NMOS tube is connected to the 6th NMOS tube and is connected to the positive input LO+ of the local oscillator signal. The gate of the 4th NMOS tube is connected to the 5th NMOS tube and is connected to the other differential input LO- of the local oscillator signal. The drain of the 3rd NMOS tube is connected to the 5th NMOS tube and is connected to the load on the left. The drain of the 4th NMOS tube is connected to the 6th NMOS tube and is connected to the load on the right.

[0012] The first PMOS tube and the second PMOS tube are a pair of PMOS transistors, which are used to reduce the flicker noise of the circuit; the drain of the first PMOS tube is connected to the source of the third NMOS tube and the fourth NMOS tube and the drain of the first NMOS tube, the drain of the second PMOS tube is connected to the source of the fifth NMOS tube and the sixth NMOS tube and the drain of the second NMOS tube, the drains of the first PMOS tube and the second PMOS tube are connected and connected to the power supply VDD, and the gates of the first PMOS tube and the second PMOS tube are connected and connected to the voltage bias VBP after passing through a load resistor R.

[0013] The calibration circuit is located at the load end and the output end of the Gilbert unit, and calibrates the second-order intermodulation of the circuit by modulating the size of the load resistance; the calibration circuit includes capacitors C1, C2, a load resistor RD and an adjustable resistor array;

[0014] After capacitor C1 is connected in parallel with the adjustable resistor array, one end is connected to the power supply VDD, and the other end is connected to the drain of the 3rd NMOS tube and the 5th NMOS tube. After capacitor C2 is connected in parallel with resistor RD, one end is connected to the power supply VDD, and the other end is connected to the drain of the 4th NMOS tube and the 6th NMOS tube. The differential output of the circuit is between the load and the switch pair transistor.

[0015] The adjustable resistor array is a combination of a k-bit resistor and a switch, and the circuit structure includes k+1 resistors and k single-pole single-throw switches S1, S2, S3, S4 and S5;

[0016] The k+1 resistors are denoted as R0, R1, ...R k The k single-pole single-throw switches are denoted as: S1, S2, S3, S4 and S5; each single-pole single-throw switch is composed of a transistor;

[0017] Among them, resistors R1 and S1 are connected in series, resistors R2 and S2 are connected in series, ..., resistor R k and S k They are connected in series and arranged from left to right and connected in parallel, with resistor R0 connected in parallel on the left side of resistors R1 and S1; the two ends of the k-way parallel connection are the input and output of the adjustable resistor array respectively;

[0018] The value range of k is 3 to 10.

[0019] Beneficial Effects

[0020] The present invention proposes a CMOS zero intermediate frequency mixer using second-order intermodulation calibration, which has the following beneficial effects compared with the prior art:

[0021] 1. The mixer replaces the circuit model with a calibration circuit, and measures the various factors causing circuit mismatch through one variable, that is, adjusting the load resistance on one side of the symmetrical circuit to reduce the mismatch of the entire circuit, thereby simplifying the process and complexity of second-order intermodulation distortion calibration;

[0022] 2. The mixer can achieve high-precision second-order intermodulation calibration with fewer control bits by connecting resistors of different resistance values ​​in parallel and controlling them through switches;

[0023] 3. The mixer adds a pair of PMOS tubes to split the total current, thereby increasing the load resistance and the size of the switch pair transistors, thereby reducing flicker noise, and at the same time leaving more voltage margin for the main circuit, thereby improving the flexibility of circuit design;

[0024] 4. The mixer improves the isolation between the RF end and the local oscillator end by adjusting the parasitic parameters of the transistors at the RF end and the local oscillator end, reduces the leakage of the local oscillator signal, and reduces the impact of DC offset on the performance of the zero intermediate frequency mixer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The present invention discloses a circuit structure of a CMOS zero intermediate frequency mixer using second-order intermodulation calibration;

[0026] Figure 2 It is a schematic diagram that replaces the circuit model and measures the mismatch of the entire circuit through the load resistance;

[0027] Figure 3 It is a schematic diagram of the circuit structure of the adjustable resistor array;

[0028] Figure 4 This is a schematic diagram of the effect of improving the second-order intermodulation before and after the zero-IF mixer is calibrated. DETAILED DESCRIPTION

[0029] In order to better illustrate the design objectives and advantages of the present invention, a CMOS zero-IF mixer using second-order intermodulation calibration of the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0030] Example 1

[0031] The zero-IF mixer directly down-converts the RF signal to the baseband, which reduces the requirements for the image rejection rate, but there are also some problems, including the second-order intermodulation distortion caused by factors such as device mismatch and temperature drift, the DC offset low-frequency band flicker noise has a greater impact, and the DC offset may be caused by local oscillator leakage, etc. Therefore, in the design process, the present invention improves the performance of the design from the above aspects.

[0032] The second-order intermodulation distortion of the zero-IF mixer is mainly caused by the mismatch of the circuit. In the actual manufacturing process of the chip, it is inevitable that the designed symmetrical circuit will actually have a large mismatch due to factors such as process, temperature, and device parameter errors, which will lead to very serious second-order intermodulation distortion of the circuit. According to known theories, in a double-balanced mixer, factors such as the difference in load resistance, the difference in transconductance of the switch to the transistor, and the difference in duty cycle of the local oscillator signal cannot be avoided. Therefore, the actual circuit cannot be completely symmetrical. The impact caused by the many asymmetries of the circuit can be measured by the offset voltage difference on both sides of the circuit, such as Figure 2 As shown, all mismatches of the entire circuit are replaced by the offset voltage generated on one side of the symmetrical circuit, and the remaining circuit is an ideal completely symmetrical circuit. On this basis, the present invention balances the offset voltage generated by the asymmetry of the circuit by calibrating the load resistance on the other side of the symmetrical circuit within an appropriate range and with appropriate accuracy, so that the zero intermediate frequency mixer can achieve a completely symmetrical effect in theory, and calibrate the mismatch degree of the entire circuit to a large extent, thereby reducing the second-order intermodulation distortion of the mixer.

[0033] like Figure 3 As shown, the adjustable resistor array is composed of six resistors with different resistance values ​​and five switches. The leftmost resistor R0 is set to be slightly larger than the load resistor RD of the mixer, and the resistance value of the resistor R1 is set to R1||R0=RD. In this way, the 5-bit control bit can be divided into two groups of 4-bit control bits, one group can calibrate the load resistor value to be greater than RD, and the other group can calibrate the load resistor value to be less than RD. The resistance values ​​of the other four resistors increase from left to right to achieve the change of resistance values ​​in different gears. By controlling the switch through five control bits, resistors with different resistance values ​​are connected in parallel to the load circuit, which can achieve the effect of monotonically changing the size of the load resistor to balance the mismatch problem of the mixer in different design environments. According to the different resistance values, the accuracy of the resistor calibration can be as high as possible, and the impact on other indicators such as noise and gain can be minimized on the basis of improving the degree of circuit matching.

[0034] The CMOS zero-IF mixer using second-order intermodulation calibration is as follows: Figure 1As shown. The mixer described in the present invention is a structural innovation based on the Gilbert unit. The entire circuit adopts a double-balanced structure, which can reduce the influence of the duty cycle difference of the switch pair transistor signal on the second-order intermodulation distortion. NM1 and NM2 are input tubes, and the radio frequency signal enters the circuit after being biased. NM3, NM4, NM5, and NM6 constitute a switch pair transistor, and introduce a given local oscillator signal into the circuit. The input radio frequency signal and the local oscillator signal are frequency-converted through the Gilbert unit and the signal is output. The output end of the Gilbert unit is connected to the load, and a capacitor is connected in parallel at both ends of the load, which can reduce the second-order intermodulation distortion to a certain extent as the baseband frequency becomes lower. By calibrating the resistance value of one side of the resistor, the mismatch problem of the mixer is reduced, thereby reducing the second-order intermodulation distortion of the mixer. By leading a signal between the input transistor and the switch transistor and connecting it to the PMOS tube, the current of the main circuit is shunted, so that the current of the main circuit is reduced, the voltage divided by the load resistor is reduced, and sufficient voltage margin is left for the Gilbert unit to ensure that the transistor reaches saturation, increase the size of the transistor and the load resistor, increase the gain of the circuit, reduce flicker noise, and improve the performance of the circuit. In addition, in the zero intermediate frequency mixer, since the local oscillator signal is generally a large signal, its leakage may cause a large DC offset, causing serious consequences. The circuit described in the present invention adjusts the parasitic parameters of the radio frequency port and the local oscillator port transistor to achieve a higher isolation between the two ports, well suppress the local oscillator leakage, and reduce the impact of the DC offset on the circuit.

[0035] The effect of the second-order intermodulation calibration is shown as follows: Figure 4 As shown, through 5-bit control bit modulation, the load resistance can be increased by an average of more than 50dBm within a range of less than 5% change, and it has good modulation accuracy, greatly reducing the second-order intermodulation distortion of the circuit and improving the performance of the circuit.

[0036] Therefore, the circuit structure of the CMOS zero-IF mixer adopts second-order intermodulation calibration to design a high-performance zero-IF mixer while meeting the requirements and costs, and effectively reduces the impact of problems such as circuit flicker noise, thereby solving the design requirements for high-performance receivers to a certain extent and achieving good results.

[0037] The specific descriptions or embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A CMOS zero-IF mixer using second-order intermodulation calibration, characterized in that: It includes a Gilbert unit, a pair of PMOS tubes and a calibration circuit; The Gilbert unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; the pair of PMOS tubes includes a first PMOS tube and a second PMOS tube; Among them, the first NMOS tube and the second NMOS tube are differential input structures, that is, the gates of the two are respectively connected to the differential inputs RF+ and RF- of the radio frequency signal, and the sources of the two are connected and connected to the ground terminal GND; The calibration circuit is located at the load end and output end of the Gilbert unit, and calibrates the second-order intermodulation of the circuit by modulating the size of the load resistance; the calibration circuit includes capacitors C1, C2, a load resistor RD and an adjustable resistor array.

2. The CMOS zero intermediate frequency mixer according to claim 1, characterized in that: The 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube are two groups of switch pair transistors and are arranged from left to right in sequence. The source of the 3rd NMOS tube is connected to the 4th NMOS tube and is connected to the drain of the 1st NMOS tube. The source of the 5th NMOS tube is connected to the 6th NMOS tube and is connected to the drain of the 2nd NMOS tube. The gate of the 3rd NMOS tube is connected to the 6th NMOS tube and is connected to the positive input LO+ of the local oscillator signal. The gate of the 4th NMOS tube is connected to the 5th NMOS tube and is connected to the other differential input LO- of the local oscillator signal. The drain of the 3rd NMOS tube is connected to the 5th NMOS tube and is then connected to the load on the left. The drain of the 4th NMOS tube is connected to the 6th NMOS tube and is then connected to the load on the right.

3. The CMOS zero intermediate frequency mixer according to claim 2, characterized in that: The first PMOS tube and the second PMOS tube are a pair of PMOS transistors, which are used to reduce the flicker noise of the circuit; the drain of the first PMOS tube is connected to the source of the third NMOS tube and the fourth NMOS tube and the drain of the first NMOS tube, the drain of the second PMOS tube is connected to the source of the fifth NMOS tube and the sixth NMOS tube and the drain of the second NMOS tube, the drains of the first PMOS tube and the second PMOS tube are connected and connected to the power supply VDD, and the gates of the first PMOS tube and the second PMOS tube are connected and connected to the voltage bias VBP after passing through a load resistor R.

4. The CMOS zero intermediate frequency mixer according to claim 1, characterized in that: After capacitor C1 is connected in parallel with the adjustable resistor array, one end is connected to the power supply VDD, and the other end is connected to the drain of the 3rd NMOS tube and the 5th NMOS tube. After capacitor C2 is connected in parallel with resistor RD, one end is connected to the power supply VDD, and the other end is connected to the drain of the 4th NMOS tube and the 6th NMOS tube. The differential output of the circuit is between the load and the switch pair transistor.

5. The CMOS zero intermediate frequency mixer according to claim 4, characterized in that: The adjustable resistor array is a combination of a k-bit resistor and a switch, and the circuit structure includes k+1 resistors and k single-pole single-throw switches S1, S2, S3, S4 and S5; The k+1 resistors are denoted as R0, R1, ...R k ; The k single-pole single-throw switches are denoted as: S1, S2, S3, S4 and S5; each single-pole single-throw switch is composed of a transistor.

6. The CMOS zero intermediate frequency mixer according to claim 5, characterized in that: Resistors R1 and S1 are connected in series, resistors R2 and S2 are connected in series, ..., resistor R k and S k They are connected in series and arranged from left to right and connected in parallel. Resistor R0 is connected in parallel to the left side of resistors R1 and S1. The two ends of the k-way parallel connection are the input and output of the adjustable resistor array respectively.

7. The CMOS zero intermediate frequency mixer according to claim 6, characterized in that: The value range of k is 3 to 10.

Images