Flicker Noise Cancellation in the DC Bias Circuit of a Double-Balanced Mixer

Abstract

Disclosed is a transmitter that reduces the third-order harmonic (HD3) and intermodulation distortion (IMD3) of the gm stage of a mixer while reducing flicker noise. The transmitter may include a balanced mixer, a transconductance stage connected to the mixer, and a bias circuit. The bias circuit may include a programmable current source configured to provide a reference current. Additionally, the bias circuit may include a copying circuit configured to copy the DC signal of the transconductance stage. The bias circuit may further include a bias transistor configured to perform a level conversion on a bias signal obtained from the signal source based on the reference current and the DC signal of the transconductance stage determined by the copying circuit.

Description

[0001] By reference to incorporate any priority applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 062,714, filed August 7, 2020, entitled "Flicker Noise Cancellation in a Dual-Balanced Mixer DC Bias Circuit", the disclosure of which is hereby incorporated by reference in its entirety for all purposes. Any and all applications for foreign or domestic priority claims identified in the application data sheet filed with this application are hereby incorporated by reference in accordance with 37 CFR 1.57 Technical Field

[0003] Embodiments of the present invention relate to a balanced mixer, and more particularly, to the elimination of flicker noise in the DC circuit of a balanced mixer Background Art

[0004] Communication circuits typically include mixer elements that mix a carrier signal with a data signal. For example, a mixer element may mix a data signal with an oscillator signal. In addition, wireless devices typically support multiple communication frequencies. In addition, wireless devices may support different functions using different frequencies. For example, a wireless device may support cellular communication and geolocation services, which may operate at different frequencies. In some cases, harmonics of the signal and / or intermodulation between signals may cause unwanted distortion of the desired or supported signal Summary of the Invention

[0005] The systems, methods, and devices of the present disclosure each have several innovative aspects, none of which alone is responsible for all of the desired attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the following description

[0006] Certain aspects of the present disclosure relate to a transmitter that reduces third-order harmonics (HD3) and intermodulation distortion (IMD3) of a mixer gm-stage while reducing flicker noise. The transmitter may include a mixer, a transconductance stage connected to the mixer, and a bias circuit. The bias circuit may include: a programmable current source configured to provide a reference current; a replica circuit configured to replicate the DC signal of the transconductance stage; and a bias transistor configured to perform a level conversion on a bias signal obtained from the signal source based on the reference current and the DC signal of the transconductance stage. The DC signal of the transconductance stage may be determined from the replica circuit

[0007] The transmitter in the front section may include any combination and / or sub-combination of the following features: wherein the transconductance stage includes a pair of nFETs connected as a differential pair; wherein the transconductance stage includes a pair of pFETs connected as a differential pair; wherein the mixer is a Gilbert cell mixer; wherein the mixer is a double-balanced mixer; wherein the mixer is a single-balanced mixer; wherein the transistor includes a pFET; wherein the bias circuit includes a second bias transistor configured to perform level conversion on a second bias signal; wherein the phase of the bias signal and the phase of the second bias signal are the same as the phase of the DC signal; wherein the bias signal is supplied to the first transistor of the transconductance stage, and the second bias signal is supplied to the second transistor of the transconductance stage; wherein the transmitter further includes a filter before the bias circuit, wherein the filter includes a differential Sallen-Key filter; wherein the filter includes a biquadratic filter; wherein the bias circuit further includes a pair of matching resistors, wherein the first resistor of the pair of matching resistors is configured to supply a bias signal to the first transistor of the transconductance stage, and the second resistor of the pair of matching resistors is configured to supply a bias signal to the second transistor of the transconductance stage; wherein the transmitter further includes an averaging circuit configured to average a first digital-to-analog converter (DAC) current and a second DAC current, wherein the averaged DAC current is provided as an input to the transconductance stage; wherein the signal source includes a current-controlled digital-to-analog converter (DAC); wherein the bias circuit holds the DC operating point of the transconductance stage at a level that reduces or eliminates the value of the third derivative of current (gm3) over the entire temperature range; and wherein the bias circuit holds the DC operating point of the transconductance stage at a level that reduces or eliminates the value of the third derivative of current (gm3) over the entire method range.

[0008] Additional aspects of the present disclosure relate to wireless devices. The wireless device may include: an antenna configured to transmit a transmission signal; and a transmitter in communication with the antenna and configured to generate and transmit or transmit a transmission signal by the antenna. The transmitter may include: a mixer; a transconductance stage connected to the mixer; and a bias circuit. The bias circuit may include: a programmable current source configured to provide a reference current; a replica circuit configured to replicate the DC signal of the transconductance stage; and a bias transistor configured to perform level conversion on a bias signal obtained from the signal source based on the reference current and the DC signal of the transconductance stage.

[0009] The transmitter of the front stage may include any combination and / or sub - combination of the following features: where the transconductance stage includes a pair of nFETs (or pFETs) connected as a differential pair; where the mixer is a Gilbert cell mixer; where the mixer is a double - balanced mixer; where the mixer is a single - balanced mixer or single - balanced structure; where the transistor includes a pFET (or nFET); where the bias circuit includes a second bias transistor configured to perform a level conversion on a second bias signal; where the phase of the bias signal and the phase of the second bias signal are the same as the phase of the DC signal; where the bias signal is provided to the first transistor of the transconductance stage, and the second bias signal is provided to the second transistor of the transconductance stage; where the wireless device further includes a filter before the bias circuit; where the filter includes a differential Sallen - Key filter; where the filter includes a bi - second - order filter; where the bias circuit further includes a pair of matched resistors, where the first resistor of the pair of matched resistors is configured to provide a bias signal to the first transistor of the transconductance stage, and the second resistor of the pair of matched resistors is configured to provide a bias signal to the second transistor of the transconductance stage; where the wireless device further includes an averaging circuit configured to average a first digital - to - analog converter (DAC) current and a second DAC current, where the averaged DAC current is provided as an input to the transconductance stage; where the signal source includes a current - controlled digital - to - analog converter (DAC); where the wireless device further includes a DAC current source configured to generate an analog signal based on a digital data signal; where the analog signal is input to the transmitter; where the bias circuit holds the DC operating point of the transconductance stage at a level that reduces or eliminates the value of the third - derivative of the current (gm3) over the entire temperature range; and where the bias circuit holds the DC operating point of the transconductance stage at a level that reduces or eliminates the value of the third - derivative of the current (gm3) over the entire method range.

[0010] Another aspect of the present disclosure relates to a method of a transmitter. The method may include generating a reference current using a programmable current source. Additionally, the method may include: using a copy circuit to copy a DC signal of a transconductance stage, the transconductance stage being connected to a mixer. Additionally, the method may include: obtaining a bias signal from a signal source; and using a bias transistor to perform a level conversion on the bias signal based on the reference current and the DC signal. Brief Description of the Drawings

[0011] Throughout the drawings, reference numerals are reused to indicate corresponding relationships between reference elements. The drawings are provided to illustrate embodiments of the subject matter described herein and not to limit its scope.

[0012] Figure 1 A double - balanced mixer with a corresponding transconductance (gm) stage is illustrated.

[0013] Figure 2 Shows a third - order derivative plot of the current (gm3) versus the bias voltage, illustrating the points where gm3 crosses zero.

[0014] Figure 3 Illustrates a non - limiting example of a zero - intermediate - frequency (ZIF) transmitter (Tx) path with a common - mode biasing scheme to level - shift the common - mode between a digital - to - analog converter (DAC) output and a gm - stage input.

[0015] Figure 4 Illustrates a non - limiting example of a ZIF Tx path with reduced differential flicker noise in a common - mode biasing scheme. Detailed Description

[0016] The following detailed description of the embodiments presents various descriptions of specific embodiments of the present invention. However, the present invention can be implemented in many different ways. In this description, reference is made to the accompanying drawings, in which like reference numerals may indicate identical or functionally similar elements. It should be understood that the elements shown in the figures are not necessarily drawn to scale. In addition, it should be understood that some embodiments may include more elements than a subset of the elements shown in the figures and / or the accompanying drawings. Furthermore, some embodiments may combine any suitable combination of features from two or more of the figures.

[0017] A double - balanced mixer for up - conversion in a transmitter may include a mixer having balanced differential inputs on the baseband and local oscillator (LO) ports. Additionally, although not limited thereto, the double - balanced mixer may have four diodes connected in a ring. Double - balanced mixers are commonly used as part of the radio - frequency front - end circuits for both transmitters and receivers. For a transmitter, the double - balanced mixer can be used to up - convert a baseband signal to a carrier frequency, while for a receiver, the double - balanced mixer can down - convert a carrier frequency to a baseband signal. Since mixers typically operate in current mode, they are usually accompanied by a transconductance (hereinafter referred to as "gm") stage to convert an incoming baseband voltage signal into a current signal.

[0018] Systems and methods for reducing the third - order harmonic (HD3) and intermodulation distortion (IMD3) of the gm - stage of a double - balanced mixer without introducing additional flicker noise are disclosed herein. Additionally, the present disclosure provides a direct - current (DC) biasing scheme that biases the gm - stage of the mixer, which reduces or minimizes HD3 and IMD3 distortion without introducing any differential flicker noise.

[0019] As described above, a double-balanced mixer is typically used in a transmit architecture to convert a baseband voltage signal into an up-converted RF current signal. Along with the up-converted baseband signal, the gm stage may generate distortion products that can affect the RF output. Since even-order distortion products are common mode, the double-balanced mixer can effectively cancel them. However, odd-order distortion may be passed on to the output. Third-order distortion (HD3 and IMD3) may be the most prominent in the output signal. These HD3 and IMD3 distortions at the RF output can cause in-band emissions and / or reduce the EVM (Error Vector Magnitude) of a transmitter including the double-balanced mixer. Therefore, it is generally desirable to eliminate or reduce third-order distortion (HD3 and IMD3) below a specific threshold level, which may vary depending on the specific use case. For example, in a device supporting Long-Term Evolution (LTE) communication, the threshold level may be at 70 dBc or approximately 70 dBc. In a device supporting Global System for Mobile Communications (GSM), the threshold level may be at 80 dBc or approximately 80 dBc. In addition to distortion, the gm stage may introduce flicker noise, which can also cause in-band emissions. Therefore, it is desirable that the systems and methods for reducing distortion do not introduce additional flicker noise into the circuit.

[0020] Figure 1 A double-balanced mixer 102 with a corresponding transconductance (gm) stage 104 is shown. The gm stage 104 can be used to convert voltage to current, which can be supplied to the mixer 102. The mixer 102 can perform up-conversion of a baseband current signal. The up-conversion can be performed by mixing an oscillator signal (e.g., a carrier signal) with the baseband current signal, which can include data to be transmitted by the transmitter. The transistors of the gm stage 104 may have a certain degree of non-linearity, even when the transistors are operating in the linear region. This non-linearity can cause distortion. Analysis of the gm stage 104 shows that HD3 and IMD3 distortions are mainly caused by the magnitude of the third derivative of the bias current (hereinafter referred to as gm3) with respect to the bias voltage.

[0021] Figure 2 A graph 200 presenting the third derivative of the current (gm3) with respect to the bias voltage shows a point where gm3 crosses zero (minimum). The x-axis represents the common-mode voltage, or the DC voltage at which the transistors of the gm stage 104 are biased, and the y-axis represents gm3, which can correspond to the third-order coefficient of the gm stage non-linearity characteristics. Figure 2 The graph shows that there is a deviation where gm3 reaches a minimum (zero point), as shown at point 202. At Figure 2In an example, gm3 is biased at 0.3V at the point where the third derivative is 0. Therefore, a common-mode biasing circuit is needed that biases the gm stage with a specific bias current to render gm3 = 0, thereby minimizing HD3 and IMD3. Additionally, it is desirable to select a bias point such that the magnitude of gm3 remains minimal across different process and temperature points. Not only is it necessary to minimize HD3 and IMD3, but also to maintain a constant current to help keep gm3 at a minimum throughout the process. The process can refer to the fabrication of silicon or integrated circuit products (such as transmitters). As the silicon process changes, certain parameters may change, resulting in a change in gm3. By maintaining a constant current, gm3 can be kept at or near zero, or at a low enough level to maintain or reduce third-order distortion to -70dBc. Additionally, it is desirable for the current to remain constant across different process and temperature points. Additionally, it is desirable for the circuit to be programmable. Embodiments of the present disclosure achieve the above objectives.

[0022] Figure 3 Illustrates a non-limiting example of a zero-intermediate frequency (ZIF) transmitter (Tx) path with a common-mode biasing scheme to perform a level conversion of the common mode between a digital-to-analog converter (DAC) output and a gm stage input. Figure 3 Circuit 300 of illustrates a double-balanced mixer 302 and a biasing circuit 304 including a gm stage 306. Circuit 300 illustrates a common-mode biasing scheme. Circuit 300 can be referred to as common-mode because the biasing is equally applied to each of the differential branches 302a and 302b of the mixer.

[0023] A constant current bias can be used to maintain a minimum gm3 throughout the process. Prior to the gm stage 306 of circuit 300 can be a second-order biquad filter 308 and a digital-to-analog converter (DAC), which can provide an input DAC current to the filter 308 and / or the bias circuit 304. In some cases, the filter 308 can be included as part of the bias circuit 304. Additionally, maximizing the DAC headroom can minimize the distortion caused by compression at the DAC output. In certain embodiments, maximizing the DAC margin can prevent the common-mode voltage at the DAC output from exceeding a specific voltage level such that the maximum signal swing present at the DAC transistors does not enter the triode region which can cause signal distortion. Since the voltage levels for minimizing gm3 and maximizing the DAC margin may be different, a common-mode voltage offset needs to be created between the DAC and the gm stage. The common-mode biasing structure can achieve the common-mode voltage offset by providing current through transistors P1 and P2, and the desired level shift can be achieved through resistors R3 and R4. Transistors P1 and P2 can be pFET transistors. Alternatively, transistors P1 and P2 can be implemented as nFETs in parallel with the Rdac resistor. Additionally, the current can be from a programmable current source 310. The current can be referenced to the programmable current source 310, which is invariant over process and temperature. Thus, the bias circuit 304 can hold the DC operating point of the gm stage 306 at a point that keeps gm3 at 0 or within a threshold variance that achieves the desired distortion minimization (e.g., -70 or -80 dBc) over the entire process and temperature range while reducing the third harmonic distortion of the signal to be transmitted. The bias circuit 304 can hold the DC operating point of the gm stage 306 at a point that keeps gm3 at 0 within a specific temperature range. The specific temperature range is typically -40 to 110 °C. However, other temperature ranges are possible.

[0024] It is necessary to determine the voltage offset that minimizes gm3 without affecting the signal current at the gm level (opposite to the DC bias current). In other words, when the gm level is receiving a signal for transmission, it is necessary to maintain the integrity of the transmitted signal and not take actions that may change the signal. Therefore, in order to analyze or measure the signal of the gm level without modifying the signal, the circuit 300 can replicate the gm level with the gm-level replication circuit 312, so as to compare the current in the gm-level replication circuit 312 with the reference current, and modify the voltage shift voltage to maintain a fixed current in the replication circuit 312 without affecting the gm level 306. Since by design, the replication circuit 312 is an exact copy of the gm level 306, the gm level 306 can maintain the same constant current, which helps to keep gm3 = 0 throughout the process. In addition, the common-mode signal current generated by the replication circuit 312 is the same as the common-mode signal current generated by the gm level 306. As described above, the reference current can be obtained from the programmable current source 310. The current absorbed by the replicated gm level 312 compared with the reference current can be obtained from the bias voltage generated by the current flowing through the resistors R3 and R4, and this current is obtained from the DAC current source and P3.

[0025] Although the circuit 300 can reduce HD3 and IMD3 distortions, in some cases, the circuit 300 may inject flicker noise from the pMOS current sources P1 and P2. Since the flicker noise from P1 and P2 may be statistically independent, in some cases, the differential noise will be the sum of the flicker noises of P1 and P2. Flicker noise is a low-frequency noise that can be generated by MOSFET devices. It is sometimes called 1 / f noise or pink noise. Flicker noise in a zero-intermediate-frequency (ZIF) transmitter (TX) generates unwanted in-band radiation, and minimizing this noise is a major challenge for cellular transceivers. For the present design shown in the circuit 300, it is desired to reduce the flicker noise from P1 and P2 to 0 to meet the in-band emission requirements for 5G single-band time-division duplex (TDD) applications.

[0026] The present disclosure includes systems and methods for ensuring that the flicker noise from the TX baseband path bias circuit is common-mode and thus will not be converted to RF by the TX mixer 302. Figure 4 A non-limiting example of a ZIF TX path with reduced differential flicker noise in a common-mode biasing scheme is illustrated. Figure 4The circuit 400 replaces the current source structure (e.g., P1 and P2) of the circuit 300 in the bias circuit 304 with a single pMOS source P3 in the bias circuit 410 that is commonly connected to the gm stage 306. Thus, no differential flicker noise is generated. In other words, although the transistor P3 may generate flicker noise, since the gm stage 306 is a differential structure, the flicker noise is common-mode noise that is canceled by the mixer 302. Generally, no common-mode signal can pass through a perfectly balanced mixer. By using a single transistor 402, the biasing of the two gm-stage transistors is the same, thus eliminating the flicker noise. Therefore, the circuit 400 can both minimize HD3 and IMD3 distortion and reduce or eliminate flicker noise. In addition, similar to the bias circuit 304, the bias circuit 410 can maintain the DC operating point of the gm stage 306 at a point that keeps gm3 at 0 or close to 0, or at a point that keeps the third harmonic distortion of the signal to be transmitted at or below 70 dBc over the entire process and temperature range.

[0027] In addition, the circuit 400 includes additional resistor pairs R1 and R2. In the case where the two resistors R1 and R2 do not introduce any flicker noise or generate a sub-threshold amount of flicker noise, the entire circuit helps to reduce the differential flicker noise level. In some cases, the differential flicker noise generated by the entire circuit is much lower than the LTE emission standard. For example, the differential flicker noise of the circuit 400 can be equal to or lower than -15 dBm / MHz. The resistors R1 and R2 can be configured to not generate flicker noise or generate less than a threshold amount of flicker noise by appropriately adjusting the size of the resistors. Generally, resistors with large width and length are used to reduce flicker and improve matching. For example, in some non-limiting embodiments, the resistors R1 and R2 can be selected to be at least 3 times the size of the resistors R3 and R4. It should be understood that other resistor sizes can be used in the context of the present disclosure. Generally, the values of R1 and R2 are the same. In addition, the resistors R1 and R2 can be carefully selected for matching to account for any differences in layout, location, and physical design aspects to ensure that the current flowing through R1 and R2 is the same, so that the flicker noise can be canceled by the balanced mixer stage 302. R1 and R2 can be matched by adjusting the size or length of the resistors, the layout, or other characteristics of the resistors. In addition, since R1 and R2 are selected to be much larger than the filter resistors R3 and R4, the impact of any thermal noise generated is minimal. For example, the resistors R1 and R2 can be approximately 10 times the size of the resistors R3 and R4.

[0028] The common-mode bias circuit 400 can use the filter resistors Rdac, R3, and R4 to generate a bias voltage and a DAC current for the gm stage 306. The DAC current source 404 can provide a signal to be transmitted together with the DC common-mode value. This signal can be superimposed on a specific DC common-mode current. For example, the signal can be centered around the mid-rail current. Two DAC current sources 404 can provide the same signal but with opposite phases. The signal generated from the DAC 406 can be a differential signal that is above or amplitude-shifted by the DC common-mode signal. This DC signal is part of the bias signal and the DC common-mode signal generated by embodiments of the circuits described herein.

[0029] Rdac, R3, and R4 can form part of a filter 308 applied to the input signal. This filter 308 can be composed of two filters 408 that can have similar or identical configurations. Although these filters 408 can be separate from the bias circuit 410, it can form part of the bias circuit 410 or function together with the bias circuit 410. In other words, the DAC current and the resistors R3 and R4 can generate a bias signal that can be provided to the gm stage 306. However, it is desired to bias at the point where gm3 equals 0. An additional circuit including the programmable current source 310, the transistor P3 (or transistors P1 and P2 in the circuit 300), the replica circuit 312, and the resistors R1 and R2 can form an additional bias circuit that can be used to adjust the bias provided to the gm stage 306 to remove gm3 non-linearity such that gm3 is zero.

[0030] The programmable current source 310 can be programmed to account for the gm3 value. Since it is not precisely known what bias value will give gm3 = 0 when manufacturing the transmit circuit including the mixer 302 and the gm stage 306, a programmable current source can be used so that the bias circuit 410 can be fine-tuned to provide an appropriate level of bias current such that gm3 is zero. Thus, when designing and / or manufacturing the transmit circuit, the transmit circuit can be tested to determine the bias current applied to the gm stage that results in gm3 equal to 0. Once this bias current is determined, the programmable current source 310 can be programmed to provide a current that, together with the DAC current, satisfies the determined bias current.

[0031] To further facilitate the search for the gm3 = 0 point, the circuit can include a programmable current source 310 that maintains a programmable multiple of a reference current in the replica circuit 312. The programmable current source 310 can be adjusted for the optimal operating point since the exact bias current for gm3 = 0 is not known a priori and may depend on several factors including layout parasitics. Although not limited to this, in some implementations, the filter 408 can be implemented or designed using a Sallen-key. However, discrete resistors can also be used.

[0032] Circuits 300 and 400 are common-mode circuits. The common-mode signal can be obtained by averaging the differential signals from the two DAC currents. The resistor R5 in circuits 300 and 400 enables the DAC currents to be averaged to obtain the common-mode signal provided to the gm stage. The DAC common-mode current is obtained from the DAC current source and the common-mode current is generated by circuits 300 and 400. Averaging the differential signals causes the differential signals to become zero leaving the desired common-mode signal.

[0033] Circuits 300 and 400 are non-limiting examples of circuits for generating a bias voltage that reduces distortion attributed to gm3. Other embodiments are possible. For example, the way of generating the level-shifting voltage (e.g., the difference between the input common-mode from the DAC and the desired bias voltage) can be different. For example, the current from P3 (or P1 and P2 in circuit 300) can flow through different groups of resistor combinations. As another example, the loop using the reference current and the replica circuit can be arranged in a different way, or the replica circuit can be eliminated by directly using the gm stage. Similarly, there may be no DAC before the gm stage, but instead there may be some other circuit before it, which may or may not provide the common-mode current. Therefore, this common-mode circuit may need to provide all the bias voltages.

[0034] The output of mixer 302 can be fed to a variable gain amplifier (VGA) 412. The output of VGA 412 can be provided to a power amplifier or a power amplifier module including one or more power amplifiers. The input of circuit 400 can be an analog signal generated by DAC 406 in response to a differential digital input. Additionally, the input signal of circuit 300 or 400 can be a low-frequency baseband signal. For LTE and many millimeter-wave applications, such a low-frequency baseband signal is typically less than 500 MHz. Therefore, AC coupling capacitors may not be used in the signal path leading to the gm stage, which may block the low-frequency baseband signal used by the transmitter. However, in some embodiments, other filter designs are possible.

[0035] Furthermore, as mentioned previously, circuits 300 and / or 400 can be part of the transmitter path. This transmitter path can be at least partially implemented in a front-end module (FEM) that can communicate with an antenna switch module and / or an antenna. For example, the power amplifier receiving the output of VGA 412 can be part of the FEM that communicates with the antenna of the wireless device. The antenna can be configured to transmit the transmission signal of the wireless device.

[0036] Terms and Conclusions

[0037] The foregoing description may refer to an element or feature as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that an element / feature is directly or indirectly connected to another element / feature and not necessarily a mechanical connection. Similarly, unless expressly stated otherwise, “coupled” means that an element / feature is directly or indirectly coupled to another element / feature and not necessarily a mechanical coupling. Thus, although the various schematic diagrams shown in the figures depict example arrangements of elements and components, additional intermediate elements, devices, features, or components may exist in actual embodiments (assuming that the functionality of the depicted circuitry is not adversely affected).

[0038] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in many other forms; furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in many different ways. Any suitable combination of the elements and acts of the various embodiments described above may be combined to provide further embodiments.

[0039] Unless otherwise specifically stated, conditional language such as “can,” “could,” etc., is otherwise understood in context as typically being used to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and / or steps. Thus, such conditional language is generally not intended to imply that one or more embodiments in any way require the presence of features, elements, and / or steps, or that one or more embodiments necessarily include logic for deciding, with or without user input or prompting, whether to include or execute such features, elements, and / or steps in any particular embodiment.

[0040] Unless otherwise specifically stated, disjunctive language such as the phrase “at least one of X, Y, or Z” should be understood in context as typically being used to mean that items, terms, etc., may be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended nor should it be construed to imply that certain embodiments require the presence of at least one of each of X, at least one of Y, and at least one of Z.

[0041] Any process descriptions, elements, or blocks in the flowcharts described herein and / or depicted in the drawings are to be understood as potentially representing portions of modules, segments, or code that include one or more executable instructions for implementing specific logical functions or elements in a process. Alternative implementations are included within the scope of the embodiments described herein, where elements or functions may be deleted, executed out of order from that shown or discussed, including substantially concurrently or in reverse order, as would be understood by one of ordinary skill in the art, depending on the functionality involved.

[0042] Unless otherwise expressly stated, articles such as "a" or "an" shall generally be construed to include one or more of the items described. Thus, phrases such as "a device configured to" are intended to include one or more of the recited devices. Such one or more recited devices may also be jointly configured to perform the recited operations. For example, "a processor configured to perform operations A, B, and C" may include a first processor configured to perform operation A working in cooperation with a second processor configured to perform operations B and C.

[0043] It should be emphasized that many variations and modifications can be made to the above-described embodiments, with the elements being understood as other acceptable examples. All such modifications and variations are intended to be included within the scope of the present disclosure and protected by the following claims.

Claims

1. A transmitter, comprising: A mixer; A transconductance stage connected to the mixer; And A bias circuit connected to the transconductance stage, the bias circuit comprising: A programmable current source configured to provide a reference current; A copy circuit connected between the programmable current source and the transconductance stage, the copy circuit being configured to copy the DC bias of the transconductance stage; and A bias transistor connected to the copy circuit and the transconductance stage, the bias transistor being configured to level-shift a bias signal obtained from a signal source based on the reference current and the DC bias of the transconductance stage.

2. The transmitter according to claim 1, wherein the transconductance stage comprises a pair of nFETs connected as a differential pair.

3. The transmitter according to claim 1, wherein the mixer is a double-balanced mixer or a Gilbert cell mixer.

4. The transmitter according to claim 1, wherein the bias circuit comprises a second bias transistor configured to level-shift a second bias signal.

5. The transmitter according to claim 4, wherein the phase of the bias signal and the phase of the second bias signal are the same as the phase of the DC bias.

6. The transmitter according to claim 4, wherein the bias signal is provided to a first transistor of the transconductance stage, and the second bias signal is provided to a second transistor of the transconductance stage.

7. The transmitter according to claim 1, further comprising a filter before the bias circuit.

8. The transmitter according to claim 7, wherein the filter comprises a differential Sallen-Key filter.

9. The transmitter according to claim 1, wherein the bias circuit further comprises a pair of matched resistors, wherein a first resistor of the pair of matched resistors is configured to provide a bias signal to a first transistor of the transconductance stage, and a second resistor of the pair of matched resistors is configured to provide a bias signal to a second transistor of the transconductance stage.

10. The transmitter according to claim 1, further comprising an averaging circuit configured to average a first digital-to-analog converter (DAC) current and a second DAC current to obtain an average DAC current, wherein the average DAC current is provided as an input to the transconductance stage.

11. The transmitter according to claim 1, wherein the signal source comprises a DAC current source.

12. The transmitter according to claim 1, wherein the bias circuit holds the DC operating point of the transconductance stage at a level that maintains the third derivative of the current (gm3) over the entire temperature range.

13. A wireless device, comprising: An antenna configured to transmit a transmission signal; And A transmitter in communication with the antenna, the transmitter comprising: A mixer; A transconductance stage connected to the mixer; and A bias circuit connected to the transconductance stage, the bias circuit comprising: A programmable current source configured to provide a reference current; A copy circuit connected between the programmable current source and the transconductance stage, the copy circuit being configured to copy the DC signal of the transconductance stage; and A bias transistor, connected to the replica circuit and the transconductance stage, the bias transistor being configured to level-shift a bias signal obtained from a signal source based on the reference current and a DC signal of the transconductance stage.

14. The wireless device of claim 13, wherein the bias circuit includes a second bias transistor configured to level-shift a second bias signal.

15. The wireless device of claim 14, wherein the phase of the bias signal and the phase of the second bias signal are the same as the phase of the DC signal.

16. The wireless device of claim 14, wherein the bias signal is provided to a first transistor of the transconductance stage, and the second bias signal is provided to a second transistor of the transconductance stage.

17. The wireless device of claim 13, further comprising a Sallen-Key filter before the bias circuit.

18. The wireless device of claim 13, wherein the bias circuit further includes a pair of matched resistors, wherein a first resistor of the pair of matched resistors is configured to provide a bias signal to a first transistor of the transconductance stage, and a second resistor of the pair of matched resistors is configured to provide a bias signal to a second transistor of the transconductance stage.

19. The wireless device of claim 13, further comprising an averaging circuit configured to average a first digital-to-analog converter (DAC) current and a second DAC current to obtain an average DAC current, wherein the average DAC current is provided as an input to the transconductance stage.

20. A method for transmitter biasing, the method comprising: generating a reference current using a programmable current source; using a replica circuit connected between the programmable current source and the transconductance stage to replicate a DC signal of the transconductance stage, the transconductance stage being connected to a mixer; obtaining a bias signal from a signal source; and using a bias transistor connected to the replica circuit and the transconductance stage to level-shift the bias signal based on the reference current and the DC signal.

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