An improved cascade low-noise and low-power dynamic comparator

Abstract

The present invention discloses an improved cascade low-noise and low-power dynamic comparator, belonging to the field of integrated circuit design. The comparator comprises: a reset unit connected to the output end of a differential input amplifier unit to reset the output end of the differential input amplifier unit; the differential input amplifier unit comprises a cascade input structure, the control end of the cascade input structure is connected to a tail current source control unit, the output end of the cascade input structure is connected to a latch unit for receiving a differential input signal, amplifying the differential input signal multiple times through the cascade input structure to obtain a differential amplified signal, and outputting the differential amplified signal to the latch unit; the tail current source control unit provides a stable current to the differential input amplifier unit; the latch unit receives the differential amplified signal and establishes a latch to output a differential output signal. The present invention can improve comparison speed while reducing power consumption while achieving low noise.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and in particular relates to an improved cascade low-noise and low-power dynamic comparator. Background Art

[0002] The analog-to-digital converter (ADC) is a crucial electronic component responsible for converting continuously changing analog information into discrete digital information that can be recognized and processed by computers, microprocessors, or digital systems. Comparators, an essential component of ADCs, are used in successive approximation register (SAR) ADCs, pipeline ADCs, and delta-sigma ADCs. Applications in medical electronics, aerospace, automotive electronics, and advanced instrumentation often require high ADC precision, necessitating a low-noise comparator.

[0003] Currently, existing technologies often significantly increase the power consumption of comparators or limit their bandwidth while reducing the noise of comparators. Figure 1 The figure shows a traditional double-tail dynamic comparator. The comparator consists of two stages. The lower half is the pre-amplifier stage and the upper half is the regenerative latch stage. When CLK is low, is high, at this time, M3 and M4 tubes are turned on, fp node and fn node are charged to VDD, MR1 tube and MR2 tube are turned on, at the same time, because When CLK is high, the Mtail2 tube is turned off, and the Outn node and the Outp node are discharged to zero. This is the reset phase. When CLK is high, the comparison phase begins. At this time, the Mtail2 tube is turned on, so the M1 tube and the M2 tube begin to discharge the fp node and the fn node until the MR1 tube / MR2 tube conduction threshold is reached. Figure 1 In the figure, INN and INP are input signals, and the difference between them will make the discharge speed of M1 and M2 different. Assuming INP>INN, the discharge speed of M2 is faster than that of M1, so MR2 will be cut off before MR1. is low, so the Mtail2 tube is turned on, and the M7 and M8 tubes charge the Outn and Outp nodes, so the Outp node is charged to a high level first. In addition, if the voltage between the Outp and Outn nodes is greater than the threshold of the second-stage latch, the second-stage latch will be triggered, further speeding up the comparison process. This structure reduces the kickback noise and offset of the second-stage latch by introducing a pre-amplifier stage. In addition, in order to obtain better noise performance, this structure increases Figure 1The capacitor C Lfp and capacitor C Lfn , to reduce the noise of the first stage, but this approach will obviously reduce the bandwidth of the comparator and increase its power consumption. Figure 2 The figure shows a CI dynamic comparator, which consists of two stages. The first stage adopts a cascade input stage structure. This structure can increase the gain of the pre-amplifier stage and further reduce the noise of the second stage. At the same time, the noise of the pre-amplifier stage will also decrease as the number of input tube cascades increases. Its equivalent input noise is expressed as: where σ one is the input-referred noise of the input pair (single stage), σ latch is the input-referred noise of the latch stage (SR Latch), A input is the gain of the preamplifier stage, and S is the number of cascaded stages. For an ideal latch stage (no noise), the noise performance of the comparator improves by a factor of sqrt(S); when there is noise in the latch stage, the latch stage noise dominates, and the noise performance of the comparator improves by a factor of S; Figure 3 As shown, in this CI dynamic comparator, transistors M1p and M1n turn on, beginning to discharge Vop1 and Von1 until either M2p or M2n turns on. At this point, the voltage difference between Vop1 and Von1 is ΔV. After ΔT1, the other transistor, M2p or M2n, also turns on. Therefore, when either M3p or M3n turns on, the voltage difference between Vop2 and Von2 is equal to 2ΔV. The time it takes for both M3p and M3n to turn on is ΔT1 + ΔT2, and the voltage difference between Vop3 and Von3 is 3ΔV. M3p and M3n then discharge until all the MOS transistors in the latch stage turn on or off, a time period of ΔT1 + ΔT2 + ΔT3. This structure triples the voltage amplified compared to a single-input pair transistor as the input stage, improving the comparator's response speed. At the same time, since its integration time is also increased, its noise is also reduced. However, compared with the traditional method of adding capacitors at the output node of the large stage, this structure can only reduce the noise of the input to the tube, but cannot reduce the noise of the latch stage.

[0004] In the aforementioned prior art, the CI dynamic comparator pulls the Vop1 & Von1, Vop2 & Von2, and Vop3 & Von3 nodes completely low after each comparison. This requires recharging these nodes to VDD during each reset phase, resulting in unnecessary power loss. Furthermore, for transistors MR1 ​​and MR2 in a conventional double-tail dynamic comparator, since the output nodes of the pre-comparison stage are pulled very low during the amplification phase, these two transistors will not be fully conductive, or may even be cut off. Consequently, during the latch phase, the effective transconductance of MR1 and MR2 cannot be effectively utilized, resulting in a waste of resources. Summary of the Invention

[0005] The object of the present invention is to provide an improved cascade low-noise and low-power dynamic comparator, which can improve the comparison speed and reduce power consumption while achieving low noise.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, an improved cascade low-noise and low-power dynamic comparator includes:

[0008] a reset unit connected to the output end of the differential input amplifying unit, configured to receive an inverted clock control signal and reset the output end of the differential input amplifying unit according to the inverted clock control signal;

[0009] A differential input amplifier unit, comprising a cascade input structure, wherein a control end of the cascade input structure is connected to a tail current source control unit, and an output end of the cascade input structure is connected to a latch unit, and is configured to receive a differential input signal, amplify the differential input signal multiple times through the cascade input structure to obtain a differential amplified signal, and output the differential amplified signal to the latch unit;

[0010] a tail current source control unit, configured to receive a clock control signal and provide a stable current to the differential input amplification unit according to the clock control signal;

[0011] The latch unit is used to receive the differential amplified signal and output a differential output signal after establishing a latch.

[0012] In some embodiments, the differential input amplification unit includes a PMOS transistor M1, a PMOS transistor M2, and a cascade input structure;

[0013] The sources of the PMOS tube M1 and the PMOS tube M2 are respectively connected to the tail current source control unit, the gate of the PMOS tube M1 is connected to the positive input signal VP, the gate of the PMOS tube M2 is connected to the negative input signal VN, and the drains of the PMOS tube M1 and the PMOS tube M2 are connected to the cascade input structure.

[0014] In some embodiments, the cascade input structure includes: a PMOS transistor M3, a PMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, and an NMOS transistor M8;

[0015] The gate of the PMOS transistor M3 is connected to the positive input signal VP, the gate of the PMOS transistor M4 is connected to the negative input signal VN, the source of the PMOS transistor M3 is connected to the drain of the PMOS transistor M1, the drain of the NMOS transistor M5 and the gate of the NMOS transistor M6, the source of the PMOS transistor M4 is connected to the drain of the PMOS transistor M2, the drain of the NMOS transistor M6 and the gate of the NMOS transistor M5, the drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M7 and the gate of the NMOS transistor M8, the drain of the PMOS transistor M4 is connected to the drain of the NMOS transistor M8 and the gate of the NMOS transistor M7, and the sources of the NMOS transistors M5, M6, M7 and M8 are respectively connected to the power supply.

[0016] In some embodiments, the reset unit includes a first switch, a second switch, a third switch, and a fourth switch;

[0017] The input end of the reset unit is connected to the inverted clock control signal, a node on2 is formed between the drain of the PMOS transistor M3 and the gate of the NMOS transistor M8, a node op2 is formed between the drain of the PMOS transistor M4 and the gate of the NMOS transistor M7, a node on1 is formed between the source of the PMOS transistor M3, the drain of the PMOS transistor M1 and the gate of the NMOS transistor M6, and a node op1 is formed between the source of the PMOS transistor M4, the drain of the PMOS transistor M2 and the gate of the NMOS transistor M5;

[0018] The first switch is connected to a node no2, the second switch is connected to a node on1, the third switch is connected to a node op1, and the fourth switch is connected to a node op2.

[0019] In some embodiments, the tail current source control unit includes: a PMOS transistor M9, a PMOS transistor Msw1, and a PMOS transistor Msw2;

[0020] The source of the PMOS transistor M9 is grounded, the gate of the PMOS transistor M9 is connected to the clock control signal, the drain of the PMOS transistor M9 is connected to the sources of the PMOS transistors Msw1 and Msw2, the drain of the PMOS transistor Msw1 is connected to the source of the PMOS transistor M1, the drain of the PMOS transistor Msw2 is connected to the source of the PMOS transistor M2, the gate of the PMOS transistor Msw1 is connected to the node op2, and the gate of the PMOS transistor Msw2 is connected to the node on2.

[0021] In some embodiments, when the clock control signal is at a low level, the inverted clock control signal is at a high level, and when the clock control signal is at a high level, the inverted clock control signal is at a low level.

[0022] When the clock control signal is at a high level, the tail current source control unit provides a stable current to the differential input amplification unit.

[0023] In some embodiments, when the inverted clock control signal is at a high level, the reset unit resets the output end of the differential input amplification unit.

[0024] In a second aspect, a control method of the dynamic comparator as described above comprises the following steps:

[0025] A low-level clock control signal is input to the tail current source control unit to turn off the PMOS transistor M9, and an inverted clock control signal is input to the reset unit. After the first switch, the second switch, the third switch, and the fourth switch are closed, the nodes on2, on1, op1, and op2 are reset to high levels respectively;

[0026] A high-level clock control signal is input to the tail current source control unit to turn on the PMOS transistor M9. At this time, the inverted clock control signal is at a low level, the first switch, the second switch, the third switch, and the fourth switch are turned off, and the nodes on2 and op2 remain at a high level. After the PMOS transistors Msw1 and Msw2 are turned on, the PMOS transistors M1 and M2 discharge the nodes on1 and op1.

[0027] If the positive input signal VP is greater than the negative input signal VN, the discharge speed of the PMOS tube M1 is greater than the discharge speed of the PMOS tube M2, the PMOS tube M3 is turned on before the PMOS tube M4, the NMOS tube M6 is turned on, and the NMOS tube M5 is turned off, thereby increasing the voltage between the node on1 and the node op1, the NMOS tube M8 is turned on, and the NMOS tube M7 is turned off, thereby increasing the voltage between the node on2 and the node op2;

[0028] According to the voltage between the node on2 and the node op2, the latch unit quickly establishes latching and outputs a differential output signal.

[0029] In some embodiments, the following steps are further included:

[0030] If the negative input signal VN is greater than the positive input signal VP, the discharge speed of the PMOS transistor M2 is greater than the discharge speed of the PMOS transistor M1, the PMOS transistor M4 is turned on before the PMOS transistor M3, the NMOS transistor M5 is turned on, and the NMOS transistor M6 is turned off, thereby increasing the voltage between the node on1 and the node op1, the NMOS transistor M7 is turned on, and the NMOS transistor M8 is turned off, thereby increasing the voltage between the node on2 and the node op2;

[0031] According to the voltage between the node on2 and the node op2, the latch unit quickly establishes latching and outputs a differential output signal.

[0032] An analog-to-digital converter uses the improved cascade low-noise and low-power dynamic comparator.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention provides an improved cascade low-noise and low-power dynamic comparator. When the dynamic comparator does not need to make comparisons, the present invention can turn off the current source through a reset unit and a tail current source control unit, thereby reducing static power consumption and achieving low-power operation. At the same time, a cascade input structure is adopted in the differential input amplification unit to amplify the differential input signal multiple times, which can quickly respond to changes in the differential input signal and reduce noise interference during the transmission and amplification process of the signal, thereby achieving low noise, improving the comparison speed and reducing power consumption.

[0035] Furthermore, the present invention uses NMOS transistors M5, M6, M7, and M8 to improve the dynamic comparator, thereby achieving regulation of nodes op1, on1, on2, and op2, avoiding unnecessary node charging and discharging processes, and saving power consumption of the comparator. At the same time, NMOS transistors M5, M6, M7, and M8 increase the output voltage of the pre-amplifier stage, have more superior noise performance, and can improve the latching speed of the second-stage latch unit.

[0036] Furthermore, the present invention introduces the PMOS transistor Msw1 and the PMOS transistor Msw2 to avoid potential risks of a power-to-ground path and achieve lower power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural diagram of a traditional double-tail dynamic comparator;

[0038] Figure 2 It is a structural diagram of CI dynamic comparator;

[0039] Figure 3 This is the working principle diagram of the CI dynamic comparator;

[0040] Figure 4 A schematic structural diagram of the improved cascade low-noise and low-power dynamic comparator provided in Example 1;

[0041] Figure 5 This is a schematic diagram of the structure of the latch used in Example 1. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings. The content described is intended to explain rather than limit the present invention.

[0043] It should be noted that the terms "including" and "having" and any variations thereof in the description and claims of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, systems, products or apparatus.

[0044] Example 1

[0045] like Figure 4 As shown, this embodiment provides an improved cascade low-noise and low-power dynamic comparator, which consists of two stages: a pre-amplifier stage and a latch stage. The pre-amplifier stage adopts a cascade input structure to obtain better noise performance;

[0046] The pre-amplifier stage includes: a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, an NMOS transistor M8, a first switch, a second switch, a third switch, a fourth switch, a PMOS transistor M9, a PMOS transistor Msw1, and a PMOS transistor Msw2;

[0047] The gate of the PMOS transistor M3 is connected to the positive input signal VP, the gate of the PMOS transistor M4 is connected to the negative input signal VN, the source of the PMOS transistor M3 is connected to the drain of the PMOS transistor M1, the drain of the NMOS transistor M5, and the gate of the NMOS transistor M6, the source of the PMOS transistor M4 is connected to the drain of the PMOS transistor M2, the drain of the NMOS transistor M6, and the gate of the NMOS transistor M5, the drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M7 and the gate of the NMOS transistor M8, the drain of the PMOS transistor M4 is connected to the drain of the NMOS transistor M8 and the gate of the NMOS transistor M7, and the sources of the NMOS transistors M5, M6, M7, and M8 are respectively connected to the power supply;

[0048] A node on2 is formed between the drain of the PMOS transistor M3 and the gate of the NMOS transistor M8, a node op2 is formed between the drain of the PMOS transistor M4 and the gate of the NMOS transistor M7, a node on1 is formed between the source of the PMOS transistor M3, the drain of the PMOS transistor M1 and the gate of the NMOS transistor M6, and a node op1 is formed between the source of the PMOS transistor M4, the drain of the PMOS transistor M2 and the gate of the NMOS transistor M5;

[0049] The first switch is connected to the node no2, the second switch is connected to the node on1, the third switch is connected to the node op1, and the fourth switch is connected to the node op2;

[0050] The source of the PMOS transistor M9 is grounded, the gate of the PMOS transistor M9 is connected to the clock control signal, the drain of the PMOS transistor M9 is connected to the sources of the PMOS transistors Msw1 and Msw2, the drain of the PMOS transistor Msw1 is connected to the source of the PMOS transistor M1, the drain of the PMOS transistor Msw2 is connected to the source of the PMOS transistor M2, the gate of the PMOS transistor Msw1 is connected to the node op2, and the gate of the PMOS transistor Msw2 is connected to the node on2;

[0051] like Figure 5 As shown, a latch structure of the latch stage is shown. During the comparison phase, the nodes op2 and on2 will continue to decrease, and the MOS transistors MR1 ​​and MR2 will be completely turned off. However, the dynamic comparator of this embodiment can ensure that one side of the MOS transistors can always remain turned on during the comparison process. This has the advantage that the effective transconductance of the MOS transistors MR1 ​​and MR2 can be effectively utilized by the latch stage, thereby accelerating the latching speed of the second stage.

[0052] This embodiment adopts a two-stage cascade connection. When the clock CLK is at a low level, the comparator is reset, the tail current source M9 is turned off, and at the same time, CLKN is at a high level, the switch is closed, and the op1 node & on1 node and the op2 node & on2 node are reset to a high level.

[0053] When the clock CLK is high, a comparison is performed, CLKN is low, and the switch is turned off. At this time, the tail current source M9 is turned on. At the same time, because the op2 node and the on2 node are reset to a high level, the PMOS transistors Msw1 and Msw2 remain turned on, and the PMOS transistors M1 and M2 begin to discharge the op1 node and the on1 node. Since the differential input terminal VP and the differential input terminal VN are different in size, the discharge speeds are also different. If the differential input terminal VP> the differential input terminal VN, the discharge speed of the PMOS transistor M1 will be faster than the discharge speed of the PMOS transistor M2. Therefore, the PMOS transistor M3 will be turned on before the PMOS transistor M4. If the turn-on threshold of the NMOS transistor M6 is also reached at the same time, the NMOS transistor M6 will pull up the op1 node, causing the NMOS transistor M5 to be further turned off, thereby increasing the voltage difference between op1 and on1. Therefore, the PMOS tube M3 will be turned on more completely, while the PMOS tube M4 cannot be fully turned on or even turned off due to the NMOS tube M6. Therefore, the NMOS tube M8 will be turned on and the NMOS tube M7 will be turned off, further forming positive feedback, thereby increasing the voltage difference between op2 and on2. The voltage difference between op2 and on2 can enable the latch stage to quickly establish a latch, thereby speeding up the comparison speed.

[0054] If the differential input terminal VN > the differential input terminal VP, the discharge rate of PMOS transistor M2 will be faster than the discharge rate of PMOS transistor M1. Therefore, PMOS transistor M4 will turn on before PMOS transistor M3. If the conduction threshold of NMOS transistor M5 is also reached at the same time, NMOS transistor M5 will pull up the op1 node, causing NMOS transistor M6 to further turn off, thereby increasing the voltage difference between op1 and on1. As a result, PMOS transistor M4 will turn on more completely, while PMOS transistor M3 will not be fully turned on due to NMOS transistor M5, or may even turn off. Therefore, NMOS transistor M7 will turn on, and NMOS transistor M8 will be turned off, further forming positive feedback, thereby increasing the voltage difference between op2 and on2. The voltage difference between op2 and on2 enables the latch stage to quickly establish a latch, accelerating the comparison speed.

[0055] Example 2

[0056] This embodiment provides an improved cascade low-noise and low-power dynamic comparator, comprising: a reset unit, a differential input amplification unit, a tail current source control unit, and a latch unit;

[0057] The reset unit is connected to the output end of the differential input amplifying unit, and is used to receive an inverted clock control signal and reset the output end of the differential input amplifying unit according to the inverted clock control signal;

[0058] The differential input amplifier unit includes a cascade input structure, a control end of the cascade input structure is connected to the tail current source control unit, and an output end of the cascade input structure is connected to the latch unit, and is used to receive a differential input signal, and obtain a differential amplified signal after amplifying the differential input signal multiple times through the cascade input structure, and output the differential amplified signal to the latch unit;

[0059] The tail current source control unit is used to receive a clock control signal and provide a stable current to the differential input amplification unit according to the clock control signal;

[0060] The latch unit is used to receive the differential amplified signal and output a differential output signal after establishing a latch;

[0061] When the clock control signal is at a low level, the corresponding inverted clock control signal is at a high level; when the clock control signal is at a high level, the corresponding inverted clock control signal is at a low level;

[0062] When the clock control signal is at a high level, the tail current source control unit provides a stable current to the differential input amplifying unit; when the inverted clock control signal is at a high level, the reset unit resets the output end of the differential input amplifying unit;

[0063] The control method of the dynamic comparator includes the following steps: inputting a low-level clock control signal to the tail current source control unit to turn off the PMOS transistor M9, and simultaneously inputting an inverted clock control signal to the reset unit, so that after the first switch, the second switch, the third switch, and the fourth switch are closed, the nodes on2, on1, op1, and op2 are reset to high levels respectively;

[0064] A high-level clock control signal is input to the tail current source control unit to turn on the PMOS transistor M9. At this time, the inverted clock control signal is at a low level, the first switch, the second switch, the third switch, and the fourth switch are turned off, and the nodes on2 and op2 remain at a high level. After the PMOS transistors Msw1 and Msw2 are turned on, the PMOS transistors M1 and M2 discharge the nodes on1 and op1.

[0065] If the positive input signal VP is greater than the negative input signal VN, the discharge speed of the PMOS tube M1 is greater than the discharge speed of the PMOS tube M2, the PMOS tube M3 is turned on before the PMOS tube M4, the NMOS tube M6 is turned on, and the NMOS tube M5 is turned off, thereby increasing the voltage between the node on1 and the node op1, the NMOS tube M8 is turned on, and the NMOS tube M7 is turned off, thereby increasing the voltage between the node on2 and the node op2; if the negative input signal VN is greater than the positive input signal VP, the discharge speed of the PMOS tube M2 is greater than the discharge speed of the PMOS tube M1, the PMOS tube M4 is turned on before the PMOS tube M3, the NMOS tube M5 is turned on, and the NMOS tube M6 is turned off, thereby increasing the voltage between the node on1 and the node op1, the NMOS tube M7 is turned on, and the NMOS tube M8 is turned off, thereby increasing the voltage between the node on2 and the node op2;

[0066] According to the voltage between the node on2 and the node op2, the latch unit quickly establishes latching and outputs a differential output signal;

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered by the scope of protection of the claims of the present invention.

Claims

1. An improved cascade low-noise and low-power dynamic comparator, characterized in that: include: a reset unit connected to the output end of the differential input amplifying unit, configured to receive an inverted clock control signal and reset the output end of the differential input amplifying unit according to the inverted clock control signal; A differential input amplifier unit, comprising a cascade input structure, wherein a control end of the cascade input structure is connected to a tail current source control unit, and an output end of the cascade input structure is connected to a latch unit, and is configured to receive a differential input signal, amplify the differential input signal multiple times through the cascade input structure to obtain a differential amplified signal, and output the differential amplified signal to the latch unit; a tail current source control unit, configured to receive a clock control signal and provide a stable current to the differential input amplification unit according to the clock control signal; A latch unit, configured to receive the differential amplified signal and output a differential output signal after establishing a latch; The differential input amplification unit includes a PMOS tube M1, a PMOS tube M2 and a cascade input structure; The sources of the PMOS transistors M1 and M2 are respectively connected to the tail current source control unit, the gate of the PMOS transistor M1 is connected to the positive input signal VP, the gate of the PMOS transistor M2 is connected to the negative input signal VN, and the drains of the PMOS transistors M1 and M2 are connected to the cascade input structure; The cascade input structure includes: a PMOS tube M3, a PMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7 and an NMOS tube M8; The gate of the PMOS transistor M3 is connected to the positive input signal VP, the gate of the PMOS transistor M4 is connected to the negative input signal VN, the source of the PMOS transistor M3 is connected to the drain of the PMOS transistor M1, the drain of the NMOS transistor M5, and the gate of the NMOS transistor M6, the source of the PMOS transistor M4 is connected to the drain of the PMOS transistor M2, the drain of the NMOS transistor M6, and the gate of the NMOS transistor M5, the drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M7 and the gate of the NMOS transistor M8, the drain of the PMOS transistor M4 is connected to the drain of the NMOS transistor M8 and the gate of the NMOS transistor M7, and the sources of the NMOS transistors M5, M6, M7, and M8 are respectively connected to the power supply; The reset unit includes a first switch, a second switch, a third switch and a fourth switch; The tail current source control unit includes: a PMOS transistor M9, a PMOS transistor Msw1 and a PMOS transistor Msw2.

2. The improved cascade low-noise and low-power dynamic comparator according to claim 1, characterized in that: The input end of the reset unit is connected to the inverted clock control signal, a node on2 is formed between the drain of the PMOS transistor M3 and the gate of the NMOS transistor M8, a node op2 is formed between the drain of the PMOS transistor M4 and the gate of the NMOS transistor M7, a node on1 is formed between the source of the PMOS transistor M3, the drain of the PMOS transistor M1 and the gate of the NMOS transistor M6, and a node op1 is formed between the source of the PMOS transistor M4, the drain of the PMOS transistor M2 and the gate of the NMOS transistor M5; The first switch is connected to a node no2, the second switch is connected to a node on1, the third switch is connected to a node op1, and the fourth switch is connected to a node op2.

3. The improved cascade low-noise and low-power dynamic comparator according to claim 2, characterized in that: The source of the PMOS transistor M9 is grounded, the gate of the PMOS transistor M9 is connected to the clock control signal, the drain of the PMOS transistor M9 is connected to the sources of the PMOS transistors Msw1 and Msw2, the drain of the PMOS transistor Msw1 is connected to the source of the PMOS transistor M1, the drain of the PMOS transistor Msw2 is connected to the source of the PMOS transistor M2, the gate of the PMOS transistor Msw1 is connected to the node op2, and the gate of the PMOS transistor Msw2 is connected to the node on2.

4. The improved cascade low-noise and low-power dynamic comparator according to claim 1, characterized in that: When the clock control signal is at a low level, the corresponding inverted clock control signal is at a high level; when the clock control signal is at a high level, the corresponding inverted clock control signal is at a low level; When the clock control signal is at a high level, the tail current source control unit provides a stable current to the differential input amplification unit.

5. The improved cascade low-noise and low-power dynamic comparator according to claim 1, characterized in that: When the inverted clock control signal is at a high level, the reset unit resets the output end of the differential input amplifying unit.

6. A control method for a dynamic comparator as claimed in claim 3, characterized in that: The following steps are involved: A low-level clock control signal is input to the tail current source control unit to turn off the PMOS transistor M9, and an inverted clock control signal is input to the reset unit. After the first switch, the second switch, the third switch, and the fourth switch are closed, the nodes on2, on1, op1, and op2 are reset to high levels respectively; A high-level clock control signal is input to the tail current source control unit to turn on the PMOS transistor M9. At this time, the inverted clock control signal is at a low level, the first switch, the second switch, the third switch, and the fourth switch are turned off, and the nodes on2 and op2 remain at a high level. After the PMOS transistors Msw1 and Msw2 are turned on, the PMOS transistors M1 and M2 discharge the nodes on1 and op1. If the positive input signal VP is greater than the negative input signal VN, the discharge speed of the PMOS tube M1 is greater than the discharge speed of the PMOS tube M2, the PMOS tube M3 is turned on before the PMOS tube M4, the NMOS tube M6 is turned on, and the NMOS tube M5 is turned off, thereby increasing the voltage between the node on1 and the node op1, the NMOS tube M8 is turned on, and the NMOS tube M7 is turned off, thereby increasing the voltage between the node on2 and the node op2; According to the voltage between the node on2 and the node op2, the latch unit quickly establishes latching and outputs a differential output signal.

7. The control method according to claim 6, characterized in that: The following steps are also included: If the negative input signal VN is greater than the positive input signal VP, the discharge speed of the PMOS transistor M2 is greater than the discharge speed of the PMOS transistor M1, the PMOS transistor M4 is turned on before the PMOS transistor M3, the NMOS transistor M5 is turned on, and the NMOS transistor M6 is turned off, thereby increasing the voltage between the node on1 and the node op1, the NMOS transistor M7 is turned on, and the NMOS transistor M8 is turned off, thereby increasing the voltage between the node on2 and the node op2; According to the voltage between the node on2 and the node op2, the latch unit quickly establishes latching and outputs a differential output signal.

8. An analog-to-digital converter, characterized in that The analog-to-digital converter uses the improved cascade low-noise and low-power dynamic comparator according to any one of claims 1 to 5.

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