A simulation verification model with flexibly configurable addressing mode for I2C interface IP verification

Abstract

The present invention discloses a simulation verification model based on I2C interface IP verification in the field of IP design verification technology in semiconductor integrated circuits, with flexibly configurable addressing modes. The model comprises: a data response send / receive module for responding to device addresses and memory addresses; the data response send / receive module contains an I2C protocol transmission state machine for state jumps between I2C write transmission and read transmission, and controls the send or receive state of the data response send / receive module; the I2C protocol usually first transmits an addressing byte, that is, addresses the device mounted on the bus. The I2C protocol specifies two addressing modes, 7-bit and 10-bit. Data transmission can begin after the corresponding device responds to the address. The present invention supports I2C interface simulation in both 7-bit and 10-bit addressing modes, making system-level simulation of I2C modules more convenient and faster, meeting a wider range of verification needs.

Description

Technical Field

[0001] The present invention relates to the technical field of IP design verification in semiconductor integrated circuits, and in particular to a simulation verification model with flexibly configurable addressing modes for IP verification based on an I2C interface. Background Art

[0002] The Inter-Integrated Circuit (I2C) interface is a serial, half-duplex interface bus developed by Philips. It enables synchronous serial communication between microprocessors and peripheral chips. It is primarily used for short-range, low-speed communication and is commonly used for data exchange between storage devices such as EEPROMs and for controlling peripherals such as sensors and displays. The I2C interface requires only two bidirectional signal lines for data transmission: a clock line (SCL) for clock synchronization between the communicating parties and a data line (SDA) for sending and receiving data. The I2C bus interface features a simple hardware structure, simplified PCB layout, pin savings, and reduced system costs, making it widely used in many fields.

[0003] Devices connected to the I2C bus are categorized as masters and slaves. The master can initiate and terminate data communications, while the slave can only be called passively. Because the I2C bus uses only two signal lines for data transmission and can connect multiple I2C devices, each I2C device has a specific and unique device address. The master sends the device address to the bus, and the corresponding slave responds to the address, completing device addressing.

[0004] On-chip I2C bus interfaces typically utilize an I2C interface IP (Intelligent Programming Interface) (IP) mounted on the on-chip system bus to interact with the processor core. System-level verification typically involves the processor sending instructions and data to the I2C IP via the system bus, controlling it to generate the SCL clock and transmit SDA data. The SCL and SDA signals are connected to a dedicated simulation model that simulates the logical behavior of devices with an I2C interface. This model includes basic functions such as receiving, sending, and storing I2C data, and sending responses to the I2C IP. Additional logic is also included to verify the correctness of data transmission across the I2C interface.

[0005] I2C device addresses are classified into two types: 7-bit and 10-bit. Therefore, I2C transmissions also have two addressing modes: 7-bit and 10-bit. Research has shown that most I2C devices use 7-bit device addresses, but some products, such as certain sensors, use 10-bit device addresses. Currently, common simulation models typically simulate the read and write transfer format of I2C device EEPROMs, which only support 7-bit addressing. Currently, there are no patents or papers that support both 7-bit and 10-bit addressing modes. Verification requirements for some I2C 10-bit addressing modes are often not met. Summary of the Invention

[0006] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a simulation verification model with flexibly configurable addressing modes for IP verification based on an I2C interface, which can simulate both 7-bit and 10-bit addressing modes simultaneously in a verification environment.

[0007] To achieve the above object, the present invention is implemented by adopting the following technical solutions:

[0008] In a first aspect, the present invention provides a simulation verification model with flexibly configurable addressing modes based on I2C interface IP verification, including a data response sending / receiving module for responding to device addresses and memory addresses; the data response sending / receiving module contains an I2C protocol transmission state machine for state jumps between I2C write transmission and read transmission, and controls the sending or receiving state of the data response sending / receiving module; the I2C protocol transmission state machine includes:

[0009] DA_H device address high byte status, DA_L device address low byte status, MA_H memory address high byte status, MA_L memory address low byte status, W_D write data status, R_D read data status and NS unselected status;

[0010] If the data response sending / receiving module detects the START bit sent by the host, it jumps to the DA_H device address high byte state;

[0011] When the DA_H device address is in high byte state, the signal mode is set to RECV;

[0012] If the data received by the current byte is 11110 in bit [7:3], the addressing mode of the I2C transmission is determined to be 10-bit addressing mode; if the data received by the current byte is the set 7-bit device address, the addressing mode of the I2C transmission is determined to be 7-bit addressing mode;

[0013] If the addressing mode is 10-bit addressing mode, and the data bits [2:1] of the current byte received are bits [9:8] of the set 10-bit device address, then the address is preliminarily matched;

[0014] If the address is preliminarily matched and the 0th bit of the data received in the current byte is 1, jump to the R_D read data state, set the signal mode to SEND, and prepare to send data;

[0015] If the address matches initially and the 0th bit of the data received in the current byte is 0, jump to the DA_L device address low byte state, keep the signal mode at RECV, and continue to receive the device address low byte;

[0016] If the addressing mode is 7-bit addressing mode, jump to the MA_H memory address high byte state and prepare to receive the memory address high byte;

[0017] If the addressing mode is not 10-bit addressing mode or 7-bit addressing mode, jump to NS unselected state, set the signal mode to PASSIVE, and simulate and verify that the model is not addressed;

[0018] When the MA_H memory address is in the high byte state, the signal mode is RECV. After waiting for the signal done, it enters the MA_L memory address low byte state and continues to receive the memory address low byte.

[0019] When the MA_L memory address is in the low byte state, the signal mode is RECV, and after waiting for the signal done, it enters the W_D write data state, and the I2C bus is ready to write data to the simulation verification model;

[0020] When W_D is in the data writing state, the signal mode is RECV. After all data are written, the host sends the STOP bit.

[0021] When R_D is in the data reading state, the signal mode is SEND. After all data are read out, the host sends the STOP bit.

[0022] NS is in the unselected state and jumps back to the DA_H device address high byte state after one SCL cycle.

[0023] Among them, if the data response sending / receiving module detects the STOP bit sent by the host, it jumps to the NS unselected state; when the data response sending / receiving module sends a signal done, it represents that one byte transmission is completed.

[0024] Optionally, the data response sending / receiving module is externally connected to SDA and SCL of the host I2C interface IP through two tri-state gates.

[0025] Optionally, an assign statement is used to realize the connection between the two tri-state gates;

[0026] If the signal scl_oe is true, SCL is 0, otherwise, SCL is in high impedance state;

[0027] Assign the value of SCL to the signal scl_in;

[0028] If the signal sda_oe is true, SDA is 0, otherwise, SDA is in high impedance state;

[0029] Assign the value of SDA to signal sda_in;

[0030] Among them, the signal scl_oe and the signal sda_oe are enable signals of SCL and SDA; the signal scl_in and the signal sda_in are interactive signals of the three-state gate.

[0031] Optionally, the data response sending / receiving module further includes a data response sending / receiving state machine; the data response sending / receiving state machine includes:

[0032] IDLE idle state, RECV_START receive start bit state, RECV_DATA receive data state, SEND_ACK send response bit state, SEND_DATA send data state, RECV_ACK receive response bit state, WAIT_STOP wait stop bit state;

[0033] In the IDLE idle state, when the signal sda_in changes from high level to low level, it means that the data response sending / receiving module detects the START bit sent by the host and jumps to the RECV_START receiving start bit state;

[0034] When RECV_START receives the start bit state, the data response send / receive module receives the START bit on the I2C bus, lasts for one SCL cycle, and jumps to the RECV_DATA receive data state;

[0035] When the RECV_DATA receiving data state is in progress, the data response sending / receiving module receives the data on the I2C bus, and the counter counts the number of received data bits. When the count reaches 7, it jumps to the SEND_ACK sending response bit state.

[0036] When the SEND_ACK send response bit state is on, the data response send / receive module sends a response ACK or a non-response NAK to the I2C bus; if the signal mode is SEND, it jumps to the SEND_DATA send data state and sends a done signal; if the mode is PASSIVE, it jumps to the WAIT_STOP wait stop bit state and sends a done signal;

[0037] When in the SEND_DATA state, the data response send / receive module sends data to the I2C bus. The counter counts the number of bits of data to be sent. When the count reaches 7, it jumps to the RECV_ACK state.

[0038] When the RECV_ACK receive response bit state, the data response send / receive module receives the response ACK or non-response NAK sent on the I2C bus; if the signal mode is SEND, it jumps to the SEND_DATA send data state and sends a done signal. If the mode is PASSIVE, it jumps to the WAIT_STOP wait stop bit state and sends a done signal.

[0039] In the WAIT_STOP waiting state, when sda_in changes from low level to high level, it means that the data response sending / receiving module detects the STOP bit sent by the host and jumps to the IDLE state;

[0040] Among them, if the data response sending / receiving module detects the STOP bit sent by the host, it jumps to the IDLE idle state.

[0041] Optionally, if the RESTART bit sent by the host is detected in the RECV_DATA receiving data state, it jumps to the RECV_START receiving start bit state.

[0042] Optionally, when SCL is high, SDA changes from high to low for the START bit; when SCL is high, SDA changes from low to high for the STOP bit; during data transmission, when SCL is high, SDA changes from high to low for the RESTART bit.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] The present invention provides a simulation verification model with flexibly configurable addressing modes based on I2C interface IP verification. The model can simulate both 7-bit and 10-bit addressing modes in a verification environment. The model can independently determine whether the address is 7-bit or 10-bit based on the addressing mode characteristics specified in the protocol. The model can receive, send, and store I2C data and respond to addresses, data, and instructions issued by the host, completing I2C read and write transmissions. This makes system-level simulation of I2C modules more convenient and quick, meeting a wider range of verification needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a diagram of the I2C IP system-level verification environment provided by an embodiment of the present invention;

[0046] Figure 2Schematic diagram of I2C bus lines and connection methods provided by an embodiment of the present invention;

[0047] Figure 3 This is a schematic diagram of the connection of the I2C interface signal tri-state gates provided by an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of the START and STOP bits of the I2C interface protocol provided by an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of the I2C interface protocol data transmission format provided by an embodiment of the present invention;

[0050] Figure 6 Schematic diagram of a data response sending / receiving state machine provided by an embodiment of the present invention;

[0051] Figure 7 7-bit / 10-bit addressing mode according to an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram of the read and write transmission format of an EEPROM device provided by an embodiment of the present invention;

[0053] Figure 9 Schematic diagram of the I2C protocol transmission state machine provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0055] Example 1:

[0056] The embodiment of the present invention designs a simulation verification model that can be used to verify the read and write behavior of I2C 7-bit and 10-bit addressing modes. This model can interact with IP as a slave. Its functions include but are not limited to receiving and detecting START, RESTART, and STOP bits; receiving and judging 7-bit or 10-bit device addresses and issuing responses; receiving and sending I2C data; including a memory module to store I2C data; receiving or issuing I2C responses, etc. The structure diagram of the I2C IP system-level verification environment is as follows: Figure 1 shown.

[0057] Figure 1In the code, tb stands for testbench, chip_top represents the top-level RTL design for a chip, I2C IP represents the integrated I2C interface IP, and I2C Simulation Model represents the simulation verification model. Because the I2C bus is a half-duplex bus with only one data line, bidirectional data transmission is required. The six I2C signal lines of the I2C interface IP are connected to two tri-state gates on the chip_top layer to change the transmission direction. The signals processed by the tri-state gates become standard I2C interface signals and are connected to the simulation model.

[0058] (1) Three-state gate design description

[0059] like Figure 2 As shown, the I2C bus can connect multiple masters and slaves. When multiple I2C devices are connected via the I2C bus, wired-AND operations must be implemented between the devices. Therefore, the I2C pins on the chip typically use open-drain outputs to implement wired-AND operations. As long as the pin level of one I2C device is low, the corresponding SCL or SDA bus will also be low. However, open-drain outputs lack the ability to output high levels, so pull-up resistors are required at the output. When the chip's SDA and SCL pin output MOSFETs are turned off, the output state is high-impedance. The presence of the pull-up resistors ensures that the level on the I2C signal line is high.

[0060] Because the I2C bus supports multiple devices, they are connected to the bus in a high-impedance configuration. This ensures that the bus is automatically released when a device is not using it, allowing other devices to gain access. Therefore, device ports must be connected to the bus through tri-state buffers. When a device is not using the bus, its output is in a high-impedance state. Because the simulation model represents an I2C slave device connected to the bus, tri-state gates are also implemented within the model for the I2C signals.

[0061] like Figure 3 As shown in the figure, the I2C interface signal tri-state gate connection diagram is shown. The tri-state gate connection is directly implemented using the assign statement in the model.

[0062] assign SCL = scl_oe? 1'b0 : 1'bz;

[0063] assign scl_in = SCL;

[0064] assign SDA = sda_oe? 1'b0 : 1'bz;

[0065] assign sda_in = SDA;

[0066] In the testbench, define SCL and SDA as tri1 type to implement pull-up.

[0067] (2) Data response sending / receiving module design description

[0068] The functions implemented by this module include: realizing the processing of interface signals by three-state gates, including the state machine for receiving and sending data or responding to bits; data shifting and counting; identifying the START, RESTART and STOP bits on the bus; and controlling the level of sda_oe, that is, controlling when the model occupies the bus and when it releases the bus.

[0069] like Figure 4 As shown in Figure 1, the I2C interface protocol specifies that when SCL is high, SDA transitions from high to low, indicating a START bit; when SCL is high, SDA transitions from low to high, indicating a STOP bit. The RESTART bit typically occurs during data transmission to change the direction of data transmission. Its signal is also a transition from SDA from high to low while SCL is high. Therefore, SDA level edge changes can be used as a basis for model detection of the START, RESTART, and STOP bits.

[0070] The I2C interface protocol stipulates that the bus transmits data in bytes, that is, it takes 9 clock cycles to transmit one byte of data, of which the first 8 bits are data bits and the 9th bit is the response bit. The response bit is sent by the receiver and is valid at low level. The transmission format of each byte is as follows: Figure 5 shown.

[0071] The model needs to receive and send data and respond. Therefore, the data response sending and receiving state machine is designed as follows Figure 6 shown.

[0072] Figure 6 There are 7 states in the state machine, namely IDLE idle state; RECV_START receive start bit state; RECV_DATA receive data state; SEND_ACK send response bit state; SEND_DATA send data state; RECV_ACK receive response bit state; WAIT_STOP wait for stop bit state.

[0073] Since the host may initiate the STOP bit at any time, it will jump to the IDLE state immediately after detecting the STOP bit on the bus at any time, indicating that the current transmission is completed and waiting for the next transmission to start.

[0074] Figure 6 In the IDLE state, when sda_in changes from high level to low level, it represents the START bit, that is, jumps to the RECV_START state;

[0075] Figure 6In the RECV_START state, the model receives the START bit on the bus. Since START lasts for one SCL cycle, RECV_START also lasts for one SCL cycle. Since the first byte of each transmission is usually the master sending the device address, the master sends and the slave receives, so it jumps to the RECV_DATA state;

[0076] Figure 6 In the RECV_DATA state, the model receives data from the bus. The counter begins counting. Since each data bit is 8 bits, the model jumps to 7 when the counter reaches 7. The model then sends a response to the bus, so the state jumps to SEND_ACK. If the RESTART bit is detected in this state, the model jumps back to the RECV_START state.

[0077] Figure 6 In the SEND_ACK state, the model sends an ACK or NAK to the bus. The mode is controlled by the I2C protocol transmission state machine described below, and the state transitions depend on the mode value. This state emits a done signal, indicating that a byte has been transferred.

[0078] Figure 6 In the SEND_DATA state, the model sends data to the bus. The counter starts counting. Since each data is 8 bits, the state jumps when the counter reaches 7. The model will receive the response sent by the host to the bus, so the state jumps to RECV_ACK.

[0079] Figure 6 In the RECV_ACK state, the model receives the ACK or NAK sent by the host to the bus. The mode is controlled by the I2C protocol transmission state machine described below, and the state transitions depend on the mode value. This state emits a done signal, indicating that a byte transfer is complete.

[0080] Figure 6 When in the WAIT_STOP state, it means that the last byte has been transmitted. The model no longer occupies the bus and enters this state to wait for the host to send the STOP bit. After detecting the STOP bit, it returns to the IDLE state, the transmission is completed, and the bus is released.

[0081] (3) Simulation model design description

[0082] The functions implemented by this module include: integrated data response sending / receiving module to respond to device addresses and internal memory addresses; built-in I2C protocol transmission state machine: realizes the state jump of I2C write transmission and read transmission, realizes data storage, and controls the sending or receiving status of the data response sending / receiving module.

[0083] The I2C protocol usually transmits the address byte first, that is, addresses the device mounted on the bus. After the corresponding device responds to the address, data transmission can begin. There are two addressing modes specified by the I2C protocol, 7-bit and 10-bit, with the following formats: Figure 7 shown.

[0084] Figure 7 In the 10-bit addressing mode, the first five bits of the first byte are 11110, which can be used as the basis for judging the addressing mode. As long as the first five bits of the first byte of each transmission are 11110, it can be determined as a 10-bit addressing mode transmission.

[0085] Figure 8 The simulation model designed in this embodiment simulates the read and write logic behavior of EEPROM, which is a common I2C device and can realize single-byte and multi-byte read and write transmission. Figure 8 Design the I2C protocol transmission state machine as follows Figure 9 shown.

[0086] Figure 9 The state machine has a total of 7 states, namely DA_H: device address high byte state; DA_L: device address low byte state; MA_H: memory address high byte state; MA_L: memory address low byte state; W_D: write data state; R_D: read data state; NS: unselected state. When the data response sending / receiving module detects the START bit at any time, the state machine immediately jumps to the DA_H state.

[0087] After detecting STOP, it will jump to NS state immediately. All state jumps occur when the data response sending / receiving module sends a done signal, which means that one byte transmission is completed.

[0088] Figure 9 In the DA_H state, the mode signal is set to RECV. If bits [7:3] of the received data are 11110, the byte is considered in 10-bit addressing mode. If bits [2:1] match bits [9:8] of the set 10-bit device address, the address is preliminarily matched. Data bit 0 indicates a read or write transfer. If it is a write, the DA_L state is jumped, the mode signal remains at RECV, and the low-byte device address is received. If it is a read, the R_D state is jumped, and the mode signal is set to SEND, preparing to send data. If the received data is equal to the set 7-bit device address, the MA_H state is jumped directly to prepare to receive the memory address. If neither of them matches, the NS state is jumped, and the mode signal is set to PASSIVE, indicating that the model has not been addressed.

[0089] Figure 9In the DA_L state, the mode signal is RECV. If the data of this byte matches the [7:0] bits of the set 10-bit device address, the 10-bit device address is addressed and the state jumps to MA_H, ready to receive the memory address; if it does not match, it jumps to NS and the mode signal is set to PASSIVE, indicating that the model has not been addressed.

[0090] Figure 9 In the MA_H state, the mode signal is RECV, and after waiting for the done signal, it enters MA_L and continues to receive the low byte of the memory address;

[0091] Figure 9 In the MA_L state, the mode signal is RECV, and after waiting for the done signal, it enters W_D, and the bus is ready to write data to the model;

[0092] Figure 9 In the W_D state, the mode signal is RECV. After waiting for all data to be written, the host sends a STOP bit. After detecting the STOP bit, it enters the NS state.

[0093] Figure 9 In the R_D state, the mode signal is SEND. After waiting for all data to be read out, the host sends a STOP bit. After detecting the STOP bit, it enters the NS state.

[0094] Figure 9 When in the NS state, the state lasts for one SCL cycle and then jumps back to DA_H, waiting for the next transmission to start.

[0095] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0096] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A simulation verification model with flexibly configurable addressing mode for I2C interface IP verification, characterized in that: It includes a data response sending / receiving module for responding to device addresses and memory addresses; the data response sending / receiving module contains an I2C protocol transmission state machine for state jumps of I2C write transmission and read transmission, and controls the sending or receiving state of the data response sending / receiving module; The I2C protocol transmission state machine includes: DA_H device address high byte status, DA_L device address low byte status, MA_H memory address high byte status, MA_L memory address low byte status, W_D write data status, R_D read data status and NS unselected status; If the data response sending / receiving module detects the START bit sent by the host, it jumps to the DA_H device address high byte state; When the DA_H device address is in high byte state, the signal mode is set to RECV; If the data received by the current byte is 11110 in bit [7:3], the addressing mode of the I2C transmission is determined to be 10-bit addressing mode; if the data received by the current byte is the set 7-bit device address, the addressing mode of the I2C transmission is determined to be 7-bit addressing mode; If the addressing mode is 10-bit addressing mode, and the data bits [2:1] of the current byte received are bits [9:8] of the set 10-bit device address, then the address is preliminarily matched; If the address is preliminarily matched and the 0th bit of the data received in the current byte is 1, jump to the R_D read data state, set the signal mode to SEND, and prepare to send data; If the address matches initially and the 0th bit of the data received in the current byte is 0, jump to the DA_L device address low byte state, keep the signal mode at RECV, and continue to receive the device address low byte; If the addressing mode is 7-bit addressing mode, jump to the MA_H memory address high byte state and prepare to receive the memory address high byte; If the addressing mode is not 10-bit addressing mode or 7-bit addressing mode, jump to NS unselected state, set the signal mode to PASSIVE, and simulate and verify that the model is not addressed; When the MA_H memory address is in the high byte state, the signal mode is RECV. After waiting for the signal done, it enters the MA_L memory address low byte state and continues to receive the memory address low byte. When the MA_L memory address is in the low byte state, the signal mode is RECV, and after waiting for the signal done, it enters the W_D write data state, and the I2C bus is ready to write data to the simulation verification model; When W_D is in the data writing state, the signal mode is RECV. After all data are written, the host sends the STOP bit. When R_D is in the data reading state, the signal mode is SEND. After all data are read out, the host sends the STOP bit. NS is in the unselected state and jumps back to the DA_H device address high byte state after one SCL cycle. Among them, if the data response sending / receiving module detects the STOP bit sent by the host, it jumps to the NS unselected state; when the data response sending / receiving module sends a signal done, it represents that one byte transmission is completed.

2. The simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification according to claim 1, characterized in that: The data response sending / receiving module is externally connected to the SDA and SCL of the host I2C interface IP through two tri-state gates.

3. The simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification according to claim 2, characterized in that: Using assign statement to realize the connection of the two tri-state gates; If the signal scl_oe is true, SCL is 0, otherwise, SCL is in high impedance state; Assign the value of SCL to the signal scl_in; If the signal sda_oe is true, SDA is 0, otherwise, SDA is in high impedance state; Assign the value of SDA to signal sda_in; Among them, the signal scl_oe and the signal sda_oe are enable signals of SCL and SDA; the signal scl_in and the signal sda_in are interactive signals of the three-state gate.

4. The simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification according to claim 3, characterized in that: The data response sending / receiving module also includes a data response sending / receiving state machine; The data response sending / receiving state machine includes: IDLE idle state, RECV_START receive start bit state, RECV_DATA receive data state, SEND_ACK send response bit state, SEND_DATA send data state, RECV_ACK receive response bit state, WAIT_STOP wait stop bit state; In the IDLE idle state, when the signal sda_in changes from high level to low level, it means that the data response sending / receiving module detects the START bit sent by the host and jumps to the RECV_START receiving start bit state; When RECV_START receives the start bit state, the data response send / receive module receives the START bit on the I2C bus, lasts for one SCL cycle, and jumps to the RECV_DATA receive data state; When the RECV_DATA receiving data state is in progress, the data response sending / receiving module receives the data on the I2C bus, and the counter counts the number of received data bits. When the count reaches 7, it jumps to the SEND_ACK sending response bit state. When the SEND_ACK send response bit state is on, the data response send / receive module sends a response ACK or a non-response NAK to the I2C bus; if the signal mode is SEND, it jumps to the SEND_DATA send data state and sends a done signal; if the mode is PASSIVE, it jumps to the WAIT_STOP wait stop bit state and sends a done signal; When in the SEND_DATA state, the data response send / receive module sends data to the I2C bus. The counter counts the number of bits of data to be sent. When the count reaches 7, it jumps to the RECV_ACK state. When the RECV_ACK receive response bit state, the data response send / receive module receives the response ACK or non-response NAK sent on the I2C bus; if the signal mode is SEND, it jumps to the SEND_DATA send data state and sends a done signal. If the mode is PASSIVE, it jumps to the WAIT_STOP wait stop bit state and sends a done signal. In the WAIT_STOP waiting state, when sda_in changes from low level to high level, it means that the data response sending / receiving module detects the STOP bit sent by the host and jumps to the IDLE state; Among them, if the data response sending / receiving module detects the STOP bit sent by the host, it jumps to the IDLE idle state.

5. The simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification according to claim 4, characterized in that: If the RESTART bit sent by the host is detected in the RECV_DATA receiving data state, it jumps to the RECV_START receiving start bit state.

6. The simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification according to claim 5, characterized in that: When SCL is high, SDA changes from high to low for the START bit; when SCL is high, SDA changes from low to high for the STOP bit; during data transmission, when SCL is high, SDA changes from high to low for the RESTART bit.

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