Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a channel region, a source region located at one side of the channel region, and a drain region located at the other side of the channel region; the doping layer is located in the substrate of the channel region; the channel layer is positioned on the top surface of the substrate in the channel region, has high electronic thermal conductivity and is in contact with the doping layer; the source electrode is located at the top of the substrate of the source region, and the source electrode is in contact with one end of the channel layer; the drain electrode is located at the top of the substrate of the drain region, and the drain electrode is in contact with the other end of the channel layer. And the response rate and the response time of the semiconductor structure are improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Terahertz detectors are important basic equipment for terahertz technology. Ideal terahertz detectors should have short response time, high responsivity, low noise, wide detection bandwidth and room temperature operation. However, current terahertz detectors cannot meet all these requirements. Commercial terahertz detectors such as Golay cells, pyroelectric detectors and bolometers have long response times. Bolometer terahertz detectors do not have room temperature operation. Compared with these terahertz detectors, photothermoelectric (PTE) terahertz detectors are very likely to meet all the above requirements.

[0003] However, the performance of photothermal terahertz detectors still needs to be improved. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to further improve the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a channel region, a source region located on one side of the channel region, and a drain region located on the other side of the channel region; a doping layer located in the substrate in the channel region; a channel layer located on the top surface of the substrate in the channel region, the channel layer having high electronic thermal conductivity and the channel layer in contact with the doping layer; a source electrode located on the top of the substrate in the source region, the source electrode in contact with one end of the channel layer; and a drain electrode located on the top of the substrate in the drain region, the drain electrode in contact with the other end of the channel layer.

[0006] Optionally, the material of the channel layer includes one or more of Cn, NiTe2, NiSe2, PtTe2, PtSe2, PdTe2 and PdSe2.

[0007] Optionally, the doping layer is located in the substrate of the channel region on the side of the source region; or, the doping layer is located in the substrate of the channel region on the side of the drain region; or, the doping layer is located in the substrate of the channel region on the side of the source region, and the doping layer is located in the substrate of the channel region on the side of the drain region.

[0008] Optionally, along the normal direction of the substrate surface, the thickness of the doping layer is 50 nanometers to 200 nanometers.

[0009] Optionally, along the normal direction of the substrate surface, the number of atomic layers of the channel layer is 1 to 20 layers.

[0010] Optionally, the material of the substrate includes intrinsic silicon.

[0011] Optionally, the semiconductor structure further includes: a metal layer located on the side of the doped layer and on the top of the substrate in the channel region opposite to the source; or a metal layer located on the side of the doped layer and on the top of the substrate in the channel region opposite to the drain.

[0012] Optionally, the material of the metal layer includes one or more of gold, copper, chromium, titanium, aluminum, tungsten, tantalum and nickel.

[0013] Optionally, the semiconductor structure further includes: a dielectric layer located between the metal layer and the channel layer.

[0014] Optionally, the material of the dielectric layer includes one or more of SiO2, Al2O3, Si3N4 and h-BN.

[0015] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a channel region, a source region located on one side of the channel region, and a drain region located on the other side of the channel region; forming a doping layer in the substrate in the channel region; forming a channel layer on the top surface of the substrate in the channel region, the channel layer having high electronic thermal conductivity and the channel layer in contact with the doping layer; forming a source electrode on the top of the substrate in the source region, the source electrode in contact with one end of the channel layer, and forming a drain electrode on the top of the substrate in the drain region, the drain electrode in contact with the other end of the channel layer.

[0016] Optionally, in the step of forming the doping layer, the doping layer is located in the substrate of the channel region on the side of the source region; or, in the step of forming the doping layer, the doping layer is located in the substrate of the channel region on the side of the drain region; or, in the step of forming the doping layer, the doping layer is located in the substrate of the channel region on the side of the source region, and the doping layer is located in the substrate of the channel region on the side of the drain region.

[0017] Optionally, the step of forming a doping layer in the substrate in the channel region includes: forming a patterned shielding layer on the top surface of the substrate, the shielding layer covering the source and the drain and exposing a portion of the top surface of the substrate in the channel region; performing a doping treatment on the exposed substrate in the channel region to form a doping layer in the substrate in the channel region; and removing the shielding layer.

[0018] Optionally, the process of performing doping treatment on the exposed channel region substrate includes an ion implantation process.

[0019] Optionally, the parameters of the ion implantation process include: the doping ions include N-type ions or P-type ions; the doping dose range is 1E13atom / cm 3To 1E15atom / cm 3 ; The implantation energy range is 10kev to 200kev.

[0020] Optionally, the process of forming the channel layer on the top surface of the substrate in the channel region includes a wet transfer process, an in-situ growth process or a dry transfer process.

[0021] Optionally, after forming the source and the drain, the method for forming the semiconductor structure further includes: forming a metal layer on the side of the doping layer and on the top of the substrate in the channel region opposite to the source; or forming a metal layer on the side of the doping layer and on the top of the substrate in the channel region opposite to the drain.

[0022] Optionally, after forming the source and drain and before forming the metal layer, the method further includes: forming a dielectric layer on the top of the channel layer on the side of the doping layer; in the step of forming the metal layer, the metal layer covers the dielectric layer.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0024] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein a doping layer is formed in a substrate in a channel region, and a channel layer is formed on a top surface of the substrate in the channel region, wherein the channel layer has high electronic thermal conductivity and the channel layer is in contact with the doping layer, so that the doping layer can adjust the Fermi level of the channel layer, thereby improving the Seebeck coefficient of the channel layer. The magnitude of the Seebeck coefficient can determine the response rate of the semiconductor structure. The larger the Seebeck coefficient, the higher the response rate of the semiconductor structure. The doping layer can also provide additional hot carriers for the channel layer, thereby further improving the response rate of the semiconductor structure. At the same time, the channel layer has high electronic thermal conductivity, which can reduce the response time of the semiconductor structure, thereby improving both the response rate and the response time of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a corresponding structure in an embodiment of a semiconductor structure of the present invention;

[0026] Figures 2 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0027] At present, the performance of photothermal electric terahertz detectors depends on the Seebeck coefficient, which depends on the material properties. Materials with low electronic thermal conductivity lose electron energy slowly and exhibit a higher Seebeck coefficient. Therefore, photothermal electric terahertz detectors have a long response time but high responsiveness. Materials with high electronic thermal conductivity lose electron energy quickly and exhibit a lower Seebeck coefficient. Therefore, photothermal electric terahertz detectors have a fast response time but low responsiveness. In summary, existing photothermal electric terahertz detectors cannot simultaneously have the functions of fast response time and high responsiveness.

[0028] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a channel region; forming a doping layer in the substrate in the channel region; forming a channel layer on the top surface of the substrate in the channel region, the channel layer having high electron thermal conductivity and the channel layer in contact with the doping layer; forming a source electrode on the top of the substrate on one side of the channel region, the source electrode in contact with one end of the channel layer, and forming a drain electrode on the top of the substrate on the other side of the channel region, the drain electrode in contact with the other end of the channel layer.

[0029] In this embodiment, a doping layer is formed in the substrate in the channel region, and a channel layer is formed on the top surface of the substrate in the channel region. The channel layer has high electronic thermal conductivity and is in contact with the doping layer, so that the doping layer can adjust the Fermi level of the channel layer, thereby improving the Seebeck coefficient of the channel layer. The magnitude of the Seebeck coefficient can determine the response rate of the semiconductor structure. The larger the Seebeck coefficient, the higher the response rate of the semiconductor structure. The doping layer can also provide additional hot carriers for the channel layer, further improving the response rate of the semiconductor structure. At the same time, the channel layer has high electronic thermal conductivity, which can reduce the response time of the semiconductor structure, thereby improving both the response rate and the response time of the semiconductor structure.

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] Figure 1 It is a schematic diagram of the corresponding structure in one embodiment of the semiconductor structure of the present invention.

[0032] The semiconductor structure includes: a substrate 200, wherein the substrate 200 includes a channel region 200A, a source region 200B located on one side of the channel region 200A, and a drain region 200C located on the other side of the channel region 200A; a doping layer 201 located in the substrate 200 in the channel region 200A; a channel layer 202 located on the top surface of the substrate 200 in the channel region 200A, wherein the channel layer 202 has high electron thermal conductivity and the channel layer 202 is in contact with the doping layer 201; a source electrode 216 located on the top of the substrate 200 in the source region 200B, wherein the source electrode 216 is in contact with one end of the channel layer 202; and a drain electrode 206 located on the top of the substrate 200 in the drain region 200C, wherein the drain electrode 206 is in contact with the other end of the channel layer 202.

[0033] Specifically, a doping layer 201 is arranged in the substrate 200 of the channel region 200A, and a channel layer 202 is formed on the top surface of the substrate 200 of the channel region 200A. The channel layer 202 has high electronic thermal conductivity and is in contact with the doping layer 201, so that the doping layer 201 can adjust the Fermi level of the channel layer 202, thereby improving the Seebeck coefficient of the channel layer 202. The magnitude of the Seebeck coefficient can determine the response rate of the semiconductor structure. The larger the Seebeck coefficient, the higher the response rate of the semiconductor structure. The doping layer 201 can also provide additional hot carriers for the channel layer 202, thereby further improving the response rate of the semiconductor structure. At the same time, the channel layer 201 has high electronic thermal conductivity, which can reduce the response time of the semiconductor structure, thereby improving both the response rate and the response time of the semiconductor structure.

[0034] The substrate 200 provides a process platform for setting up photothermoelectric terahertz detectors (PTE TDs).

[0035] Terahertz waves are between microwaves and infrared rays in the electromagnetic spectrum. Photothermal electric terahertz detectors have ultra-wideband photon absorption capabilities, which specifically include two energy conversion processes: photothermal conversion and thermoelectric conversion. Photothermal conversion depends on the device structure, while thermoelectric conversion depends on the material properties. When the photothermal electric terahertz detector is heated, the carrier temperature rises, and a carrier temperature gradient is formed inside it. Driven by the temperature gradient, the carriers diffuse from the hot end to the cold end, thereby generating an electric potential difference between the hot and cold ends of the photothermal electric terahertz detector.

[0036] In this embodiment, the material of the substrate 200 includes intrinsic silicon.

[0037] It should be noted that the material of the substrate 200 is intrinsic silicon, which is a silicon single crystal with a complete lattice and no impurities. After the doping layer 201 is subsequently formed in the substrate 200 in the channel region 200A, the probability of the carriers in the doping layer 201 diffusing into the substrate 200 can be reduced, so that the doping layer 201 can provide more hot carriers for the subsequently formed channel layer 202, adjust the Fermi level of the channel layer 202, and then improve the Seebeck coefficient of the channel layer 202. The size of the Seebeck coefficient can determine the response rate of the semiconductor structure. The larger the Seebeck coefficient, the faster the response rate of the semiconductor structure.

[0038] In other embodiments, the material of the substrate may also be Ge, InAs, InSb, GaAs or GaN.

[0039] The channel region 200A is used as a region for disposing the channel layer 202 , and provides a channel for carriers to flow between the source 216 and the drain 206 .

[0040] The doping layer 201 is located in the substrate 200 in the channel region 200A at the side of the source region 200B.

[0041] Hot carriers in the doping layer 201 in the substrate 200 of the channel region 200A located at the side of the source region 200B diffuse from the source region 200B to the drain region 200C, so that there are more hot carriers in the channel layer 202, thereby adjusting the Fermi level of the channel layer 202.

[0042] In other embodiments, the doping layer may also be located in the substrate of the channel region on the side of the drain region, or the doping layer is located in the substrate of the channel region on the side of the source region, and the doping layer is located in the substrate of the channel region on the side of the drain region.

[0043] In this embodiment, the doping layer 201 has doping ions, and the doping ions include N-type ions or P-type ions.

[0044] Specifically, the N-type ions include nitrogen, phosphorus, arsenic, antimony, fluorine, chlorine, bromine or iodine, and the P-type ions include boron, aluminum, gallium, indium, beryllium, magnesium, calcium or strontium.

[0045] It should be noted that the concentration of doped ions in the doping layer 201 should not be too large or too small. If the concentration of doped ions is too large, it is easy to cause the temperature of a single hot electron to be not high enough, and the total reflection with half-wave loss weakens the surface light intensity; if the concentration of doped ions is too small, it is easy to cause too few carriers in the doping layer 201, and it is impossible to provide more hot carriers for the channel layer 202, so that the Fermi level of the channel layer 202 is not adjusted, thereby reducing the Seebeck coefficient of the channel layer 202, and then slowing down the response rate of the semiconductor structure, affecting the performance of the semiconductor structure. For this reason, in this embodiment, the concentration range of the doped ions in the doping layer 201 is 1E13atom / cm 3 To 1E15atom / cm 3 .

[0046] Specifically, along the normal direction of the surface of the substrate 200, the thickness of the doping layer 201 should not be too large or too small. If the thickness of the doping layer 201 is too small, it is easy to cause too few carriers in the doping layer 201, and it is impossible to provide more hot carriers for the channel layer 202, so that the Fermi level of the channel layer 202 is not adjusted, thereby reducing the Seebeck coefficient of the channel layer 202, and then slowing down the response rate of the semiconductor structure, affecting the performance of the semiconductor structure; if the thickness of the doping layer 201 is too large, it is easy to cause the hot electrons in the doping layer to spend more time to reach the channel, increasing the response time. For this reason, in this embodiment, along the normal direction of the surface of the substrate 200, the thickness of the doping layer 201 is 50 nanometers to 200 nanometers.

[0047] The channel layer 202 provides a channel for carrier flow between the source 216 and the drain 206. On the one hand, the channel layer 202 has high electronic thermal conductivity, which makes the electron energy loss of the channel layer 202 faster, thereby making the response time of the photothermoelectric terahertz detector faster. On the other hand, the channel layer 202 is in contact with the doping layer 201, so that the doping layer 201 can provide more hot carriers for the channel layer 202, adjust the Fermi level of the channel layer 202, and thus improve the Seebeck coefficient of the channel layer 202. The size of the Seebeck coefficient can determine the response rate of the semiconductor structure. The larger the Seebeck coefficient, the faster the response rate of the semiconductor structure, thereby improving the response rate and response time of the semiconductor structure.

[0048] In this embodiment, the material of the channel layer 202 includes one or more of Cn, NiTe2, NiSe2, PtTe2, PtSe2, PdTe2 and PdSe2.

[0049] Specifically, Cn, NiTe2, NiSe2, PtTe2, PtSe2, PdTe2 and PdSe2 are all materials with Dirac band structure, and therefore have high electronic thermal conductivity. High electronic thermal conductivity makes the thermal electron energy loss of the channel layer 202 faster, thereby making the response time of the photothermoelectric terahertz detector faster. At the same time, the channel layer 202 is in contact with the doping layer 201, so that the doping layer 201 can provide more hot carriers for the channel layer 202, thereby improving the response rate of the semiconductor structure without sacrificing the response time. Therefore, both the response rate and response time of the semiconductor structure are improved.

[0050] It should be noted that the number of atomic layers of the channel layer 202 should not be too many along the normal direction of the surface of the substrate 200. If the number of atomic layers of the channel layer 202 is too many, the doping of the channel layer 202 by the doping layer 201 will be weakened. For this reason, in this embodiment, the number of atomic layers of the channel layer 202 is 1 to 20 layers.

[0051] The source 216 contacts one end of the channel layer 202, and the drain 206 contacts the other end of the channel layer 202. After the source 216 and the drain 206 are electrically connected to the external circuit structure, the source 216 and the drain 206 are electrically connected through the channel layer 202, providing a channel for carrier flow between the source 216 and the drain 206.

[0052] In this embodiment, the semiconductor structure further includes a dielectric layer 208 located between the metal layer 210 and the channel layer 202 .

[0053] The dielectric layer 208 is used to electrically isolate the channel layer 202 from a subsequently formed metal layer 210 , thereby reducing the risk of electrical leakage between the metal layer 210 and the channel layer 202 .

[0054] In this embodiment, the material of the dielectric layer 208 includes one or more of SiO 2 , Al 2 O 3 , Si 3 N 4 and h-BN.

[0055] Specifically, SiO 2 , Al 2 O 3 , Si 3 N 4 and h-BN materials are all dielectric materials with good insulation properties, and can play a good role in electrically isolating the metal layer 210 from the channel layer 202 .

[0056] In this embodiment, the semiconductor structure also includes: a metal layer 210, located on the side of the doping layer 201 and on the top of the substrate 200 in the channel region 200A opposite to the source 216; or, a metal layer 210, located on the side of the doping layer 201 and on the top of the substrate 200 in the channel region 200A opposite to the drain 206.

[0057] Specifically, the metal layer 210 has the function of gathering the terahertz waves received by the photothermoelectric terahertz detector, thereby increasing the terahertz intensity in the local area, causing the temperature of the local area of ​​the photothermoelectric terahertz detector to rise, forming a temperature gradient inside, and driving the hot carriers to diffuse from the hot end to the cold end under the drive of the temperature gradient, thereby generating a charge difference in the photothermoelectric terahertz detector.

[0058] The metal layer 210 also covers the dielectric layer 208 , reducing the risk of electrical leakage between the metal layer 210 and the doping layer 201 .

[0059] In this embodiment, the material of the metal layer 210 includes one or more of gold, copper, chromium, titanium, aluminum, tungsten, tantalum and nickel.

[0060] Among them, copper, chromium, titanium, aluminum, tungsten, tantalum, and nickel are metal materials commonly used in semiconductor manufacturing processes. From a preparation perspective, they are compatible with existing large-scale processing technologies. While the metal layer 210 realizes the function of gathering terahertz waves, it will cause loss of light energy. Gold and aluminum will reduce the loss of light energy.

[0061] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure. Figures 2 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0062] refer to Figure 2 , providing a substrate 100, wherein the substrate 100 includes a channel region 100A, a source region 100B located on one side of the channel region 100A, and a drain region 100C located on the other side of the channel region 100A.

[0063] The substrate 100 provides a process platform for the subsequent formation of photothermoelectric terahertz detectors (PTE TDs).

[0064] Terahertz waves are between microwaves and infrared rays in the electromagnetic spectrum. Photothermal terahertz detectors have ultra-wideband photon absorption capabilities, which specifically include two energy conversion processes: photothermal conversion and thermoelectric conversion. Photothermal conversion depends on the device structure, while hot spot conversion depends on material properties. When the photothermal terahertz detector is heated and the carrier temperature rises, a carrier temperature gradient is formed inside it. Driven by the temperature gradient, the carriers diffuse from the hot end to the cold end, thereby generating an electric potential difference between the hot and cold ends of the photothermal terahertz detector.

[0065] In this embodiment, the material of the substrate 100 includes intrinsic silicon.

[0066] It should be noted that the material of the substrate 100 is intrinsic silicon, which is a silicon single crystal with a complete lattice and no impurities. After a doped layer is subsequently formed in the substrate 100 in the channel region 100A, the probability of carriers in the doped layer diffusing into the substrate 100 can be reduced, so that the doped layer can provide more hot carriers for the subsequently formed channel layer, adjust the Fermi level of the channel layer, and then improve the Seebeck coefficient of the channel layer. The size of the Seebeck coefficient can determine the response rate of the semiconductor structure. The larger the Seebeck coefficient, the faster the response rate of the semiconductor structure.

[0067] In other embodiments, the material of the substrate may also be Ge, InAs, InSb, GaAs or GaN.

[0068] The channel region 100A is used as a region for subsequently forming a channel layer, and provides a channel for carrier flow between a source electrode and a drain electrode that are subsequently formed.

[0069] The source region 100B is a region where a source electrode is subsequently formed, and the drain region 100C is a region where a drain electrode is subsequently formed.

[0070] refer to Figure 3 , a doping layer 101 is formed in the substrate 100 in the channel region 100A.

[0071] Specifically, by forming a doping layer 101 in the substrate 100 of the channel region 100A, and subsequently forming a channel layer on the top surface of the substrate 100 in the channel region 100A, the channel layer has high electronic thermal conductivity and the channel layer is in contact with the doping layer 101, so that the doping layer 101 can adjust the Fermi level of the channel layer, thereby improving the Seebeck coefficient of the channel layer. The size of the Seebeck coefficient can determine the response rate of the semiconductor structure. The larger the Seebeck coefficient, the higher the response rate of the semiconductor structure. The doping layer can also provide additional hot carriers for the channel layer, further improving the response rate of the semiconductor structure. At the same time, the channel layer has high electronic thermal conductivity, which can reduce the response time of the semiconductor structure, thereby improving both the response rate and the response time of the semiconductor structure.

[0072] In this embodiment, in the step of forming the doping layer 101 , the doping layer 101 is located in the substrate 100 in the channel region 100A at the side of the source region 100B.

[0073] After the channel layer is subsequently formed, hot carriers in the doping layer 101 in the substrate 100 of the channel region 100A located at the side of the source region 100B diffuse from the source region 100B to the drain region 100C, so that there are more hot carriers in the channel layer, thereby adjusting the Fermi level of the channel layer.

[0074] In other embodiments, the doping layer may also be located in the substrate of the channel region on the side of the drain region, or the doping layer is located in the substrate of the channel region on the side of the source region, and the doping layer is located in the substrate of the channel region on the side of the drain region.

[0075] In this embodiment, the step of forming a doping layer 101 in the substrate 100 in the channel region 100A includes: forming a patterned shielding layer on the top surface of the substrate 100, the shielding layer covering the source region 100B and the drain region 100C and exposing a portion of the top surface of the substrate 100 in the channel region 100A; performing a doping treatment on the exposed substrate 100 in the channel region 100A to form a doping layer 101 in the substrate 100 in the channel region 100A.

[0076] The patterned shielding layer protects the covered area. In the subsequent doping process of the substrate 100 in the exposed channel area 100A, the probability of doping ions entering the area covered by the shielding layer is reduced, thereby improving the performance of the semiconductor structure.

[0077] In this embodiment, the material of the shielding layer includes silicon nitride, silicon oxide, or a stack of silicon nitride and silicon oxide.

[0078] As an example, the step of forming a patterned blocking layer on the top surface of the substrate 100 includes: forming a blocking material layer on the top surface of the substrate 100; forming a patterned photoresist layer on the top surface of the blocking material layer, the photoresist layer exposing the top surface of the channel region 100A portion of the substrate 100; using the photoresist layer as a mask, patterning the blocking material layer to form a patterned blocking layer on the top surface of the substrate 100.

[0079] In this embodiment, the process of performing doping treatment on the exposed channel region 100A of the substrate 100 includes an ion implantation process.

[0080] It should be noted that the ion implantation process has the characteristics of high controllability of doping depth and concentration. By adopting the ion implantation process to dope the substrate 100 of the exposed channel area 100A, the concentration of doped ions in the doping layer 101 can meet the process, so that the doping layer 101 can adjust the Fermi level of the channel layer, thereby improving the Seebeck coefficient of the channel layer.

[0081] It should also be noted that during the ion implantation process, the doped ions include N-type ions or P-type ions.

[0082] Specifically, the N-type ions include nitrogen, phosphorus, arsenic, antimony, fluorine, chlorine, bromine or iodine, and the P-type ions include boron, aluminum, gallium, indium, beryllium, magnesium, calcium or strontium.

[0083] It should be noted that during the ion implantation process, the doping dose should not be too large or too small. If the doping dose is too large, it may easily lead to the temperature of a single hot electron not being high enough, the diffusion distance not being large enough, and total reflection with half-wave loss, which may reduce the surface light intensity and affect the light absorption of the device; if the doping dose is too small, it may easily lead to too few carriers in the doping layer 101, which cannot provide more hot carriers for the channel layer, and the Fermi level of the channel layer is not adjusted, thereby reducing the Seebeck coefficient of the channel layer, and further slowing down the response rate of the semiconductor structure, affecting the performance of the semiconductor structure. For this reason, in this embodiment, during the ion implantation process, the doping dose range is 1E13atom / cm 3 To 1E15atom / cm 3 .

[0084] It should also be noted that during the ion implantation process, the implantation energy should not be too large or too small. If the implantation energy is too large, it is easy to cause the doping depth of the doping layer 101 to be too large, resulting in the doping layer 101 being unable to contact the channel layer, thereby causing the doping layer 101 to fail to provide more hot carriers to the channel layer, thereby affecting the response rate of the semiconductor structure; if the implantation energy is too small, it is easy to cause too few carriers in the doping layer 101, failing to provide more hot carriers to the channel layer, causing the Fermi level of the channel layer to not be adjusted, thereby reducing the Seebeck coefficient of the channel layer, and then slowing down the response rate of the semiconductor structure, affecting the performance of the semiconductor structure. For this reason, in the present embodiment, during the ion implantation process, the implantation energy is 10kev to 200kev.

[0085] Specifically, along the normal direction of the surface of the substrate 100, the thickness of the doping layer 101 should not be too large or too small. If the thickness of the doping layer 101 is too small, it is easy to cause too few carriers in the doping layer 101, and it is impossible to provide more hot carriers for the channel layer, so that the Fermi level of the channel layer is not adjusted, thereby reducing the Seebeck coefficient of the channel layer, and then slowing down the response rate of the semiconductor structure, affecting the performance of the semiconductor structure; if the thickness of the doping layer 101 is too large, it is easy to cause the hot electrons in the doping layer to spend more time to reach the channel, increasing the response time. For this reason, in this embodiment, along the normal direction of the surface of the substrate 100, the thickness of the doping layer 101 is 50 nanometers to 200 nanometers.

[0086] It should be noted that, after forming the doping layer 101 , the method for forming the semiconductor structure further includes: removing the shielding layer.

[0087] The blocking layer is removed to provide a process basis for subsequently forming a channel layer on the top surface of the substrate 100 in the channel region 100A.

[0088] In this embodiment, the process of removing the shielding layer includes a wet etching process.

[0089] refer to Figure 4 A channel layer 102 is formed on the top surface of the substrate 100 in the channel region 100A. The channel layer 102 has high electron thermal conductivity and is in contact with the doping layer 101 .

[0090] The channel layer 102 provides a channel for carrier flow between the subsequently formed source and drain. On the one hand, the channel layer 102 has a high electronic thermal conductivity, which makes the electron energy loss of the channel layer 102 faster, thereby making the response time of the photothermoelectric terahertz detector faster. On the other hand, the channel layer 102 is in contact with the doping layer 101, so that the doping layer 101 can adjust the Fermi level of the channel layer 102, thereby improving the Seebeck coefficient of the channel layer 102. The size of the Seebeck coefficient can determine the response rate of the semiconductor structure. The larger the Seebeck coefficient, the higher the response rate of the semiconductor structure. The doping layer 101 can also provide additional hot carriers for the channel layer 102, further improving the response rate of the semiconductor structure. At the same time, the channel layer 102 has a high electronic thermal conductivity, which can reduce the response time of the semiconductor structure, thereby improving the response rate and response time of the semiconductor structure.

[0091] In this embodiment, the process of forming the channel layer 102 on the top surface of the substrate 100 in the channel region 100A includes a wet transfer process, an in-situ growth process or a dry transfer process.

[0092] The in-situ growth process can directly grow two-dimensional materials on the substrate surface, avoiding contamination and damage to the material. The wet transfer process is currently the most commonly used process for transferring large-area non-in-situ grown two-dimensional materials, causing less damage to the material. The dry transfer process can avoid the contamination of the two-dimensional material surface by the chemicals used in the wet transfer process, reducing the impact of the transfer process on the mobility of the two-dimensional material.

[0093] In this embodiment, the material of the channel layer 102 includes one or more of Cn, NiTe2, NiSe2, PtTe2, PtSe2, PdTe2 and PdSe2.

[0094] Specifically, Cn, NiTe2, NiSe2, PtTe2, PtSe2, PdTe2 and PdSe2 are all materials with Dirac band structure, and therefore have high electronic thermal conductivity. High electronic thermal conductivity makes the thermal electron energy loss of the channel layer 102 faster, thereby making the response time of the photothermoelectric terahertz detector faster. At the same time, the channel layer 102 is in contact with the doping layer 101, so that the doping layer 101 can provide more hot carriers for the channel layer 102, thereby improving the response rate and response time of the semiconductor structure.

[0095] It should be noted that the number of atomic layers of the channel layer 102 should not be too many along the normal direction of the surface of the substrate 100. If the number of atomic layers of the channel layer 102 is too many, the doping of the channel layer 102 by the doping layer 101 will be weakened. For this reason, in this embodiment, the number of atomic layers of the channel layer 102 is 1 to 20 layers.

[0096] refer to Figure 5 A source electrode 116 is formed on the top of the substrate 100 in the source region 100B, and the source electrode 116 contacts one end of the channel layer 102 . A drain electrode 106 is formed on the top of the substrate 100 in the drain region 100C, and the drain electrode 106 contacts the other end of the channel layer 102 .

[0097] In this embodiment, the steps of forming the source 116 and the drain 106 include: forming a source material layer on the top of the substrate 100; forming a patterned first mask layer on the top of the source material layer, the first mask layer being located at the top of the source region 100B; patterning the source material layer using the first mask layer as a mask to form the source 116 on the top of the source region 100B; forming a drain material layer on the top of the substrate 100, the drain material layer also covering the first mask layer; forming a patterned second mask layer on the top of the drain material layer, the second mask layer being located at the top of the drain region 100C; patterning the drain material layer using the second mask layer as a mask to form the source 116 on the top of the source region 100B; and removing the first mask layer and the second mask layer.

[0098] It should be noted that the source 116 is in contact with one end of the channel layer 102, and the drain 106 is in contact with the other end of the channel layer 102. After the source 116 and the drain 106 are electrically connected to the external circuit structure, the source 116 and the drain 106 are electrically connected through the channel layer 102, providing a channel for carrier flow between the source 116 and the drain 106.

[0099] refer to Figure 6After forming the source 116 and the drain 106 and before subsequently forming the metal layer 110 , the method further includes: forming a dielectric layer 108 on the top of the channel layer 102 at the side of the doping layer 101 .

[0100] The dielectric layer 108 is used to electrically isolate the channel layer 102 from a subsequently formed metal layer 110 , thereby reducing the risk of electrical leakage between the metal layer 110 and the channel layer 102 .

[0101] In this embodiment, the process of forming the dielectric layer 108 includes a chemical vapor deposition process or an atomic layer deposition process.

[0102] In this embodiment, the material of the dielectric layer 108 includes one or more of SiO 2 , Al 2 O 3 , Si 3 N 4 and h-BN.

[0103] Specifically, SiO 2 , Al 2 O 3 , Si 3 N 4 and h-BN materials are all dielectric materials with good insulation properties, and can play a good role in electrically isolating the metal layer 110 from the channel layer 102 .

[0104] refer to Figure 7 After forming the source 116 and the drain 106 , the method for forming the semiconductor structure further includes: forming a metal layer 110 on the top of the substrate 100 in the channel region 100A on the side of the doping layer 101 and away from the source 116 .

[0105] Specifically, the metal layer 110 has the function of gathering the terahertz waves received by the photothermoelectric terahertz detector, thereby increasing the terahertz intensity in the local area, causing the temperature of the local area of ​​the photothermoelectric terahertz detector to rise, forming a temperature gradient inside, and hot carriers diffuse from the hot end to the cold end driven by the temperature gradient, thereby generating a charge difference in the photothermoelectric terahertz detector.

[0106] In this embodiment, the step of forming the metal layer 110 includes: forming a metal material layer on the top surface of the substrate 100 in the channel region 100A; performing patterning on the metal material layer to form a metal layer 110 on the top of the substrate 100 in the channel region 100A on the side of the doping layer 101 and away from the source 116.

[0107] It should be noted that, in the step of forming the metal layer 110 , the metal layer 110 also covers the dielectric layer 108 , thereby reducing the risk of leakage between the metal layer 110 and the doping layer 101 .

[0108] In this embodiment, the material of the metal layer 110 includes one or more of gold, copper, chromium, titanium, aluminum, tungsten, tantalum and nickel.

[0109] Among them, copper, chromium, titanium, aluminum, tungsten, tantalum, and nickel are metal materials commonly used in semiconductor manufacturing processes. From a preparation perspective, they are compatible with existing large-scale processing technologies. While the metal layer 110 realizes the function of gathering terahertz waves, it will cause loss of light energy. Gold and aluminum will reduce the loss of light energy.

[0110] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include; A substrate, the substrate comprising a channel region, a source region located on one side of the channel region, and a drain region located on the other side of the channel region; a doping layer, located in the substrate in the channel region; A channel layer, located on the top surface of the substrate in the channel region, the channel layer has high electron thermal conductivity and is in contact with the doping layer; A source electrode is located at the top of the substrate in the source region, and the source electrode contacts one end of the channel layer; a drain electrode is located at the top of the substrate in the drain region, and the drain electrode contacts the other end of the channel layer.

2. The semiconductor structure according to claim 1, wherein: The material of the channel layer includes one or more of Cn, NiTe2, NiSe2, PtTe2, PtSe2, PdTe2 and PdSe2.

3. The semiconductor structure according to claim 1, wherein: The doping layer is located in the substrate of the channel region on the side of the source region; or, the doping layer is located in the substrate of the channel region on the side of the drain region; or, the doping layer is located in the substrate of the channel region on the side of the source region, and the doping layer is located in the substrate of the channel region on the side of the drain region.

4. The semiconductor structure according to claim 1, wherein: Along the normal direction of the substrate surface, the thickness of the doping layer is 50 nanometers to 200 nanometers.

5. The semiconductor structure according to claim 1, wherein: Along the normal direction of the substrate surface, the number of atomic layers of the channel layer is 1 to 20.

6. The semiconductor structure according to claim 1, wherein: The material of the substrate includes intrinsic silicon.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a metal layer located on the side of the doped layer and on the top of the substrate in the channel region away from the source; or a metal layer located on the side of the doped layer and on the top of the substrate in the channel region away from the drain.

8. The semiconductor structure according to claim 7, wherein: The material of the metal layer includes one or more of gold, copper, chromium, titanium, aluminum, tungsten, tantalum and nickel.

9. The semiconductor structure according to claim 7, wherein: The semiconductor structure further includes a dielectric layer located between the metal layer and the channel layer.

10. The semiconductor structure according to claim 9, wherein: The material of the dielectric layer includes one or more of SiO2, Al2O3, Si3N4 and h-BN.

11. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a channel region, a source region located on one side of the channel region, and a drain region located on the other side of the channel region; forming a doped layer in the substrate in the channel region; forming a channel layer on the top surface of the substrate in the channel region, wherein the channel layer has high electron thermal conductivity and is in contact with the doping layer; A source electrode is formed on the top of the substrate in the source region, the source electrode is in contact with one end of the channel layer, and a drain electrode is formed on the top of the substrate in the drain region, the drain electrode is in contact with the other end of the channel layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming the doping layer, the doping layer is located in the substrate of the channel region at the side of the source region; or, in the step of forming the doping layer, the doping layer is located in the substrate of the channel region at the side of the drain region; Alternatively, in the step of forming the doping layer, the doping layer is located in the substrate of the channel region at the side of the source region, and the doping layer is located in the substrate of the channel region at the side of the drain region.

13. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming a doping layer in the substrate in the channel region includes: forming a patterned shielding layer on the top surface of the substrate, the shielding layer covers the source region and the drain region and exposes a portion of the top surface of the substrate in the channel region; Performing a doping process on the exposed substrate in the channel region to form a doping layer in the substrate in the channel region; The shielding layer is removed.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process of performing doping treatment on the exposed channel region substrate includes an ion implantation process.

15. The method for forming a semiconductor structure according to claim 14, wherein: The parameters of the ion implantation process include: the doping ions include N-type ions or P-type ions; the doping dose range is 1E13atom / cm 3 To 1E15atom / cm 3 ; The implantation energy range is 10kev to 200kev.

16. The method for forming a semiconductor structure according to claim 11, wherein: The process of forming the channel layer on the top surface of the substrate in the channel region includes a wet transfer process, an in-situ growth process or a dry transfer process.

17. The method for forming a semiconductor structure according to claim 11, wherein: After forming the source and drain, the method for forming the semiconductor structure further includes: forming a metal layer on the side of the doping layer and on the top of the substrate in the channel region opposite to the source; or forming a metal layer on the side of the doping layer and on the top of the substrate in the channel region opposite to the drain.

18. The method for forming a semiconductor structure according to claim 17, wherein: After forming the source and drain, and before forming the metal layer, the method further comprises: forming a dielectric layer on the top of the channel layer at the side of the doping layer; In the step of forming the metal layer, the metal layer covers the dielectric layer.

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