Machine learning attack resistant strong PUF circuit based on delay deviation screening strategy

Abstract

The invention discloses an anti-machine learning attack strong PUF circuit based on a delay deviation screening strategy, which comprises n delay modules, n-1 interconnection modules, an arbiter array and an exclusive-OR gate, n is an integer greater than or equal to 1, each delay module is realized based on a deviation source structure, n-1 is an integer greater than or equal to 1, n-1 is an integer greater than or equal to 1, n-1 is an integer greater than or equal to 1, and n-1 is an integer greater than or equal to 1. The deviation source structure characteristic of the delay module can increase the number of transmission paths of input signals at the deviation source structure characteristic, and transmission diversity is achieved, so that the mapping relation between excitation and response can have high complexity and unpredictability without arranging multiple strong PUFs. Meanwhile, transmission characteristics (namely transmission paths) of input signals can be further disrupted by using an interconnection module, and in addition, response output is generated by using an exclusive-OR gate, so that the stability is further improved; the method has the advantages of being high in machine learning attack resistance, low in hardware overhead and high in stability.

Description

Technical Field

[0001] The present invention relates to a strong PUF circuit, and in particular to a strong PUF circuit resistant to machine learning attacks based on a delay deviation screening strategy. Background Art

[0002] With the rapid development of the Internet of Things, information transmission between devices is extremely critical, and protecting this information from attacks has become extremely important. Traditional encryption methods rely on key storage, and various attack methods such as invasive attacks and side-channel attacks (SCA) pose serious threats to them, making them difficult to apply to resource-constrained IoT devices. Physical Unclonable Function (PUF) can generate feature keys with randomness, uniqueness and unclonability by extracting the inevitable process deviations in the chip manufacturing process. It is suitable for information security fields such as device authentication, key storage, IP protection, etc. PUF can be divided into weak PUF and strong PUF according to its ability to generate challenge-response pairs (CRP). The number of CRPs generated by weak PUF is small, and it grows linearly with the entropy source area, which is suitable for key generation. Strong PUF can generate exponential CRPs through entropy source reuse, which is suitable for IoT device authentication, but the responses generated in this way are easily attacked by machine learning (ML) modeling.

[0003] To address the above problems, researchers usually increase the complexity of the stimulus-response mapping relationship to improve the ability of strong PUF to resist machine learning modeling attacks. For example, Ma et al. proposed in the paper "MAXuejiao, WANG Pengjun, LI Gang, et al. Machine learning attacks resistant strong PUF design utilizing response obfuscates challenge with lower hardware overhead [J]. Microelectronics Journal, 2023, 142." to use the internal response of PUF to initially obfuscate the original stimulus, and then replace the obfuscated stimulus with bytes through S-box to improve the ability to resist ML attacks. Zhang et al. proposed in the paper "ZHOU Ziyu, WANG Pengjun, LI Gang. Bagua Protocol: AWhole-Process Configurable Protocol for IoT Sensing Devices Security Based on Strong PUF [J]. IEEE Internet of Things Journal, 2024, 11 (1): 805-819." an AC-XOR-PUF based on amplifier bias voltage and amplification relationship, which uses the process deviation and amplification information of two identical amplifier chains to increase the number of ML modeling parameters, thereby resisting ML modeling attacks. Zhou et al. proposed a whole-process configurable protocol in the document "ZHOU Ziyu, WANG Pengjun, LI Gang. Bagua Protocol: A Whole-Process Configurable Protocol for IoT Sensing Devices Security Based on Strong PUF[J]. IEEE Internet of Things Journal, 2024, 11(1): 805-819." This protocol increases the ability of strong PUF to resist ML attacks by configuring different matrix encryption methods for different devices.Tanaka et al. proposed a CF-PUF that uses the strong nonlinear relationship between the convergence time of the bistable loop and the change in threshold voltage in the document “TANAKA Yuki, BIAN Song, HIROMOTO Masayuki, et al. Coinflipping PUF: A novel PUF with improved resistance against machine learning attacks [J]. IEEE transactions on circuits and systems II: express briefs, 2018, 65 (5): 602-606”. Chang et al. in the document “CHANG Zhengtai, SHI Shanshan, SONG Binwei, et al. Modeling attack resistant arbiter PUF with time-variant obfuscation scheme [C]. proceedings of the 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), 2021: 60-63” add a linear feedback shift register before the stimulus to confuse the relationship between the stimulus and the response. Zhang et al. proposed a strong PUF obfuscation technology based on random sets in the paper "ZHANG Jiliang, SHEN Chaoqun. Set-based obfuscation for strong PUFs against machine learning attacks[J]. IEEE transactions on circuits and systems I: regular papers, 2020, 68(1): 288-300", which uses two random numbers to perform XOR on the stimulus and response respectively to achieve the purpose of resisting ML attacks.

[0004] As for simple and practical APUF, researchers have developed variant PUFs based on different combinational logic by using logical operations between multiple APUF responses, such as the XOR-PUF proposed in the paper "SANTIKELLUR Pranesh, CHAKRABORTY RajatSubhra. A Computationally Efficient Tensor Regression Network-Based Modeling Attack on XOR Arbiter PUF and Its Variants[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, 40(6): 1197-1206.", the paper "ALI Rashid, MA Haoyuan, HOU Zhengyi, et al. A Reconfigurable Arbiter MPUF With High Resistance Against Machine Learning Attack[J]. IEEE Transactions on Magnetics, 2021, 57(10): 1-7." and the paper "SAHOO Durga Prasad, MUKHOPADHYAY Debdeep, CHAKRABORTY Rajat Subhra, et al.AMultiplexer-BasedArbiter PUF Composition with Enhanced Reliability and Security[J].IEEETransactions on Computers,2018,67(3):403-417.” The MPUF proposed in the document “YAO Jianrong,PANG Lihui,SU Yang,et al.Design and Evaluate Recomposited OR-AND-XOR-PUF[J].IEEE Transactions on Emerging Topics in Computing,2022:1-1.”

[0005] The above-mentioned strong PUFs resist machine learning modeling attacks by increasing the complexity of the mapping relationship between stimulus and response. Although they have strong resistance to machine learning attacks, they use multiple APUF responses and logical operations between responses to develop variant PUFs based on different combinational logics, which requires the use of multiple strong PUFs, resulting in increased hardware overhead. In addition, the output of each strong PUF may be affected by noise factors such as temperature fluctuations and voltage fluctuations. When the outputs of these strong PUFs interact with each other during the obfuscation process, the output fluctuation of any strong PUF may cause instability in the final output, thereby reducing the stability of the entire strong PUF. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a strong PUF circuit that is resistant to machine learning attacks based on a delay deviation screening strategy, which has strong resistance to machine learning attacks, low hardware overhead, and high stability.

[0007] The technical solution adopted by the present invention to solve the above technical problems is: a strong PUF circuit resistant to machine learning attacks based on a delay deviation screening strategy, comprising n delay modules, n-1 interconnection modules, an arbitrator array and an XOR gate, n is an integer greater than or equal to 1, each delay module is implemented based on a deviation source structure, each delay module has 2×d input terminals, a l-bit selection terminal and d output terminals, d=2 i, i is an integer greater than or equal to 2, l is an integer greater than or equal to 1, each interconnection module has d input terminals and 2×d output terminals, the arbitrator array has d input terminals and d / 2 output terminals, and the XOR gate has d / 2 input terminals and one output terminal; when n=1, the d output terminals of the nth delay module are connected to the d input terminals of the arbitrator array in a one-to-one correspondence, when n is equal to 2, the d output terminals of the first delay module are connected to the d input terminals of the first interconnection module in a one-to-one correspondence, the 2×d output terminals of the first interconnection module are connected to the 2×d input terminals of the second delay module in a one-to-one correspondence, the d output terminals of the nth delay module are connected to the d input terminals of the arbitrator array in a one-to-one correspondence, and when n is greater than or equal to 3, the d output terminals of the pth delay module are connected to the d input terminals of the pth interconnection module in a one-to-one correspondence. , the 2×d output ends of the pth interconnection module are connected to the 2×d input ends of the p+1th delay module in a one-to-one correspondence, p=1, 2, ..., n-1, the d output ends of the nth delay module are connected to the d input ends of the arbiter array in a one-to-one correspondence; the d / 2 output ends of the arbiter array are connected to the d / 2 input ends of the XOR gate in a one-to-one correspondence; the l-bit selection ends of the n delay modules constitute the n×l-bit excitation ends of the strong PUF circuit against machine learning attacks, which are used to access the n×l-bit excitation signal, the output end of the XOR gate is the output end of the strong PUF circuit against machine learning attacks, which is used to output the PUF response, and the 2×d input ends of the first delay module are the 2×d-bit trigger ends of the strong PUF circuit against machine learning attacks, which are used to access the 2×d-bit input signal, and the 2×d-bit input signal is used as the trigger signal;The l-bit selection end of each delay module is used to access the l-bit excitation signal, and the 2×d input ends of each delay module are used to access 2×d input signals. Under the control of the l-bit excitation signal connected to its l-bit selection end, each delay module from the first delay module to the n-1th delay module combines the 2×d input signals connected to its 2×d input ends in pairs and divides them into d groups for screening. Among them, each of the d / 2 groups screens out the ones with larger delays, and each of the other d / 2 groups screens out the ones with smaller delays, and according to The d / 2 selected ones with larger delays and the d / 2 selected ones with smaller delays generate d output signals as the d input signals of the interconnection modules connected thereto, and are output to the d input terminals of the interconnection modules connected thereto through their d output terminals in a one-to-one correspondence. Under the control of the l-bit excitation signal connected to its l-bit selection terminal, the nth delay module combines the 2×d input signals connected to its 2×d input terminals in pairs and divides them into d groups for screening, wherein the ones with larger delays are screened out in each of the d / 2 groups, and the ones with smaller delays are screened out in each of the other d / 2 groups. Screen out the ones with smaller delays, and generate d output signals according to the screened d / 2 ones with larger delays and d / 2 ones with smaller delays, as the d input signals of the arbiter array, and output them to the d input terminals of the arbiter array through its d output terminals one by one. The arbiter array combines the d input signals connected to its d input terminals in pairs, divides them into d / 2 groups for judgment, and obtains d / 2 judgment signals as the d / 2 input signals of the XOR gate, and outputs them to the d / 2 input terminals of the XOR gate one by one through its d / 2 output terminals. The XOR gate performs XOR operation on the d / 2 input signals connected to its d / 2 input terminals, and obtains PUF response and outputs them through its output terminals. Each interconnection module is used to replicate the d input signals connected to its d input terminals, and generates 2×d output signals as the 2×d input signals of the delay module connected to it, and outputs them to the 2×d input terminals of the delay module connected to it through its 2×d output terminals one by one. ;

[0008] Each of the delay modules comprises 1 level of upper deviation source, 1 level of lower deviation source, d / 2 AND gates and d / 2 OR gates, each level of upper deviation source and each level of lower deviation source has d input terminals, d output terminals and 1 selection terminal, each AND gate has 2 input terminals and 1 output terminal, and each OR gate has 2 input terminals and 1 output terminal; the selection terminal of each level of upper deviation source is used to access a 1-bit excitation signal, and the d input terminals of each level of upper deviation source are used to access d input signals. Under the control of the excitation signal accessed by its selection terminal, each level of upper deviation source controls the transmission paths of the d input signals accessed by its d input terminals. The first stage upper deviation source and the second stage lower deviation source are respectively output through the d output terminals, the selection terminal of each stage lower deviation source is used to access the 1-bit excitation signal, the d input terminals of each stage lower deviation source are used to access the d input signals, and the transmission paths of the d input signals accessed by the d input terminals of each stage lower deviation source are transformed under the control of the excitation signal accessed by the selection terminal, and the d output signals are respectively output through the d output terminals; the d input terminals of the first stage upper deviation source and the d input terminals of the first stage lower deviation source, a total of 2×d input terminals, are used as the 2×d input terminals of the delay module, and the output terminals of the d / 2 AND gates are used as the 2×d input terminals of the delay module. The first and second input ends of the delay module are connected in a one-to-one correspondence manner, and the first and second input ends of the delay module are connected in a one-to-one correspondence manner. The first and second input ends of the delay module are connected in a one-to-one correspondence manner, and the first and second input ends of the delay module are connected in a one-to-one correspondence manner. The first and second input ends of the delay module are connected in a one-to-one correspondence manner, and the first and second input ends of the delay module are connected in a one-to-one correspondence manner. The first and second input ends of the delay module are connected in a one-to-one correspondence manner, and the first and second input ends of the delay module are connected in a one-to-one correspondence manner. The first and second input ends of the delay module are connected in a one-to-one correspondence manner, and the first and second input ends of the delay module are connected in a one-to-one correspondence manner. The second input end of the d OR gates, a total of d input ends are connected in one-to-one correspondence, the d output signals generated by the first-stage upper side deviation source are combined in one-to-one correspondence with the d output signals generated by the first-stage lower side deviation source to form d groups of input signals, which are output in one-to-one correspondence to the two input ends of the d / 2 AND gates and the two input ends of the d / 2 OR gates, each d / 2 AND gate performs an AND operation on the two input signals connected to its two input ends, and obtains the operation result as an output signal and outputs it through its output end, each d / 2 OR gate performs an OR operation on the two input signals connected to its two input ends, and obtains the operation result as an output signal and outputs it through its output end;When l=2, the d output terminals of the first-stage upper deviation source are connected to the d input terminals of the second-stage upper deviation source in one-to-one correspondence, the d output terminals of the second-stage upper deviation source are connected to the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence, the d output terminals of the first-stage lower deviation source are connected to the d input terminals of the second-stage lower deviation source in one-to-one correspondence, the d output terminals of the second-stage lower deviation source are connected to the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence, the d output terminals generated by the first-stage upper deviation source are used as the d input signals connected to the d input terminals of the second-stage upper deviation source, and the d output signals generated by the first-stage lower deviation source are connected to the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence. The d output signals are used as the d input signals connected to the d input terminals of the second-stage lower deviation source. The d output signals generated by the second-stage upper deviation source are combined with the d output signals generated by the second-stage lower deviation source in a one-to-one correspondence to form d groups of input signals, which are output to the two input terminals of d / 2 AND gates and the two input terminals of d / 2 OR gates in a one-to-one correspondence. Each d / 2 AND gate performs an AND operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal. Each d / 2 OR gate performs an OR operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal. When l≥3, the d output signals of the q-th upper deviation source are combined with the d output signals generated by the second-stage upper deviation source in a one-to-one correspondence to form d groups of input signals, which are output to the two input terminals of d / 2 AND gates and the two input terminals of d / 2 OR gates in a one-to-one correspondence. The output terminals of the q+1th level upper deviation source are connected one-to-one with the d input terminals, q=1, 2, ..., l-1, the d output terminals of the lth level upper deviation source are connected one-to-one with the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals are connected one-to-one with the d output terminals of the sth level lower deviation source are connected one-to-one with the d input terminals of the s+1th level lower deviation source, s=1, 2, ..., l-1, the d output terminals of the lth level lower deviation source are connected one-to-one with the second input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals are connected one-to-one with the d output signals generated by the qth level upper deviation source as the d input terminals connected to the d input terminals of the q+1th level upper deviation source. Signal; the d output signals generated by the qth level lower side deviation source are used as the d input signals connected to the d input terminals of the q+1th level lower side deviation source; the d output signals generated by the lth level upper side deviation source and the d output signals generated by the lth level lower side deviation source are combined one by one to form d groups of input signals, which are output one by one to the two input terminals of d / 2 AND gates and the two input terminals of d / 2 OR gates. Each d / 2 AND gate performs an AND operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal. Each d / 2 OR gate performs an OR operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal. ;

[0009] Each of the upper deviation sources includes d multiplexers, each of which has two data input terminals, one selection terminal and one output terminal, and the two data input terminals are respectively referred to as the first input terminal and the second input terminal. When the selection terminal is connected to 0, the first input terminal is connected to the output terminal, and when the selection terminal is connected to the digital signal 1, the second input terminal is connected to the output terminal; the selection terminals of the d multiplexers are connected, and the connection terminal is the selection terminal of the upper deviation source; the output terminals of the d multiplexers are used as the d output terminals of the upper deviation source; when d=4, the first input terminal of the first multiplexer is connected to the second input terminal of the second multiplexer, and the connection terminal thereof is the first input terminal of the upper deviation source, the second input terminal of the first multiplexer is connected to the first input terminal of the third multiplexer, and the connection terminal thereof is the second input terminal of the upper deviation source, the first input terminal of the second multiplexer is connected to the second input terminal of the fourth multiplexer, and the connection terminal thereof is the third input terminal of the upper deviation source , the second input terminal of the third multiplexer is connected to the first input terminal of the fourth multiplexer, and the connection terminal thereof is the fourth input terminal of the upper deviation source; when d is greater than 4, the first input terminal of the first multiplexer is connected to the second input terminal of the second multiplexer, and the connection terminal thereof is the first input terminal of the upper deviation source, the first input terminal of the mth multiplexer is connected to the second input terminal of the m-2th multiplexer, and the connection terminal thereof is the m-1th input terminal of the upper deviation source, where m is an odd number. number, and m=3, 5, 7, …, d-1, the first input terminal of the w-th multiplexer is connected to the second input terminal of the w+2-th multiplexer, and the connecting end thereof is the w+1-th input terminal of the upper side deviation source, wherein w is an even number, and w=2, 4, 6, …, d-2, the first input terminal of the d-th multiplexer is connected to the second input terminal of the d-1-th multiplexer, and the connecting end thereof is the d-th input terminal of the upper side deviation source; the structure of each lower side deviation source is exactly the same as the structure of each upper side deviation source.

[0010] When d=4, the first input end of the interconnection module is connected to its second output end and sixth output end, the second input end of the interconnection module is connected to its first output end and fifth output end, the third input end of the interconnection module is connected to its third output end and seventh output end, and the fourth input end of the interconnection module is connected to its fourth output end and eighth output end; when d is greater than 4, the first input end of the interconnection module is connected to its second output end and The interconnected modules are connected to d+2 output terminals, the 2nd input terminal of the interconnected modules is connected to the 1st output terminal and the d+1th output terminal thereof, the hth input terminal of the interconnected modules is connected to the hth output terminal and the d+hth output terminal thereof, wherein h=3, 4, ..., d-2, the d-1th input terminal of the interconnected modules is connected to the dth output terminal and the 2×dth output terminals thereof, and the dth input terminal of the interconnected modules is connected to the d-1th output terminal and the 2×d-1th output terminals thereof.

[0011] The arbitrator array includes d / 2 arbitrator units, each of which has two input terminals and one output terminal. Each input terminal of each arbitrator unit is connected to one input signal. Each arbitrator unit arbitrates the two input signals connected to its two input terminals, and obtains the arbitration result as an output signal through its output terminal; the two input terminals of the d / 2 arbitrator units, a total of d input terminals, are the d input terminals of the arbitrator array, and the output terminals of the d / 2 arbitrator units, a total of d / 2 output terminals, are the d input terminals of the arbitrator array.

[0012] Each arbitrator unit includes two two-input NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two two-input NAND gates are respectively referred to as a first two-input NAND gate and a second two-input NAND gate. The first input terminal of the first two-input NAND gate and the second input terminal of the second two-input NAND gate are the two input terminals of the arbitrator unit. The second input terminal of the first two-input NAND gate is connected to the output terminal of the second two-input NAND gate, and the connection terminal thereof is the output terminal of the arbitrator unit. The output terminal of the first two-input NAND gate is connected to the first input terminal of the second two-input NAND gate.

[0013] Compared with the prior art, the advantage of the present invention is that a strong PUF circuit resistant to machine learning attacks is constructed by n delay modules, n-1 interconnection modules, an arbitrator array and an XOR gate. Each delay module is implemented based on a deviation source structure. Therefore, the deviation source structural characteristics of the delay module can increase the number of transmission paths of the input signal thereat, thereby realizing the diversity of transmission. At the same time, the use of the interconnection module can further disrupt the transmission characteristics (i.e., the transmission path) of the input signal, so that there is no need to set up multiple strong PUFs to make the mapping relationship between the stimulus and the response have high complexity and unpredictability, thereby improving the ability to resist machine learning attacks and avoiding the instability problem caused by setting up multiple strong PUFs. In addition, an XOR gate is finally used to generate a response output, thereby further improving stability. Therefore, the present invention has a strong ability to resist machine learning attacks, a small hardware overhead, and high stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural diagram of a strong PUF circuit resistant to machine learning attacks based on a delay deviation screening strategy of the present invention;

[0015] Figure 2 It is a structural diagram of the delay module of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention;

[0016] Figure 3 It is a structural diagram of the upper side deviation source of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention;

[0017] Figure 4 It is a structural diagram of the interconnection modules of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention;

[0018] Figure 5 It is a structural diagram of the arbiter array of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention;

[0019] Figure 6 It is a structural diagram of the arbiter unit of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention;

[0020] Figure 7 This is a prediction accuracy diagram of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention under logistic regression;

[0021] Figure 8 This is a prediction accuracy diagram of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention under the support vector machine;

[0022] Fig. 9This is a graph showing the prediction accuracy of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention under an artificial neural network attack;

[0023] Fig.10 This is a graph showing the prediction accuracy of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention under the attack of a lightweight gradient boosting machine;

[0024] Fig.11 A graph showing the relationship between the number of test repetitions and stability of a strong PUF circuit resistant to machine learning attacks based on a delay deviation screening strategy of the present invention;

[0025] Fig.12 The diagram is a diagram of the bit error rate and unstable bit ratio of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention at different temperatures when n=1, l=64, d=4;

[0026] Fig.13 The diagram of bit error rate and unstable bit ratio at different temperatures for the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention when n=16, l=4, d=4;

[0027] Fig.14 It is the inter-chip Hamming distance and intra-chip Hamming distance diagram of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below with reference to the accompanying drawings.

[0029] Embodiment 1: Figure 1 As shown in FIG. 1 , a strong PUF circuit against machine learning attacks based on a delay deviation screening strategy includes n delay modules, n-1 interconnect modules, an arbiter array and an XOR gate XOR1, where n is an integer greater than or equal to 1, and each delay module is implemented based on a deviation source structure. Each delay module has 2×d input terminals, a l-bit selection terminal and d output terminals, where d=2 i, i is an integer greater than or equal to 2, l is an integer greater than or equal to 1, each interconnection module has d input terminals and 2×d output terminals, the arbitrator array has d input terminals and d / 2 output terminals, and the XOR gate NOR1 has d / 2 input terminals and one output terminal; when n=1, the d output terminals of the nth delay module are connected to the d input terminals of the arbitrator array in a one-to-one correspondence, when n is equal to 2, the d output terminals of the 1st delay module are connected to the d input terminals of the 1st interconnection module in a one-to-one correspondence, the 2×d output terminals of the 1st interconnection module are connected to the 2×d input terminals of the 2nd delay module in a one-to-one correspondence, the d output terminals of the nth delay module are connected to the d input terminals of the arbitrator array in a one-to-one correspondence, and when n is greater than or equal to 3, the d output terminals of the pth delay module are connected to the d input terminals of the pth interconnection module in a one-to-one correspondence. One-to-one connection, 2×d output terminals of the p-th interconnection module are connected to 2×d input terminals of the p+1-th delay module in a one-to-one correspondence, p=1, 2, ..., n-1, d output terminals of the n-th delay module are connected to d input terminals of the arbiter array in a one-to-one correspondence; d / 2 output terminals of the arbiter array are connected to d / 2 input terminals of the XOR gate NOR1 in a one-to-one correspondence; the l-bit selection terminals of the n delay modules constitute the n×l-bit excitation terminals of the strong PUF circuit against machine learning attacks, which are used to access the n×l-bit excitation signal, the output terminal of the XOR gate NOR1 is the output terminal of the strong PUF circuit against machine learning attacks, which is used to output the PUF response, and the 2×d input terminals of the first delay module are the 2×d-bit trigger terminals of the strong PUF circuit against machine learning attacks, which are used to access the 2×d-bit input signal, and the 2×d-bit input signal is used as the trigger signal;The l-bit selection end of each delay module is used to access the l-bit excitation signal, and the 2×d input ends of each delay module are used to access 2×d input signals. Under the control of the l-bit excitation signal connected to its l-bit selection end, each delay module from the first delay module to the n-1th delay module combines the 2×d input signals connected to its 2×d input ends in pairs and divides them into d groups for screening, wherein each of the d / 2 groups screens out the ones with larger delays, and each of the other d / 2 groups screens out the ones with smaller delays, and According to the d / 2 selected ones with larger delays and d / 2 selected ones with smaller delays, d output signals are generated as d input signals of the interconnection modules connected thereto, and are output to the d input terminals of the interconnection modules connected thereto through their d output terminals in a one-to-one correspondence. Under the control of the l-bit excitation signal connected to its l-bit selection terminal, the nth delay module combines the 2×d input signals connected to its 2×d input terminals in pairs and divides them into d groups for screening, wherein the one with larger delay is screened out from each of the d / 2 groups, and the other d / 2 Each group in the group selects the one with smaller delay, and generates d output signals according to the selected d / 2 ones with larger delay and d / 2 ones with smaller delay, as the d input signals of the arbiter array, which are output to the d input ends of the arbiter array through its d output ends one by one. The arbiter array combines the d input signals connected to its d input ends in pairs, divides them into d / 2 groups for judgment, and obtains d / 2 judgment signals as the d / 2 input signals of the exclusive OR gate NOR1, which are output to the d input ends of the arbiter array one by one through its d / 2 output ends. The corresponding output is sent to the d / 2 input terminals of the XOR gate NOR1. The XOR gate NOR1 performs an XOR operation on the d / 2 input signals connected to its d / 2 input terminals, and obtains the PUF response and outputs it through its output terminals. Each interconnection module is used to replicate the d input signals connected to its d input terminals, and generates 2×d output signals as the 2×d input signals of the delay module connected to it, and outputs them to the 2×d input terminals of the delay module connected to it through its 2×d output terminals one by one. ;

[0030] In this embodiment, each delay module is implemented based on the deviation source structure, so that the deviation source structural characteristics of the delay module can increase the number of transmission paths of the input signal thereat, thereby realizing transmission diversity. At the same time, the use of the interconnection module can further disrupt the transmission characteristics (i.e., the transmission path) of the input signal, so that there is no need to set up multiple strong PUFs to make the mapping relationship between the stimulus and the response have high complexity and unpredictability, thereby improving the ability to resist machine learning attacks and avoiding the instability problem caused by setting up multiple strong PUFs. In addition, an XOR gate is finally used to generate a response output, thereby further improving stability. Therefore, while having strong resistance to machine learning attacks, the hardware overhead is small and the stability is high.

[0031] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: Figure 2As shown, in this embodiment, each delay module includes 1 level of upper side deviation source, 1 level of lower side deviation source, d / 2 AND gates and d / 2 OR gates, each level of upper side deviation source and each level of lower side deviation source have d input terminals, d output terminals and 1 selection terminal, each AND gate has 2 input terminals and 1 output terminal, and each OR gate has 2 input terminals and 1 output terminal; the selection terminal of each level of upper side deviation source is used to access a 1-bit excitation signal, and the d input terminals of each level of upper side deviation source are used to access d input signals. Under the control of the excitation signal accessed to its selection terminal, each level of upper side deviation source controls the d input terminals accessed to its d input terminals. The transmission path of the signal is transformed to generate d output signals which are outputted through its d output terminals in one-to-one correspondence. The selection terminal of each lower deviation source is used to access a 1-bit excitation signal. The d input terminals of each lower deviation source are used to access d input signals. Under the control of the excitation signal accessed to its selection terminal, each lower deviation source transforms the transmission path of the d input signals accessed to its d input terminals to generate d output signals which are outputted through its d output terminals in one-to-one correspondence. The d input terminals of the first-stage upper deviation source and the d input terminals of the first-stage lower deviation source, a total of 2×d input terminals, are used as 2×d input terminals of the delay module. / 2 output ends of the AND gates and d / 2 output ends of the OR gates, a total of d output ends serve as d output ends of the delay module, the selection end of the l-th level upper deviation source is connected to the selection end of the l-th level lower deviation source, and the connection end is the l-th selection end of the delay module, the 1st selection end to the l-th selection end of the delay module, a total of l selection ends, constitute the l-bit selection end of the delay module; when l=1, the d output ends of the 1st level upper deviation source are connected one-to-one with the first input end of the d / 2 AND gates and the d / 2 OR gates, a total of d input ends, the d output ends of the 1st level lower deviation source are connected with the d / 2 AND gates and the d / 2 OR gates. The second input terminal of the gate, a total of d input terminals are connected one-to-one, the d output signals generated by the first-stage upper side deviation source are combined one-to-one with the d output signals generated by the first-stage lower side deviation source to form d groups of input signals, which are output one-to-one to two input terminals of d / 2 AND gates and two input terminals of d / 2 OR gates, each d / 2 AND gate performs an AND operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal, each d / 2 OR gate performs an OR operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal;When l=2, the d output terminals of the first-stage upper deviation source are connected to the d input terminals of the second-stage upper deviation source in one-to-one correspondence, the d output terminals of the second-stage upper deviation source are connected to the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence, the d output terminals of the first-stage lower deviation source are connected to the d input terminals of the second-stage lower deviation source in one-to-one correspondence, the d output terminals of the second-stage lower deviation source are connected to the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence, the d output terminals generated by the first-stage upper deviation source are used as the d input signals connected to the d input terminals of the second-stage upper deviation source, and the d output signals generated by the first-stage lower deviation source are connected to the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence. The d output signals are used as the d input signals connected to the d input terminals of the second-stage lower deviation source. The d output signals generated by the second-stage upper deviation source are combined with the d output signals generated by the second-stage lower deviation source in a one-to-one correspondence to form d groups of input signals, which are output to the two input terminals of d / 2 AND gates and the two input terminals of d / 2 OR gates in a one-to-one correspondence. Each d / 2 AND gate performs an AND operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal. Each d / 2 OR gate performs an OR operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal. When l≥3, the d output signals of the q-th upper deviation source are combined with the d output signals generated by the second-stage upper deviation source in a one-to-one correspondence to form d groups of input signals, which are output to the two input terminals of d / 2 AND gates and the two input terminals of d / 2 OR gates in a one-to-one correspondence. The output terminals of the q+1th level upper deviation source are connected one-to-one with the d input terminals, q=1, 2, ..., l-1, the d output terminals of the lth level upper deviation source are connected one-to-one with the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals are connected one-to-one with the d output terminals of the sth level lower deviation source are connected one-to-one with the d input terminals of the s+1th level lower deviation source, s=1, 2, ..., l-1, the d output terminals of the lth level lower deviation source are connected one-to-one with the second input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals are connected one-to-one with the d output signals generated by the qth level upper deviation source as the d input terminals connected to the d input terminals of the q+1th level upper deviation source. Signal; the d output signals generated by the qth level lower side deviation source are used as the d input signals connected to the d input terminals of the q+1th level lower side deviation source; the d output signals generated by the lth level upper side deviation source and the d output signals generated by the lth level lower side deviation source are combined one by one to form d groups of input signals, which are output one by one to the two input terminals of d / 2 AND gates and the two input terminals of d / 2 OR gates. Each d / 2 AND gate performs an AND operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal. Each d / 2 OR gate performs an OR operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal. ;

[0032] like Figure 3As shown, in this embodiment, each upper deviation source includes d multiplexers, each of which has two data input terminals, one selection terminal and one output terminal, and its two data input terminals are respectively referred to as its first input terminal and its second input terminal. When its selection terminal is connected to 0, its first input terminal is connected to its output terminal, and when its selection terminal is connected to a digital signal 1, its second input terminal is connected to its output terminal; the selection terminals of the d multiplexers are connected, and their connection terminals are the selection terminals of the upper deviation source; the d multiplexers of output terminal, as d output terminals of the upper deviation source; when d=4, the first input terminal of the first multiplexer is connected to the second input terminal of the second multiplexer, and the connection terminal thereof is the first input terminal of the upper deviation source, the second input terminal of the first multiplexer is connected to the first input terminal of the third multiplexer, and the connection terminal thereof is the second input terminal of the upper deviation source, the first input terminal of the second multiplexer is connected to the second input terminal of the fourth multiplexer, and the connection terminal thereof is the third input terminal of the upper deviation source The second input terminal of the third multiplexer is connected to the first input terminal of the fourth multiplexer, and the connection terminal thereof is the fourth input terminal of the upper deviation source; when d is greater than 4, the first input terminal of the first multiplexer is connected to the second input terminal of the second multiplexer, and the connection terminal thereof is the first input terminal of the upper deviation source, the first input terminal of the mth multiplexer is connected to the second input terminal of the m-2th multiplexer, and the connection terminal thereof is the m-1th input terminal of the upper deviation source, where m is an odd number. number, and m=3, 5, 7, …, d-1, the first input terminal of the w-th multiplexer is connected to the second input terminal of the w+2-th multiplexer, and the connecting end thereof is the w+1-th input terminal of the upper side deviation source, wherein w is an even number, and w=2, 4, 6, …, d-2, the first input terminal of the d-th multiplexer is connected to the second input terminal of the d-1-th multiplexer, and the connecting end thereof is the d-th input terminal of the upper side deviation source; the structure of each lower side deviation source is exactly the same as the structure of each upper side deviation source.

[0033] In this embodiment, a delay module is formed by l-level upper deviation source, l-level lower deviation source, d / 2 AND gates and d / 2 OR gates. Both the upper deviation source and the lower deviation source are implemented by a symmetrically connected deviation source structure formed by a multiplexer, thereby increasing the diversity of input signal transmission. Then, d / 2 AND gates and d / 2 OR gates are used to further disrupt the transmission path of the input signal, thereby increasing the unpredictability of signal transmission and improving the ability to resist machine learning attacks.

[0034] Embodiment 3: This embodiment is basically the same as Embodiment 1, except that: Figure 4As shown, in this embodiment, when d=4, the first input end of the interconnected module is connected to its second output end and the sixth output end, the second input end of the interconnected module is connected to its first output end and the fifth output end, the third input end of the interconnected module is connected to its third output end and the seventh output end, and the fourth input end of the interconnected module is connected to its fourth output end and the eighth output end; when d is greater than 4, the first input end of the interconnected module is connected to its second output end and the d+2th output end, the second input end of the interconnected module is connected to its first output end and the d+1th output end, and the hth input end of the interconnected module is connected to its hth output end and the d+hth output end, wherein h=3, 4, ..., d-2, the d-1th input end of the interconnected module is connected to its dth output end and the 2×dth output end, and the dth input end of the interconnected module is connected to its d-1th output end and the 2×d-1th output end.

[0035] In this embodiment, the interconnection module connects its d input terminals with the 2×d output terminals accordingly, and copies the d input signals to form 2×d output signals, thereby disrupting the transmission paths of the d input signals, increasing the unpredictability of signal transmission, and improving the ability to resist machine learning attacks.

[0036] Embodiment 4: This embodiment is basically the same as Embodiment 1, except that: Figure 5 As shown, in this embodiment, the arbitrator array includes d / 2 arbitrator units, each of which has two input terminals and one output terminal. Each input terminal of each arbitrator unit is connected to one input signal. Each arbitrator unit arbitrates the two input signals connected to its two input terminals, and obtains the arbitration result as an output signal and outputs it through its output terminal; the two input terminals of the d / 2 arbitrator units, a total of d input terminals, are the d input terminals of the arbitrator array, and the output terminals of the d / 2 arbitrator units, a total of d / 2 output terminals, are the d input terminals of the arbitrator array.

[0037] like Figure 6 As shown, in this embodiment, each arbitrator unit includes two two-input NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two two-input NAND gates are respectively referred to as a first two-input NAND gate NAND1 and a second two-input NAND gate NAND2. The first input terminal of the first two-input NAND gate NAND1 and the second input terminal of the second two-input NAND gate NAND2 are two input terminals of the arbitrator unit. The second input terminal of the first two-input NAND gate NAND1 is connected to the output terminal of the second two-input NAND gate NAND2, and the connection terminal thereof is the output terminal of the arbitrator unit. The output terminal of the first two-input NAND gate NAND1 is connected to the first input terminal of the second two-input NAND gate NAND2.

[0038] In this embodiment, the arbiter unit judges two input signals and outputs a 1-bit output signal. The arbiter array uses multiple arbiter units to combine two input signals on a symmetric path and output them in pairs, thereby reducing the number of input signals of the XOR gate and improving the stability of the strong PUF circuit based on the delay deviation screening strategy of the present invention that is resistant to machine learning attacks.

[0039] In order to verify the performance of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention, the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention was tested.

[0040] Logistic regression is used to perform machine learning attack tests on the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention. A total of 600,000 stimulus response pairs are collected. The number of stimulus response pairs in the training set is 500, 1000, 5000, 10000, 50000, 100000 and 500000 respectively, and the number of stimulus response pairs in the test set is 100,000. The prediction accuracy is as follows: Figure 7 shown. Figure 7 In the present invention, the strong PUF circuit based on the delay deviation screening strategy for resisting machine learning attacks was tested when n=1, l=64, d=4 (i.e. (1,64,4)-CO-PUF), when n=2, l=32, d=4 (i.e. (2,32,4)-CO-PUF), when n=4, l=16, d=4 (i.e. (4,16,4)-CO-PUF), when n=8, l=8, d=4 (i.e. (8,8,4)-CO-PUF), when n=16, l=4, d=4 (i.e. (16,4,4)-CO-PUF). Analysis Figure 7 It can be seen that the prediction accuracy of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention under logistic regression is lower than 59%, and has good resistance to logistic regression attacks.

[0041] The support vector machine is used to perform a machine learning attack test on the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention. A total of 600,000 stimulus response pairs are collected. The number of stimulus response pairs in the training set is 500, 1000, 5000, 10000, 50000, 100000 and 500000 respectively, and the number of stimulus response pairs in the test set is 100,000. The prediction accuracy is as follows: Figure 8 shown. Figure 8In the present invention, the strong PUF circuit based on the delay deviation screening strategy for resisting machine learning attacks was tested when n=1, l=64, d=4 (i.e. (1,64,4)-CO-PUF), when n=2, l=32, d=4 (i.e. (2,32,4)-CO-PUF), when n=4, l=16, d=4 (i.e. (4,16,4)-CO-PUF), when n=8, l=8, d=4 (i.e. (8,8,4)-CO-PUF), when n=16, l=4, d=4 (i.e. (16,4,4)-CO-PUF). Analysis Figure 8 It can be seen that the prediction accuracy of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention under the support vector machine is lower than 59%, and it has good resistance to support vector machine attacks.

[0042] The artificial neural network is used to perform a machine learning attack test on the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention. A total of 600,000 stimulus response pairs are collected. The number of stimulus response pairs in the training set is 500, 1000, 5000, 10000, 50000, 100000 and 500000 respectively, and the number of stimulus response pairs in the test set is 100,000. The prediction accuracy is as follows: Fig. 9 shown. Fig. 9 In the present invention, the strong PUF circuit based on the delay deviation screening strategy for resisting machine learning attacks was tested when n=1, l=64, d=4 (i.e. (1,64,4)-CO-PUF), when n=2, l=32, d=4 (i.e. (2,32,4)-CO-PUF), when n=4, l=16, d=4 (i.e. (4,16,4)-CO-PUF), when n=8, l=8, d=4 (i.e. (8,8,4)-CO-PUF), when n=16, l=4, d=4 (i.e. (16,4,4)-CO-PUF). Analysis Fig. 9 It can be seen that the prediction accuracy of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention under artificial neural network attacks is lower than 59%, and has good resistance to artificial neural network attacks.

[0043] A lightweight gradient boosting machine is used to perform a machine learning attack test on the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention. A total of 600,000 stimulus response pairs are collected. The number of stimulus response pairs in the training set is 500, 1000, 5000, 10000, 50000, 100000 and 500000 respectively, and the number of stimulus response pairs in the test set is 100,000. The prediction accuracy is as follows: Fig.10 shown. Fig.10In the present invention, the strong PUF circuit based on the delay deviation screening strategy for resisting machine learning attacks was tested when n=1, l=64, d=4 (i.e. (1,64,4)-CO-PUF), when n=2, l=32, d=4 (i.e. (2,32,4)-CO-PUF), when n=4, l=16, d=4 (i.e. (4,16,4)-CO-PUF), when n=8, l=8, d=4 (i.e. (8,8,4)-CO-PUF), when n=16, l=4, d=4 (i.e. (16,4,4)-CO-PUF). Analysis Fig.10 It can be seen that the prediction accuracy of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention under the attack of the lightweight gradient boosting machine is less than 59%, and it has good resistance to the attack of the lightweight gradient boosting machine.

[0044] The stability of the strong PUF circuit based on the delay deviation screening strategy of the present invention, which is resistant to machine learning attacks, was tested under the same FPGA and room temperature. 10,000 sets of the same stimulus were used for repeated testing, and its stability was calculated after each repetition. The relationship between the number of repetitions and the stability of the strong PUF circuit based on the delay deviation screening strategy of the present invention is shown in Figure 2. Fig.11 As shown, Fig.11 In the present invention, the stability of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy is tested when n=1, l=64, d=4 (i.e. (1,64,4)-CO-PUF), when n=2, l=32, d=4 (i.e. (2,32,4)-CO-PUF), when n=4, l=16, d=4 (i.e. (4,16,4)-CO-PUF), when n=8, l=8, d=4 (i.e. (8,8,4)-CO-PUF), when n=16, l=4, d=4 (i.e. (16,4,4)-CO-PUF). Fig.11 It can be seen that after 50 repeated tests, the stability of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention is stable at more than 95%, which has good stability.

[0045] The bit error rate and unstable bit ratio of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention were tested at different temperatures when n=1, l=64, and d=4. It was placed in a constant temperature box with a temperature range of -20°C to 80°C. One thousand groups of responses were extracted under the same stimulus for each test and repeated 20 times. The 20 responses at 27°C were used as a benchmark by majority voting, and the 20 responses measured at other temperatures were compared with the benchmark to obtain the bit error rate of each test at this temperature, and the worst, best, and average bit error rates of each time and 20 times were counted. The bit error rate and unstable bit ratio of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention at different temperatures are shown in the figure below. Fig.12 shown; from Fig.12 It can be seen that the average bit error rate of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention is 1.54% at -20°C, the average bit error rate at 80°C is 2.68%, and the instability at 0°C is the lowest.

[0046] The bit error rate and unstable bit ratio of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention when n=16, l=4, d=4 were tested at different temperatures. It was placed in a constant temperature box with a temperature range of -20°C to 80°C. One thousand groups of responses were extracted under the same stimulus for each test and repeated 20 times. The 20 responses at 27°C were used as a benchmark by majority voting, and the 20 responses measured at other temperatures were compared with the benchmark to obtain the bit error rate of each test at this temperature, and the worst, best and average bit error rates of each time and 20 times were counted. The bit error rate and unstable bit ratio of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention at different temperatures are shown in the figure below. Fig.13 shown; from Fig.13 It can be seen that the average bit error rate of the strong PUF circuit against machine learning attacks based on the delay deviation screening strategy of the present invention is 1.94% at -20°C, the average bit error rate at 80°C is 2.63%, and the unstable bit at 0°C is the lowest.

[0047] Uniqueness describes the ability of a PUF instance to distinguish itself from other PUF instances. The strong PUF circuit based on the delay deviation screening strategy of the present invention is placed in a normal temperature and pressure environment to read the output response cyclically. The inter-chip Hamming distance and intra-chip Hamming distance of the strong PUF circuit based on the delay deviation screening strategy of the present invention are measured experimentally as shown in the figure below: Fig.14 shown. Fig.14In the paper, the intra-chip Hamming distance and inter-chip Hamming distance of the strong PUF circuit based on the delay deviation screening strategy of the present invention against machine learning attacks are tested when n=1, l=64, d=4 (i.e., (1,64,4)-CO-PUF) and when n=16, l=4, d=4 (i.e., (16,4,4)-CO-PUF). Fig.14 It can be seen that the inter-chip Hamming distance and intra-chip Hamming distance of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention are 49.821% and 0.00992 respectively when n=1, l=64, d=4, which are close to the ideal values ​​of 50% and 0, and have good uniqueness. The inter-chip Hamming distance and intra-chip Hamming distance of the strong PUF circuit resistant to machine learning attacks based on the delay deviation screening strategy of the present invention are 50.013% and 0.01203 respectively when n=16, l=4, d=4, which are close to the ideal values ​​of 50% and 0, and have good uniqueness.

Claims

1. A strong PUF circuit against machine learning attacks based on a delay deviation screening strategy, characterized in that The invention comprises n delay modules, n-1 interconnect modules, an arbiter array and an XOR gate, wherein n is an integer greater than or equal to 1, each delay module is implemented based on a deviation source structure, and each delay module has 2×d input terminals, a l-bit selection terminal and d output terminals, wherein d=2 i , i is an integer greater than or equal to 2, l is an integer greater than or equal to 1, each interconnection module has d input terminals and 2×d output terminals, the arbitrator array has d input terminals and d / 2 output terminals, and the XOR gate has d / 2 input terminals and one output terminal; when n=1, the d output terminals of the nth delay module are connected to the d input terminals of the arbitrator array in a one-to-one correspondence, when n is equal to 2, the d output terminals of the first delay module are connected to the d input terminals of the first interconnection module in a one-to-one correspondence, the 2×d output terminals of the first interconnection module are connected to the 2×d input terminals of the second delay module in a one-to-one correspondence, the d output terminals of the nth delay module are connected to the d input terminals of the arbitrator array in a one-to-one correspondence, and when n is greater than or equal to 3, the d output terminals of the pth delay module are connected to the d input terminals of the pth interconnection module in a one-to-one correspondence. , the 2×d output ends of the pth interconnection module are connected to the 2×d input ends of the p+1th delay module in a one-to-one correspondence, p=1, 2, ..., n-1, the d output ends of the nth delay module are connected to the d input ends of the arbiter array in a one-to-one correspondence; the d / 2 output ends of the arbiter array are connected to the d / 2 input ends of the XOR gate in a one-to-one correspondence; the l-bit selection ends of the n delay modules constitute the n×l-bit excitation ends of the strong PUF circuit against machine learning attacks, which are used to access the n×l-bit excitation signal, the output end of the XOR gate is the output end of the strong PUF circuit against machine learning attacks, which is used to output the PUF response, and the 2×d input ends of the first delay module are the 2×d-bit trigger ends of the strong PUF circuit against machine learning attacks, which are used to access the 2×d-bit input signal, and the 2×d-bit input signal is used as the trigger signal;The l-bit selection end of each delay module is used to access the l-bit excitation signal, and the 2×d input ends of each delay module are used to access 2×d input signals. Under the control of the l-bit excitation signal connected to its l-bit selection end, each delay module from the first delay module to the n-1th delay module combines the 2×d input signals connected to its 2×d input ends in pairs and divides them into d groups for screening. Among them, each of the d / 2 groups screens out the ones with larger delays, and each of the other d / 2 groups screens out the ones with smaller delays, and according to The d / 2 selected ones with larger delays and the d / 2 selected ones with smaller delays generate d output signals as the d input signals of the interconnection modules connected thereto, and are output to the d input terminals of the interconnection modules connected thereto through their d output terminals in a one-to-one correspondence. Under the control of the l-bit excitation signal connected to its l-bit selection terminal, the nth delay module combines the 2×d input signals connected to its 2×d input terminals in pairs and divides them into d groups for screening, wherein the ones with larger delays are screened out in each of the d / 2 groups, and the ones with smaller delays are screened out in each of the other d / 2 groups. Screen out the ones with smaller delays, and generate d output signals according to the screened d / 2 ones with larger delays and d / 2 ones with smaller delays, as the d input signals of the arbiter array, and output them to the d input terminals of the arbiter array through its d output terminals one by one. The arbiter array combines the d input signals connected to its d input terminals in pairs, divides them into d / 2 groups for judgment, and obtains d / 2 judgment signals as the d / 2 input signals of the XOR gate, and outputs them to the d / 2 input terminals of the XOR gate one by one through its d / 2 output terminals. The XOR gate performs XOR operation on the d / 2 input signals connected to its d / 2 input terminals, and obtains PUF response and outputs them through its output terminals. Each interconnection module is used to replicate the d input signals connected to its d input terminals, and generates 2×d output signals as the 2×d input signals of the delay module connected to it, and outputs them to the 2×d input terminals of the delay module connected to it through its 2×d output terminals one by one. ; 2. A strong PUF circuit against machine learning attacks based on a delay deviation screening strategy according to claim 1, characterized in that Each of the delay modules includes 1 level of upper deviation source, 1 level of lower deviation source, d / 2 AND gates and d / 2 OR gates, each level of upper deviation source and each level of lower deviation source has d input terminals, d output terminals and 1 selection terminal, each AND gate has 2 input terminals and 1 output terminal, and each OR gate has 2 input terminals and 1 output terminal; the selection terminal of each level of upper deviation source is used to access a 1-bit excitation signal, the d input terminals of each level of upper deviation source are used to access d input signals, and each level of upper deviation source, under the control of the excitation signal accessed by its selection terminal, transforms the transmission paths of the d input signals accessed by its d input terminals, generates d output signals and outputs them one by one through its d output terminals, the selection terminal of each level of lower deviation source is used to access a 1-bit excitation signal, and the d input terminals of each level of lower deviation source are used to Access d input signals, and under the control of the excitation signal connected to the selection end of each level of the lower deviation source, the transmission path of the d input signals connected to its d input ends is transformed to generate d output signals which are outputted through its d output ends in one-to-one correspondence; the d input ends of the first level of the upper deviation source and the d input ends of the first level of the lower deviation source, a total of 2×d input ends, are used as 2×d input ends of the delay module, d / 2 output ends of the AND gate and d / 2 output ends of the OR gate, a total of d output ends, are used as d output ends of the delay module, the selection end of the lth level of the upper deviation source is connected to the selection end of the lth level of the lower deviation source, and the connection end thereof is the lth selection end of the delay module, and the lth selection end to the lth selection end of the delay module, a total of l selection ends, constitute the lth selection end of the delay module; When l=1, the d output terminals of the first-stage upper deviation source are connected to the first input terminals of the d / 2 AND gates and the d / 2 OR gates, a total of d input terminals, in one-to-one correspondence, and the d output terminals of the first-stage lower deviation source are connected to the second input terminals of the d / 2 AND gates and the d / 2 OR gates, a total of d input terminals, in one-to-one correspondence. The d output signals generated by the first-stage upper deviation source are combined with the d output signals generated by the first-stage lower deviation source in one-to-one correspondence to form d groups of input signals, which are output to the two input terminals of the d / 2 AND gates and the two input terminals of the d / 2 OR gates in one-to-one correspondence. Each d / 2 AND gate performs an AND operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal. Each d / 2 OR gate performs an OR operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal. When l=2, the d output terminals of the first-stage upper deviation source are connected to the d input terminals of the second-stage upper deviation source in one-to-one correspondence, the d output terminals of the second-stage upper deviation source are connected to the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence, the d output terminals of the first-stage lower deviation source are connected to the d input terminals of the second-stage lower deviation source in one-to-one correspondence, the d output terminals of the second-stage lower deviation source are connected to the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence, the d output signals generated by the first-stage upper deviation source are used as the d input signals connected to the d input terminals of the second-stage upper deviation source, and the d output terminals of the first-stage lower deviation source are connected to the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence. The d output signals generated by the side deviation source are used as the d input signals connected to the d input terminals of the second-stage lower side deviation source, the d output signals generated by the second-stage upper side deviation source are combined one-to-one with the d output signals generated by the second-stage lower side deviation source to form d groups of input signals, which are output one-to-one to the two input terminals of d / 2 AND gates and the two input terminals of d / 2 OR gates, each d / 2 AND gate performs an AND operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal, and each d / 2 OR gate performs an OR operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal and outputs it through its output terminal; When l≥3, the d output terminals of the qth level upper deviation source are connected to the d input terminals of the q+1th level upper deviation source in one-to-one correspondence, q=1, 2, ..., l-1, the d output terminals of the lth level upper deviation source are connected to the first input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence, the d output terminals of the sth level lower deviation source are connected to the d input terminals of the s+1th level lower deviation source in one-to-one correspondence, s=1, 2, ..., l-1, the d output terminals of the lth level lower deviation source are connected to the second input terminals of d / 2 AND gates and d / 2 OR gates, a total of d input terminals in one-to-one correspondence, wherein the d output signals generated by the qth level upper deviation source are used as the d input terminals of the q+1th level upper deviation source. The d input signals connected to the qth lower side deviation source are used as the d input signals connected to the d input terminals of the q+1th lower side deviation source; the d output signals generated by the lth level upper side deviation source and the d output signals generated by the lth level lower side deviation source are combined one-to-one to form d groups of input signals, which are output one-to-one to the two input terminals of d / 2 AND gates and the two input terminals of d / 2 OR gates, each d / 2 AND gate performs an AND operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal which is output through its output terminal, and each d / 2 OR gate performs an OR operation on the two input signals connected to its two input terminals, and obtains the operation result as an output signal which is output through its output terminal.

3. A strong PUF circuit against machine learning attacks based on a delay deviation screening strategy according to claim 2, characterized in that Each of the upper deviation sources includes d multiplexers, each of which has two data input terminals, one selection terminal and one output terminal, and the two data input terminals are respectively referred to as the first input terminal and the second input terminal. When the selection terminal is connected to 0, the first input terminal is connected to the output terminal, and when the selection terminal is connected to the digital signal 1, the second input terminal is connected to the output terminal; the selection terminals of the d multiplexers are connected, and the connection terminal is the selection terminal of the upper deviation source; the output terminals of the d multiplexers are used as the d output terminals of the upper deviation source; when d=4, the first input terminal of the first multiplexer is connected to the second input terminal of the second multiplexer, and the connection terminal thereof is the first input terminal of the upper deviation source, the second input terminal of the first multiplexer is connected to the first input terminal of the third multiplexer, and the connection terminal thereof is the second input terminal of the upper deviation source, the first input terminal of the second multiplexer is connected to the second input terminal of the fourth multiplexer, and the connection terminal thereof is the third input terminal of the upper deviation source , the second input terminal of the third multiplexer is connected to the first input terminal of the fourth multiplexer, and the connection terminal thereof is the fourth input terminal of the upper deviation source; when d is greater than 4, the first input terminal of the first multiplexer is connected to the second input terminal of the second multiplexer, and the connection terminal thereof is the first input terminal of the upper deviation source, the first input terminal of the mth multiplexer is connected to the second input terminal of the m-2th multiplexer, and the connection terminal thereof is the m-1th input terminal of the upper deviation source, where m is an odd number. number, and m=3, 5, 7, …, d-1, the first input terminal of the w-th multiplexer is connected to the second input terminal of the w+2-th multiplexer, and the connecting end thereof is the w+1-th input terminal of the upper side deviation source, wherein w is an even number, and w=2, 4, 6, …, d-2, the first input terminal of the d-th multiplexer is connected to the second input terminal of the d-1-th multiplexer, and the connecting end thereof is the d-th input terminal of the upper side deviation source; the structure of each lower side deviation source is exactly the same as the structure of each upper side deviation source.

4. A strong PUF circuit against machine learning attacks based on a delay deviation screening strategy according to claim 1, characterized in that When d=4, the first input end of the interconnection module is connected to its second output end and sixth output end, the second input end of the interconnection module is connected to its first output end and fifth output end, the third input end of the interconnection module is connected to its third output end and seventh output end, and the fourth input end of the interconnection module is connected to its fourth output end and eighth output end; when d is greater than 4, the first input end of the interconnection module is connected to its second output end and The interconnected modules are connected to d+2 output terminals, the 2nd input terminal of the interconnected modules is connected to the 1st output terminal and the d+1th output terminal thereof, the hth input terminal of the interconnected modules is connected to the hth output terminal and the d+hth output terminal thereof, wherein h=3, 4, ..., d-2, the d-1th input terminal of the interconnected modules is connected to the dth output terminal and the 2×dth output terminals thereof, and the dth input terminal of the interconnected modules is connected to the d-1th output terminal and the 2×d-1th output terminals thereof.

5. A strong PUF circuit against machine learning attacks based on a delay deviation screening strategy according to claim 1, characterized in that The arbitrator array includes d / 2 arbitrator units, each of which has two input terminals and one output terminal. Each input terminal of each arbitrator unit is connected to one input signal. Each arbitrator unit arbitrates the two input signals connected to its two input terminals, and obtains the arbitration result as an output signal through its output terminal; the two input terminals of the d / 2 arbitrator units, a total of d input terminals, are the d input terminals of the arbitrator array, and the output terminals of the d / 2 arbitrator units, a total of d / 2 output terminals, are the d input terminals of the arbitrator array.

6. A strong PUF circuit against machine learning attacks based on a delay deviation screening strategy according to claim 5, characterized in that Each arbitrator unit includes two two-input NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two two-input NAND gates are respectively referred to as a first two-input NAND gate and a second two-input NAND gate. The first input terminal of the first two-input NAND gate and the second input terminal of the second two-input NAND gate are the two input terminals of the arbitrator unit. The second input terminal of the first two-input NAND gate is connected to the output terminal of the second two-input NAND gate, and the connection terminal thereof is the output terminal of the arbitrator unit. The output terminal of the first two-input NAND gate is connected to the first input terminal of the second two-input NAND gate.

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