Solid-state imaging device

Abstract

The present disclosure relates to a solid-state imaging device capable of suppressing light leakage from large pixels to small pixels. The solid-state imaging device includes a pixel array unit in which a plurality of unit pixels are two-dimensionally arranged, and each of the unit pixels includes a first photoelectric conversion unit formed in a semiconductor substrate, a second photoelectric conversion unit having an area smaller than that of the first photoelectric conversion unit, and an inter-pixel light shielding film provided on at least a part of a boundary between the unit pixels on an incident light side with respect to the semiconductor substrate, a spacer layer provided on an incident light side with respect to the inter-pixel light shielding film, and a light shielding wall provided on at least a portion of a boundary between the unit pixels on the incident light side with respect to the inter-pixel light shielding film and separating the spacer layer. The present disclosure can be applied to, for example, a back-illuminated solid-state imaging device or the like.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device, and more particularly to a solid-state imaging device capable of suppressing light leakage from a large pixel to a small pixel. Background Art

[0002] As a structure for expanding the dynamic range of pixels, there is a solid-state imaging device that includes large pixels with high sensitivity in which the area of ​​the photoelectric conversion region is enlarged and small pixels with low sensitivity in which the area of ​​the photoelectric conversion region is reduced (for example, refer to Patent Document 1).

[0003] [Citation list]

[0004] [Patent Document]

[0005] [Patent Document 1]: Japanese Patent Application Publication No. JP 2017-163010 Summary of the invention

[0006] [Technical issues]

[0007] In a solid-state imaging device provided with large pixels and small pixels as described above, the amount of light received by the large pixels is significantly greater than that of the small pixels. If light leakage from the large pixels to the small pixels occurs, even a small amount of light leakage to the large pixels may significantly affect the image quality of the small pixels. In a pixel structure provided with large pixels and small pixels, more light leakage may occur in a specific direction, depending on the configuration of the pixels and the configuration of the color filter, and glare with characteristic hue and anisotropy may occur.

[0008] The present disclosure has been made in view of such circumstances, and an object thereof is to suppress light leakage from large pixels to small pixels.

[0009] [Solution to the problem]

[0010] A solid-state imaging device according to a first aspect of the present disclosure includes:

[0011] A pixel array unit in which a plurality of unit pixels are two-dimensionally arranged,

[0012] Wherein, each of the unit pixels includes

[0013] a first photoelectric conversion unit formed in a semiconductor substrate,

[0014] The second photoelectric conversion unit has an area smaller than that of the first photoelectric conversion unit,

[0015] an inter-pixel light shielding film provided on at least a portion of a boundary between the unit pixels on the incident light side relative to the semiconductor substrate,

[0016] a spacer layer disposed on the incident light side relative to the inter-pixel light shielding film, and

[0017] A light shielding wall is provided on at least a portion of a boundary between the unit pixels on the incident light side relative to the inter-pixel light shielding film and partitions the spacer layer.

[0018] In a first aspect of the present disclosure, a pixel array unit is provided in which a plurality of unit pixels are two-dimensionally arranged, and each of the unit pixels includes a first photoelectric conversion unit formed in a semiconductor substrate, a second photoelectric conversion unit having an area smaller than that of the first photoelectric conversion unit, an inter-pixel shading film provided on at least a portion of a boundary between the unit pixels on the incident light side relative to the semiconductor substrate, a spacer layer provided on the incident light side relative to the inter-pixel shading film, and a shading wall provided on at least a portion of a boundary between the unit pixels on the incident light side relative to the inter-pixel shading film and separating the spacer layer.

[0019] A solid-state imaging device according to a second aspect of the present disclosure includes:

[0020] A pixel array unit in which a plurality of unit pixels are two-dimensionally arranged,

[0021] Wherein, each of the unit pixels includes

[0022] a first photoelectric conversion unit formed in a semiconductor substrate,

[0023] The second photoelectric conversion unit has an area smaller than that of the first photoelectric conversion unit,

[0024] a color filter disposed on the incident light side relative to the semiconductor substrate, and

[0025] A low N wall is formed in the same layer as the color filter and has a refractive index lower than that of the color filter.

[0026] In a second aspect of the present disclosure, a pixel array unit is provided in which a plurality of unit pixels are two-dimensionally arranged, and each unit pixel includes a first photoelectric conversion unit formed in a semiconductor substrate, a second photoelectric conversion unit having an area smaller than that of the first photoelectric conversion unit, a color filter provided on the incident light side relative to the semiconductor substrate, and a low-N wall formed in the same layer as the color filter and having a refractive index lower than that of the color filter.

[0027] The solid-state imaging device may be an independent device or a module incorporated into other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 1 is a diagram showing a schematic configuration of a solid-state imaging device to which the disclosed technology is applied.

[0029] Figure 2 is a plan view showing a first layout example of unit pixels.

[0030] Figure 3 : is a plan view showing a second layout example of unit pixels.

[0031] Figure 4 1 is a diagram showing an example of arrangement of on-chip lenses when unit pixels are arranged in the second layout example.

[0032] Figure 5 is a plan view showing another layout example of unit pixels.

[0033] Figure 6 A diagram showing an example of a circuit configuration of a unit pixel.

[0034] Figure 7 is a cross-sectional view showing a configuration example of a unit pixel according to the first embodiment.

[0035] Figure 8 is a plan view of a unit pixel at a predetermined depth position according to the first embodiment.

[0036] Fig. 9 1 is a diagram showing a configuration example of a comparative unit pixel to be compared with the unit pixel according to the first embodiment.

[0037] Fig.10 is a diagram for explaining the comparison result of optical characteristics between the unit pixel according to the first embodiment and a comparative unit pixel.

[0038] Fig.11 is a diagram for explaining the comparison result of optical characteristics between the unit pixel according to the first embodiment and a comparative unit pixel.

[0039] Fig.12 This is a diagram for explaining the relationship between the width of the light shielding film between pixels and the width of the light shielding wall.

[0040] Fig.13 This is a diagram for explaining the relationship between the width of the light shielding film between pixels and the width of the light shielding wall.

[0041] Fig.14 It is a cross-sectional view showing a second configuration example of the light shielding wall.

[0042] Fig.15 1 is a diagram for explaining the comparison result of the optical characteristics between the comparison unit pixel and the unit pixel including the light shielding wall of the first structural example or the second structural example.

[0043] Fig.16 It is a cross-sectional view showing a third configuration example of the light shielding wall.

[0044] Fig.17 It is a cross-sectional view showing a fourth configuration example of the light-shielding wall.

[0045] Fig.18 2 is a diagram for explaining a method for manufacturing a unit pixel according to the first embodiment.

[0046] Fig.19 2 is a diagram for explaining a method for manufacturing a unit pixel according to the first embodiment.

[0047] Fig. 20 2 is a diagram for explaining a method for manufacturing a unit pixel according to the first embodiment.

[0048] Fig.21 2 is a diagram for explaining a method for manufacturing a unit pixel according to the first embodiment.

[0049] Fig. 22 is a cross-sectional view showing a first configuration example of a unit pixel according to a second embodiment of the present disclosure.

[0050] Fig.23 is a plan view of a unit pixel at a predetermined depth position according to the first configuration example of the second embodiment.

[0051] Fig.24 It is a diagram for explaining the effect of the first configuration example of the unit pixel according to the second embodiment.

[0052] Fig.25 2 is a plan view showing a modification example of the low N wall of the unit pixel according to the first configuration example.

[0053] Fig.26 is a cross-sectional view showing a second configuration example of a unit pixel according to the second embodiment of the present disclosure.

[0054] Fig. 27 is a plan view of a unit pixel at a predetermined depth position according to a second configuration example of the second embodiment.

[0055] Fig.28 It is a plan view showing a modified example of the recessed portion in the first configuration example and the second configuration example.

[0056] Fig.29 is a cross-sectional view showing a third configuration example of the unit pixel according to the second embodiment of the present disclosure.

[0057] Fig.30 It is a plan view showing a modified example of the recessed portion in the third configuration example.

[0058] Fig.31 is a cross-sectional view showing a fourth configuration example of the unit pixel according to the second embodiment of the present disclosure.

[0059] Fig.32 is a cross-sectional view showing a first configuration example of a unit pixel according to a third embodiment of the present disclosure.

[0060] Fig.33 is a plan view of a unit pixel at a predetermined depth position according to the first configuration example of the third embodiment.

[0061] Fig.34 is a plan view for explaining a modification example of the unit pixel according to the first configuration example of the third embodiment.

[0062] Fig.35 is a cross-sectional view showing a second configuration example of a unit pixel according to the third embodiment of the present disclosure.

[0063] Fig.36 is a plan view of a unit pixel at a predetermined depth position according to a second configuration example of the third embodiment.

[0064] Fig.37 is a cross-sectional view showing a third configuration example of a unit pixel according to the third embodiment of the present disclosure.

[0065] Fig.38 is a plan view of a unit pixel at a predetermined depth position according to a third configuration example of the third embodiment.

[0066] Fig.39 : is a diagram showing a fourth configuration example of the unit pixel according to the third embodiment of the present disclosure.

[0067] Fig.40 is a diagram showing a fifth configuration example of the unit pixel according to the third embodiment of the present disclosure.

[0068] Fig.41 is a diagram showing a sixth configuration example of the unit pixel according to the third embodiment of the present disclosure.

[0069] Fig.42 is a diagram showing a seventh configuration example of the unit pixel according to the third embodiment of the present disclosure.

[0070] Fig.43 : is a diagram showing an eighth configuration example of the unit pixel according to the third embodiment of the present disclosure.

[0071] Fig.44 is a cross-sectional view of a unit pixel according to a fourth embodiment of the present disclosure.

[0072] Fig.45 is a diagram for explaining the effect of the unit pixel according to the fourth embodiment.

[0073] Fig.46is a diagram for explaining the effect of the unit pixel according to the fourth embodiment.

[0074] Fig.47 is a diagram for explaining the effect of the unit pixel according to the fourth embodiment.

[0075] Fig.48 is a cross-sectional view showing a unit pixel according to a modification of the fourth embodiment.

[0076] Fig.49 is a cross-sectional view showing a unit pixel according to a modification of the fourth embodiment.

[0077] Fig.50 This is a schematic diagram for explaining a Fresnel-type on-chip lens.

[0078] Fig.51 : is a diagram showing a first configuration example of a unit pixel according to a fifth embodiment of the present disclosure.

[0079] Fig.52 : is a diagram showing a second configuration example of a unit pixel according to the fifth embodiment of the present disclosure.

[0080] Fig.53 is a diagram showing a third configuration example of a unit pixel according to the fifth embodiment of the present disclosure.

[0081] Fig.54 : is a diagram showing a fourth configuration example of a unit pixel according to the fifth embodiment of the present disclosure.

[0082] Fig.55 is a diagram showing a fifth configuration example of a unit pixel according to a fifth embodiment of the present disclosure.

[0083] Fig.56 is a diagram showing a sixth configuration example of the unit pixel according to the fifth embodiment of the present disclosure.

[0084] Fig.57 is a diagram showing a seventh configuration example of the unit pixel according to the fifth embodiment of the present disclosure.

[0085] Fig.58 This is an explanatory diagram of a usage example of a solid-state imaging device.

[0086] Fig.59 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the technology of the present disclosure is applied.

[0087] Fig.60 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0088] Fig.61 1 is a diagram illustrating an example of the installation positions of the vehicle exterior information detection unit and the imaging portion. DETAILED DESCRIPTION

[0089] Hereinafter, a form for embodying the technology of the present disclosure (hereinafter referred to as an "embodiment") will be described with reference to the drawings. The description will be made in the following order.

[0090] 1. Schematic Configuration Example of Solid-State Imaging Device

[0091] 2. Example of unit pixel layout

[0092] 3. Circuit example of unit pixel

[0093] 4. First Implementation Method of Unit Pixel

[0094] 4.1 Example of unit pixel composition

[0095] 4.2 Unit Pixel Structure in Comparative Example

[0096] 4.3 Optical property results of the first embodiment and the comparative example

[0097] 4.4 Relationship between the width of the inter-pixel light shielding film and the width of the light shielding wall

[0098] 4.5 Second Configuration Example of Light-Shielding Wall

[0099] 4.6 The third configuration example of the light shielding wall

[0100] 4.7 Fourth Configuration Example of Light-Shielding Wall

[0101] 4.8 Manufacturing method of the first embodiment

[0102] 4.9 Summary of the First Implementation Plan

[0103] 5. Second Implementation Method of Unit Pixel

[0104] 5.1 First Configuration Example of Second Implementation Method

[0105] 5.2 Variations of Low N Wall

[0106] 5.3 Second Configuration Example of the Second Implementation Method

[0107] 5.4 Variation of concave portion

[0108] 5.5 Third Configuration Example of Second Implementation Method

[0109] 5.6 Variation of concave portion

[0110] 5.7 Fourth Configuration Example of the Second Implementation Method

[0111] 5.8 Summary of the Second Implementation Plan

[0112] 6. Third Implementation Method of Unit Pixel

[0113] 6.1 First Configuration Example of the Third Implementation Method

[0114] 6.2 Second Configuration Example of the Third Implementation Method

[0115] 6.3 Third Configuration Example of the Third Implementation Method

[0116] 6.4 Fourth Configuration Example of the Third Implementation Method

[0117] 6.5 Fifth Configuration Example of the Third Implementation Method

[0118] 6.6 Sixth Configuration Example of the Third Implementation Method

[0119] 6.7 Seventh Configuration Example of the Third Implementation Method

[0120] 6.8 Eighth Configuration Example of the Third Implementation Method

[0121] 6.9 Summary of the Third Implementation Plan

[0122] 7. Fourth Implementation Method of Unit Pixel

[0123] 7.1 Configuration Example of the Fourth Embodiment

[0124] 7.2 Variations

[0125] 7.3 Summary of the Fourth Implementation Plan

[0126] 8. Fifth Implementation Method of Unit Pixel

[0127] 8.1 First Configuration Example of the Fifth Implementation Method

[0128] 8.2 Second Configuration Example of the Fifth Implementation Method

[0129] 8.3 Third Configuration Example of the Fifth Implementation Method

[0130] 8.4 Fourth Configuration Example of the Fifth Implementation Method

[0131] 8.5 Fifth Configuration Example of the Fifth Implementation Method

[0132] 8.6 Sixth Configuration Example of the Fifth Implementation Method

[0133] 8.7 Seventh Configuration Example of the Fifth Implementation Method

[0134] 8.8 Summary of the Fifth Implementation Plan

[0135] 9. Summary of all implementation plans

[0136] 10. Example of using solid-state imaging device

[0137] 11. Application examples of electronic equipment

[0138] 12. Application examples of mobile objects

[0139] In the drawings referred to in the following description, the same or similar parts will be represented by the same or similar reference numerals, and redundant descriptions will be omitted. The drawings are schematic, and the relationship between the thickness and the plan view size, the thickness ratio of each layer, etc. are different from the actual. In addition, in some cases, the drawings may include parts whose size relationships and ratios are different between the drawings.

[0140] In addition, it should be understood that the definitions of directions such as upward and downward in the following description are merely provided for simplicity and are not intended to limit the technical ideas of the present disclosure. For example, when an object is observed after being rotated 90 degrees, up and down are converted and interpreted as left and right, while when the object is observed after being rotated 180 degrees, up and down are interpreted as inverted.

[0141] Furthermore, regarding a P-type or N-type semiconductor region in the following description, even semiconductor regions of the same conductivity type do not mean that the impurity concentrations in the semiconductor regions are the same in a strict sense.

[0142] <1. Schematic Configuration Example of Solid-State Imaging Device>

[0143] Figure 1 1 is a diagram showing a schematic configuration of a solid-state imaging device to which the disclosed technology is applied.

[0144] As Figure 1 The solid-state imaging device 1 in FIG. 1 shows the configuration of a CMOS image sensor, which is, for example, a solid-state imaging device of an XY address method. The CMOS image sensor is an image sensor manufactured by applying or partially using a CMOS process.

[0145] The solid-state imaging device 1 includes a pixel array unit 11 and a peripheral circuit unit. The peripheral circuit unit includes, for example, a vertical drive unit 12, a column processing unit 13, a horizontal drive unit 14, and a system control unit 15.

[0146] The solid-state imaging device 1 further includes a signal processing unit 16 and a data storage unit 17. The signal processing unit 16 and the data storage unit 17 may be mounted on the same substrate as the pixel array unit 11, the vertical drive unit 12, etc., or may be configured on another substrate. In addition, an external signal processing unit (for example, a digital signal processor (DSP) circuit, etc.) provided on a semiconductor chip different from the solid-state imaging device 1 may be caused to perform processing of the signal processing unit 16 and the data storage unit 17.

[0147] The pixel array unit 11 has a configuration in which unit pixels 21 including a photoelectric conversion unit that generates and accumulates charge according to the amount of received light are two-dimensionally arranged in a matrix shape in the row direction and the column direction. Here, the row direction indicates the layout direction of the pixel rows of the pixel array unit 11 (i.e., in the horizontal direction), and the column direction indicates the layout direction of the pixel columns of the pixel array unit 11 (i.e., in the vertical direction).

[0148] Furthermore, in the pixel array unit 11, a pixel driving wiring 22 as a row signal line is wired in the row direction for each pixel row, and a vertical signal line 23 as a column signal line is wired in the column direction for each pixel column. The pixel driving wiring 22 transmits a driving signal for performing driving when reading out a signal from the unit pixel 21. Figure 1 The pixel driving wiring 22 is shown as one wiring, but the number thereof is not limited to one. One end of the pixel driving wiring 22 is connected to the output terminal corresponding to each row of the vertical driving unit 12.

[0149] The vertical driving unit 12 is composed of a shift register, an address decoder, etc., and simultaneously drives each unit pixel 21 of the pixel array unit 11 in a row unit, etc. The vertical driving unit 12 constitutes a driving unit that controls the operation of each unit pixel 21 of the pixel array unit 11 together with the system control unit 15. Although the description of the specific configuration will be omitted, the vertical driving unit 12 generally has two scanning systems, namely, a readout scanning system and a sweep-out scanning system.

[0150] The readout scanning system selectively scans the unit pixels 21 of the pixel array unit 11 in sequence in row units to read out signals from the unit pixels 21. The signals read out from the unit pixels 21 are analog signals. The sweep-out scanning system performs sweep-out scanning for the exposure time before the readout scanning on the readout row for which the readout scanning is performed by the readout scanning system.

[0151] The sweep-out scanning performed by the sweep-out scanning system sweeps out unnecessary charges from the photoelectric conversion unit of the unit pixel 21 in the readout row, thereby resetting each unit pixel 21. The so-called electronic shutter operation is performed by sweeping out (resetting) unnecessary charges performed by the sweep-out scanning system. Here, the electronic shutter operation refers to an operation of discarding the charge of the photoelectric conversion unit and restarting exposure (starting accumulation of charge).

[0152] The signal read out by the readout operation in the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or the electronic shutter operation. In addition, the period from the readout timing in the immediately preceding readout operation or the sweep timing in the electronic shutter operation to the readout timing in the current readout operation is the exposure period of the unit pixel 21.

[0153] The signals output from the respective unit pixels 21 in the pixel row selected and scanned by the vertical driving unit 12 are input to the column processing unit 13 through the respective vertical signal lines 23 for the respective pixel columns. The column processing unit 13 performs predetermined signal processing on the signals output from the respective unit pixels 21 of the selected row through the vertical signal lines 23 for each pixel column of the pixel array unit 11, and temporarily holds the pixel signals after the signal processing.

[0154] Specifically, the column processing unit 13 performs at least noise removal processing such as correlated double sampling (CDS) processing and double data sampling (DDS) processing as signal processing. For example, the CDS processing removes fixed pattern noise inherent to pixels such as reset noise and threshold variation of an amplifier transistor within a unit pixel. In addition to the noise removal processing, the column processing unit 13 may also have, for example, an analog-to-digital (AD) conversion function to convert an analog pixel signal into a digital signal and output the digital signal.

[0155] The horizontal driving unit 14 is composed of a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns of the column processing unit 13. Through selective scanning of the horizontal driving unit 14, pixel signals subjected to signal processing for each unit circuit in the column processing unit 13 are sequentially output.

[0156] The system control unit 15 is constituted by a timing generator that generates various timing signals and the like, and performs drive control on the vertical drive unit 12 , the column processing unit 13 , the horizontal drive unit 14 and the like based on the various timings generated by the timing generator.

[0157] The signal processing unit 16 has at least a calculation processing function, and performs various signal processing such as calculation processing on the pixel signal output from the column processing unit 13. The data storage unit 17 temporarily stores data required for the signal processing in the signal processing unit 16. The pixel signal on which the signal processing unit 16 has performed the signal processing is converted into a predetermined format and output from the output unit 18 to the outside of the device.

[0158] <2. Example of Unit Pixel Layout>

[0159] Figure 2 A is a plan view showing a first layout example of the unit pixels 21 in the pixel array unit 11 .

[0160] Figure 2 A is a plan view, in which 2 x 2 unit pixels 21 are arranged, that is, two unit pixels are arranged in the row direction and the column direction respectively. For example, each unit pixel 21 is composed of Figure 2 The unit structure is surrounded by the dotted line in A, and includes a first photoelectric conversion unit 51L and a second photoelectric conversion unit 51S arranged on the upper right side with respect to the first photoelectric conversion unit 51L.

[0161] The first photoelectric conversion unit 51L is formed to have an octagonal planar shape, and has a larger photoelectric conversion area than the second photoelectric conversion unit 51S. The second photoelectric conversion unit 51S is formed to have a rhombus shape obtained by rotating a quadrilateral by 45 degrees, and has a smaller photoelectric conversion area than the first photoelectric conversion unit 51L. Therefore, the first photoelectric conversion unit 51L is a photoelectric conversion unit with high sensitivity, and the second photoelectric conversion unit 51S is a photoelectric conversion unit with low sensitivity. The second photoelectric conversion unit 51S is arranged at a corner position in a diagonal direction of the first photoelectric conversion unit 51L.

[0162] Note that, hereinafter, without particularly distinguishing between the first photoelectric conversion unit 51L and the second photoelectric conversion unit 51S, they are simply referred to as the photoelectric conversion unit 51. In addition, in the unit pixel 21, the area corresponding to the first photoelectric conversion unit with high sensitivity can be referred to as a large pixel, and the area corresponding to the second photoelectric conversion unit with low sensitivity can be referred to as a small pixel.

[0163] For example, Figure 2 As shown in FIG. 1B , the color filters are arranged in a Bayer layout with the unit pixel 21 as the same color unit. The on-chip lenses are arranged above the first photoelectric conversion unit 51L and the second photoelectric conversion unit 51S in circular shapes with different diameters according to the area of ​​the photoelectric conversion region.

[0164] Figure 3 A is a plan view showing a second layout example of the unit pixels 21 in the pixel array unit 11 .

[0165] Figure 3 A is an example in which 2x 2 unit pixels 21 are configured, that is, two unit pixels are configured in the row direction and the column direction, and each unit pixel 21 is formed to have a quadrilateral planar shape, and has a first photoelectric conversion unit 51L formed in an L shape and a second photoelectric conversion unit 51S formed in a quadrilateral in the quadrilateral area. The L shape is a shape obtained by connecting a longitudinal line and a transverse line, and the lengths of the longitudinal line and the transverse line may be the same or different from each other. In addition, the direction of L in the L shape may be any direction. In other words, the L shape may be a direction obtained by rotating the letter L by 90 degrees, 180 degrees, or 270 degrees.

[0166] For example, Figure 3 As shown in FIG. 8B , the color filters are arranged in a Bayer layout with the unit pixel 21 as a same-color unit.

[0167] Figure 4 2 is a diagram showing an example of arrangement of on-chip lenses when the unit pixels 21 are arranged in the second layout example.

[0168] For example, when the unit pixels 21 are arranged in the second layout example, as shown in FIG. Figure 4 As shown in FIG. 8A , on-chip lenses 81 having the same shape and size may be arranged in a 2×2 arrangement within each unit pixel 21 .

[0169] Alternatively, if Figure 4 As shown in FIG. 1B , the small on-chip lenses 81S with a small diameter and the large on-chip lenses 83L with a large diameter can be aligned in the diagonal direction, and the small on-chip lenses 81S and the large on-chip lenses 83L can be alternately arranged in the column direction and the row direction. The small on-chip lenses 81S are arranged on the second photoelectric conversion unit 51S.

[0170] Figure 5 2 is a plan view showing another layout example of the unit pixel 21. Figure 5 , for simplification, the photoelectric conversion unit 51 and the color filter are shown in an overlapping manner.

[0171] Figure 5 A shows an example in which a second photoelectric conversion unit 51S formed to have a quadrilateral planar shape is arranged at the positions of the four corners of a first photoelectric conversion unit 51 formed to have a quadrilateral planar shape so that the second photoelectric conversion unit 51S has a shape similar to that of the first photoelectric conversion unit 51L.

[0172] Figure 5 B shows a configuration in which each unit pixel 21 has a quadrilateral planar shape and its area is divided into a first photoelectric conversion unit 51L and a second photoelectric conversion unit 51S. However, the second photoelectric conversion unit 51S occupies a smaller area within the unit pixel 21 than the first photoelectric conversion unit 51L.

[0173] Figure 5 C shows an example in which a first photoelectric conversion unit 51L is configured to be offset by a predetermined amount (within the size of the first photoelectric conversion unit 51L) in the row direction and the column direction from an adjacent first photoelectric conversion unit 51L, and a second photoelectric conversion unit 52S is configured in a gap between adjacent first photoelectric conversion units 51L.

[0174] Note that although the following embodiments will describe an example in which each unit pixel 21 includes two types of photoelectric conversion units 51 with different areas of the photoelectric conversion region in a plan view, each unit pixel 21 may be composed of three types of photoelectric conversion units 51, large, medium, and small, or may be composed of four types of photoelectric conversion units 51.

[0175] The color filter is also not limited to the primary colors, i.e., red (R), green (G), and blue (B), but may be complementary colors, such as cyan, magenta, and yellow. In addition, the color filter may be a white filter (transparent filter) or an IR filter. In addition, a layout in which the above-mentioned various color filters are appropriately combined or a configuration in which the color filter is omitted may be adopted. In addition, a surface plasmon filter may be configured instead of a color filter, or a wire grid type polarization element may be configured.

[0176] <3. Example of Unit Pixel Circuit>

[0177] Figure 6 An example of the circuit configuration of the unit pixel 21 is shown.

[0178] As described above, each unit pixel 21 includes the first photoelectric conversion unit 51L and the second photoelectric conversion unit 51S, which are two photoelectric conversion units 51 having different sensitivities.

[0179] The unit pixel 21 further includes a first transfer transistor 53 , a second transfer transistor 54 , a third transfer transistor 55 , a floating diffusion (FD) unit 56 , a reset transistor 57 , an amplification transistor 58 , and a selection transistor 59 .

[0180] The reset transistor 57 and the amplifier transistor 58 are connected to the power supply voltage VDD. The first photoelectric conversion unit 51L includes a so-called buried photodiode in which an N-type impurity region is formed inside a P-type impurity region formed in a semiconductor substrate. Similarly, the second photoelectric conversion unit 51S includes a buried photodiode. The first photoelectric conversion unit 51L and the second photoelectric conversion unit 51S generate charges according to the amount of light received, and accumulate the generated charges to a certain amount.

[0181] The unit pixel 21 further includes a charge accumulation unit 61. The charge accumulation unit 61 is configured by, for example, a MOS capacitor or a MIS capacitor.

[0182] exist Figure 6 , the first transfer transistor 53, the second transfer transistor 54, and the third transfer transistor 55 are connected in series between the first photoelectric conversion unit 51L and the second photoelectric conversion unit 51S. The floating diffusion layer connected between the first transfer transistor 53 and the second transfer transistor 54 corresponds to the FD unit 56. The FD unit 56 includes a parasitic capacitance C10.

[0183] The floating diffusion layer connected between the second transfer transistor 54 and the third transfer transistor 55 corresponds to a node 62. The node 62 is provided with a parasitic capacitance C11. The floating diffusion layer connected between the third transfer transistor 55 and the second photoelectric conversion unit 51S corresponds to a node 63. The charge accumulation unit 61 is connected to the node 63.

[0184] For the unit pixel 21, for example, a plurality of driving wirings are wired for each pixel row as Figure 1 In addition, various drive signals TRG, FDG, FCG, RST and SEL are sent from Figure 1 The vertical drive unit 12 in the pixel is supplied via a plurality of drive wirings. Since each transistor of the unit pixel 21 is composed of an NMOS transistor, these drive signals are pulse signals, and a high level (for example, the power supply voltage VDD) state is an active state, and a low level state (for example, a negative potential) is an inactive state.

[0185] The drive signal TRG is applied to the gate electrode of the first transfer transistor 53. Once the drive signal TRG enters an active state, the first transfer transistor 53 enters an on state, and the charge accumulated in the first photoelectric conversion unit 51L is transferred to the FD unit 56 via the first transfer transistor 53.

[0186] The driving signal FDG is applied to the gate electrode of the second transfer transistor 54. When the driving signal FDG becomes active and the second transfer transistor 54 becomes conductive, the potentials of the FD unit 56 and the node 62 are combined to form one charge accumulation region.

[0187] The drive signal FCG is applied to the gate electrode of the third transfer transistor 55. When the drive signal FDG and the drive signal FCG become active and the second transfer transistor 54 and the third transfer transistor 55 become conductive, the potentials of the FD unit 56 and the charge accumulation unit 61 are combined to form one charge accumulation region.

[0188] exist Figure 6 , the first electrode of the two electrodes of the charge accumulation unit 61 is a node electrode connected to the node 63. The second electrode of the two electrodes of the charge accumulation unit 61 is a grounded electrode. Note that as a modification, the second electrode may be connected to a specific potential other than the ground potential, such as a power supply potential.

[0189] For example, when the charge accumulation unit 61 is a MOS capacitor or a MIS capacitor, the second electrode is an impurity region formed on a silicon substrate, and the dielectric film forming the capacitor is an oxide film or a nitride film formed on the silicon substrate. The first electrode is an electrode formed of a conductive material such as polysilicon or a metal over the second electrode and the dielectric film.

[0190] In the case where the second electrode is set to the ground potential, the second electrode may be a P-type impurity region electrically connected to a P-type impurity region included in the first photoelectric conversion unit 51L or the second photoelectric conversion unit 51S. In the case where the second electrode is set to a specific potential other than the ground potential, the second electrode may be an N-type impurity region formed in the P-type impurity region.

[0191] In addition to the second transfer transistor 54, a reset transistor 57 is also connected to the node 62. A certain potential, such as the power supply voltage VDD, is connected to the reset transistor 57. A drive signal RST is applied to a gate electrode of the reset transistor 57. Once the drive signal RST enters an active state, the reset transistor 57 enters a conductive state, and the potential of the node 62 is reset to the level of the power supply voltage VDD.

[0192] If the drive signal FDG of the second transfer transistor 54 and the drive signal FCG of the third transfer transistor 55 enter an active state when the drive signal RST enters an active state, the combined potential of the node 62, the FD unit 56 and the charge accumulation unit 61 is reset to the level of the power supply voltage VDD.

[0193] Note that it goes without saying that the potentials of the FD unit 56 and the charge accumulation unit 61 can be individually (independently) reset to the level of the power supply voltage VDD by individually controlling the drive signal FDG and the drive signal FCG.

[0194] The FD unit 56 as a floating diffusion layer is a charge-voltage conversion device. That is, when charges are transferred to the FD unit 56, the potential of the FD unit 56 changes according to the amount of transferred charges.

[0195] The current source 64 connected to one end of the vertical signal line 23 is connected to the source side of the amplifier transistor 58, and the power supply voltage VDD is connected to the drain side thereof, whereby the amplifier transistor 58 and they constitute a source follower circuit. The FD unit 56 is connected to the gate electrode of the amplifier transistor 58 and serves as an input of the source follower circuit.

[0196] The selection transistor 59 is connected between the source of the amplification transistor 58 and the vertical signal line 23. The drive signal SEL is applied to the gate electrode of the selection transistor 59. When the drive signal SEL becomes active, the selection transistor 59 becomes conductive, and the unit pixel 21 enters a selected state.

[0197] When the charge is transferred to the FD unit 56, the potential of the FD unit 56 reaches a potential corresponding to the amount of the transferred charge, and the potential is input to the above-mentioned source follower circuit. When the drive signal SEL becomes active, the potential of the FD unit 56 corresponding to the amount of charge is output to the vertical signal line 23 via the selection transistor 59 as the output of the source follower circuit.

[0198] The light receiving area of ​​the photodiode of the first photoelectric conversion unit 51L is larger than that of the second photoelectric conversion unit 51S. Therefore, when an object with a certain illumination is imaged within a certain exposure time, the amount of charge generated by the first photoelectric conversion unit 51L is larger than that generated by the second photoelectric conversion unit 51S.

[0199] Therefore, when the charges generated by the first photoelectric conversion unit 51L and the charges generated by the second photoelectric conversion unit 51S are transferred to the FD unit 56 and respectively subjected to charge-voltage conversion, a voltage change before and after the charges generated by the first photoelectric conversion unit 51L are transferred to the FD unit 56 is greater than a voltage change before and after the charges generated by the second photoelectric conversion unit 51S are transferred to the FD unit 56. Therefore, when comparing the first photoelectric conversion unit 51L and the second photoelectric conversion unit 51S, the first photoelectric conversion unit 51L has a higher sensitivity than the second photoelectric conversion unit 51S.

[0200] On the other hand, even if high-illuminance light is incident on the second photoelectric conversion unit 51S and generates charges exceeding the saturation charge amount of the second photoelectric conversion unit 51S, charges exceeding the saturation charge amount can be accumulated in the charge accumulation unit 61, so when the charges generated by the second photoelectric conversion unit 51S are charge-to-voltage conversion, the charge-to-voltage conversion can be performed after adding both the charges accumulated in the second photoelectric conversion unit 51S and the charges accumulated in the charge accumulation unit 61.

[0201] In this manner, the second photoelectric conversion unit 51S can capture an image having grayscale in a wider illuminance range than the first photoelectric conversion unit 518L. In other words, the second photoelectric conversion unit 51S can capture an image having a wider dynamic range.

[0202] Two images, i.e., an image with high sensitivity captured using the first photoelectric conversion unit 51L and an image with a wide dynamic range captured using the second photoelectric conversion unit 51S, are synthesized into one image through a wide dynamic range image synthesis process for synthesizing one image from the two images, for example, by a signal processing unit 16 included in the solid-state imaging device 1 or an image signal processing device connected to the outside of the solid-state imaging device 1.

[0203] <4. First Implementation of Unit Pixel>

[0204] <4.1 Example of Unit Pixel Configuration>

[0205] Figure 7 is a cross-sectional view showing a configuration example of a unit pixel 21 according to a first embodiment of the present disclosure, and shows a cross-sectional view along Figure 8 A cross-sectional view along line XX'. Figure 8A~C are Figure 7 A plan view of a unit pixel 21 at a predetermined depth position.

[0206] In a first embodiment, using Figure 2 A first layout example is shown as a layout of the unit pixel 21 .

[0207] The unit pixel 21 according to the first embodiment is composed of a large pixel 100L including a first photoelectric conversion unit 51L having high sensitivity formed in an octagon and a small pixel 100S including a second photoelectric conversion unit 51S having low sensitivity formed in a rhombus obtained by rotating a quadrilateral by 45 degrees. In the case where the first photoelectric conversion unit 51L and the second photoelectric conversion unit 51S are not particularly distinguished, they are simply referred to as a photoelectric conversion unit 51.

[0208] The unit pixel 21 according to the first embodiment includes a semiconductor substrate 121 and a wiring layer 122 formed on the front side (lower side in the figure) thereof.

[0209] The semiconductor substrate 121 is composed of, for example, a silicon substrate using silicon (Si) as a semiconductor. The thickness of the semiconductor substrate 121 is appropriately set according to the expected wavelength region of the incident light. For example, if the expected wavelength region is only the visible light region, the thickness of the semiconductor substrate 121 is about 2 μm to 6 μm, and if the near-infrared region is also detected, the thickness is about 3 μm to 15 μm. Of course, the thickness of the semiconductor substrate 121 is not limited to this range.

[0210] The first photoelectric conversion unit 51L is formed in the region of the large pixel 100L in the semiconductor substrate 121, and the second photoelectric conversion unit 51S is formed in the region of the small pixel 100S. The semiconductor substrate 121 is composed of, for example, a P-type (first conductivity type) semiconductor region. The photoelectric conversion unit 51 is composed of a PN junction photodiode in which an N-type (second conductivity type) semiconductor region is formed in the region of the P-type semiconductor region in the semiconductor substrate 121. Near the interface of the front and back sides of the semiconductor substrate 121 is a P-type semiconductor region, which also serves as a hole charge accumulation region to suppress dark current.

[0211] In the semiconductor substrate 121, an element separation unit 141 that separates the photoelectric conversion unit (photoelectric conversion element) 51 is formed in a region between adjacent photoelectric conversion units 51. The element separation unit 141 is formed by burying a fixed charge film 181 and an insulating film 182 inside a groove formed by digging it to a predetermined depth from the back side of the semiconductor substrate 121. By including these in this way, crosstalk caused by the rolling of electrons can be blocked with the insulating film 182, and crosstalk as light can also be suppressed by interface reflection due to a difference in refractive index. The element separation unit 141 can be formed of a P-type semiconductor region and have a grounded configuration.

[0212] In addition, in addition to the fixed charge film 181 and the insulating film 182, the element separation unit 141 can also be formed by burying a light-shielding metal in the groove. The light-shielding metal is preferably a material having high light-shielding properties and can be processed with high precision by micro-processing such as etching, and is preferably formed of a metal film such as Al, W or Cu. In other cases, it can be composed of silver, gold, platinum, Mo, Cr, Ti, nickel, iron, tellurium or an alloy containing these metals. In order to enhance adhesion with the insulating film 182 as a substrate, a barrier metal such as Ti, Ta, W, Co, Mo or an alloy, nitride, oxide or carbide thereof may be included under the light-shielding metal.

[0213] The element separation unit 141 may have a shape surrounding the entire periphery of the first photoelectric conversion unit 51L and the second photoelectric conversion unit 51S in a plan view, or may have a shape surrounding a portion of the periphery. Figure 7 In the example shown in FIG. 1 , the element separation unit 141 does not penetrate the semiconductor substrate 121 , but the element separation unit 142 may be formed to penetrate the semiconductor substrate 121 and reach the wiring layer 122 .

[0214] The wiring layer 122 includes a multilayer metal wiring 131 and an interlayer insulating film 132. The multilayer metal wiring 131 in the wiring layer 122 transmits an image signal generated by the unit pixel 21 and transmits a signal to be applied to the unit pixel 21. The metal wiring 131 can be composed of a metal such as Al or Cu, for example. The through hole connecting the upper and lower metal wirings 131 can be composed of a metal such as W or Cu, for example. For example, a silicon oxide film or the like can be used as the interlayer insulating film 132.

[0215] In addition, one or more pixel transistors Tr are formed at the interface between the semiconductor substrate 121 and the wiring layer 122. The pixel transistor Tr corresponds to Figure 6Any one of the first transfer transistor 53, the second transfer transistor 54, the third transfer transistor 55, the reset transistor 57, the amplification transistor 58 and the selection transistor 59 described in the above. The pixel transistor Tr includes an N-type source region and a drain region formed in a P-type semiconductor region, and is constituted by forming a gate electrode on a substrate surface between the source region and the drain region via a gate insulating film. The bonding electrode 133 is formed on a surface on the opposite side of the semiconductor substrate 121 side of the wiring layer 122, and is electrically connected to a bonding electrode of a logic substrate not shown by a metal bonding such as a Cu-Cu bonding. By establishing a connection with the logic substrate and vertically stacking various peripheral circuit functions, the chip size can be reduced.

[0216] The fixed charge film 181 is formed to cover the semiconductor substrate 121 directly above the P-type semiconductor region on the back side of the surface as the upper side in the figure. The fixed charge film 181 includes a negative fixed charge caused by the dipole of oxygen and is used to enhance pinning. The fixed charge film 181 can be, for example, composed of an oxide or nitride containing at least one of Hf, Al, zirconium, Ta and Ti. The fixed charge film 181 can be formed by CVD, sputtering or atomic layer deposition (ALD). When ALD is used, a silicon oxide film that reduces the interface energy level can be formed at the same time as the fixed charge film 181 is formed, which is preferred. The fixed charge film 181 is composed of an oxide or nitride containing at least one of lanthanum, cerium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, thulium, ytterbium, lutetium and yttrium. The fixed charge film 181 can also be composed of hafnium oxynitride or aluminum oxynitride. In addition, silicon or nitrogen may be added to the fixed charge film 181 in an amount that does not impair insulation. This can improve heat resistance, etc. It is expected that the fixed charge film 181 also functions as an anti-reflection film for a silicon substrate having a high refractive index by controlling the film thickness or by stacking multiple layers.

[0217] The insulating film 182 is formed on the upper side of the fixed charge film 181. In addition, from the viewpoint of anti-reflection, the insulating film 182 preferably has a lower refractive index than the fixed charge film 181, and for example, SiO2 or a composite material containing SiO2 as a main component (such as SiON or SiOC) can be used. Deterioration of dark characteristics can be suppressed by the insulating film 182.

[0218] The inter-pixel light shielding film 183 and the light shielding wall 184 are formed on the insulating film 182 above the element separation unit 141 , and the spacer 185 is formed above the photoelectric conversion unit 51 where the inter-pixel light shielding film 183 and the light shielding film 184 are not formed.

[0219] The inter-pixel light shielding film 183 has a planar shape on the on-chip lens 187 side relative to the semiconductor substrate 121, and the photoelectric conversion unit 51 is opened from the top thereof, and the inter-pixel light shielding film 183 blocks the light at the boundary between the unit pixels 21 and suppresses the crosstalk between the unit pixels. Although the inter-pixel light shielding film 183 only needs to be a light-shielding material, it is preferably formed of a metal film such as Al, W, or Cu, as a material having high light-shielding properties and that can be processed with high precision by micro-processing such as etching. In other cases, it can be composed of silver, gold, platinum, Mo, Cr, Ti, nickel, iron, tellurium, or an alloy containing such a metal. In addition, the inter-pixel light shielding film 183 can also be formed by stacking a plurality of such materials. In order to enhance the adhesion with the insulating film 182 as a substrate, a barrier metal such as Ti, Ta, W, Co, Mo, or an alloy, nitride, oxide, or carbide thereof may be included under the light-shielding metal. In addition, the inter-pixel light shielding film 183 can also be used as a light shield for pixels that determine the optical black level, and can also be used as a light shield to prevent noise from entering the peripheral circuit area. It is desirable that the inter-pixel light shielding film 183 is grounded so that it will not be damaged by plasma damage caused by accumulated charge during processing. The grounding structure may include a grounding structure in an area outside the effective area so that all inter-pixel light shielding films 183 are electrically connected.

[0220] The light shielding wall 184 is located between the on-chip lens 187 and the semiconductor substrate 121, and is included at least on a portion of each boundary between the unit pixels 21. The light shielding wall 184 is formed, for example, by burying a light shielding metal in the formed groove. The light shielding metal is preferably formed of a metal film such as Al, W or Cu, as a material having high light shielding properties and that can be processed with high precision by micro-processing such as etching. In other cases, it can be composed of silver, gold, platinum, Mo, Cr, Ti, nickel, iron, tellurium or an alloy containing such a metal. Alternatively, the light shielding wall 184 may have a structure in which a low refractive index material having a refractive index lower than that of the spacer layer 185 is buried to suppress crosstalk by a total reflection phenomenon caused by a refractive index difference. Instead of burying a low refractive index material, the light shielding wall 184 may be composed of an air gap (refractive index 1) by blocking the upper end of the groove.

[0221] The spacer layer 185 is a layer obtained by burying the area above the photoelectric conversion unit 51 to the same height as the height H, which is the total height of the inter-pixel light shielding film 183 and the light shielding wall 184, to increase the height of the on-chip lens 187. It is desirable that the material of the spacer layer 185 is transparent with respect to the target wavelength so as to guide the light from the on-chip lens 187 to the photoelectric conversion unit 51 without any loss, and SiO2, SiN, or SiON, for example, can be used. Note that the total height H of the inter-pixel light shielding film 183 and the light shielding wall 184 can vary depending on the pixel size ratio between the large pixel 100L and the small pixel 100S and the incident angle specification of the module lens. The upper limit value of the height H is set so that sensitivity loss does not occur within the angle range of the module lens.

[0222] The color filter 186 is formed on the upper surfaces of the light shielding wall 184 and the spacer layer 185 , and the large on-chip lens 187L, the small on-chip lens 187S, and the anti-reflection film 188 are formed on the color filter 186 .

[0223] The color filter 186 is a color filter that allows any color of red, green, or blue to be selectively transmitted. The color filter 186 is formed by spin coating a photosensitive resin containing a colorant (eg, a pigment or a dye). For example, although it is assumed that Figure 8 As shown in A, each color of red, green and blue is configured in a Bayer layout for each unit pixel 21, but these colors can also be configured in other layout methods. Considering the color reproducibility based on the spectrum and the sensor sensitivity specification, the thickness of the color filter 186 can be different for each color. In the case of a monochrome sensor, an infrared sensor, etc., the color filter 186 may not be included.

[0224] The on-chip lens 187 collects incident light from the object to be written on the photoelectric conversion unit 51 via a module lens. The on-chip lens 187 includes a large on-chip lens 187L located above the first photoelectric conversion unit 51L and a small on-chip lens 187S located above the second photoelectric conversion unit 51S. The small on-chip lens 187S may not be formed above the second photoelectric conversion unit 51S so as not to collect light on the photoelectric conversion unit 51 as a low-sensitivity pixel. The on-chip lens 187 may be composed of an organic material such as a styrene resin, an acrylic resin, a styrene acrylic resin, or a siloxane resin, for example. In addition, the on-chip lens 187 may also be formed by dispersing titanium oxide particles in the above-mentioned organic material or polyimide resin. In addition, the on-chip lens 187 may be composed of an inorganic material such as silicon nitride (SiN) or silicon oxynitride (SiON). In addition, an anti-reflection film 188 is formed on the surface of the on-chip lens 187 using a material having a different refractive index from the on-chip lens 187. When the refractive index is defined as n and the expected average wavelength is defined as λ, it is desirable that the film thickness d of the anti-reflection film 188 approximately satisfies d=λ / (4n).

[0225] Figure 8 B shows a plan view of the light shielding wall 184, Figure 8 C shows a plan view of the inter-pixel light shielding film 183.

[0226] By comparing the width A of the inter-pixel light shielding film 183 and the width B of the light shielding wall 184, as shown in FIG. Figure 7 As shown in the cross-sectional view in FIG. 1 , the width A of the inter-pixel light shielding film 183 is formed to be larger than the width B of the light shielding wall 184 (width A>width B).

[0227] Figure 8 The minimum opening width W of the inter-pixel light shielding film 183 shown in C is the width of the inter-pixel light shielding film 183 surrounding the second photoelectric conversion unit 51S, and is formed to be equal to or smaller than Figure 7 The total height of the inter-pixel light shielding film 183 and the light shielding wall 184 in the cross-sectional view of FIG. 1 is H (W≤H). The minimum opening width W of the inter-pixel light shielding film 183 is more preferably equal to or less than 1 / 2 of the height H (W≤H / 2).

[0228] In the solid-state imaging device 1 including the unit pixel 21 according to the first embodiment configured as described above, it is a back-illuminated solid-state imaging device in which incident light is collected on the on-chip lens 187 formed on the back side of the semiconductor substrate 121, and photoelectrically converted by the photoelectric conversion unit 51. The unit pixel 21 according to the first embodiment includes a large pixel 100L and a small pixel 100S having different areas of photoelectric conversion units, and is capable of high-sensitivity imaging using the large pixel 100L and low-sensitivity imaging using the small pixel 100S.

[0229] The unit pixel 21 according to the first embodiment includes a first photoelectric conversion unit 51L and a second photoelectric conversion unit 51S having different areas of photoelectric conversion regions formed in a semiconductor substrate 121, an inter-pixel light-shielding film 183 arranged on at least a portion of the boundary between the unit pixels 21 on the incident light side relative to the semiconductor substrate 121, a spacer layer 185 arranged on the incident light side relative to the inter-pixel light-shielding film 183, a light-shielding wall 184 arranged on at least a portion of the boundary between the unit pixels 21 on the incident light side relative to the inter-pixel light-shielding film 183 and separating the spacer layer 185, and an on-chip lens 187 that collects incident light on the photoelectric conversion unit 51.

[0230] The unit pixel 21 according to the first embodiment includes a spacer layer 185 for increasing the height of an on-chip lens 187 and a light shielding wall 184 for partitioning the spacer layer 185 in units of the photoelectric conversion unit 51 and shielding light, thereby suppressing crosstalk from the large pixel 100L to the small pixel 100S.

[0231] <4.2 Unit Pixel Structure in Comparative Example>

[0232] Will refer to Fig. 9 A unit pixel 21 ′ in a comparative example (hereinafter also referred to as a comparative unit pixel 21 ′) to be compared with the unit pixel 21 according to the first embodiment will be described.

[0233] Fig. 9 A is a cross-sectional view showing a configuration example of a comparative unit pixel 21', and shows a cross-sectional view along Fig. 9 A cross-sectional view along line XX' in FIG. Fig. 9 B is a plan view of a comparison unit pixel 21 ′.

[0234] Similar to the unit pixel 21 according to the first embodiment, the comparative unit pixel 21' includes a large pixel 100L' and a small pixel 100S' having different areas of photoelectric conversion units. The components of the large pixel 100L' and the small pixel 100S' corresponding to the unit pixel 21 are represented by the same reference numerals.

[0235] The comparison unit pixel 21' is different from the unit pixel 21 according to the first embodiment in that the comparison unit pixel 21' does not include a spacer layer 185 and a light shielding wall 184 separating the spacer layer 185. In other words, an inter-pixel light shielding film 183 is formed on the insulating film 182 on the light incident surface side of the semiconductor substrate 121, and a color filter 186 is formed just above the inter-pixel light shielding film 183. The other configurations of the comparison unit pixel 21' are similar to those of the unit pixel 21 according to the first embodiment.

[0236] <4.3 Results of Optical Characteristics in First Embodiment and Comparative Example>

[0237] Will refer to Fig.10 and Fig.11 A comparison result of optical characteristics of the unit pixel 21 according to the first embodiment and the unit pixel 21 ′ according to the comparative example is described.

[0238] Fig.10 Optical simulation results of the oblique incidence characteristics of the unit pixel 21 and the comparative unit pixel 21 ′ along a diagonal direction at a wavelength of 530 nm are shown.

[0239] Fig.11 The light intensity distribution of the unit pixel 21 and the comparative unit pixel 21 ′ at each incident angle along the diagonal direction at a wavelength of 530 nm is shown.

[0240] In the optical simulation, the calculation was performed by setting the longitudinal and lateral lengths of the octagon with the missing portion in the diagonal direction to 3 μm as the plane size of the first photoelectric conversion unit 51L of the large pixel 100L of the unit pixel 21, and setting the longitudinal and lateral lengths of the square to 1.12 μm as the plane size of the second photoelectric conversion unit 51S of the small pixel 100S. In addition, the minimum opening width W of the inter-pixel light shielding film 183 was set to 740 nm, and the height H as the total height of the inter-pixel light shielding film 183 and the light shielding wall 184 was set to 1260 nm, including the thickness of the inter-pixel light shielding film 183 of 260 nm. The width A of the inter-pixel light shielding film 183 surrounding the small pixel was set to 540 nm, and the width B of the light shielding wall 184 was set to 240 nm. The same conditions other than the height H and the width B of the light shielding wall 184 also apply to the comparative unit pixel 21'.

[0241] In the optical simulation, the calculation was performed by distributing parallel light with a wavelength of 530 nm in diagonal directions from 0 to 80 degrees in units of 10 degrees. The area of ​​about ±20 degrees with a dot pattern represents the angle range of the upper and lower rays assumed for the module lens.

[0242] First, regarding the unit pixel 21' of the comparative example, referring to Fig.10 In view of the oblique incidence characteristics in the module lens, the output of the green pixel corresponding to the 530nm incident wavelength (green component) is reflected in both the large pixel 100L' and the small pixel 100S' within the angle range of the module lens. Although slight color mixing is observed in the large pixel 100L', it can be corrected by signal processing that takes color mixing into consideration (such as linear matrix processing or white balance processing).

[0243] On the other hand, in a region where the incident angle of the small pixel 100S' is equal to or greater than 50 degrees, extreme output floating due to crosstalk from the large pixel 100L' occurs, and crosstalk several times the original output (near 0 degrees) of the small pixel 100S' occurs.

[0244] Next, regarding the unit pixel 21' in the comparative example, referring to Fig.11 In the light intensity distribution in the area equal to or greater than 50 degrees, it can be determined that the light collected by the large on-chip lens 187L of the large pixel 100L' passes over the inter-pixel light shielding film 183 and strongly leaks to the second photoelectric conversion unit 51S of the adjacent small pixel 100S'. In the case where a high-angle glare component occurs in the large and small pixel structure, not only output floating but also extreme coloring occurs, which has an unacceptable effect on image quality.

[0245] In addition, for the large pixel 100L' in the comparative example, refer to Fig.10 The oblique incidence characteristics in the pixel 100L' can ensure that high sensitivity is maintained at less than ±40 degrees, which is wider than the angle range of the upper and lower rays of the module lens. In the state where the sensitivity to unnecessary light in the large pixel 100L' is high, various stray light components are likely to be captured, which is not ideal from the perspective of glare.

[0246] Next, with respect to the large pixel 100L of the unit pixel 21 according to the first embodiment, referring to Fig.10 In the oblique incidence characteristic, high sensitivity is maintained up to ±20 degrees, which is approximately the same as the angle range of the upper and lower rays of the module lens, and the sensitivity is suppressed to low at a larger angle. For the small pixel 100S, extreme output fluctuation due to crosstalk from the large pixel 100L' is suppressed, as occurs in the region where the incident angle is equal to or greater than 50 degrees in the unit pixel 21' of the comparative example.

[0247] Next, refer to Fig.11 In the light intensity distribution in the incident angle equal to or greater than 60 degrees, the effect of the unit pixel 21 according to the first embodiment appears. For example, focusing on the light intensity distribution of 60 degrees surrounded by the white line, it can be determined that in the unit pixel 21' of the comparative example, light passes over the inter-pixel light shielding film 183 and leaks directly from the large pixel 100L' to the small pixel 100S', while in the unit pixel 21 according to the first embodiment, light from the large on-chip lens 187L of the large pixel 100L passes over the light shielding wall 184, and then hits the light shielding wall 184 on the opposite side before reaching the second photoelectric conversion unit 51S of the small pixel 100S, and is attenuated.

[0248] In this way, by providing the spacer layer 185, increasing the height of the on-chip lens 187, and providing the light shielding wall 184 at the boundary portion of the large and small pixels, the unnecessary light at a high angle and the crosstalk hitting the light shielding wall 184 and thus the crosstalk from the large pixel 100L to the small pixel 100S can be significantly suppressed. In addition, the sensitivity of the unnecessary light at the large pixel 100L can be suppressed. Glare is suppressed by suppressing the sensitivity of the crosstalk and the unnecessary light. In particular, this effect is significantly seen in the pixel structure of the unit pixel 21 in which the ratio of the area of ​​the photoelectric conversion region of the first photoelectric conversion unit 51L of the large pixel 100L and the second photoelectric conversion unit 51S of the small pixel 100S is equal to or greater than twice.

[0249] <4.4 Relationship between the Width of the Inter-Pixel Light Shielding Film and the Width of the Light Shielding Wall>

[0250] Next, we will refer to Fig.12 and Fig.13 The relationship between the width A of the inter-pixel light shielding film 183 and the width B of the light shielding wall 184 will be described.

[0251] As described above, the relationship between the width A of the inter-pixel light shielding film 183 and the width B of the light shielding wall 184 is A>B, that is, the thickness A of the inter-pixel light shielding film 183 is formed to be larger than the width B of the light shielding wall 184 .

[0252] like Fig.12 As shown in the left figure in FIG. 1 , when the inter-pixel light shielding film 183 is not provided but only the light shielding wall 184 is formed, the stray light generated in the imaging module housing will jump into the photoelectric conversion unit 51 and cause glare.

[0253] On the contrary, by providing the inter-pixel light shielding film 183 and the light shielding wall 184 having a relationship of width A>width B, stray light is reflected upward by the inter-pixel light shielding film 183 which protrudes more in the plane direction (lateral direction) than the light shielding wall 184, and the stray light is prevented from jumping into the photoelectric conversion unit 51. Therefore, the effect of suppressing glare sensitivity can be improved.

[0254] In the inter-pixel light shielding film 183, a protrusion having a different width (length in the planar direction) that protrudes more than the light shielding wall 184 in the planar direction may be provided for each of the large pixel 100L side and the small pixel 100S side. Fig.13 As shown, by forming the width C1 of the protrusion 183L on the large pixel side to be smaller than the width C2 of the protrusion 183S on the small pixel side, that is, by forming them to satisfy the relationship of width C1<width C2, the effect of suppressing glare sensitivity can be enhanced. In addition, this leads to the effect of expanding the sensitivity difference between the large pixel 100L and the small pixel 100S, and there is also an effect of expanding the dynamic range of the solid-state imaging device 1.

[0255] <4.5 Second Configuration Example of Light Shielding Wall>

[0256] Next, a second configuration example of the light shielding wall 184 will be described assuming that the configuration example of the light shielding wall 184 described above is the first configuration example.

[0257] Fig.14 It is a cross-sectional view showing a second configuration example of the light shielding wall.

[0258] In the first configuration example of the light shielding wall 184 described above, the height of the upper surface of the light shielding wall 184 is the same as the height of the bottom surface of the color filter 186, and the light shielding wall 184 is formed further downward than the layer of the color filter 186. In contrast, the light shielding wall 184A, which is a second configuration example of the light shielding wall 184, is formed in at least a portion of the same layer as the color filter 186.

[0259] For example, Fig.14 As shown in FIG. 1A , the light shielding wall 184A extends to the same height as the upper surface of the color filter 186 and may have a structure that completely separates the color filter 186. Alternatively, as Fig.14 As shown in FIG. 1B , the light shielding wall 184A may extend from the bottom surface of the color filter 186 to a height h1 in the middle and may have a configuration of partitioning a portion of the color filter 186 .

[0260] In adopting the same Fig.14 In the case of a configuration in which the color filter 186 is completely separated as in A, the effect of suppressing crosstalk is enhanced, but due to the presence of the light shielding wall 184A, the problem of uneven coating of the color filter 186 may occur.

[0261] On the contrary, in Fig.14 In the case of a structure in which a part of the color filter 186 is separated as in B, the problem of uneven coating of the color filter 186 is reduced, but the effect of suppressing crosstalk is also limited.

[0262] Fig.15 The optical simulation results of the oblique incidence characteristics of the unit pixel 21' in the comparative example and the unit pixel 20 including the light shielding wall 184 of the first configuration example or the second configuration example along the diagonal direction at a wavelength of 530nm are shown. As the second configuration example of the light shielding wall 184, a light shielding wall 184A is used in which a part of the color filter 186 is separated. Fig.14 The structure in B is as follows, and the height h1 from the bottom surface of the color filter 186 is set to 260 nm.

[0263] Since the oblique incidence characteristics of the unit pixel 21' in the comparative example and the unit pixel 21 including the light shielding wall 184 of the first configuration example are different from Fig.10 is similar to that in , so its description will be omitted.

[0264] By comparing the oblique incidence characteristics of the unit pixel 21 including the light shielding wall 184 of the first configuration example and the unit pixel 21 including the light shielding wall 184 of the second configuration example, it can be determined that in the area of ​​the small pixel 100S equal to or greater than ±50 degrees of the unit pixel 21 including the light shielding wall 184 of the second configuration example, the sensitivity of R and B is suppressed, and the crosstalk component through the color filter 186 can be suppressed. Although the configuration in which the light shielding wall 184 is extended to the color filter 186 is also desirable because extreme coloring can be solved from the viewpoint of glare, the number of processing steps increases.

[0265] <4.6 Third Configuration Example of Light-Shielding Wall>

[0266] Fig.16 It is a cross-sectional view showing a third configuration example of the light shielding wall.

[0267] like Fig.16 As shown, the light-shielding wall 184B as the third configuration example of the light-shielding wall 184 is composed of a light-shielding wall 184B1 of a lower section (first section) and a light-shielding wall 184B2 of an upper section (second section). The light-shielding wall 184B2 of the upper section is provided with an offset in the plane direction at the position where pupil correction is performed on the light-shielding wall 184B1 of the lower section. In other words, the light-shielding wall 184B2 of the upper section is configured to be offset on the center side of the pixel array unit 11 than the light-shielding wall 184B1 of the lower section. In addition, the color filter 186 and the on-chip lens 187, which are higher layers than the light-shielding wall 184B2 of the upper section, are also configured to be offset on the center side of the pixel array unit 11 than the light-shielding wall 184B1 of the lower section in a similar manner. By configuring the light-shielding wall 184B into two sections in this manner, the degree of freedom of pupil correction is increased, and the degradation of the oblique incidence characteristics at the corner ends of the image can be suppressed. Note that, as Fig.16 As shown, it is desirable that the upper light shielding wall 184B2 and the lower light shielding wall 184B1 are in contact with each other without a gap therebetween to suppress crosstalk.

[0268] although Fig.16 The third configuration example shown is an example in which the light shielding wall 184B is composed of two sections, that is, the light shielding wall 184B1 of the lower section and the light shielding wall 184B2 of the upper section, but a multi-section configuration including three or more sections may also be adopted. Although there is a problem of poor embedding of the light shielding material when the aspect ratio of the light shielding wall 184 is high, poor embedding can be avoided by splitting processing into two or more sections like the light shielding wall 184B.

[0269] <4.7 Fourth Configuration Example of Light-Shielding Wall>

[0270] Fig.17 It is a cross-sectional view showing a fourth configuration example of the light-shielding wall.

[0271] like Fig.17As shown, the light shielding wall 184C as a fourth configuration example of the light shielding wall 184 is composed of a light shielding wall 184C1 on the on-chip lens 187 side closer to the inter-pixel light shielding film 183 and a light shielding wall 184C2 on the semiconductor substrate 121 side. The light shielding wall 184C1 on the on-chip lens 187 side extends not only to the color filter 186 but also to the on-chip lens 187, and is configured to separate the on-chip lens 187. The light shielding wall 184C2 on the semiconductor substrate 121 side extends to a predetermined depth of the semiconductor substrate 121, and the periphery of the light shielding wall 184C2 in the semiconductor substrate 121 is electrically isolated from the semiconductor substrate 121 by the insulating film 191. It is also possible to block a crosstalk path in the on-chip lens 187 by the light shielding wall 184C1 on the on-chip lens 187 side, and block a crosstalk path in the substrate by the light shielding wall 184C2 on the semiconductor substrate 121 side. Although the light shielding wall 184C of the fourth configuration example can solve the problem of extreme coloring from the viewpoint of glare, the number of processing steps increases. In addition, there is also a problem of deterioration of dark characteristics.

[0272] <4.8 Manufacturing method of the first embodiment>

[0273] Next, we will refer to Figure 18 to Figure 21 A method for manufacturing the unit pixel 21 according to the first embodiment is described. Figure 18 to Figure 21 In the following, the method of forming the inter-pixel light shielding film 183 and the light shielding wall 184 will be mainly described, and the figure marks of other parts will be appropriately omitted.

[0274] First, if Fig.18 As shown in A, after the photoelectric conversion unit 51 and the element separation unit 141 are formed in the semiconductor substrate 121, the wiring layer 122 is formed on the front side of the semiconductor substrate 121, and the fixed charge film 181 and the insulating film 182 are formed on the back side of the semiconductor substrate 121.

[0275] More specifically, in the region where the pixel region is to be formed of the semiconductor substrate 121 such as a silicon substrate, a photoelectric conversion unit 51 separated by an element separation unit 141 composed of a P-type semiconductor region is formed. The photoelectric conversion unit 51 is formed to have a PN junction, and the PN junction includes an N-type semiconductor region spanning the entire region in the substrate thickness direction and a P-type semiconductor region in contact with the N-type semiconductor region and facing the front and back sides of the substrate. The impurity region of the N-type semiconductor region or the P-type semiconductor region can be formed by ion implanting the required impurities from the front side of the substrate using a resist as a mask. The P-type semiconductor well region in contact with the element separation unit 141 is formed in the region of the substrate surface corresponding to each of the large pixel 100L and the small pixel 100S, and a plurality of pixel transistors Tr are formed in the P-type semiconductor well region. The pixel transistor Tr is formed by an N-type source region and a drain region, a gate insulating film, and a gate electrode.

[0276] In addition, a wiring layer 122 is formed on the front surface of the semiconductor substrate 121. The wiring layer 122 includes a multilayer metal wiring 131 composed of, for example, aluminum or copper, and an interlayer insulating film 132 located therebetween and composed of a silicon oxide film or the like. The pixel transistor Tr is connected to a predetermined metal wiring 131 via a through hole, and a driving voltage for driving the pixel transistor Tr is applied to the pixel transistor Tr. After the interlayer insulating film 132 of the silicon oxide film or the like is flattened by chemical mechanical polishing (CMP), a multilayer metal wiring 131 is formed by repeating the formation of through holes to establish a connection with the metal wiring 131 of the lower layer and further forming the metal wiring 131 thereon.

[0277] Next, a fixed charge film 181 and an insulating film 182 are formed on the back side of the semiconductor substrate 121 using chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD), or the like. It is desirable to form the fixed charge film 181 in contact with the surface of the semiconductor substrate 121 by ALD, and satisfactory coverage can be obtained at the atomic layer level by ALD. For example, in the case of forming silicon oxide by ALD as the insulating film 182 formed thereon, if the film thickness is reduced, film peeling due to a blistering phenomenon is likely to occur, and the film thickness of the insulating layer 182 is at least equal to or greater than 20 nm, and preferably equal to or greater than 50 nm in thickness.

[0278] Next, if Fig.18 As shown in A, an inter-pixel shading film material 201 is formed on the insulating film 182. The inter-pixel shading film material 201 is, for example, tungsten (W), and CVD or sputtering can be used as a film forming method. An opening portion 202 in which the fixed charge film 181 and the insulating film 182 are opened is provided in the area outside the pixel array unit 11, and the inter-pixel shading film material 201 is connected to the P-type semiconductor region of the semiconductor substrate 121 through the opening portion 202. Since there is a risk of plasma damage when the inter-pixel shading film material 201 is processed in an electrically floating state, film formation is performed so that the inter-pixel shading film material 201 is connected to the P-type semiconductor region grounded to the ground potential at the opening portion 202. The opening portion 202 can be formed by forming a resist pattern having a width of several μm on the insulating film 182 and performing anisotropic etching or wet etching.

[0279] The inter-pixel light shielding film material 201 may be formed as a plurality of stacked films to enhance adhesion to the underlying insulating film 182. For example, titanium, titanium nitride, or a stacked film thereof may be formed as a layer that closely adheres to the insulating film 182. The inter-pixel light shielding film material 201 may also be used as a light shielding film for a black level calculation pixel (which is a pixel for calculating the black level of an image signal), or as a light shielding film for preventing operation errors of peripheral circuits.

[0280] Next, if Fig.18 As shown in FIG. 1B, the resist 203 is patterned in the formation region of the inter-pixel light shielding film 183 on the inter-pixel light shielding film material 201, and then the inter-pixel light shielding film material 201 is partially removed by anisotropic etching or the like. In this way, as Fig.18 As shown in FIG. C, an inter-pixel light shielding film 183 is formed. If necessary, residues are removed by chemical cleaning.

[0281] Next, if Fig.19 As shown in FIG. 1A , a transparent inorganic film such as silicon oxide (SiO 2 ) is formed on the insulating film 182 and the inter-pixel light shielding film 183 by using CVD or the like, thereby forming a spacer layer 185. Fig.19 In the case where the top surface of the spacer layer 185 is uneven due to the processing step difference of the inter-pixel light shielding film 183 as the base, as shown in FIG. Fig.19 As shown in FIG. 1B, a reverse-processed resist mask 211 may be formed for a region of the inter-pixel light shielding film 183 that is relatively large and in contact with the semiconductor substrate 121, and as shown in FIG. Fig.18 As shown in C in FIG. 1 , the protruding portion of the spacer layer 185 can be removed by etching with time management. Fig. 20 As shown in A, the spacer layer 185 can be planarized by CMP. Note that in the case where the planarity of the spacer layer 185 is satisfactory, the step of Fig.19 B to Fig. 20 The process of A.

[0282] Next, if Fig. 20 As shown in FIG. 1B, after forming the resist mask 212 in the region other than the region where the light shielding wall 184 is formed, as shown in FIG. Fig. 20 As shown in FIG. 1C, the spacer layer 185 is removed by etching, and the upper portion of the inter-pixel light shielding film 183 is exposed. In a plan view, the region where the spacer layer 185 is removed has an octagonal or quadrilateral shape, which is consistent with Figure 8 The planar shape of the light shielding wall 184 shown in B is the same. Note that since there is a problem of cracking due to stress concentration in such high aspect ratio micro-processing, the finished corners of each side of the octagon or quadrilateral may not be linear and may be intentionally rounded. In this case, the radius of curvature is preferably equal to or greater than 1 / 10 of the pixel size of the small pixel 100S, and more preferably equal to or greater than 1 / 7.

[0283] Next, if Fig.21 As shown in A, a light shielding wall metal material 213 is formed on the resist mask 212. The light shielding wall metal material 213 is, for example, tungsten (W), and CVD or sputtering can be used as a film forming method. The light shielding wall metal material 213 is also buried in the groove portion of the spacer layer 185 above the inter-pixel light shielding film 183.

[0284] Next, if Fig.21 As shown in FIG. 1B , the light shielding wall metal material 213 in the upper layer of the spacer layer 185 is removed by CMP or entire surface etch-back. In this way, the light shielding wall 184 is completed.

[0285] Next, if Fig.21 As shown in FIG. C, the spacer layer 185 and the light shielding wall 184 are protected by a protective film 214 such as an oxide film. Figure 7 The protective film 214 is omitted in the cross-sectional view of FIG. 1 , but the protective film 214 is a film for protection because the organic material of the color filter 186 or the like formed on the spacer layer 185 may come into contact with the light shielding wall 184 which is a metal material and may be deteriorated. The protective film 214 also has a function of protecting the metal material of the inter-pixel light shielding film 183 from the influence of a stripping agent or the like when it is necessary to strip a layer above the color filter 186 due to an exposure problem or out of specification.

[0286] Next, although illustration is omitted, the color filter 186 is formed by spin-coating, for example, a photosensitive agent and a resist containing a pigment or dye onto the wafer, followed by exposure, development, and post-baking. In the case where the color filter 186 is a dye resist, UV curing or additional baking may be performed.

[0287] Finally, the on-chip lens 187 is formed. First, for example, an organic material such as a styrene resin (refractive index n is about 1.6), an acrylic resin (n is about 1.5), or a styrene-acrylic copolymer resin (n is about 1.5 to 1.6) is formed by spin coating as the material of the on-chip lens 187. The material of the on-chip lens 187 may be a mixture of organic and inorganic materials in which TiO fine particles are dispersed in the above resin or polyimide resin. Alternatively, an inorganic material such as SiN (n is about 1.9 to 2) or SiON (about 1.45 to 1.9) may be formed as the material of the on-chip lens 187 by CVD or the like. Then, by exposing and reflowing on the material of the on-chip lens 187, a resist is formed into a lens shape, and the lens shape of the resist is transferred to the material of the on-chip lens 187 by anisotropic etching. Next, in order to improve sensitivity and prevent glare, an anti-reflection film 188 is formed on the surface of the on-chip lens 187. For example, it is desirable to use SiO2 as the material of the anti-reflection film 188, and to apply it roughly according to the anti-reflection design following the 4 / λ law. The anti-reflection film 188 is not necessarily limited to a single layer, but may be a multilayer film. By forming the anti-reflection film 188, it is also possible to reduce the area of ​​the flat and ineffective region of the diagonal portion where the curved surface of the on-chip lens 187 is not formed.

[0288] Note that the large on-chip lens 187L above the first photoelectric conversion unit 51L and the small on-chip lens 187S above the second photoelectric conversion unit 51S having different areas and lens thicknesses can be formed by two processes, namely, photolithography, etching, photolithography, and etching. In the case where control can be achieved only by a resist mask, one exposure and one etching can be used.

[0289] The unit pixel 21 according to the first embodiment can be manufactured as described above.

[0290] <4.9 Summary of the First Implementation Plan>

[0291] The unit pixel 21 according to the first embodiment includes a first photoelectric conversion unit 51L and a second photoelectric conversion unit 51S having different areas of photoelectric conversion regions formed in a semiconductor substrate 121, an inter-pixel light-shielding film 183 arranged on at least a portion of the boundary between the unit pixels 21 on the incident light side relative to the semiconductor substrate 121, a spacer layer 185 arranged on the incident light side relative to the inter-pixel light-shielding film 183, a light-shielding wall 184 arranged on at least a portion of the boundary between the unit pixels 21 on the incident light side relative to the inter-pixel light-shielding film 183 and separating the spacer layer 185, and an on-chip lens 187 that collects incident light on the photoelectric conversion unit 51.

[0292] The unit pixel 21 according to the first embodiment can suppress crosstalk from the large pixel 100L to the small pixel 100S by including the spacer layer 185 that increases the height of the on-chip lens 187 and the light shielding wall 184 that separates the spacer layer 185 and shields light. In addition, the sensitivity of unnecessary light at the large pixel 100L can be suppressed. By suppressing the crosstalk and the sensitivity of unnecessary light, glare can be suppressed.

[0293] <5. Second Implementation Method of Unit Pixel>

[0294] <5.1 First Configuration Example of Second Implementation Method>

[0295] Fig. 22 is a cross-sectional view showing a first configuration example of a unit pixel 21 according to a second embodiment of the present disclosure, and shows a cross-sectional view along Fig.23 A cross-sectional view along line XX' in FIG. Fig.23 A~C are Fig. 22 A plan view of a unit pixel 21 at a predetermined depth position.

[0296] In a second embodiment, using Figure 3 The second layout example shown is used as the layout of the unit pixel 21. As the layout of the on-chip lens, a configuration of the same shape and size is adopted. Figure 4Although different reference numerals are applied in the second embodiment from those in the above-described first embodiment, portions corresponding to those in the first embodiment will be briefly described.

[0297] For the unit pixel 21 in the first embodiment described above, the configuration for suppressing crosstalk by forming the spacer layer 185 and increasing the height of the on-chip lens 187 has been described. In contrast, for the unit pixel 21 in the second embodiment, the spacer layer 185 is omitted, and instead, a light shielding wall (hereinafter referred to as a low-N wall) made of a low-refractive-index material is provided in the same layer as the color filter.

[0298] like Fig.23 As shown in A of FIG. 1 , the unit pixel 21 according to the first configuration example of the second embodiment is formed to have a quadrilateral planar shape. In the unit pixel 21, for example, Fig. 22 As shown, a first photoelectric conversion unit 311L having a large photoelectric conversion region and a second photoelectric conversion unit 311S having a smaller photoelectric conversion region than the first photoelectric conversion unit 311L are formed on a semiconductor substrate 301 composed of a P-type (first conductive type) semiconductor region. Fig.23 B). The semiconductor substrate 301 is composed of, for example, a silicon substrate using silicon (Si) as a semiconductor, and corresponds to the semiconductor substrate 121 according to the first embodiment. Although similar to the first embodiment, in which the pixel transistor Tr ( Figure 7 ) are formed on the front side of the semiconductor substrate 301 (ie, the lower side in the figure), but are not shown in the figure.

[0299] like Fig.23 As shown in B, the first photoelectric conversion unit 311L is formed into an L shape in a plan view, and the second photoelectric conversion unit 311S is formed into a quadrilateral. Therefore, the first photoelectric conversion unit 311L is a photoelectric conversion unit 311 with high sensitivity, and the second photoelectric conversion unit 311S is a photoelectric conversion unit 311 with low sensitivity. The first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S are composed of PN junction photodiodes similar to the first embodiment. In the case where the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S are not particularly distinguished, they are simply referred to as photoelectric conversion units 311. An element separation unit 312 that separates the photoelectric conversion element is formed at the boundary between the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S and the boundary between adjacent unit pixels 21.

[0300] like Fig. 22 As shown, the element separation unit 312 is formed by embedding an insulating film such as a silicon oxide film (SiO2) in a groove penetrating the semiconductor substrate 301. On the light receiving surface side of the semiconductor substrate 301, a concave portion 313 having an inverted pyramid structure is formed. Fig.23 As shown in FIG. 1B, in the unit pixel 21, four recesses 313 are arranged in a 2x 2 layout, three recesses 313 are arranged in the first photoelectric conversion unit 311L, and one recess 313 is arranged in the second photoelectric conversion unit 311S. The surface of the recess 313 is formed by the (111) surface of the semiconductor substrate 301, and the plane portion of the semiconductor substrate 301 where the recess 313 is not formed is formed by the (100) surface of the semiconductor substrate 301. An insulating film 314 of the same material as the element separation unit 312 is buried in the upper part of the (111) surface of the recess 313 of the inverted pyramid structure.

[0301] exist Fig. 22 In the embodiment, the color filter 315 is formed on the back side of the surface which is the upper side of the semiconductor substrate 301. For example, the color filter 315 of red (R), green (G) or blue (B) is arranged in a Bayer layout for each unit pixel 21, as shown in FIG. Figure 3 B. The low N wall 316 composed of a laminate of an inter-pixel light shielding film 321 and a low refractive index resin film 322 is formed in the same layer as the color filter 315 just above the element separation unit 312 .

[0302] The inter-pixel shading film 321 is made of a material similar to the inter-pixel shading film 183 in the first embodiment. In other words, the inter-pixel shading film 321 is made of any material as long as the material is light-shielding, and is preferably formed of a metal film such as Al, W or Cu, as a material having high light-shielding properties and that can be processed with high precision by micro-processing such as etching. In other cases, it can be composed of silver, gold, platinum, Mo, Cr, Ti, nickel, iron, tellurium or an alloy containing such a metal. In addition, the inter-pixel shading film 321 can also be formed by stacking a plurality of such materials. In order to enhance adhesion to the element separation unit 312 as a substrate, a barrier metal such as Ti, Ta, W, Co, Mo or an alloy, nitride, oxide or carbide thereof may be included under the shading metal.

[0303] The low-refractive-index resin film 322 is made of a material having a lower refractive index than the color filter 315. The low-refractive-index resin film 322 may be formed of an organic material film such as a styrene resin, an acrylic resin, a styrene-acrylic copolymer resin, or a siloxane resin. The low-refractive-index resin film 322 may be formed of an inorganic film such as SiN, SiO2, or SiON.

[0304] Fig.23 C is a plan view of the color filter 315 and the low N wall 316. The low N wall 316 has the same Fig.23The element separation unit 312 in B is configured similarly, specifically, a low N wall 316 is formed at a boundary between the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S and a boundary between adjacent unit pixels 21 .

[0305] like Fig. 22 As shown, on-chip lens 317 is formed on color filter 186 and low N wall 316. Fig.23 As shown in A, four on-chip lenses 317 are arranged in a 2x 2 arrangement in each unit pixel 21, wherein three on-chip lenses 317 are arranged on the first photoelectric conversion unit 311L, and one on-chip lens 317 is arranged on the second photoelectric conversion unit 311S. Similar to the first embodiment, an anti-reflection film may be formed on the surface of the on-chip lens 317.

[0306] In the solid-state imaging device 1 including the unit pixel 21 according to the second embodiment configured as described above, it is a back-illuminated solid-state imaging device in which incident light is collected on the on-chip lens 317 formed on the back side of the semiconductor substrate 301, and photoelectrically converted by the photoelectric conversion unit 311. The unit pixel 21 according to the second embodiment includes a large pixel having a first photoelectric conversion unit 311L having a large area of ​​a photoelectric conversion region and a small pixel having a second photoelectric conversion unit 311S having a smaller photoelectric conversion region than the first photoelectric conversion region 311L, and is capable of high-sensitivity imaging using the large pixel and low-sensitivity imaging using the small pixel.

[0307] The unit pixel 21 according to the first configuration example of the second embodiment includes a first photoelectric conversion unit 311L and a second photoelectric conversion unit 311S having photoelectric conversion regions of different areas formed in a semiconductor substrate 301, an element separation unit 312 that penetrates the semiconductor substrate 301 and separates the first photoelectric conversion unit 311L from the second photoelectric conversion unit 311S, a color filter 315 provided on the incident light side relative to the semiconductor substrate 301, a low N wall 316 provided between the color filters 315, a recess 313 provided on the light receiving surface side of the semiconductor substrate 301, and an on-chip lens 317 that collects incident light on the photoelectric conversion unit 311.

[0308] According to the unit pixel 21 of the first configuration example of the second embodiment, by providing the low N wall 316 at the boundary between the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S in the same layer as the color filter 315 and at the boundary between adjacent unit pixels 21, Fig.24As shown by the arrow 331 in FIG. 2 , incident light or stray light at a high angle that is about to pass between unit pixels 21 or between large pixels and small pixels can be reflected, and color mixing between pixels can be suppressed. Therefore, color glare can be suppressed. In addition, by stacking a low-refractive-index resin film 322 on the inter-pixel shading film 321 to form a low-N wall 316, the metal absorption loss caused by the inter-pixel shading film 321 as a metal film is reduced. Therefore, the light receiving sensitivity can be improved.

[0309] Furthermore, according to the unit pixel 21 of the first configuration example of the second embodiment, by providing the concave portion 313 on the light receiving surface side of the semiconductor substrate 301, as shown in FIG. Fig.24 As shown by arrow 332 in FIG. 3 , the light path length can be increased through the light scattering effect, and the light receiving sensitivity can be improved. This is beneficial to improve the sensitivity to near-infrared wavelengths.

[0310] <5.2 Modification of Low N Wall>

[0311] Fig.25 is a plan view showing a modification of the low N wall 316 of the unit pixel 21 according to the first modification. Fig.25 There are shown a plan view of the low N wall 316 and a plan view of the element separation unit 312. In the plan view of the low N wall 316, the recess 313 is shown by a dotted line.

[0312] exist Fig. 22 and 23 In the structure of the unit pixel 21 according to the first configuration example shown in the figure, the low N wall 316 is formed in the same configuration as the element separation unit 312. In other words, the low N wall 316 is provided at the boundary between the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S and at the boundary between adjacent unit pixels 21.

[0313] On the contrary, Fig.25 In the first modification example shown in A of FIG. 1 , the low N wall 316 is provided only at the boundary between adjacent unit pixels 21, and is not provided at the boundary between the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S. According to the first modification example, color mixing between unit pixels 21 can be suppressed and color glare can be suppressed. In addition, since a part of the low N wall 316 is omitted compared with the structure in the first configuration example, the metal absorption loss caused by the inter-pixel light shielding film 321 as a metal film can be reduced. Therefore, compared with the basic structure of the first configuration example, the light receiving sensitivity of the unit pixel 21 can be improved.

[0314] On the other hand, Fig.25In the second modification shown in FIG. 1B , the low N wall 316 is provided at a 1 / 4 pixel period of the unit pixel 21. In other words, similar to the low N wall 316 provided around one concave portion 313 in the second photoelectric conversion unit 311S, the low N wall 316L is also provided in units of the concave portion 313 in the first photoelectric conversion unit 311. Fig.25 The cross-sectional view of line XX' in B is as follows Fig.26 According to the second modification, the symmetry of the low N wall 316 is ensured, so the asymmetry of the sensitivity output of the large and small pixels in response to oblique incident light can be solved.

[0315] <5.3 Second Configuration Example of Second Implementation Method>

[0316] Fig. 27 A is a cross-sectional view showing a second configuration example of the unit pixel 21 according to the second embodiment of the present disclosure, and shows a cross-sectional view along Fig. 27 A cross-sectional view along line XX' in FIG. Fig. 27 B is Fig. 27 A is a plan view of the unit pixel 21 in FIG. 1 at a predetermined depth position.

[0317] exist Fig. 27 In, with Fig. 22 and Fig.23 The corresponding parts in the first configuration example shown are denoted by the same reference numerals, and the description will focus on the parts different from the first configuration example.

[0318] In the first configuration example, three recesses 313 formed in the light receiving surface of the semiconductor substrate 301 are arranged above the first photoelectric conversion unit 311L, one recess 313 is arranged above the second photoelectric conversion unit 311S, and four recesses 313 are arranged in a 2x2 layout within the unit pixel 21.

[0319] On the contrary, compared with the concave portion 313 in the first configuration example, Fig. 27 In the second configuration example, each concave portion 313 is formed to have a smaller size, and sixteen small-sized concave portions 311 are arranged in a 4×4 layout in the unit pixel 21. Twelve small-sized concave portions 313 are arranged above the first photoelectric conversion unit 311L, and four small-sized concave portions 313 are arranged above the second photoelectric conversion unit 311S.

[0320] The unit pixel 21 in the second configuration example is similar to that in the first configuration example except that the size of each recess 313 and the number of recesses 313 arranged above each of the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S are different.

[0321] The size of the recess 313 can be appropriately determined according to the target wavelength of the incident light for which the quantum efficiency (QE) thereof is desired to be improved. As the size of the recess 313 increases, the sensitivity to longer wavelengths can be improved. In the case where a wavelength of about 940 nm is set as the target wavelength in order to improve the sensitivity to near-infrared light of about 850 nm to 940 nm, four recesses 313 can be arranged in a 2x 2 manner in the unit pixel 21 as in the first configuration example, or in the case where a wavelength of about 850 nm is set as the target wavelength, sixteen recesses 313 can be arranged in a 4x 4 manner as in the second configuration example.

[0322] In the unit pixel 21 according to the second configuration example, by providing a low N wall 316 in the same layer as the color filter 315, color mixing between pixels can also be suppressed. Therefore, color glare can be suppressed. Since the low N wall 316 formed by stacking a low refractive index resin film 322 on the inter-pixel shading film 321 reduces metal absorption loss, the light receiving sensitivity can be improved. In addition, by providing a recess 313 on the light receiving surface side of the semiconductor substrate 301, the optical path length can be increased by the light scattering effect, and the light receiving sensitivity can be improved.

[0323] <5.4 Modification of concave portion>

[0324] Fig.28 It is a plan view showing a modified example of the recessed portion 313 in the first configuration example and the second configuration example.

[0325] In the above-described first and second configuration examples, a plurality of recesses 313 having the same size are provided in the unit pixel 21 .

[0326] However, the large-sized concave portion 313 and the small-sized concave portion 313 may be appropriately combined and arranged within the unit pixel 21. Alternatively, there may be a region where the concave portion 313 is not arranged.

[0327] For example, you can use Fig.28 A shows a configuration in which three large-sized recesses 313 are arranged above the first photoelectric conversion unit 311L and four small-sized recesses 313 are arranged above the second photoelectric conversion unit 311S.

[0328] Alternatively, for example, one may use Fig.28 B shows a configuration in which three large-sized recesses 313 are arranged above the first photoelectric conversion unit 311L and no recess 313 is arranged above the second photoelectric conversion unit 311S.

[0329] Alternatively, for example, one may use Fig.28C shows a configuration in which the recess 313 is not arranged above the first photoelectric conversion unit 311L and a large-sized recess 313 is arranged above the second photoelectric conversion unit 311S.

[0330] Alternatively, for example, one may use Fig.28 D shows a configuration in which twelve small-sized recesses 313 are arranged above the first photoelectric conversion unit 311L and one large-sized recess 313 is arranged above the second photoelectric conversion unit 311S.

[0331] Alternatively, for example, one may use Fig.28 FIG. 1 shows a configuration in which twelve small-sized recesses 313 are arranged above the first photoelectric conversion unit 311L and no recess 313 is arranged above the second photoelectric conversion unit 311S.

[0332] Alternatively, for example, one may use Fig.28 FIG. 5 shows a configuration in which the recess 313 is not arranged above the first photoelectric conversion unit 311L and four small-sized recesses 313 are arranged above the second photoelectric conversion unit 311S.

[0333] As described above, the unit pixel 21 according to the second embodiment may have a configuration in which one or more recesses 313 are provided in at least one of the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S. A configuration in which the recess 313 is not provided in one of the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S may be adopted.

[0334] Note that, needless to say, you can use Fig.28 For example, the size of each recess 313 may be further reduced, and the number of recesses 313 to be arranged above the first photoelectric conversion unit 311L may be increased to more than twelve, or the number of recesses 313 to be arranged above the second photoelectric conversion unit 311S may be increased to more than four.

[0335] <5.5 Third Configuration Example of Second Implementation Method>

[0336] exist Fig.29 , A is a cross-sectional view showing a third configuration example of the unit pixel 21 according to the second embodiment of the present disclosure, and shows a cross-sectional view along Fig.29 A cross-sectional view of the line XX' in B. Fig.29 In the above table, B is Fig.29 A is a plan view of the unit pixel 21 in FIG. 1 at a predetermined depth position.

[0337] Fig.29The unit pixel 21 according to the third configuration example of the second embodiment shown is different in that the concave portion 313 in the first configuration example is replaced by a concave portion 351 , and other points are the same as those of the first configuration example.

[0338] The recess 313 in the first configuration example is formed of an inverted pyramid structure with respect to the light receiving surface of the semiconductor substrate 301. In contrast, the recess 351 in the third configuration example is formed of a groove structure obtained by digging the semiconductor substrate 301 to a predetermined depth with a certain width.

[0339] like Fig.29 As shown in the plan view in B, in the unit pixel 21, four recesses 351 formed by the groove structure are arranged in a 2x 2 layout, three recesses 351 are arranged in the first photoelectric conversion unit 311L, and one recess 351 is arranged in the second photoelectric conversion unit 311S. One recess 351 is formed into a rectangular shape that is elongated in the horizontal direction, the vertical direction, or the oblique direction, and scatters light in a direction perpendicular to the longitudinal direction of the rectangular shape as shown by the thick black arrow. Compared with the recess 313 in the first configuration example formed by the inverted pyramid structure, the recess 351 formed by the groove structure can enhance the scattering effect and can improve the light receiving sensitivity. On the other hand, there is a problem of increased light leakage to the adjacent unit pixel 21.

[0340] <5.6 Modification of concave portion>

[0341] Fig.30 It is a plan view showing a modified example of the recessed portion 351 in the third configuration example.

[0342] and Fig.28 Similar to the modified example of the inverted pyramid structure concave portion 313 described in the embodiment, the concave portion 351 of the groove structure can also be modified as follows: Fig.30 A configuration in which three recesses 351 are arranged above the first photoelectric conversion unit 311L and no recess 351 is arranged above the second photoelectric conversion unit 311S, or Fig.30 A configuration in which no recess 351 is arranged above the first photoelectric conversion unit 311L and one recess 351 is arranged above the second photoelectric conversion unit 311S is shown in B. In addition, the number and shape of the recess 351 arranged above at least one of the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S may be changed.

[0343] According to the unit pixel 21 of the third configuration example, by providing a low N wall 316 in the same layer as the color filter 315, color mixing between pixels can also be suppressed. Therefore, color glare can be suppressed. Since the low N wall 316 formed by stacking a low refractive index resin film 322 on the inter-pixel shading film 321 reduces metal absorption loss, the light receiving sensitivity can be improved. In addition, by providing a recess 351 on the light receiving surface side of the semiconductor substrate 301, the optical path length can be increased by the light scattering effect, and the light receiving sensitivity can be improved.

[0344] <5.7 Fourth Configuration Example of Second Implementation Method>

[0345] Fig.31 is a cross-sectional view showing a fourth configuration example of the unit pixel 21 according to the second embodiment of the present disclosure.

[0346] exist Fig.31 In, with Fig. 22 The corresponding parts in the first configuration example shown are denoted by the same reference numerals, and the description will focus on the parts different from the first configuration example.

[0347] exist Fig. 22 In the first configuration example shown, the upper portion of the (111) surface of the recess 313 formed in the light receiving surface of the semiconductor substrate 301 is formed flat by an insulating film 314 of the same material as the element separation unit 312, and a color filter 315 or a low N wall 316 is formed on the flat insulating film 312.

[0348] On the contrary, Fig.31 In the fourth configuration example, the color filter 315' is formed on the upper part of the (111) surface of the recess 313 formed in the light receiving surface of the semiconductor substrate 301 via an insulating film 314' having a predetermined film thickness. In other words, the lower side of the color filter 315' is not flat, and the color filter 315' is buried in the depression of the recess 313. In this way, the position of the upper side of the color filter 315' can be lowered compared to the position of the upper side of the color filter 315 in the first configuration example. By lowering the position of the upper side of the color filter 315', the thickness D1 from the upper side of the color filter 315' to the lowest part (depression) of the hemispherical surface of the on-chip lens 317 can be formed thinner than in the first configuration example. The thickness D1 of the lowest part of the hemispherical surface of the on-chip lens 317 can be formed thin, thereby forming a total thickness D2 of the on-chip lens 317 thin.

[0349] Since the thickness D1 of the lowest portion of the hemispherical surface of the on-chip lens 317 corresponds to the path through which high-angle oblique incident light passes, as the thickness D1 can be formed thinner, crosstalk between unit pixels and inter-pixel crosstalk between large pixels and small pixels can be further suppressed.

[0350] According to the unit pixel 21 of the fourth configuration example, by providing a low N wall 316 in the same layer as the color filter 315', color mixing between pixels can also be suppressed. Therefore, color glare can be suppressed. Since the low N wall 316 formed by stacking a low refractive index resin film 322 on the inter-pixel shading film 321 reduces the metal absorption loss, the light receiving sensitivity can be improved. In addition, by providing a recess 313 on the light receiving surface side of the semiconductor substrate 301, the optical path length can be increased by the light scattering effect, and the light receiving sensitivity can be improved. By burying the color filter 315' in the depression of the recess 313, the on-chip lens 317 can be formed to have a thin total thickness D2, and crosstalk between pixels can be suppressed.

[0351] <5.8 Summary of the Second Implementation Plan>

[0352] The unit pixel 21 according to the second embodiment includes a first photoelectric conversion unit 311L and a second photoelectric conversion unit 311S having different areas of photoelectric conversion regions formed in a semiconductor substrate 301, an element separation unit 312 that penetrates the semiconductor substrate 301 and separates the first photoelectric conversion unit 311L and the second photoelectric conversion unit 311S, a color filter 315 (or 315') provided on the incident light side relative to the semiconductor substrate 301, a low N wall 316 formed in the same layer as the color filter 315 and having a refractive index lower than that of the color filter 315, a recess 313 (or recess 351) provided on the light receiving surface side of the semiconductor substrate 301, and an on-chip lens 317 that collects incident light on the photoelectric conversion unit 311.

[0353] According to the unit pixel 21 of the second embodiment, by providing the low N wall 316 in the same layer as the color filter 315, the incident light or stray light at a high angle that will pass between the unit pixels 21 or between the large pixel and the small pixel can be reflected, and the color mixing between the pixels can be suppressed. Therefore, the color glare can be suppressed. In addition, by stacking the low refractive index resin film 322 on the inter-pixel shading film 321 to form the low N wall 316, the metal absorption loss caused by the inter-pixel shading film 321 as a metal film is reduced. Therefore, the light receiving sensitivity can be improved.

[0354] Furthermore, according to the unit pixel 21 of the second embodiment, by providing the recess 313 or 351 on the light receiving surface side of the semiconductor substrate 301 , the optical path length can be increased by the light scattering effect, and the light receiving sensitivity can be improved.

[0355] <6. Third Implementation Method of Unit Pixel>

[0356] <6.1 First Configuration Example of the Third Implementation Method>

[0357] Fig.32is a cross-sectional view showing a first configuration example of the unit pixel 21 according to the third embodiment of the present disclosure. Fig.32 A shows the Fig.33 The cross-sectional view of the line X-X' in Fig.32 B shows a cross-sectional view along line YY'. Fig.33 A and B are Fig.32 A plan view of a unit pixel 21 at a predetermined depth position.

[0358] In a third embodiment, using Figure 3 The second layout example shown is the layout of the unit pixel 21 . Figure 4 The layout shown in B is used as the layout of the on-chip lens. Although different reference numerals from those in the above-described first and second embodiments are applied in the third embodiment, portions corresponding to the first or second embodiment will be briefly described.

[0359] The unit pixel 21 according to the third embodiment is similar to the above-mentioned second embodiment in that the low-N wall as the light-shielding wall made of a low refractive index material is included in the same layer as the color filter. On the other hand, the unit pixel 21 according to the third embodiment is different from the above-mentioned second embodiment in that no concave portion is provided in the light receiving surface of the semiconductor substrate. A specific description is provided below.

[0360] The unit pixel 21 according to the third embodiment includes a large pixel 410L including a first photoelectric conversion unit 411L having high sensitivity formed in an L shape and a small pixel 410S including a second photoelectric conversion unit 411S having low sensitivity formed in a quadrilateral shape. In the case where the first photoelectric conversion unit 411L and the second photoelectric conversion unit 411S are not particularly distinguished, they are simply referred to as a photoelectric conversion unit 411.

[0361] The unit pixel 21 according to the third embodiment includes a semiconductor substrate 421 and a wiring layer 422 formed on the front side (lower side in the figure) thereof.

[0362] The semiconductor substrate 421 is composed of, for example, a silicon substrate using silicon (Si) as a semiconductor. The thickness of the semiconductor substrate 421 is appropriately set according to the expected wavelength region of the incident light. For example, if the expected wavelength region is only the visible light region, the thickness of the semiconductor substrate 421 is about 2 μm to 6 μm, and if the near-infrared region is also detected, the thickness is about 3 μm to 15 μm. Of course, the thickness of the semiconductor substrate 421 is not limited to this range.

[0363] The first photoelectric conversion unit 411L is formed in the region of the large pixel 400L in the semiconductor substrate 421, and the second photoelectric conversion unit 411S is formed in the region of the small pixel 410S. The semiconductor substrate 421 is composed of, for example, a P-type (first conductivity type) semiconductor region. The photoelectric conversion unit 411 is composed of a PN junction photodiode in which an N-type (second conductivity type) semiconductor region is formed in the region of the P-type semiconductor region in the semiconductor substrate 421. Near the interface of the front and back sides of the semiconductor substrate 421 is a P-type semiconductor region, which also serves as a hole charge accumulation region to suppress dark current.

[0364] In the semiconductor substrate 421, an element separation unit 441 that separates the photoelectric conversion unit (photoelectric conversion element) 411 is formed in a region between adjacent photoelectric conversion units 411. The element separation unit 441 is composed of an element separation unit 441S that separates the first photoelectric conversion unit 411L of the large pixel 410L and the second photoelectric conversion unit 411S of the small pixel 410S, and an element separation unit 441L that separates the first photoelectric conversion unit 411L of the large pixel 410L. In other words, the element separation unit 441 is composed of the element separation unit 441S around the second photoelectric conversion unit 411S of the small pixel 410S and the element separation unit 441L at the pixel boundary portion of the unit pixel 21 other than this. As will be described in detail later, in the unit pixel 21 of the first configuration example, the element separation unit 441S and the element separation unit 441L are configured to have different widths (thicknesses) in the planar direction.

[0365] The element separation unit 441 is formed by burying an insulating film such as a silicon oxide film (SiO2) in a groove penetrating the semiconductor substrate 421. The element separation unit 441 can be formed by burying a light shielding metal as in the first embodiment.

[0366] The wiring layer 422 includes a multilayer metal wiring 431 and an interlayer insulating film 432. The multilayer metal wiring 431 in the wiring layer 422 transmits an image signal generated by the unit pixel 21 and transmits a signal to be applied to the unit pixel 21. The metal wiring 431 can be composed of a metal such as Al or Cu, for example. The through hole connecting the upper and lower metal wirings 431 can be composed of a metal such as W or Cu, for example. For example, a silicon oxide film or the like can be used as the interlayer insulating film 432.

[0367] In addition, one or more pixel transistors Tr are formed at the interface between the semiconductor substrate 421 and the wiring layer 422. The pixel transistor Tr corresponds to Figure 6The bonding electrode 433 is formed on the surface of the wiring layer 422 on the opposite side of the semiconductor substrate 421 side, and is electrically connected to the bonding electrode of the logic substrate not shown by metal bonding such as Cu-Cu bonding. By establishing a connection with the logic substrate and vertically stacking various peripheral circuit functions, the chip size can be reduced.

[0368] In the drawings, an insulating film 451 composed of a silicon oxide film (SiO2) or the like is formed on the back side of the surface as the upper side of the semiconductor substrate 421. Note that the insulating film 451 may be formed on the fixed charge film as in the first embodiment. For the insulating film 451, similarly to the insulating film 182 in the first embodiment, SiO2 or a composite material containing SiO2 as a main component (such as SiON or SiOC) may be used.

[0369] The color filter 452 is formed on the upper side of the insulating film 451. For example, the color filter 452 of red (R), green (G), or blue (B) is arranged in a Bayer layout for each unit pixel 21, as shown in FIG. Figure 3 The low N wall 453 is formed above the element separation unit 441 in the same layer as the color filter 315. The low N wall 453 is composed of a material having a lower refractive index than the color filter 315. For example, a material similar to the low refractive index resin film 322 in the second embodiment can be used as the material of the low N wall 453.

[0370] Similar to the element separation unit 441, the low N wall 453 is composed of a low N wall 453S that separates the first photoelectric conversion unit 411L of the large pixel 410L and the second photoelectric conversion unit 411S of the small pixel 410S, and a low N wall 453L that separates the first photoelectric conversion unit 411L of the large pixel 410L. In other words, the low N wall 453 is composed of the low N wall 453S around the second photoelectric conversion unit 411S of the small pixel 410S and the low N wall 453L at the pixel boundary portion of the unit pixel 21 other than that. As will be described in detail later, in the unit pixel 21 according to the first configuration example, the low N wall 453S and the low N wall 453L are configured to have different widths (thicknesses) in the planar direction.

[0371] The on-chip lens 454 is formed above the color filter 452 and the low N wall 453. The on-chip lens 454 includes a large on-chip lens 454L and a small on-chip lens 454S. As the material of the on-chip lens 454, a material similar to that of the on-chip lens 187 in the first embodiment can be used. In addition, an anti-reflection film 455 is formed on the surface of the on-chip lens 454 using a material having a different refractive index from that of the on-chip lens 454.

[0372] Fig.33 A shows a plan view of the configuration of the first photoelectric conversion unit 411L and the second photoelectric conversion unit 411S in the unit pixel 21 and the configuration of the large on-chip lens 454L and the small on-chip lens 454S. Fig.33 The boundary of the unit pixel 21 of A is shown by a dotted line.

[0373] As Fig.33 shown in A, the first photoelectric conversion unit 411L with a large area of the photoelectric conversion region is formed in an L shape within the unit pixel 21, and the second photoelectric conversion unit 411S with a smaller area of the photoelectric conversion region than the first photoelectric conversion unit 411L is formed in a quadrilateral shape at the remaining corner within the unit pixel 21. Regarding the on-chip lens 454, two large on-chip lenses 454L and one small on-chip lens 454S are arranged above the first photoelectric conversion unit 411L, and one small on-chip lens 454S is arranged above the second photoelectric conversion unit 411S.

[0374] Here, when comparing the width WS1 in the planar direction of the element isolation unit 441S that is formed around the second photoelectric conversion unit 411S and separates the first photoelectric conversion unit 411L and the second photoelectric conversion unit 411S with the width WL1 in the planar direction of the element isolation unit 441L that separates the adjacent first photoelectric conversion units 411L, the width WS1 of the element isolation unit 441S is formed to be greater than the width WL1 of the element isolation unit 441L (WL1 < WS1). This enhances the suppression of crosstalk from the large pixel 410L to the small pixel 410S within the semiconductor substrate 421.

[0375] Fig.33 B shows a plan view of the color filter 452 and the low N wall 453. The boundary of the unit pixel 21 is also Fig.33 shown by a dotted line in B.

[0376] Similar to the element isolation unit 441, also regarding the low N wall 453, in the plan view, when comparing the width WS1' in the planar direction of the low N wall 453S that is formed around the second photoelectric conversion unit 411S and separates the first photoelectric conversion unit 411L and the second photoelectric conversion unit 411S with the width WL1' in the planar direction of the low N wall 453L that separates the adjacent first photoelectric conversion units 411L, the width WS1' of the low N wall 453S is formed to be greater than the width WL' of the low N wall 453L (WL1' < WS1'). This enhances the suppression of crosstalk from the large pixel 410L to the small pixel 410S on the incident surface side with respect to the semiconductor substrate 421.

[0377] The width WL1 of the element isolation unit 441L and the width WL1' of the low-N wall 453L can be the same (WL1 = WL1'), or they can be different from each other (WL1 < WL1' or WL1 > WL1'). The width WS1 of the element isolation unit 441S in the planar direction and the width WS1' of the low-N wall 453S can be the same (WS1 = WS1'), or they can be different from each other (WS1 < WS1' or WS1 > WS1').

[0378] In the solid-state imaging device 1 including the unit pixel 21 according to the third embodiment configured as described above, which is a back-illuminated solid-state imaging device, incident light is collected on the on-chip lens 410 formed on the back side of the semiconductor substrate 421 and is photoelectrically converted by the photoelectric conversion unit 411. The unit pixel 21 according to the third embodiment includes a large pixel 410L having a first photoelectric conversion unit 411L with a large area of the photoelectric conversion region and a small pixel 410S having a second photoelectric conversion unit 411S with a photoelectric conversion region smaller than that of the first photoelectric conversion unit 411L, and can perform high-sensitivity imaging using the large pixel 410R and low-sensitivity imaging using the small pixel 410L.

[0379] The unit pixel 21 according to the first configuration example of the third embodiment includes a first photoelectric conversion unit 411L and a second photoelectric conversion unit 411S having different areas of the photoelectric conversion region formed in the semiconductor substrate 421, an element isolation unit 441 that penetrates the semiconductor substrate 421 and separates the first photoelectric conversion unit 411L and the second photoelectric conversion unit 411S, a color filter 452 provided on the incident light side with respect to the semiconductor substrate 421, a low-N wall 453 formed in the same layer as the color filter 452 and having a refractive index lower than that of the color filter 452, and an on-chip lens 454 that collects the incident light on the photoelectric conversion unit 421.

[0380] The element isolation unit 441 is formed such that the width WS1 of the element isolation unit 441S formed around the second photoelectric conversion unit 411S is greater than the width WL1 of the element isolation unit 441L that separates the first photoelectric conversion unit 411L (WL1 < WS1), thereby enhancing the suppression of crosstalk from the large pixel 410L to the small pixel 410S within the semiconductor substrate 421.

[0381] Similarly, the low-N wall 453 is formed such that the width WS1' in the planar direction of the low-N wall 453S formed around the second photoelectric conversion unit 411S is greater than the width WL1' in the planar direction of the low-N wall 453L that separates the first photoelectric conversion unit 411L (WL1' < WS1'), thereby enhancing the suppression of crosstalk from the large pixel 410L to the small pixel 410S on the upper side of the semiconductor substrate 421.

[0382] Therefore, according to the unit pixel 21 of the first configuration example of the third embodiment, color mixing between unit pixels 21 can be suppressed, and the suppression of color mixing from the large pixel 410L to the small pixel 410S can be further enhanced. Therefore, color glare can be suppressed and the degradation of image quality of the small pixel 410S can be reduced.

[0383] Note that although the size (diameter) of the small on-chip lens 454S arranged above the first photoelectric conversion unit 411L and the small on-chip lens 454S arranged above the second photoelectric conversion unit 411S are the same in the first configuration example, Fig.34 As shown, the small on-chip lens 454S arranged above the second photoelectric conversion unit 411S can be changed to a small on-chip lens 454S' having a size larger or smaller than the small on-chip lens 454S arranged above the first photoelectric conversion unit 411L. By changing the size of the small on-chip lens 454S' above the second photoelectric conversion unit 411S, the sensitivity ratio between the large pixel 410L and the small pixel 410S can be adjusted.

[0384] <6.2 Second Configuration Example of the Third Implementation Method>

[0385] Fig.35 is a cross-sectional view showing a second configuration example of the unit pixel 21 according to the third embodiment of the present disclosure. Fig.35 A shows the Fig.36 The cross-sectional view of the line X-X' in Fig.35 B shows a cross-sectional view along line YY'. Fig.36 A and B are Fig.35 A plan view of a unit pixel 21 at a predetermined depth position.

[0386] exist Fig.35 and Fig.36 In, with Fig.32 and Fig.33 The corresponding parts in the first configuration example shown are denoted by the same reference numerals, and the description will focus on the parts different from the first configuration example.

[0387] In the unit pixel 21 according to the second configuration example, the element separation unit 441 is configured similarly to the first configuration example. Fig.36 As shown in FIG. 1A , the width WS1 of the element separation unit 441S around the second photoelectric conversion unit 411S is formed to be larger than the width WL1 (WL1 <WS1)。

[0388] On the other hand, although in the first configuration example, the low-N wall 453 is formed such that the width WS1' of the low-N wall 453S formed around the second photoelectric conversion unit 411S is greater than the width WL1' of the low-N wall 453L that separates the first photoelectric conversion unit 411L (WL1' < WS1'), in the second configuration example, as Fig.36 shown in B of, the low-N wall 453 is formed such that the width WS1' of the low-N wall 453S and the width WL1' of the low-N wall 453L are the same (WL1' = WS1').

[0389] In other words, in the second configuration example, as can be seen from the cross-sectional view of Fig.35 , only the element isolation unit 441S formed around the second photoelectric conversion unit 411S is formed thicker, and the element isolation unit 441L, the low-N wall 453L, and the low-N wall 453S are formed thinner than the element isolation unit 441S.

[0390] Therefore, the unit pixel 21 according to the second configuration example of the third embodiment can suppress color glare by enhancing the suppression of crosstalk from the large pixel 410L to the small pixel 410S in the semiconductor substrate 421, and reduce the deterioration of the image quality of the small pixel 410S.

[0391] <6.3 Third Configuration Example of the Third Embodiment>

[0392] Fig.37 is a cross-sectional view showing a third configuration example of the unit pixel 21 according to the third embodiment of the present disclosure. Fig.37 A of shows a cross-sectional view along the line X-X' in Fig.38 , and Fig.37 B of shows a cross-sectional view along the line Y-Y'. Fig.38 A and B of are Fig.37 plan views of the unit pixel 21 at a predetermined depth position in.

[0393] In Fig.37 and Fig.38 , the parts corresponding to those in the first configuration example shown in Fig.32 and Fig.33 are denoted by the same reference numerals, and the parts different from the first configuration example will be mainly described.

[0394] In the unit pixel 21 according to the third configuration example, the low-N wall 453 is configured similarly to the first configuration example. In other words, as Fig.38 shown in B of, the width WS1' of the low-N wall 453S formed around the second photoelectric conversion unit 411S is formed to be greater than the width WL1' of the low-N wall 453L that separates the first photoelectric conversion unit 411L (WL1' < WS1').

[0395] On the other hand, although in the first configuration example, the element isolation unit 441 is formed such that the width WS1 of the element isolation unit 441S around the second photoelectric conversion unit 411S is greater than the width WL1 of the element isolation unit 441L that separates the first photoelectric conversion unit 411L (WL1 < WS1), in the third configuration example, as Fig.38 shown in A of

[0396] , the width WS1 of the element isolation unit 441S and the width WL1 of the element isolation unit 441L are formed to be the same (WL1 = WS1). Fig.37 That is to say, in the third configuration example, as can be seen from the cross-sectional view of

[0397] , only the low-N wall 453S is formed thicker, and the element isolation unit 441L, the element isolation unit 441S, and the low-N wall 453L are formed thinner than the low-N wall 453S.

[0398] <6.4 Fourth Configuration Example of the Third Embodiment>

[0399] Fig.39 FIG. Fig.39 A of Fig.39 is a cross-sectional view taken along the line X-X' in B of Fig.39 , and B of Fig.39 is a plan view of the unit pixel 21 at a predetermined depth position in A of

[0400] In Fig.39 , the parts corresponding to those in the first configuration example shown in Fig.32 and Fig.33 are denoted by the same reference numerals, and the parts different from the first configuration example will be mainly described.

[0401] Fig.39 The fourth configuration example of Fig.32 and Fig.33 differs from the first configuration example shown in Figure 2 in that the first layout example shown in

[0402] is used as the layout of the unit pixel 21. Fig.32 and Fig.33 On the other hand, the widths of the element isolation unit 441 and the low-N wall 453 in the planar direction around the photoelectric conversion unit 411 are the same as those in the first configuration example shown in

[0403] Fig.39 B of FIG. shows a plan view of the photoelectric conversion unit 411 and the element isolation unit 441, and as shown in Fig.39 B of FIG., the element isolation unit 411 is formed such that the width WS1 of the element isolation unit 441S formed around the second photoelectric conversion unit 411S is greater than the width WL1 of the element isolation unit 441L that separates the first photoelectric conversion unit 411L (WL1 < WS1). This enhances the suppression of crosstalk from the large pixel 410L to the small pixel 410S in the semiconductor substrate 421.

[0404] Similarly, although not shown, the low N wall 453 is also formed such that the width WS1' of the low N wall 453S formed around the second photoelectric conversion unit 411S is greater than the width WL1' of the low N wall 453L that separates the first photoelectric conversion unit 411L (WL1' < WS1'). This enhances the suppression of crosstalk from the large pixel 410L to the small pixel 410S on the upper side of the semiconductor substrate 421.

[0405] Therefore, the unit pixel 21 according to the fourth configuration example of the third embodiment can suppress color mixing between unit pixels 21 and further enhance the suppression of color mixing from the large pixel 410L to the small pixel 410S. Therefore, color glare can be suppressed, and deterioration of the image quality of the small pixel 410S can be reduced.

[0406] <6.5 Fifth Configuration Example of the Third Embodiment>

[0407] Fig.40 FIG. shows a fifth configuration example of the unit pixel 21 according to the third embodiment of the present disclosure. Fig.40 A of FIG. is a cross-sectional view along the line X-X' in Fig.40 B of FIG., Fig.40 B of FIG. is Fig.40 a plan view of the unit pixel 21 at a predetermined depth position in A of FIG.

[0408] In Fig.40 , parts corresponding to the first to fourth configuration examples are denoted by the same reference numerals, and different parts will be mainly described.

[0409] Fig.40 The fifth configuration example in Fig.39 is the same as the third configuration example shown in Fig.32 and Fig.33 The difference from the first configuration example shown in Figure 2 is that the first layout example shown in

[0410] is used as the layout of the unit pixel 21. On the other hand, the widths of the element isolation unit 441 and the low N wall 453 in the planar direction around the photoelectric conversion unit 411 are the same as Fig.35 and Fig.36 has the same width as that in the second configuration example shown in

[0411] Fig.40 Figure B of Fig.40 shows a plan view of the photoelectric conversion unit 411 and the element separation unit 441, and as shown in Fig.40 Figure B of Fig.40 , the element separation unit 411 is formed such that the width WS1 of the element separation unit 441S formed around the second photoelectric conversion unit 411S is greater than the width WL1 of the element separation unit 441L that separates the first photoelectric conversion unit 411L (WL1 < WS1). This enhances the suppression of crosstalk from the large pixel 410L to the small pixel 410S in the semiconductor substrate 421.

[0412] Although not shown in the figure, the low N wall 453 is formed such that the width WS1' of the low N wall 453S formed around the second photoelectric conversion unit 411S and the width WL1' of the low N wall 453L that separates the first photoelectric conversion unit 411L are the same width (WL1' = WS1').

[0413] In other words, only the element separation unit 441S is formed thicker, and the element separation unit 441L, the low N wall 453L, and the low N wall 453S are formed thinner than the element separation unit 441S.

[0414] Therefore, the unit pixel 21 according to the fifth configuration example of the third embodiment can suppress color glare by enhancing the suppression of crosstalk from the large pixel 410L to the small pixel 410S in the semiconductor substrate 421, and reduce the deterioration of the image quality of the small pixel 410S.

[0415] <6.6 Sixth Configuration Example of the Third Embodiment>

[0416] Fig.41 is a diagram showing a sixth configuration example of the unit pixel 21 according to the third embodiment of the present disclosure. Fig.41 Figure A of Fig.41 is a cross-sectional view along the line X-X' in Fig.41 Figure B of Fig.41 , Fig.41 Figure B of Fig.41 is Fig.41 a plan view of the unit pixel 21 in Figure A of Fig.41 at a predetermined depth position.

[0417] In Fig.41 Fig.41 , parts corresponding to the first to fifth configuration examples are denoted by the same reference numerals, and different parts will be mainly described.

[0418] Fig.41 The sixth configuration example in Fig.41 is the same as the third configuration example shown in Fig.39 Fig.39 , and is different from the first configuration example shown in Fig.32 and Fig.33 Fig.33 in that Figure 2 The first layout example shown is used as the layout of the unit pixel 21 .

[0419] On the other hand, the width of the element separation unit 441 and the low N wall 453 in the plane direction around the photoelectric conversion unit 411 is equal to Fig.37 and Fig.38 The widths are the same in the third configuration example shown.

[0420] Fig.41 B shows a plan view of the color filter 452 and the low N wall 453, and as Fig.41 As shown in FIG. 1B, the low N wall 454 is formed so that the width WS1′ of the low N wall 453S formed around the second photoelectric conversion unit 411S is greater than the width WL1′ (WL1′) of the low N wall 453L separating the first photoelectric conversion unit 411L. <WS1’)。

[0421] Although illustration is omitted, the element separation unit 441 is formed so that a width WS1 of the element separation unit 441S around the second photoelectric conversion unit 411S and a width WL1 of the element separation unit 441L separating the first photoelectric conversion unit 411L are the same width ( WL1 = WS1 ).

[0422] In other words, only the low N wall 453S is formed thicker, and the element separation unit 441L, the element separation unit 441S, and the low N wall 453L are formed thinner than the low N wall 453S.

[0423] Therefore, according to the unit pixel 21 of the sixth configuration example of the third embodiment, color glare can be suppressed and degradation of image quality of the small pixel 410S can be reduced by enhancing suppression of crosstalk from the large pixel 410L to the small pixel 410S on the upper side of the semiconductor substrate 421.

[0424] <6.7 Seventh Configuration Example of the Third Implementation Method>

[0425] Fig.42 is a diagram showing a seventh configuration example of the unit pixel 21 according to the third embodiment of the present disclosure. Fig.42 The A is along Fig.42 The cross-sectional view of line XX' in C, Fig.42 B is along Fig.42 The cross-sectional view of the line Y-Y' in C, Fig.43 C is Fig.42 A and B are plan views of the unit pixel 21 at a predetermined depth position.

[0426] exist Fig.42 In, with Fig.32 and Fig.33In the corresponding part of the first configuration example shown, the same reference numerals are used, and different parts will be mainly described.

[0427] In Fig.32 and Fig.33 In the first configuration example shown, both the element isolation unit 441 and the low-N wall 453 are configured such that the width around the entire second photoelectric conversion unit 411S of the small pixel 410S is greater than the width of the pixel boundary portion of the unit pixel 21 other than this.

[0428] In contrast, in the seventh configuration example, as shown in C of Fig.42 only the boundary portion that separates the first photoelectric conversion unit 411L and the second photoelectric conversion unit 411S in the region closer to the inside than the pixel boundary between the unit pixels 21 has a larger width, rather than all the widths around the second photoelectric conversion unit 411S.

[0429] More specifically, the width WS2 of the element isolation unit 441S' at the boundary portion that separates the first photoelectric conversion unit 411L and the second photoelectric conversion unit 411S is formed to be greater than the width WL1 of the element isolation unit 441L at the pixel boundary portion of the unit pixel 21 (WS2 > WL1). This enhances the suppression of crosstalk from the large pixel 410L to the small pixel 410S in the semiconductor substrate 421.

[0430] Similarly, the low-N wall 453 is also formed such that at the boundary portion that separates the first photoelectric conversion unit 411L and the second photoelectric conversion unit 411S, the width WS2' of the low-N wall 453S' is greater than the width WL1' above the element isolation unit 441L at the pixel boundary portion of the unit pixel 21 (WL1' < WS2'). This enhances the suppression of crosstalk from the large pixel 410L to the small pixel 410S on the incident surface side with respect to the semiconductor substrate 421.

[0431] In this way, the width of at least a part rather than the entire periphery around the second photoelectric conversion unit 411S of the small pixel 410S can be formed to be greater than other parts. Other configurations of the seventh configuration example are the same as those of Fig.32 and Fig.33 the first configuration example shown.

[0432] Therefore, for the unit pixel 21 of the seventh configuration example of the third embodiment, color mixing between the unit pixels 21 can be suppressed, and further suppression of color mixing from the large pixel 410L to the small pixel 410S can be enhanced. Therefore, color glare can be suppressed, and deterioration of the image quality of the small pixel 410S can be reduced.

[0433] <6.8 Eighth Configuration Example of the Third Embodiment>

[0434] Fig.43 is a cross-sectional view showing an eighth configuration example of the unit pixel 21 according to the third embodiment of the present disclosure, and shows Fig.33 A cross-sectional view of the portion corresponding to line XX'.

[0435] In the above-mentioned first to seventh configuration examples, examples have been described in which the element separation unit 441 of the separation photoelectric conversion unit 411 and the low N wall 453 of the separation filter 452 are formed so that the width of at least a portion of the periphery of the second photoelectric conversion unit 411S of the small pixel 410S is greater than the other widths.

[0436] Incidentally, there is a case where, in addition to the element separation unit 441 and the low N wall 453 , for example, a separation unit for separating unit pixels or separating large and small pixels may be provided in the on-chip lens 454 and the wiring layer 422 .

[0437] For example, by adding a lens separation unit 471 for separating the on-chip lens 454 and a wiring layer separation unit 481 for separating a part of the wiring layer 422 to Fig.32 In the structure of the unit pixel 21 shown in A, the structure is constructed according to Fig.43 The unit pixel 21 of the eighth configuration example shown. Such a lens separation unit 471 and a wiring layer separation unit 481 may also adopt a configuration in which the width of at least a portion of the periphery of the second photoelectric conversion unit 411S of the small pixel 410S is formed to be larger than the other widths, similar to the configuration of the element separation unit 441 or the low N wall 453 in any one of the first to seventh configuration examples described above. For the lens separation unit 471, a light-transmitting material different from the on-chip lens 454 and having a lower refractive index than the on-chip lens 454 may be used. As a material for the wiring layer separation unit 481, for example, a material having a lower refractive index than the silicon oxide film (SiO2) as the material of the interlayer insulating film 432 or a material similar to the material of the metal wiring 431 such as Al, Cu, or W may be used.

[0438] exist Fig.43 In the eighth configuration example shown in FIG. 1 , the configuration other than the lens separation unit 471 and the wiring layer separation unit 481 is the same as that of FIG. Fig.32 The configuration in the first configuration example shown is similar, so the description thereof will be omitted.

[0439] Similarly, in the unit pixel 21 of the eighth configuration example of the third embodiment described above, color mixing between the unit pixels 21 can be suppressed, and the suppression of color mixing from the large pixel 410L to the small pixel 410S can be further enhanced. Therefore, color glare can be suppressed, and the degradation of the image quality of the small pixel 410S can be reduced.

[0440] <6.9 Summary of the Third Implementation Plan>

[0441] The unit pixel 21 according to the third embodiment includes a first photoelectric conversion unit 411L and a second photoelectric conversion unit 411S having different areas of photoelectric conversion regions formed in a semiconductor substrate 421, an element separation unit 441 that penetrates the semiconductor substrate 421 and separates the first photoelectric conversion unit 411L and the second photoelectric conversion unit 411S, a color filter 452 that is provided on the incident light side relative to the semiconductor substrate 421, a low N wall 453 that is formed in the same layer as the color filter 452 and has a refractive index lower than that of the color filter 452, and an on-chip lens 454 that collects incident light on the photoelectric conversion unit 411.

[0442] According to the unit pixel 21 of the third embodiment, by providing the low N wall 453 in the same layer as the color filter 452, high-angle incident light or stray light that is to pass between the unit pixels 21 or between the large pixel 410L and the small pixel 410S can be reflected, and color mixing between the unit pixels 21 can be suppressed. Therefore, color glare can be suppressed.

[0443] Furthermore, according to the unit pixel 21 in the third embodiment, at least one of the element separation unit 441 separating the photoelectric conversion unit 411, the low N wall 453 separating the color filter 452, the lens separation unit 471 separating the on-chip lens 454, and the wiring layer separation unit 481 separating a portion of the wiring layer 422 is constructed so that the width of the first boundary portion as the boundary between the first photoelectric conversion unit 411L of the large pixel 410L and the second photoelectric conversion unit 411S of the small pixel 410S is different from the width of the second boundary portion as the boundary between the first photoelectric conversion unit 411L of the large pixel 410L and the first photoelectric conversion unit 411L of the other large pixel 410L. In this way, the suppression of color mixing from the large pixel 410L to the small pixel 410S can be further enhanced, and color glare can be suppressed. The degradation of the image quality of the small pixel 410S can be reduced.

[0444] <7. Fourth Implementation Method of Unit Pixel>

[0445] <7.1 Configuration Example of the Fourth Implementation Method>

[0446] Fig.44 is a cross-sectional view of a unit pixel 21 according to a fourth embodiment of the present disclosure.

[0447] In a fourth embodiment, using Figure 2 The first layout example shown is the layout of the unit pixel 21. Fig.44 Corresponds to Figure 2Although different reference numerals are applied in the fourth embodiment from those in the first to third embodiments described above, portions corresponding to those in the first to third embodiments will be briefly described.

[0448] The unit pixel 21 according to the fourth embodiment includes a large pixel 500L having a first photoelectric conversion unit 511L with high sensitivity and a small pixel 500S having a second photoelectric conversion unit 511 with low sensitivity. The first photoelectric conversion unit 511L and the second photoelectric conversion unit 511S have photoelectric conversion regions of different areas formed in the semiconductor substrate 501, and the second photoelectric conversion unit 511S is formed of a photoelectric conversion region having a smaller area than the first photoelectric conversion unit 511L. The semiconductor substrate 421 is composed of, for example, a silicon substrate using silicon (Si) as a semiconductor, and corresponds to the semiconductor substrate 121 in the first embodiment. Although the pixel transistor Tr ( Figure 7 ) etc. are formed on the front side of the semiconductor substrate 501 which is the lower side in the figure, but are omitted from the illustration.

[0449] In the drawings, an insulating film 513 composed of a silicon oxide film (SiO2) or the like is formed on the back side of the surface as the upper side of the semiconductor substrate 501. Note that the insulating film 513 may be formed on the fixed charge film as in the first embodiment. For the insulating film 513, similarly to the insulating film 182 in the first embodiment, SiO2 or a composite material containing SiO2 as a main component (such as SiON or SiOC) may be used.

[0450] The color filter 514 is formed on the upper side of the insulating film 513. For example, the color filter 514 of red (R), green (G), or blue (B) is arranged in a Bayer layout for each unit pixel 21, as shown in FIG. Figure 2 B. The inter-pixel light shielding film 515 is formed above the element separation unit 512 in the same layer as the color filter 514. The inter-pixel light shielding film 515 can be formed using a material similar to that of the inter-pixel light shielding film 183 in the first embodiment.

[0451] The on-chip lens 516 is formed above the color filter 514 and the inter-pixel light shielding film 515. The on-chip lens 516 includes a large on-chip lens 516L formed in the large pixel 500L and a small on-chip lens 516S formed in the small pixel 500S. In the case where the large on-chip lens 516L and the small on-chip lens 516S are not distinguished, they are simply referred to as the on-chip lens 516. As a material for the on-chip lens 516, for example, an organic resin material such as a styrene-based resin including a styrene thermosetting resin (STSR), an acrylic resin, a styrene acrylic resin, or a siloxane-based resin can be used. In addition, as a material for the on-chip lens 516, a material having a higher refractive index than the color filter 514 of the lower layer, such as SiN or SiON, can be used. The refractive index of STSR is about 1.4 to 1.6, and the refractive index of SiN is equal to or greater than 1.9. The material of the on-chip lens 187 illustrated as an example in the above-mentioned first embodiment can be used as the material of the on-chip lens 516. An anti-reflection film 517 is formed on the surface of the on-chip lens 516 using a material having a different refractive index from that of the on-chip lens 516. A silicon oxide film such as a low temperature oxide (LTO) film can be used as the material of the anti-reflection film 517. The refractive index of the LTO film is about 1.45.

[0452] like Fig.44 As shown, the on-chip lens 516 has a quadrilateral shape in a plan view, and is formed in a rectangular parallelepiped shape in which a plane parallel to the substrate surface of the semiconductor substrate 501 serves as an upper surface and a plane perpendicular to the upper surface serves as a side wall surface.

[0453] Will refer to Figure 45 to Figure 47 The effect of the on-chip lens 516 formed in a rectangular parallelepiped shape will be described.

[0454] like Fig.45 As shown, glare occurs due to high-angle incident light in the hemispherical on-chip lens 521 (large on-chip lens 521L and small on-chip lens 521S) or light reflected again from the sealing glass or the like arranged above the on-chip lens 523. In particular, in a unit pixel in which a large pixel and a small pixel are arranged, as shown by an arrow 531, color glare occurs due to light passing through the boundary portion between the large on-chip lens 521L and the small on-chip lens 521S.

[0455] By reducing the height of the large on-chip lens 521L and the small on-chip lens 521S, the thickness of the recess at the boundary between the large on-chip lens 521L and the small on-chip lens 521S, which is the thinnest part of the on-chip lens 521, can be minimized to reduce the amount of light passing through the boundary between the large on-chip lens 521L and the small on-chip lens 521S and reduce color mixing.

[0456] However, in the case where the on-chip lens 521 is hemispherical, vignetting occurs at a portion of the inter-pixel light shielding film 522 surrounded by a dotted circle, and light reception sensitivity deteriorates.

[0457] As in the present embodiment, by adopting a rectangular parallelepiped shape as the shape of the on-chip lens 516 and obtaining a rectangular lens with a shorter focal length, vignetting due to the inter-pixel light shielding film 515 can be reduced and degradation of light reception sensitivity can be prevented.

[0458] In addition, if Fig.46 As shown, when the shape of the on-chip lens is hemispherical, the thickness LD1 between the recessed bottom of the on-chip lens and the substrate is thicker than the thickness LD2 of the thinnest part of the lens layer (LD1>LD2) to ensure a manufacturing margin.

[0459] On the contrary, when the shape of the on-chip lens is a quadrilateral, the processing can be controlled with high precision so that the thickness LD1 between the recessed bottom of the on-chip lens and the substrate is formed to be the same as or close to the thickness LD2 of the thinnest part of the lens layer (LD1=LD2). In this way, the height of the on-chip lens 516 can be reduced compared to the hemispherical shape.

[0460] In addition, if Fig.47 As shown in FIG. 1 , even when the on-chip lens shape is hemispherical, it is difficult to control the widths RD1 and RD2 of the on-chip lens in the plane direction, and the variation in the sensitivity ratio between large pixels and small pixels increases. When the on-chip lens shape is quadrilateral, control is easy, so the variation in the sensitivity ratio between large pixels and small pixels can be suppressed.

[0461] <7.2 Modifications>

[0462] Fig.48 and Fig.49 is a cross-sectional view showing a unit pixel 21 according to a modification of the fourth embodiment.

[0463] Although as Fig.44 In the basic structure of the fourth embodiment shown in FIG. 1 , an example has been described in which each shape of the large-chip lens 516L and the small-chip lens 516S is a rectangular parallelepiped shape having a quadrilateral in a plan view, but the shape is not limited to the rectangular parallelepiped shape. Fig.48 A~C or Fig.49 The shapes shown in A and B.

[0464] Fig.48 A shows an example in which each shape of the large on-chip lens 516L and the small on-chip lens 516S is a truncated quadrangular pyramid having a quadrilateral in a plan view, and a side wall thereof is inclined toward the center side.

[0465] exist Fig.48 B shows an example in which each shape of the large-chip on-lens 516L and the small-chip on-lens 516S is a rectangular parallelepiped shape having a quadrilateral in a plan view, and is a chamfered shape obtained by obliquely cutting a corner between an upper surface and a side wall surface.

[0466] exist Fig.48 C shows an example in which each shape of the large on-chip lens 516L and the small on-chip lens 516S is a quadrangular pyramid shape having a quadrilateral in a plan view.

[0467] Fig.49 A shows an example in which the shape of the large on-chip lens 516L is a rectangular parallelepiped shape and the shape of the small on-chip lens 516S is a hemispherical shape.

[0468] Fig.49 B shows an example in which the shape of the lens 516L on the large chip is a hemispherical shape and the shape of the lens 516S on the small chip is a rectangular parallelepiped shape.

[0469] Fig.49 A and B are examples in which the shape of any one of the lens 516L on the large chip and the lens 516S on the small chip is a hemispherical shape, and the other is a rectangular parallelepiped shape, and the combination may be a truncated quadrangular pyramid shape other than the rectangular parallelepiped shape or a combination between a quadrangular pyramid shape and a hemispherical shape. In addition, the combination may not be a combination with a hemispherical shape, and the shapes of the lens 516L on the large chip and the lens 516S on the small chip may be any combination of a rectangular parallelepiped shape, a truncated quadrangular pyramid shape, and a quadrangular pyramid shape.

[0470] In addition, the shapes of the large-chip lens 516L and the small-chip lens 516 are not limited to prisms, truncated pyramids, or pyramids having quadrilateral shapes in a plan view, but may also be prisms, truncated pyramids, or pyramids having polygonal shapes other than quadrilateral shapes. Fig.48 B shows a prism or a truncated pyramid having a polygon other than a quadrilateral obtained by obliquely cutting the upper corners.

[0471] The shape of at least one of the large lens 516L and the small lens 516S may be a lens shape having at least two plane areas. In other words, in the case where at least one of the large lens 516L and the small lens 516S adopts a shape in which the corners between the faces are not rounded, the lens shape only needs to have one or more vertices, and the vertex may include roundness caused by the processing accuracy.

[0472] <7.3 Summary of the Fourth Implementation Plan>

[0473] The unit pixel 21 according to the fourth embodiment includes a first photoelectric conversion unit 511L and a second photoelectric conversion unit 511S having different areas of photoelectric conversion regions formed in a semiconductor substrate 501, an element separation unit 512 that penetrates the semiconductor substrate 501 and separates the first photoelectric conversion unit 501L and the second photoelectric conversion unit 501S, a color filter 514 that is arranged on the incident light side relative to the semiconductor substrate 501, an inter-pixel shading film 515 formed in the same layer as the color filter 514, and an on-chip lens 516 that collects incident light on the photoelectric conversion unit 513.

[0474] At least one of the large on-chip lens 516L and the small on-chip lens 516S in the unit pixel 21 according to the fourth embodiment has a lens shape including at least two plane areas. In this way, light leakage from the large pixel 410L to the small pixel 410S can be suppressed, and color glare can be suppressed.

[0475] The on-chip lens 516 according to the fourth embodiment can be mounted as the on-chip lens in the above-described first to third embodiments.

[0476] <8. Fifth Implementation Method of Unit Pixel>

[0477] Next, a configuration example of the unit pixel 21 according to a fifth embodiment of the present disclosure will be described.

[0478] In the fifth embodiment, a Fresnel type on-chip lens is adopted as the lens shape of the on-chip lens.

[0479] Fig.50 It is a cross-sectional view of a hemispherical on-chip lens (hereinafter also referred to as a hemispherical lens) and a Fresnel-type on-chip lens.

[0480] The thickness of the on-chip lens as a hemispherical lens is different for large pixels and small pixels whose photoelectric conversion regions have different areas, and the thickness of the on-chip lens of the large pixel is thicker than that of the on-chip lens of the small pixel. In this way, the amount of sensitivity reduction of the small pixel is greater when light is incident obliquely than when light is incident vertically on the lens. In other words, due to the change in sensitivity ratio, the amount of reduction in SN ratio and the dynamic range at the signal connection position from the large pixel as a high-sensitivity pixel to the small pixel as a low-sensitivity pixel changes with the F value of the lens.

[0481] The Fresnel lens is a lens that is concentrically divided into a plurality of regions in a plan view, and each of the divided regions has a sawtooth shape in a cross-sectional view. Fig.50In the example, the number of divisions of the concentric circle area of ​​the lens on the large chip is four, and the number of divisions of the concentric circle area of ​​the lens on the small chip is two. The curved surfaces of the multiple divided concentric circle areas are different from each other. By dividing the Fresnel lens concentrically into multiple areas (e.g., concentric circle areas) in a plan view and forming it into a sawtooth shape in a cross-sectional view, the Fresnel lens can be formed to have a thinner thickness compared to the hemispherical on-chip lens, and its thickness can be the same or approximately the same in the center and periphery of the lens. In this way, the difference in sensitivity characteristics with respect to the light incident angle between high-sensitivity pixels and low-sensitivity pixels is reduced, the sensitivity ratio is kept constant regardless of how the F value of the lens changes, and the reduction in the SN ratio at the signal connection position and the change in the dynamic range can be suppressed. In addition, since the on-chip lens can be formed thin, the glare of the small pixel caused by light leakage from the large pixel to the small pixel can be suppressed. In addition, compared with the hemispherical lens, the material used can also be reduced.

[0482] <8.1 First Configuration Example of Fifth Implementation Method>

[0483] Fig.51 A is a cross-sectional view showing a first configuration example of a unit pixel 21 according to a fifth embodiment of the present disclosure, and shows a cross-sectional view taken along Fig.51 A cross-sectional view along line XX' in FIG. Fig.51 B is a plan view of the unit pixel 21 according to the second configuration example of the fifth embodiment.

[0484] In the first configuration example of the fifth embodiment, Figure 2 The first layout example is shown as the layout of the unit pixel 21. Although different reference numerals from those in the above-described first to fourth embodiments are applied in the fifth embodiment, portions corresponding to those in the first to fourth embodiments will be briefly described.

[0485] The unit pixel 21 according to the first configuration example includes a large pixel 600L having a first photoelectric conversion unit 611L with high sensitivity and a small pixel 600S having a second photoelectric conversion unit 611S with low sensitivity. The first photoelectric conversion unit 611L and the second photoelectric conversion unit 611S have photoelectric conversion regions of different areas formed in the semiconductor substrate 601, and the second photoelectric conversion unit 611S is formed of a photoelectric conversion region having a smaller area than the first photoelectric conversion unit 6110L. In the case where the first photoelectric conversion unit 611L and the second photoelectric conversion unit 611S are not particularly distinguished, they are simply referred to as the photoelectric conversion unit 611.

[0486] The semiconductor substrate 601 is composed of, for example, a silicon substrate using silicon (Si) as a semiconductor, and is composed of, for example, a P-type (first conductivity type) semiconductor region. The photoelectric conversion unit 611 is composed of a PN junction photodiode, in which an N-type (second conductivity type) semiconductor region is formed in the P-type semiconductor region of the semiconductor substrate 601. Near the interface between the front and back sides of the semiconductor substrate 601 is a P-type semiconductor region, which also serves as a hole charge accumulation region to suppress dark current. Although the pixel transistor Tr ( Figure 7 ) etc. are formed on the front side of the semiconductor substrate 601 which is the lower side in the figure, but are omitted from the illustration.

[0487] In the semiconductor substrate 601, an element separation unit 612 for separating the photoelectric conversion unit 611 (photoelectric conversion element) is formed in a region between the first photoelectric conversion unit 611L and the second photoelectric conversion unit 611S. The element separation unit 612 is formed by burying the fixed charge film 631 and the insulating film 632 inside a groove formed by digging it to a predetermined depth from the back side of the semiconductor substrate 601. The effect of the element separation unit 612 is similar to that of the element separation unit 141 ( Figure 7 )similar.

[0488] The color filter 634 is formed on the upper side of the insulating film 632 above the semiconductor substrate 601. The color filter 634 is formed in a similar manner to Figure 2 The inter-pixel light shielding film 633 is configured in the layout configuration of B, that is, red (R), green (G) or blue (B) is configured in a Bayer layout for each unit pixel 21. The inter-pixel light shielding film 633 is buried in the color filter 634 in the same layer as the color filter 634 and is located above the element separation unit 612. The inter-pixel light shielding film 633 can be formed using a material similar to that of the inter-pixel light shielding film 183 in the first embodiment.

[0489] A large on-chip lens 635L and a small on-chip lens 635S are formed on the color filter 634. The large on-chip lens 635L is a Fresnel type on-chip lens formed in the large pixel 600L, and the small on-chip lens 635S is a Fresnel type on-chip lens formed in the small pixel 500S. In the case where the large on-chip lens 635L and the small on-chip lens 635S are not distinguished, they are simply referred to as on-chip lenses 635. For example, the on-chip lens 635 can be formed using a material similar to the on-chip lens 187 in the first embodiment.

[0490] The anti-reflection film can be formed on the surface of the large on-chip lens 635L and the small on-chip lens 635S using the same material as the anti-reflection film 188 in the first embodiment.

[0491] Fig.51FIG. B shows the layout of the large on-chip lens 635L, the small on-chip lens 635S, and the color filter 634. Fig.51 In B, after the reference numerals of the large on-chip lens 635L and the small on-chip lens 635S, hyphens and “R,” “Gr,” “Gb,” and “B” corresponding to the colors of the color filter 634 are applied.

[0492] Each lens 635L on a large chip has an octagonal planar shape and is divided into four areas in a concentric circle shape. Each lens 635S on a small chip has a quadrilateral planar shape and is divided into two areas with concentric quadrilaterals. Considering the influence of diffraction, the actual number of divisions of the Fresnel lens is optimized.

[0493] As described above, the solid-state imaging device 1 including the unit pixel 21 according to the fifth embodiment is a back-illuminated solid-state imaging device in which incident light is collected by the on-chip lens 635 formed on the back side of the semiconductor substrate 601 and then photoelectrically converted by the photoelectric conversion unit 611. The unit pixel 21 according to the fifth embodiment includes the large pixel 600L having the first photoelectric conversion unit 611L having a large area of ​​the photoelectric conversion region and the small pixel 600S having the second photoelectric conversion unit 611S having a smaller photoelectric conversion region than the first photoelectric conversion unit 611L, and is capable of high-sensitivity imaging using the large pixel 600L and low-sensitivity imaging using the small pixel 600S.

[0494] The unit pixel 21 according to the first configuration example of the fifth embodiment includes a first photoelectric conversion unit 611L and a second photoelectric conversion unit 611S having photoelectric conversion regions of different areas formed in a semiconductor substrate 601, an element separation unit 612 separating the first photoelectric conversion unit 611L and the second photoelectric conversion unit 611S, a color filter 634 provided on the incident light side relative to the semiconductor substrate 601, and an on-chip lens 635 collecting incident light on the photoelectric conversion unit 611.

[0495] According to the unit pixel 21 of the first configuration example, the large on-chip lens 635L and the small on-chip lens 635S are formed by a Fresnel type on-chip lens. In this way, the lens thickness of the large on-chip lens 635L in the large pixel 600L and the small on-chip lens 635S in the small pixel 600S can be the same or approximately the same, and the difference in oblique incidence characteristics due to the difference in lens thickness can be eliminated. In addition, oblique incidence caused by light reflected again from a sealing glass or the like disposed on the upper side of the on-chip lens 635 and incident at a high angle can be reduced to suppress glare and reduce color mixing.

[0496] <8.2 Second Configuration Example of the Fifth Implementation Method>

[0497] Fig.52A is a cross-sectional view showing a second configuration example of the unit pixel 21 according to the fifth embodiment of the present disclosure, and shows a cross-sectional view along Fig.52 A cross-sectional view along line XX' in FIG. Fig.52 B is a plan view of the unit pixel 21 according to the second configuration example of the fifth embodiment.

[0498] In the second configuration example of the fifth embodiment, Figure 3 The second layout example shown is used as the layout of the unit pixel 21. As the layout of the on-chip lens, a layout in which on-chip lenses of different sizes are arranged is adopted. Figure 4 The layout of B. Fig.52 In the second example of the construction, Fig.51 The corresponding parts in the first configuration example shown are denoted by the same reference numerals, and the description will focus on the parts different from the first configuration example.

[0499] exist Fig.52 In the second configuration example, an element separation unit 612' is formed instead of the element separation unit 612 in the first configuration example. Although the element separation unit 612 in the first configuration example has a groove structure obtained by digging it from the back side of the semiconductor substrate 601 to a predetermined depth and not penetrating the semiconductor substrate 601, the element separation unit 612' in the second configuration example penetrates and completely separates the semiconductor substrate 601. The element separation unit 612' is formed by burying an insulating film such as a silicon oxide (SiO2) film in the groove penetrating the semiconductor substrate 601.

[0500] A large on-chip lens 635L' and a small on-chip lens 635S' are formed on the color filter 634. Similar to the first configuration example, the large on-chip lens 635L' and the small on-chip lens 635S' are Fresnel type on-chip lenses.

[0501] Fig.52 FIG. B shows the layout of the large on-chip lens 635L′, the small on-chip lens 635S′, and the color filter 634. Fig.52 In FIG. 1B, after the reference numerals of the large on-chip lens 635L′ and the small on-chip lens 635S′, hyphens and “R,” “Gr,” “Gb,” and “B” corresponding to the colors of the color filter 634 are applied.

[0502] In the second configuration example, Figure 3 The second layout example is shown as the layout of the unit pixel 21 , so that the first photoelectric conversion unit 611L formed in an L shape and the second photoelectric conversion unit 611S formed in a quadrilateral are arranged in the unit pixel 21 of a quadrilateral surrounded by the element separation unit 612 ′.

[0503] like Fig.52As shown in FIG. 1B , the large on-chip lenses 635L′ and the small on-chip lenses 635S′ are respectively aligned in diagonal directions, and the small on-chip lenses 635S′ and the large on-chip lenses 635L′ are alternately arranged in the column direction and the row direction. The small on-chip lenses 635S′ are arranged on the second photoelectric conversion unit 611S′.

[0504] Each large on-chip lens 635L' has a circular planar shape and is concentrically divided into three regions. Each small on-chip lens 635S' has a circular planar shape and is concentrically divided into two regions. Considering the influence of diffraction, the actual number of divisions of the Fresnel lens is optimized.

[0505] According to the unit pixel 21 of the second configuration example, the large on-chip lens 635L' and the small on-chip lens 635S' are formed by a Fresnel type on-chip lens. In this way, the lens thickness of the large on-chip lens 635L' in the large pixel 600L and the small on-chip lens 635S' in the small pixel 600S can be the same or approximately the same, and the difference in oblique incidence characteristics caused by the difference in lens thickness can be eliminated. In addition, oblique incidence caused by light reflected again from a sealing glass or the like disposed on the upper side of the on-chip lens 635' and incident at a high angle can be reduced to suppress glare and reduce color mixing.

[0506] <8.3 Third Configuration Example of the Fifth Implementation Method>

[0507] Fig.53 A is a cross-sectional view showing a third configuration example of the unit pixel 21 according to the fifth embodiment of the present disclosure, and shows a cross-sectional view along Fig.53 A cross-sectional view along line XX' in FIG. Fig.53 B is a top view of the unit pixel 21 according to the third configuration example of the fifth embodiment.

[0508] In the third configuration example of the fifth embodiment, Figure 2 The first layout example shown is the layout of the unit pixel 21. Fig.53 In the third example of the configuration, Fig.51 The corresponding parts in the first configuration example shown are denoted by the same reference numerals, and the description will focus on the parts different from the first configuration example.

[0509] The unit pixel 21 according to the third configuration example is different from the above-mentioned first configuration example in that the number of divisions of the concentric circular areas of the large on-chip lens 635L and the small on-chip lens 635S formed on the color filter 634 is different depending on the color of the color filter 634 (i.e., the wavelength of incident light allowed to pass through by the color filter 634).

[0510] Specifically, Fig.53As shown in the plan view of B, the number of area divisions in the large on-chip lens 635L-R on the red filter 634 is two, and the number of area divisions in the small on-chip lens 635S-R is zero (no division), that is, it is a hemispherical lens. The number of area divisions in each of the large on-chip lenses 635L-Gb and 635L-Gr on the green filter 634 is three, and the number of area divisions in each of the small on-chip lenses 635S-Gb and 635S-Gr is two. The number of divisions in the large on-chip lens 635L-B on the blue filter 634 is four, and the number of divisions in the small on-chip lens 635S-B is two.

[0511] In comparison between the large on-chip lenses 635L, the number of area divisions in the large on-chip lenses 635L-R on the red color filter 634 is two, the number of area divisions in each of the large on-chip lenses 635L-Gb and 635L-GR on the green color filter 634 is three, and the number of area divisions in the large on-chip lens 635L-B on the blue color filter 634 is four. In comparison between the small on-chip lenses 635S, the number of area divisions in the red small on-chip lens 635S-R is zero (no division), that is, it is a hemispherical lens, the number of area divisions in each of the green small on-chip lenses 635S-Gb and 635S-Gr, and the number of area divisions in the blue small on-chip lens 635S-B are both two.

[0512] According to the unit pixel 21 of the third configuration example, the large on-chip lens 635L and the small on-chip lens 635S are formed by a Fresnel type on-chip lens. In this way, the difference in oblique incidence characteristics caused by the difference in lens thickness between the large on-chip lens 635L in the large pixel 600L and the small on-chip lens 635S in the small pixel 600S can be eliminated. In addition, oblique incidence caused by light reflected again from a sealing glass or the like disposed on the upper side than the on-chip lens 635 and incident at a high angle can be reduced to suppress glare and reduce color mixing.

[0513] Furthermore, by changing the number of region divisions in the large on-chip lens 635L and the small on-chip lens 635S according to the color of the color filter 634 (i.e., the wavelength of incident light that the color filter 634 allows to pass through), the sensitivity characteristics can be optimized for each transmission wavelength and the light receiving sensitivity can be improved. Figure 2 The first layout example in FIG. 1 is used as an example of the layout of the unit pixel 21, but even if the second configuration example is adopted Figure 3 In the case of the second layout example in FIG. 6 , it is also possible to change the number of region divisions according to the wavelength of incident light that the color filter 634 allows to pass.

[0514] <8.4 Fourth Configuration Example of the Fifth Implementation Method>

[0515] Fig.54A is a cross-sectional view showing a fourth configuration example of the unit pixel 21 according to the fifth embodiment of the present disclosure, and shows a cross-sectional view along Fig.54 A cross-sectional view along line XX' in FIG. Fig.54 B is a top view of the unit pixel 21 according to the fourth configuration example of the fifth embodiment.

[0516] In the fourth configuration example of the fifth embodiment, Figure 2 The first layout example shown is the layout of the unit pixel 21. Fig.54 In the fourth example of the structure, Fig.51 The corresponding parts in the first configuration example shown are denoted by the same reference numerals, and the description will focus on the parts different from the first configuration example.

[0517] exist Fig.51 In the first configuration example shown, the large on-chip lens 635L in the large pixel 600L and the small on-chip lens 635S in the small pixel 600S are both configured by Fresnel-type on-chip lenses.

[0518] In contrast, the unit pixel 21 according to the fourth configuration example is different from the above-described first configuration example in that only the large on-chip lens 635L in the large pixel 600L is constituted by a Fresnel lens, and the small on-chip lens 635S in the small pixel 600S is constituted by a hemispherical lens.

[0519] like Fig.54 As shown in the plan view of B, each large on-chip lens 635L-R, 635L-Gb, 635L-Gr, and 635L-B is composed of a Fresnel lens with a region division number of three, and each small on-chip lens 635S-R, 635S-Gb, 635S-Gr, and 635S-B is composed of a hemispherical lens. The small on-chip lens 635S has a small planar size, and even in the case of a hemispherical lens, the lens height can be kept low, so a hemispherical lens can be used.

[0520] According to the unit pixel 21 of the fourth configuration example, the large on-chip lens 635L is composed of a Fresnel lens, and the small on-chip lens 635S is composed of a hemispherical lens. In this way, the lens thickness of the large on-chip lens 635L in the large pixel 600L and the small on-chip lens 635S in the small pixel 600S can be the same or approximately the same, and the difference in oblique incidence characteristics due to the difference in lens thickness can be eliminated. In addition, oblique incidence caused by light reflected again from a sealing glass configured on the upper side of the on-chip lens 635 and incident at a high angle can be reduced to suppress glare and reduce color mixing. Although the fourth configuration example adopts Figure 2 The first layout example in FIG. 1 is used as an example of the layout of the unit pixel 21, but even if the second configuration example is adopted Figure 3In the case of the second layout example, it is also possible that only the lens 635L on the large sheet is composed of a Fresnel lens.

[0521] <8.5 Fifth Configuration Example of the Fifth Implementation Method>

[0522] Fig.55 A is a cross-sectional view showing a fifth configuration example of the unit pixel 21 according to the fifth embodiment of the present disclosure, and shows a cross-sectional view along Fig.55 A cross-sectional view along line XX' in FIG. Fig.55 B is a top view of the unit pixel 21 according to the fifth configuration example of the fifth embodiment.

[0523] In the fifth configuration example of the fifth embodiment, Figure 2 The first layout example shown is the layout of the unit pixel 21. Fig.55 In the fifth example of the structure, Fig.51 The corresponding parts in the first configuration example shown are denoted by the same reference numerals, and the description will focus on the parts different from the first configuration example.

[0524] exist Fig.51 In the first configuration example shown, the inter-pixel light shielding film 633 is formed by being embedded in the color filter 634 .

[0525] On the contrary, Fig.55 In the fifth configuration example of A, the second insulating film 651 is stacked on the insulating film 632, and the inter-pixel light shielding film 652 is formed above the element separation unit 612 in the same layer as the second insulating film 651. Therefore, the inter-pixel light shielding film 652 is configured in a layer different from the color filter 634. The low N wall 653 using a material having a lower refractive index than the color filter 634 is formed above the inter-pixel light shielding film 652 and in the same layer as the color filter 634. The top and side walls of the low N wall 653 are covered by the second insulating film 651. The second insulating film 651 can be the same material as or different from the insulating film 632. The second insulating film 651 is composed of, for example, a silicon oxide film.

[0526] because Fig.55 The layout of the large on-chip lens 635L, the small on-chip lens 635S, and the color filter 634 shown in FIG. 6 is similar to that in the first configuration example, and thus a description thereof will be omitted.

[0527] According to the unit pixel 21 of the fifth configuration example, the large on-chip lens 635L and the small on-chip lens 635S are formed by a Fresnel type on-chip lens. In this way, the difference in oblique incidence characteristics caused by the difference in lens thickness between the large on-chip lens 635L in the large pixel 600L and the small on-chip lens 635S in the small pixel 600S can be eliminated. In addition, oblique incidence caused by light reflected again from a sealing glass or the like disposed on the upper side than the on-chip lens 635 and incident at a high angle can be reduced to suppress glare and reduce color mixing.

[0528] Furthermore, according to the unit pixel 21 of the fifth configuration example, the low N wall 653 having a lower refractive index than the color filter 634 is provided above the inter-pixel light shielding film 652 and in the same layer as the color filter 634. In this way, oblique incident light incident at a high angle can be reflected by the low N wall 653 to suppress glare and further reduce color mixing.

[0529] Although the fifth example is Figure 2 The first layout example in the example is used as an example of the layout of the unit pixel 21, but for the second configuration example, Figure 3 The pixel structure of the second layout example in FIG. 1 is also possible in which the low N wall 653 is formed in the same layer as the color filter 634 .

[0530] <8.6 Sixth Configuration Example of the Fifth Implementation Method>

[0531] Fig.56 A is a cross-sectional view showing a sixth configuration example of the unit pixel 21 according to the fifth embodiment of the present disclosure, and shows a cross-sectional view taken along Fig.56 A cross-sectional view along line XX' in FIG. Fig.56 B is a top view of the unit pixel 21 according to the sixth configuration example of the fifth embodiment.

[0532] In the sixth configuration example of the fifth embodiment, Figure 2 The first layout example shown is the layout of the unit pixel 21. Fig.56 In the sixth example of the construction of Fig.51 The corresponding parts in the first configuration example shown are denoted by the same reference numerals, and the description will focus on the parts different from the first configuration example.

[0533] Fig.56 The sixth example in Fig.51 The first configuration example shown in FIG. 1 is different in that a large on-chip lens 635L and a small on-chip lens 635S constituted of a Fresnel lens are arranged offset in the plane direction to perform pupil correction, and the other points are the same.

[0534] In other words, Fig.56As shown in A and B of , the positions of the large on-chip lens 635L and the small on-chip lens 635S relative to the positions of the first photoelectric conversion unit 611L and the second photoelectric conversion unit 611S are different depending on the pixel position in the pixel array unit 11, and are arranged offset in the direction toward the center of the pixel array unit 11. The offset amounts of the large on-chip lens 635L and the small on-chip lens 635S increase as they approach the outer periphery (image corner end) of the pixel array unit 11.

[0535] According to the unit pixel 21 of the sixth configuration example, the large on-chip lens 635L and the small on-chip lens 635S are formed by a Fresnel type on-chip lens. In this way, the difference in oblique incidence characteristics caused by the difference in lens thickness between the large on-chip lens 635L in the large pixel 600L and the small on-chip lens 635S in the small pixel 600S can be eliminated. In addition, the oblique incidence caused by the light reflected again from the sealing glass or the like arranged on the upper side than the on-chip lens 635 and incident at a high angle can be reduced to suppress glare and reduce color mixing.

[0536] In addition, according to the unit pixel 21 of the sixth configuration example, the configuration of the large on-chip lens 635L and the small on-chip lens 635S can be formed to be a configuration shifted to the position for performing pupil correction. In this way, the incident angle that increases as it approaches the periphery of the pixel array unit 11 can be addressed to suppress glare and further reduce color mixing.

[0537] Although the sixth example is Figure 2 The first layout example in FIG. 1 is used as an example of the layout of the unit pixel 21, but as in the second configuration example, Figure 3 In the pixel structure of the second layout example in , the large on-chip lens 635L and the small on-chip lens 635S can be similarly formed in a configuration shifted to the position for performing pupil correction.

[0538] <8.7 Seventh Configuration Example of the Fifth Implementation Method>

[0539] Fig.57 A is a cross-sectional view showing a seventh configuration example of the unit pixel 21 according to the fifth embodiment of the present disclosure, and shows a cross-sectional view along Fig.57 A cross-sectional view along line XX' in FIG. Fig.57 B is a top view of the unit pixel 21 according to the seventh configuration example of the fifth embodiment.

[0540] In the seventh configuration example of the fifth embodiment, Figure 2 The first layout example shown is the layout of the unit pixel 21. Fig.57 In the seventh example of the composition, Fig.51The corresponding parts in the first configuration example shown are denoted by the same reference numerals, and the description will focus on the parts different from the first configuration example.

[0541] Fig.57 The seventh example in Fig.56 The sixth configuration example in FIG. 1 is similar to that in which the large on-chip lens 635L and the small on-chip lens 635S perform pupil correction. However, instead of shifting the positions of the large on-chip lens 635L and the small on-chip lens 625S relative to the positions of the first photoelectric conversion unit 611L and the second photoelectric conversion unit 611S as in the sixth configuration example, the large on-chip lens 635L and the small on-chip lens 635S formed by the Fresnel lens are formed so that the center of gravity of their shapes differs depending on the pixel position in the pixel array unit 11. In other words, as Fig.56 As shown in A and B of FIG. 1 , the large lens 635L and the small lens 635S are formed so that as they approach the outer periphery (image corner end) of the pixel array unit 11, the center of gravity of their shapes is shifted toward the center side of the pixel array unit 11. The eccentricity of the large lens 635L and the small lens 635S increases as they approach the outer periphery (image corner end) of the pixel array unit 11. The seventh configuration example is similar to the seventh configuration example except that the center of gravity of the large lens 635L and the small lens 635S is shifted to perform pupil correction. Fig.51 The first configuration example is shown.

[0542] According to the unit pixel 21 of the seventh configuration example, the large on-chip lens 635L and the small on-chip lens 635S are formed by a Fresnel type on-chip lens. In this way, the difference in oblique incidence characteristics caused by the difference in lens thickness between the large on-chip lens 635L in the large pixel 600L and the small on-chip lens 635S in the small pixel 600S can be eliminated. In addition, oblique incidence caused by light reflected again from a sealing glass or the like disposed on the upper side than the on-chip lens 635 and incident at a high angle can be reduced to suppress glare and reduce color mixing.

[0543] In addition, according to the unit pixel 21 of the seventh configuration example, the large-chip lens 635L and the small-chip lens 635S are formed so that the center of gravity of their shapes is offset to perform pupil correction. In this way, the incident angle that increases as it approaches the periphery of the pixel array unit 11 can be resolved to suppress glare and further reduce color mixing. Although in the sixth configuration example, color mixing caused by light incident from the peripheral direction (such as light reflected again from the sealing glass, etc.) may occur in the pupil correction achieved by lens shift, this does not occur in the case of pupil correction achieved by changing the shape.

[0544] Although the seventh example is Figure 2The first layout example in FIG. 1 is used as an example of the layout of the unit pixel 21, but as in the second configuration example, Figure 3 In the pixel structure of the second layout example in , the large on-chip lens 635L and the small on-chip lens 635S can be similarly formed with the center of gravity shifted to the position where pupil correction is performed.

[0545] <8.8 Summary of the Fifth Implementation Plan>

[0546] The unit pixel 21 according to the fifth embodiment includes a first photoelectric conversion unit 611L and a second photoelectric conversion unit 611S having different areas of photoelectric conversion regions formed in a semiconductor substrate 601, an element separation unit 612 separating the first photoelectric conversion unit 601L and the second photoelectric conversion unit 601S, a color filter 634 arranged on the incident light side relative to the semiconductor substrate 601, an inter-pixel shading film 633 arranged between the color filters 634, and an on-chip lens 635 that collects incident light on the photoelectric conversion unit 611.

[0547] The large on-chip lens 635L and the small on-chip lens 635S in the unit pixel 21 according to the fifth embodiment include a Fresnel-type on-chip lens. There is a case where only the large on-chip lens 635L is a Fresnel-type on-chip lens and a case where both the large on-chip lens 635L and the small on-chip lens 635S are Fresnel-type on-chip lenses. By adopting a Fresnel-type on-chip lens as at least one of the large on-chip lens 635L or the small on-chip lens 635S, light leakage from the large pixel 600L to the small pixel 600S can be suppressed, and color glare can be suppressed. In addition, the lens thickness of the large pixel 600L and the small pixel 600S can be the same or approximately the same, and the lens thickness can be made thinner compared to the hemispherical on-chip lens. In this way, the difference in the oblique incidence characteristics of the large pixel 600L and the small pixel 600S can be reduced, and the dependence of the sensitivity ratio on the F value can be suppressed.

[0548] Pupil correction can be performed by configuring the Fresnel type large-chip lens 635L and the small-chip lens 635S to be offset toward the center side of the pixel array unit 11 by a predetermined offset amount according to the pixel position in the pixel array unit 11 or by forming it so that the center of gravity of its shape is offset toward the center side of the pixel array unit 11. In this way, the degree of freedom of lens design can be improved.

[0549] The on-chip lens 635 in the fifth embodiment can be mounted as the on-chip lens in the above-mentioned first to third embodiments.

[0550] <9. Summary of all implementation plans>

[0551] All unit pixels 21 according to the first to fifth embodiments described above can suppress light leakage from large pixels to small pixels and suppress color glare. Therefore, the degradation of image quality of small pixels can be suppressed. The structures adopted by the unit pixels 21 according to the first to fifth embodiments can be arbitrarily combined.

[0552] <10. Example of use of solid-state imaging device>

[0553] Fig.58 is a diagram showing an example of how to use an image sensor including the solid-state imaging device 1 .

[0554] As an image sensor, for example, the above-described solid-state imaging device 1 can be used in various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays as follows.

[0555] A device for taking images for viewing, such as a digital camera, a portable device with a camera function, or the like.

[0556] Devices used in traffic, used for safe driving such as automatic stopping, recognizing the driver's condition, etc., such as vehicle-mounted sensors that capture images of the front, rear, surroundings, and interior of the vehicle, surveillance cameras that monitor moving vehicles and roads, and distance sensors that measure the distance between vehicles, etc.

[0557] Devices for home appliances, such as televisions, refrigerators, or air conditioners, to capture images of user gestures and operate the device based on the gestures.

[0558] Devices used in medical care, such as endoscopes or devices that perform angiography by receiving infrared light.

[0559] Devices used for security, such as surveillance cameras for crime prevention purposes or cameras for personal authentication.

[0560] Devices used for beauty care, such as skin measuring instruments for photographing the skin or microscopes for photographing the scalp.

[0561] Devices for sports, such as sports cameras or wearable cameras used for sports applications, etc.

[0562] Devices used in agriculture, such as cameras for monitoring the status of fields or crops.

[0563] <11. Application examples of electronic equipment>

[0564] The technology disclosed in the present invention is not limited to being applicable to solid-state imaging devices. That is, the technology disclosed in the present invention is applicable to general electronic devices that use solid-state imaging devices as image capture units (photoelectric conversion units), including imaging devices such as digital cameras or video cameras, mobile terminal devices with imaging functions, and copiers that use solid-state imaging devices as image reading units. The solid-state imaging device may be in a single-chip form or a modular form with imaging functions in which its imaging unit, signal processing unit, and optical system are packaged together.

[0565] Fig.59 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the technology of the present disclosure is applied.

[0566] Fig.59 The imaging device 1000 shown in FIG. 1 includes an optical portion 1001 having a lens group, Figure 1 The solid-state imaging device 1 in the embodiment of the present invention includes a solid-state imaging device (imaging device) 1002 and a DSP (digital signal processor) circuit 1003 as a camera signal processing circuit. In addition, the imaging device 1000 includes a frame memory 1004, a display section 1005, a recording section 1006, an operation section 1007, and a power supply section 1008. The DSP circuit 1003, the frame memory 1004, the display section 1005, the recording section 1006, the operation section 1007, and the power supply section 1008 are connected to each other via a bus 1009.

[0567] The optical section 1001 captures incident light (image light) from a subject to form an image on an imaging surface of the solid-state imaging device 1002. The solid-state imaging device 1002 converts the amount of incident light whose image has been formed on the imaging surface by the optical section 1001 into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal. As the solid-state imaging device 1002, it is possible to use Figure 1 A solid-state imaging device 1, that is, a solid-state imaging device as follows, which includes at least a first photoelectric conversion unit and a second photoelectric conversion unit having different areas of photoelectric conversion regions formed in a semiconductor substrate, an element separation unit separating the first photoelectric conversion unit and the second photoelectric conversion unit, a color filter arranged on the incident light side relative to the semiconductor substrate, an inter-pixel shading film arranged between the color filters, and an on-chip lens that collects incident light on the photoelectric conversion unit, which suppresses light leakage from large pixels to small pixels and suppresses color glare.

[0568] The display section 1005 is configured by, for example, a thin display such as a liquid crystal display (LCD) or an organic electroluminescent (EL) display, and displays a moving image or a still image captured by the solid-state imaging device 1002. The recording section 1006 records the moving image or the still image captured by the solid-state imaging device 1002 onto a recording medium such as a hard disk or a semiconductor memory.

[0569] The operation unit 1007 issues operation instructions for various functions of the imaging device 1000 under the operation of the user. The power supply unit 1008 appropriately supplies various types of power as operation power to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006 and operation unit 1007 as supply objects.

[0570] <12. Application examples of mobile objects>

[0571] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is implemented as a device to be installed on any type of mobile body such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, an unmanned aerial vehicle, a ship, or a robot.

[0572] Fig.60 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0573] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.60 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0574] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device such as a drive force generating device for generating a drive force of the vehicle such as an internal combustion engine, a drive motor, etc., a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0575] The main system control unit 12020 controls the operation of various devices provided in the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, a fog light, etc. In this case, a radio wave or a signal of various switches transmitted from a portable device instead of a key may be input to the main system control unit 12020. The main system control unit 12020 receives the input of the radio wave or the signal, and controls the door lock device, the power window device, the light, etc. of the vehicle.

[0576] The vehicle exterior information detection unit 12030 detects information related to the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 can detect objects such as people, cars, obstacles, signs, text on the road, etc., or detect the distance thereto based on the received image.

[0577] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as information related to the measured distance. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared rays.

[0578] The in-vehicle information detection unit 12040 detects information related to the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the state of the driver. For example, the driver state detection unit 12041 includes a camera that captures an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or can determine whether the driver falls asleep in a sitting position.

[0579] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism or the braking device based on the information related to the inside and outside of the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and can output a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize the functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation of the vehicle, following driving based on a following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0580] In addition, the microcomputer 12051 can coordinate control by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, so as to achieve automatic driving in which the vehicle drives autonomously without relying on the driver's operation.

[0581] In addition, the microcomputer 12051 can output a control instruction to the main system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlights according to the positions of the front vehicle or the oncoming vehicle detected by the exterior information detection unit 12030 to perform coordinated control to achieve glare prevention such as switching the high beam to the low beam.

[0582] The sound / image output unit 12052 transmits at least one of a sound and an image output signal to an output device capable of visually or auditorily notifying a vehicle occupant or information outside the vehicle. Fig.60 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0583] Fig.61 The figure is an example of the installation position of the imaging unit 12031.

[0584] exist Fig.61 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0585] Imaging units 12101, 12102, 12103, 12104, and 12105 are disposed at locations such as the front of the vehicle 12100, the side mirrors, the rear bumper, and the rear door, and at locations on the upper side of the windshield inside the vehicle. The imaging unit 12101 disposed in the front of the vehicle and the imaging unit 12105 disposed on the upper side of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed in the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 disposed in the rear bumper or the rear door mainly obtains images on the rear of the vehicle 12100. The front view images acquired by the imaging units 12101 and 12105 are mainly used to detect vehicles ahead, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0586] By the way, Fig.61An example of the shooting range of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided at the front of the vehicle. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104 on each other, a bird's-eye view image of the vehicle 12100 as seen from above is obtained.

[0587] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0588] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can determine the distance to each solid object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed to the vehicle 12100), thereby extracting a solid object located on the driving route of the vehicle 12100, especially the closest solid object, and traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100 as the front vehicle. In addition, the microcomputer 12051 can set the distance between the vehicles that is previously ensured in front of the front vehicle, and can perform automatic braking control (including tracking travel stop control), automatic acceleration control (including tracking travel start control), etc. Therefore, coordinated control such as automatic driving that aims at autonomous driving of the vehicle without relying on the operation of the driver can be performed.

[0589] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into three-dimensional object data of two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles and other three-dimensional objects, extract the classified three-dimensional object data, and automatically avoid obstacles using the extracted three-dimensional object data. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines the collision risk indicating the degree of danger of collision with each obstacle. When the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 and the display unit 12062 or performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can assist driving to avoid collisions.

[0590] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether the pedestrian exists in the captured images of the imaging units 12101 to 12104. For example, the identification of the pedestrian is performed by extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and by performing pattern matching processing on a series of feature points indicating the outline of the object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that the pedestrian exists in the captured images of the imaging units 12101 to 12104 and thereby identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a quadrilateral contour line for emphasis in a manner superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon indicating the pedestrian is displayed at a desired position.

[0591] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to the imaging unit 12031 in the above-mentioned configuration. Specifically, the solid-state imaging device 1 to which at least a part of the first to fifth embodiments is applicable can be applied as the imaging unit 12031. Applying the technology of the present disclosure to the imaging unit 12031 makes it possible to obtain a clearer captured image and obtain distance information while reducing the size of each unit. In addition, the use of the captured image and distance information obtained can reduce driver fatigue and improve the safety of the driver and the vehicle.

[0592] Although the solid-state imaging device in which the first conductivity type is P type, the second conductivity type is N type, and electrons are signal charges is described in the above example, the present disclosure can also be applied to a solid-state imaging device in which holes are signal charges. In this case, the first conductivity type may be N type, the second conductivity type may be P type, and the above-mentioned respective semiconductor regions may be composed of semiconductor regions of opposite conductivity types.

[0593] In addition, the present disclosure can be applied not only to solid-state imaging devices that capture images by detecting the distribution of the incident amount of visible light, but can also be generally applied to solid-state imaging devices that capture the distribution of the incident amount of incident infrared rays, X-rays, particles, etc. as images, and in a broad sense, can also be applied to solid-state imaging devices (physical quantity distribution detection devices) such as fingerprint detection sensors that capture images by detecting the distribution of other physical quantities such as pressure or electrostatic capacitance.

[0594] Furthermore, the technology of the present disclosure can be applied not only to solid-state imaging devices but also generally to semiconductor devices having other semiconductor integrated circuits.

[0595] The embodiments of the present disclosure are not limited to the above-described embodiments, and may be modified in various ways without departing from the gist of the technology of the present disclosure.

[0596] For example, a combination of all or part of the above-described embodiments may be adopted.

[0597] The advantageous effects described in this specification are merely exemplary and not limiting, and other advantageous effects than those described in this specification may be achieved.

[0598] The technology of the present disclosure can be configured as follows.

[0599] (1) A solid-state imaging device comprising:

[0600] A pixel array unit in which a plurality of unit pixels are two-dimensionally arranged,

[0601] Wherein, each of the unit pixels includes

[0602] a first photoelectric conversion unit formed in a semiconductor substrate,

[0603] The second photoelectric conversion unit has an area smaller than that of the first photoelectric conversion unit,

[0604] an inter-pixel light shielding film provided on at least a portion of a boundary between the unit pixels on the incident light side relative to the semiconductor substrate,

[0605] a spacer layer disposed on the incident light side relative to the inter-pixel light shielding film, and

[0606] A light shielding wall is provided on at least a portion of a boundary between the unit pixels on the incident light side relative to the inter-pixel light shielding film and partitions the spacer layer.

[0607] (2) The solid-state imaging device according to (1) above, wherein a minimum opening width of the inter-pixel light shielding film surrounding the second photoelectric conversion unit is formed to be equal to or smaller than a total height of the light shielding wall and the inter-pixel light shielding film.

[0608] (3) The solid-state imaging device according to (1) or (2) above,

[0609] Each of the unit pixels further includes a color filter in at least a portion of the area, and

[0610] The light shielding wall is formed in at least a portion of the same layer as the color filter.

[0611] (4) The solid-state imaging device according to (3) above, wherein the light shielding wall is formed to reach the same height as an upper surface of the color filter.

[0612] (5) The solid-state imaging device according to any one of (1) to (4) above, wherein the light shielding wall is composed of two or more stages.

[0613] (6) The solid-state imaging device according to (5) above, wherein the light shielding wall including two or more stages is provided offset in a planar direction at a position where pupil correction is performed.

[0614] (7) The solid-state imaging device according to any one of (1) to (6) above, wherein the light shielding wall is formed to a predetermined depth reaching the semiconductor substrate.

[0615] (8) The solid-state imaging device according to any one of (1) to (7) above, wherein a width of the inter-pixel light shielding film is formed to be larger than a width of the light shielding wall.

[0616] (9) A solid-state imaging device according to (8) above, wherein, regarding a protrusion of the inter-pixel light-shielding film that protrudes in a planar direction relative to the light-shielding wall, a width of the protrusion on the first photoelectric conversion unit side is formed to be smaller than a width of the protrusion on the second photoelectric conversion unit side.

[0617] (10) The solid-state imaging device according to any one of (1) to (9) above,

[0618] Each of the unit pixels further includes an on-chip lens, which collects incident light on the first photoelectric conversion unit or the second photoelectric conversion unit, and

[0619] The on-chip lens has a lens shape including at least two planar areas.

[0620] (11) The solid-state imaging device according to (10) above, wherein a shape of the on-chip lens is a rectangular parallelepiped shape.

[0621] (12) The solid-state imaging device according to (10) above, wherein a shape of the on-chip lens is a pyramid or a truncated pyramid.

[0622] (13) The solid-state imaging device according to any one of (10) to (12) above, wherein the shape of the on-chip lens is a shape obtained by obliquely cutting a corner between an upper surface and a side wall surface of the on-chip lens.

[0623] (14) The solid-state imaging device according to any one of (10) to (13) above, wherein, in the case of a shape in which corners between surfaces are not rounded, the shape of the on-chip lens is a shape having one or more vertices.

[0624] (15) A solid-state imaging device according to any one of (10) to (14) above, wherein the shape of one of the on-chip lens that collects incident light on the first photoelectric conversion unit or the on-chip lens that collects incident light on the second photoelectric conversion unit is hemispherical.

[0625] (16) The solid-state imaging device according to any one of (10) to (15) above, wherein the on-chip lens is made of an organic resin material.

[0626] (17) The solid-state imaging device according to any one of (10) to (16) above, wherein the on-chip lens is made of a material having a higher refractive index than a lower layer thereof.

[0627] (18) The solid-state imaging device according to any one of (1) to (9) above,

[0628] Each of the unit pixels further includes an on-chip lens, which collects incident light on the first photoelectric conversion unit or the second photoelectric conversion unit, and

[0629] The on-chip lens includes a Fresnel type on-chip lens.

[0630] (19) The solid-state imaging device according to (18) above, wherein the on-chip lens provided above the first photoelectric conversion unit includes a lens of a first area division number and a lens of a second area division number different from the first area division number, and

[0631] The on-chip lens disposed above the second photoelectric conversion unit includes a lens of a third area division number and a lens of a fourth area division number different from the third area division number.

[0632] (20) The solid-state imaging device according to (18) or (19) above,

[0633] Each of the unit pixels further includes a color filter above the first photoelectric conversion unit and the second photoelectric conversion unit, and

[0634] The area division number of the Fresnel type on-chip lens is different for each of the first color and the second color of the color filter.

[0635] (21) The solid-state imaging device according to any one of (18) to (20) above, wherein only the on-chip lens provided above the first photoelectric conversion unit is a Fresnel type on-chip lens.

[0636] (22) A solid-state imaging device according to any one of (18) to (21) above, wherein the on-chip lens provided above the first photoelectric conversion unit and the on-chip lens provided above the second photoelectric conversion unit are both Fresnel-type on-chip lenses.

[0637] (23) A solid-state imaging device according to any one of (18) to (22) above, wherein the position of the on-chip lens relative to the position of the first photoelectric conversion unit or the second photoelectric conversion unit is constructed to be different depending on the pixel position within the pixel array unit.

[0638] (24) The solid-state imaging device according to any one of (18) to (23) above, wherein a shape of the on-chip lens is configured to differ depending on a pixel position within the pixel array unit.

[0639] (25) A solid-state imaging device according to any one of (18) to (24) above, wherein each of the unit pixels further includes a low-N wall formed in the same layer as the color filter and having a refractive index lower than that of the color filter.

[0640] (26) A solid-state imaging device comprising:

[0641] A pixel array unit in which a plurality of unit pixels are two-dimensionally arranged,

[0642] Wherein, each of the unit pixels includes

[0643] a first photoelectric conversion unit formed in a semiconductor substrate,

[0644] The second photoelectric conversion unit has an area smaller than that of the first photoelectric conversion unit,

[0645] a color filter disposed on the incident light side relative to the semiconductor substrate, and

[0646] A low N wall is formed in the same layer as the color filter and has a refractive index lower than that of the color filter.

[0647] (27) The solid-state imaging device according to (26) above, wherein the low-N wall includes an organic resin film.

[0648] (28) The solid-state imaging device according to (26) or (27) above, wherein the low N wall is composed of a laminated body including an inter-pixel light shielding film and a low refractive index resin film.

[0649] (29) The solid-state imaging device according to any one of (26) to (28) above, wherein the low N wall is provided only at a boundary between the unit pixels.

[0650] (30) The solid-state imaging device according to any one of (26) to (28) above, wherein the low N wall is provided at a boundary between the unit pixels and a boundary between the first photoelectric conversion unit and the second photoelectric conversion unit.

[0651] (31) The solid-state imaging device according to any one of (26) to (28) above, wherein the low N wall is provided at a 1 / 4 pixel period of the unit pixel.

[0652] (32) The solid-state imaging device according to any one of (26) to (31) above, wherein each of the unit pixels further includes one or more recessed portions formed in a light receiving surface of the semiconductor substrate.

[0653] (33) The solid-state imaging device according to (32) above, wherein a surface of the recessed portion is formed of a (111) plane.

[0654] (34) The solid-state imaging device according to (32) or (33) above, wherein the concave portion is formed of an inverted pyramid structure.

[0655] (35) The solid-state imaging device according to (32) or (33) above, wherein the recessed portion is formed of a groove structure.

[0656] (36) The solid-state imaging device according to any one of (32) to (35) above, wherein the unit pixel includes a plurality of the concave portions.

[0657] (37) The solid-state imaging device according to any one of (32) to (36) above, wherein each of the unit pixels includes one or more of the concave portions in the first photoelectric conversion unit and the second photoelectric conversion unit, respectively.

[0658] (38) The solid-state imaging device according to any one of (32) to (37) above, wherein each of the unit pixels includes a plurality of the recessed portions in the first photoelectric conversion unit and the second photoelectric conversion unit, respectively.

[0659] (39) The solid-state imaging device according to any one of (32) to (38) above, wherein the color filter is embedded in the recess.

[0660] (40) A solid-state imaging device according to (26) above, wherein, in a plan view, the width of at least a portion of a first boundary portion serving as a boundary between a first photoelectric conversion unit and a second photoelectric conversion unit is constructed to be different from the width of a second boundary portion serving as a boundary between the first photoelectric conversion unit and the other first photoelectric conversion units.

[0661] (41) The solid-state imaging device according to (40) above, wherein in a plan view, the width of all the first boundary portions surrounding the second photoelectric conversion unit is configured to be different from the thickness of the second boundary portion.

[0662] (42) The solid-state imaging device according to (40) or (41) above, wherein the first boundary portion and the second boundary portion are the low N walls.

[0663] (43) The solid-state imaging device according to (40) or (41) above, wherein the first boundary portion and the second boundary portion are element separation units that separate the first photoelectric conversion unit and the second photoelectric conversion unit in the semiconductor substrate.

[0664] (44) A solid-state imaging device according to (40) or (41) above, wherein the first boundary portion and the second boundary portion are an element separation unit and a low N wall that separate the first photoelectric conversion unit and the second photoelectric conversion unit in the semiconductor substrate.

[0665] (45) A solid-state imaging device according to any one of (40) to (44) above, wherein the first boundary portion and the second boundary portion are a lens separation unit that separates an on-chip lens that collects incident light on the first photoelectric conversion unit or the second photoelectric conversion unit.

[0666] (46) A solid-state imaging device according to any one of (40) to (45) above, wherein the first boundary portion and the second boundary portion are a wiring layer separation unit that separates a portion of a wiring layer formed on a surface opposite to the incident light side of the semiconductor substrate.

[0667] (Y1) A solid-state imaging device comprising:

[0668] A pixel array unit in which a plurality of unit pixels are two-dimensionally arranged,

[0669] Wherein, each of the unit pixels includes

[0670] a first photoelectric conversion unit formed in a semiconductor substrate,

[0671] a second photoelectric conversion unit having an area smaller than that of the first photoelectric conversion unit, and

[0672] an on-chip lens that collects incident light on the first photoelectric conversion unit or the second photoelectric conversion unit, and

[0673] The on-chip lens has a lens shape including at least two planar areas.

[0674] (M1) A solid-state imaging device comprising:

[0675] A pixel array unit in which a plurality of unit pixels are two-dimensionally arranged,

[0676] Wherein, each of the unit pixels includes

[0677] a first photoelectric conversion unit formed in a semiconductor substrate,

[0678] a second photoelectric conversion unit whose area is smaller than that of the first photoelectric conversion unit, and an on-chip lens that collects incident light on the first photoelectric conversion unit or the second photoelectric conversion unit, and

[0679] The on-chip lens includes a Fresnel type on-chip lens.

[0680] (T1) A solid-state imaging device comprising:

[0681] A pixel array unit in which a plurality of unit pixels are two-dimensionally arranged,

[0682] Wherein, each of the unit pixels includes

[0683] a first photoelectric conversion unit formed in a semiconductor substrate,

[0684] a second photoelectric conversion unit having an area smaller than that of the first photoelectric conversion unit, and

[0685] In a plan view, a width of at least a portion of a first boundary portion as a boundary between a first photoelectric conversion unit and a second photoelectric conversion unit is configured to be different from a width of a second boundary portion as a boundary between the first photoelectric conversion unit and the other first photoelectric conversion unit.

[0686] [reference numerals list]

[0687] 1 Solid-state imaging device 11 Pixel array unit

[0688] 21 unit pixels 81 on-chip lenses

[0689] 81L large on-chip lens 81S small on-chip lens

[0690] 100 pixels 100L large pixels

[0691] 100L' large pixel 100S small pixel

[0692] 100S' small pixel 121 semiconductor substrate

[0693] 122 wiring layer 131 metal wiring

[0694] 132 interlayer insulating film 133 bonding electrode

[0695] 141 element separation unit 181 fixed charge membrane

[0696] 182 insulation film 183 inter-pixel light shielding film

[0697] 183L protrusion 183S protrusion

[0698] 184 light-shielding wall 184A light-shielding wall

[0699] 184B light-shielding wall 184B1 light-shielding wall

[0700] 184B2 shading wall 184C shading wall

[0701] 184C1 shading wall 184C2 shading wall

[0702] 185 spacer layer 186 color filter

[0703] 187 on-chip lens 187L large on-chip lens

[0704] 187S small chip lens 188 anti-reflection film

[0705] 214 protective film 301 semiconductor substrate

[0706] 311 Photoelectric conversion unit 311L First photoelectric conversion unit

[0707] 311S Second photoelectric conversion unit 312 Element separation unit

[0708] 313 recessed portion 314 insulating film

[0709] 314'Insulating film 315 Color filter

[0710] 315' Color filter 316 Low N wall

[0711] 317 on-chip lens 321 inter-pixel light shielding film

[0712] 322 low refractive index resin film 351 concave portion

[0713] 400L large pixel 410 on-chip lens

[0714] 410L large pixel 410S small pixel

[0715] 411 Photoelectric conversion unit 411L First photoelectric conversion unit

[0716] 411S second photoelectric conversion unit 421 semiconductor substrate

[0717] 422 wiring layer 431 metal wiring

[0718] 432 interlayer insulating film 433 bonding electrode

[0719] 441 Component separation unit 441L Component separation unit

[0720] 441S Component Separation Unit 441S' Component Separation Unit

[0721] 451 Insulation film 452 Color filter

[0722] 453 Low N Wall 453L Low N Wall

[0723] 453S Low N Wall 453S' Low N Wall

[0724] 454 on-chip lens 454L large on-chip lens

[0725] 454S small on-chip lens 454S' small on-chip lens

[0726] 455 anti-reflection film 471 lens separation unit

[0727] 481 wiring layer separation unit 500L large pixel

[0728] 500S small pixel 501 semiconductor substrate

[0729] 501L first photoelectric conversion unit 501S second photoelectric conversion unit

[0730] 511 Photoelectric conversion unit 511L First photoelectric conversion unit

[0731] 511S second photoelectric conversion unit 512 element separation unit

[0732] 513 insulation film 514 color filter

[0733] 515 inter-pixel light shielding film 516 on-chip lens

[0734] 516L large on-chip lens 516S small on-chip lens

[0735] 517 Anti-reflection film 521 On-chip lens

[0736] 521L large on-chip lens 521S small on-chip lens

[0737] 522 pixels between light shielding film 600L large pixel

[0738] 600S small pixel 601 semiconductor substrate

[0739] 601L first photoelectric conversion unit 601S second photoelectric conversion unit

[0740] 611 Photoelectric conversion unit 611L First photoelectric conversion unit

[0741] 611S second photoelectric conversion unit 611S' second photoelectric conversion unit

[0742] 612 Component separation unit 612' Component separation unit

[0743] 631 fixed charge film 632 insulating film

[0744] 633 inter-pixel light shielding film 634 color filter

[0745] 635 on-chip lens 635' on-chip lens

[0746] 635L large chip on lens 635L' large chip on lens

[0747] 635S small on-chip lens 635S' small on-chip lens

[0748] 651 second insulating film 652 inter-pixel light shielding film

[0749] 653 Low N Wall 1000 Imaging Device

[0750] 1002 Solid-state imaging device

Claims

1. A solid-state imaging device, comprising: A pixel array unit in which a plurality of unit pixels are two-dimensionally arranged, Wherein, each of the unit pixels includes a first photoelectric conversion unit formed in a semiconductor substrate, The second photoelectric conversion unit has an area smaller than that of the first photoelectric conversion unit, an inter-pixel light shielding film provided on at least a portion of a boundary between the unit pixels on the incident light side relative to the semiconductor substrate, a spacer layer disposed on the incident light side relative to the inter-pixel light shielding film, and A light shielding wall is provided on at least a portion of a boundary between the unit pixels on the incident light side relative to the inter-pixel light shielding film and partitions the spacer layer.

2. The solid-state imaging device according to claim 1, wherein The minimum opening width of the inter-pixel light shielding film surrounding the second photoelectric conversion unit is formed to be equal to or smaller than the total height of the light shielding wall and the inter-pixel light shielding film.

3. The solid-state imaging device according to claim 1, in, Each of the unit pixels further includes a color filter in at least a portion of the region, and The light shielding wall is formed in at least a portion of the same layer as the color filter.

4. The solid-state imaging device according to claim 3, wherein The light shielding wall is formed to reach the same height as the upper surface of the color filter.

5. The solid-state imaging device according to claim 1, wherein The light shielding wall is composed of two or more sections.

6. The solid-state imaging device according to claim 5, wherein The light shielding wall including two or more stages is disposed offset in a planar direction at a position where pupil correction is performed.

7. The solid-state imaging device according to claim 1, wherein The light shielding wall is formed to reach a predetermined depth of the semiconductor substrate.

8. The solid-state imaging device according to claim 1, wherein The inter-pixel light shielding film is formed to have a width greater than a width of the light shielding wall.

9. The solid-state imaging device according to claim 8, wherein Regarding the protrusion of the inter-pixel light shielding film protruding in the planar direction relative to the light shielding wall, the width of the protrusion on the first photoelectric conversion unit side is formed to be smaller than the width of the protrusion on the second photoelectric conversion unit side.

10. The solid-state imaging device according to claim 1, in, Each of the unit pixels further includes an on-chip lens that collects incident light on the first photoelectric conversion unit or the second photoelectric conversion unit, and The on-chip lens has a lens shape including at least two planar areas.

11. The solid-state imaging device according to claim 10, wherein The on-chip lens has a rectangular parallelepiped shape.

12. The solid-state imaging device according to claim 10, wherein The on-chip lens has a pyramid or truncated pyramid shape.

13. The solid-state imaging device according to claim 10, wherein The shape of the on-chip lens is a shape obtained by obliquely cutting a corner between an upper surface and a side wall surface of the on-chip lens.

14. The solid-state imaging device according to claim 10, wherein In the case of adopting a shape in which corners between faces are not rounded, the shape of the on-chip lens is a shape having one or more vertices.

15. The solid-state imaging device according to claim 10, wherein A shape of one of the on-chip lens that collects incident light on the first photoelectric conversion unit or the on-chip lens that collects incident light on the second photoelectric conversion unit is a hemispherical shape.

16. The solid-state imaging device according to claim 10, wherein The on-chip lens is made of an organic resin material.

17. The solid-state imaging device according to claim 10, wherein The on-chip lens is composed of a material having a higher refractive index than the underlying layer.

18. The solid-state imaging device according to claim 1, in, Each of the unit pixels further includes an on-chip lens that collects incident light on the first photoelectric conversion unit or the second photoelectric conversion unit, and The on-chip lens includes a Fresnel type on-chip lens.

19. The solid-state imaging device according to claim 18, wherein The on-chip lens disposed above the first photoelectric conversion unit includes a lens of a first area division number and a lens of a second area division number different from the first area division number, and The on-chip lens disposed above the second photoelectric conversion unit includes a lens of a third area division number and a lens of a fourth area division number different from the third area division number.

20. The solid-state imaging device according to claim 18, in, Each of the unit pixels further includes a color filter above the first photoelectric conversion unit and the second photoelectric conversion unit, and The area division number of the Fresnel type on-chip lens is different for each of the first color and the second color of the color filter.

21. The solid-state imaging device according to claim 18, wherein Only the on-chip lens disposed above the first photoelectric conversion unit is a Fresnel type on-chip lens.

22. The solid-state imaging device according to claim 18, wherein The on-chip lens disposed above the first photoelectric conversion unit and the on-chip lens disposed above the second photoelectric conversion unit are both Fresnel-type on-chip lenses.

23. The solid-state imaging device according to claim 18, wherein The position of the on-chip lens relative to the position of the first photoelectric conversion unit or the second photoelectric conversion unit is configured to be different depending on the position of a pixel within the pixel array unit.

24. The solid-state imaging device according to claim 18, wherein The shape of the on-chip lens is configured to be different depending on the pixel position within the pixel array unit.

25. The solid-state imaging device according to claim 18, wherein Each of the unit pixels further includes a low-N wall formed in the same layer as the color filter and having a refractive index lower than that of the color filter.

26. A solid-state imaging device comprising: A pixel array unit in which a plurality of unit pixels are two-dimensionally arranged, Wherein, each of the unit pixels includes a first photoelectric conversion unit formed in a semiconductor substrate, The second photoelectric conversion unit has an area smaller than that of the first photoelectric conversion unit, a color filter disposed on the incident light side relative to the semiconductor substrate, and A low N wall is formed in the same layer as the color filter and has a refractive index lower than that of the color filter.

27. The solid-state imaging device according to claim 26, wherein The low-N wall includes an organic resin film.

28. The solid-state imaging device according to claim 26, wherein The low N wall is composed of a laminate including an inter-pixel light shielding film and a low refractive index resin film.

29. The solid-state imaging device according to claim 26, wherein The low N wall is provided only at the boundary between the unit pixels.

30. The solid-state imaging device according to claim 26, wherein The low N wall is provided at a boundary between the unit pixels and a boundary between the first photoelectric conversion unit and the second photoelectric conversion unit.

31. The solid-state imaging device according to claim 26, wherein The low N wall is provided at a 1 / 4 pixel period of the unit pixel.

32. The solid-state imaging device according to claim 26, wherein Each of the unit pixels further includes one or more recessed portions formed in a light receiving surface of the semiconductor substrate.

33. The solid-state imaging device according to claim 32, wherein: The surface of the recessed portion is formed by a (111) plane.

34. The solid-state imaging device according to claim 32, wherein: The concave portion is formed by an inverted pyramid structure.

35. The solid-state imaging device according to claim 32, wherein: The recess is formed by a groove structure.

36. The solid-state imaging device according to claim 32, wherein: The unit pixel includes a plurality of the concave portions.

37. The solid-state imaging device according to claim 32, wherein: Each of the unit pixels includes one or more of the concave portions in the first photoelectric conversion unit and the second photoelectric conversion unit, respectively.

38. The solid-state imaging device according to claim 37, wherein: Each of the unit pixels includes a plurality of the concave portions in the first photoelectric conversion unit and the second photoelectric conversion unit, respectively.

39. The solid-state imaging device according to claim 32, wherein: The color filter is embedded in the recess.

40. The solid-state imaging device according to claim 26, wherein In a plan view, a width of at least a portion of a first boundary portion as a boundary between a first photoelectric conversion unit and a second photoelectric conversion unit is configured to be different from a width of a second boundary portion as a boundary between the first photoelectric conversion unit and the other first photoelectric conversion unit.

41. The solid-state imaging device according to claim 40, wherein In a plan view, the width of all the first boundary portions surrounding the second photoelectric conversion unit is configured to be different from the thickness of the second boundary portions. 42 . The solid-state imaging device according to claim 40 , wherein the first boundary portion and the second boundary portion are the low N wall.

43. The solid-state imaging device according to claim 40, wherein: The first boundary portion and the second boundary portion are element separation units that separate the first photoelectric conversion unit and the second photoelectric conversion unit in the semiconductor substrate.

44. The solid-state imaging device according to claim 40, wherein The first boundary portion and the second boundary portion are an element separation unit and a low N wall that separate a first photoelectric conversion unit and a second photoelectric conversion unit in the semiconductor substrate.

45. The solid-state imaging device according to claim 40, wherein The first boundary portion and the second boundary portion are a lens separation unit that separates an on-chip lens that collects incident light on the first photoelectric conversion unit or the second photoelectric conversion unit.

46. ​​The solid-state imaging device according to claim 40, wherein The first boundary portion and the second boundary portion are wiring layer separation units that separate a part of a wiring layer formed on a surface of the semiconductor substrate opposite to the incident light side.

Images