Integrated circuit testability and test point insertion method, device, equipment and medium

Abstract

The invention provides an integrated circuit testability and test point insertion method, device, equipment and medium, and is applied to the field of integrated circuit testability design, and the method comprises the steps: firstly, judging violation setting types (such as one or more combinations of '-from', '-through' and '-to') existing on a path, and then, according to different time sequence violation settings, carrying out the test point insertion according to different time sequence violation settings. Different test point insertion strategies are adopted: for '-from' and '-through' setting, a test point is inserted behind the last non-'-to' path, so that the test point is utilized to prevent X-state backward propagation; and for the '-to' setting, related circuit nodes are masked (hidden or shielded) so as to control the X state not to influence the subsequent test. After the test points are inserted, the derivation difficulty, the operation time and the vector number of automatic test vector generation can be remarkably reduced, meanwhile, the test coverage rate is improved, and the method has wide applicability and operability.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testability, and in particular to an integrated circuit testability and test point insertion method, device, equipment, and medium. Background Art

[0002] With the continuous advancement of integrated circuit (IC) manufacturing technology, the scale and integration of chips are increasing, which makes IC testing particularly important. In integrated circuit design, the purpose of Design For Test (DFT) is to insert testable circuits in the design stage so that process or design defects in the chip can be efficiently detected in the subsequent testing process, thereby improving the factory quality and reliability of the chip. In DFT design, scan chain circuit (Scan) and automatic test pattern generation (ATPG) are two core components. The scan chain circuit allows the test vector and test results to be shifted inside the circuit, while ATPG is responsible for generating test vectors that can detect defects such as stuck-at faults (SAF) and transition faults (TF) in the circuit.

[0003] Important parameters for evaluating ATPG performance include the runtime of test vectors, test coverage, and the number of test vectors. However, in circuit design, there are timing violations (timing violations), such as false paths or multicycle paths (MCP).

[0004] In ATPG testing, although DFT and ATPG can detect fixed-type and jump faults, in traditional circuit design, timing violations require additional processing of these timing violation paths. If not handled properly, they will cause indeterminate states (X states) to continue to propagate in the circuit, increasing the difficulty of deriving test vectors, and ultimately leading to an increase in test running time and the number of test vectors. At the same time, the test coverage will also decrease due to the propagation of X states, increasing the difficulty of deriving test vectors and extending the test time.

[0005] Therefore, how to deal with timing violations in the design during the ATPG process has become an important technical challenge. Based on this, a new testing technology solution is needed. Summary of the invention

[0006] In view of this, the embodiments of the present specification provide an integrated circuit testability and test point insertion method, device, equipment, and medium, which adopt different test point insertion strategies for different violation paths, thereby avoiding the continuous propagation of indeterminate states (X states) in the circuit, thereby reducing the derivation difficulty of test vector generation, test running time, and the number of test vectors, etc. At the same time, the test coverage will also be significantly improved because it is not affected by the propagation of X states.

[0007] The embodiments of this specification provide the following technical solutions:

[0008] An integrated circuit test point insertion method, comprising:

[0009] Obtaining several timing violation paths of the circuit to be tested;

[0010] According to the capture path corresponding to each timing violation path in the test process, determine the path setting options of the capture path corresponding to each timing violation path; wherein the path setting options are used to characterize the path information of the capture path, and the path setting options include any of the following single options or a composite option of a combination of multiple options: -from, -through, -to, wherein -from is used to characterize the path starting point of the capture path, -through is used to characterize the path passing point of the capture path, and -to is used to characterize the path end point of the capture path;

[0011] A test point is inserted into each timing violation path, wherein the insertion process includes: if the capture path corresponding to the timing violation path contains more than one path setting options, a test point is inserted after the last timing violation path that does not belong to the "-to" setting option; if there is only one path setting option in the capture path corresponding to the timing violation path, and the path setting option does not belong to the "-to" setting option, a test point is inserted after the timing violation path, otherwise the end point of the timing violation path is masked during automatic vector generation.

[0012] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0013] By inserting test points into the timing violation path in a targeted manner, the indeterminate state (X) on the violation path will not continue to propagate backward, so that the circuit can be fully tested to improve the test coverage. In addition, the propagation of the indeterminate state can be controlled and limited, which reduces the complexity of the automatic test pattern generation tool in deriving the test pattern. The specific insertion strategy depends on the different settings of the timing violation path ("-from", "-through", "-to"), which reduces the difficulty of ATPG derivation.

[0014] In addition, by inserting test points in the circuit, the efficiency and quality of TransitionATPG testing of circuits containing timing violations can be significantly improved. By accurately inserting test points to control the propagation of indeterminate states, the running time and number of test vectors of ATPG can be effectively reduced, while the test coverage can be greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A test point circuit structure according to an embodiment of the present invention;

[0017] Figure 2 A flowchart of a method provided according to different timing violation settings in an embodiment of the present invention;

[0018] Figure 3 A scan circuit according to an embodiment of the present invention;

[0019] Figure 4 A timing violation path in an embodiment of the present invention;

[0020] Figure 5 For the embodiments of the present invention Figure 4 Solution for timing violation paths in ;

[0021] Figure 6 A timing violation path in an embodiment of the present invention;

[0022] Figure 7 For the embodiments of the present invention Figure 6 Solution for timing violation paths in ;

[0023] Figure 8 A timing violation path in an embodiment of the present invention;

[0024] Fig. 9 For the embodiments of the present invention Figure 8 Solution for timing violation paths in ;

[0025] Fig.10 A timing violation path in an embodiment of the present invention;

[0026] Fig.11 A timing violation path in an embodiment of the present invention;

[0027] Fig.12For the embodiments of the present invention Fig.11 Solution for timing violation paths in ;

[0028] Fig.13 A timing violation path in an embodiment of the present invention;

[0029] Fig.14 A schematic diagram of an integrated circuit testability processing method in the present invention;

[0030] Fig.15 A schematic diagram of an integrated circuit test point insertion device in the present invention;

[0031] Fig.16 It is a schematic diagram of an integrated circuit testability processing device in the present invention. DETAILED DESCRIPTION

[0032] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0033] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0034] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0035] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0036] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0037] With the continuous advancement of integrated circuit (IC) manufacturing technology, the scale and integration of chips have been significantly improved, which makes IC testing very important. Design for Test (DFT) is an important part of integrated circuit design. By embedding testable circuits in the design stage, it can effectively intercept chips with process or design defects, discover process problems, and thus improve the factory quality and reliability of chips.

[0038] The scan chain circuit (Scan) combined with Automatic Test Pattern Generation (ATPG) can detect defects such as Stuck-At Faults (SAF) and Transition Faults (TF) in the circuit. The evaluation parameters of ATPG include the running time of the test pattern, the test coverage and the number of test patterns. The goal is to generate fewer test patterns in a shorter running time and achieve a higher fault coverage (Cov), that is, a higher coverage to complete the IC test.

[0039] However, if a timing violation (Timing Exception) is set in the functional front end of the circuit, that is, a false path (False Path) or a multicycle path (Multicycle Path, MCP for short) is set, then when generating a jump test vector, the set timing violation needs to be read in to avoid errors in simulation.

[0040] In addition, although DFT and ATPG can detect fixed-type and jump faults, in traditional circuit design, timing violations require additional processing for these timing violation paths. If not handled properly, they will cause indeterminate states (X states) to continue to propagate in the circuit, increasing the difficulty of deriving test vectors, and ultimately leading to an increase in test run time and the number of test vectors. At the same time, the test coverage will also decrease due to the propagation of X states, increasing the difficulty of deriving test vectors and extending the test time. These paths need to be additionally processed in ATPG testing. If they cannot be processed, they will be regarded as X states and continue to propagate backward in the circuit, which will make the derivation of test vectors (Test Pattern) more difficult, ultimately leading to an increase in run time and the number of test vectors (Test Pattern), while reducing coverage. The coverage will also decrease with the propagation of X states. Therefore, how to handle timing violations (Timing Exception) in the design in ATPG has become a technical challenge.

[0041] In view of this, through in-depth research and improvement exploration of circuits with timing violations, it is found that:

[0042] On the one hand, in integrated circuit design, the problem of test vector generation caused by this timing violation path can be solved by inserting a circuit structure of a test point, and then using corresponding control signals for the test point circuit structure to select the test point path or the original path in the test mode, thereby identifying and isolating the unstable state in the circuit and improving the accuracy and efficiency of the test.

[0043] Secondly, by using the test point insertion strategy, the accuracy and efficiency of chip testing can be improved, timing violations can be effectively handled in the design phase, and the propagation of uncertain states during the test process can be reduced, thereby optimizing the generation of test vectors, reducing test costs, and improving chip reliability.

[0044] Third, after the test point path is activated, the test signal can be allowed to enter the test point directly without being affected by the unstable state in the original path. This design helps to control and switch the signal path during the test process, enhancing the testability and fault detection capabilities of the integrated circuit.

[0045] In general, the embodiments of this specification aim at the problem of test point insertion in the path containing timing violation in the testability design of integrated circuits. By inserting test points in the circuit, the running time of transition fault automatic test vector generation (Transition ATPG) of the circuit containing timing violation can be effectively shortened, the number of required test vectors can be reduced, and the test coverage can be significantly improved. These improvements not only optimize the test process and reduce the test cost, but also improve the reliability of the chip.

[0046] Based on this, the embodiments of this specification propose a timing-based test point insertion processing idea: different test point insertion strategies are adopted for different violation situations.

[0047] There are usually two statements used to set Timing Exception, one is set_false_path and the other is set_multicycle. Although both statements will affect the value captured by Scan Cell during Transition ATPG, as long as they can effectively prevent Scan Cell from capturing the X state of the violation path during Transition ATPG, the same strategy for inserting Test Points can be used for these two statements.

[0048] In addition, the setting statement of Timing Exception usually has three setting options, namely "-from", "-through" and "-to", and its setting is relatively flexible, and you can set only one of them or all three. However, since the "-to" statement is relatively special, because it is set at the end point of the Timing Exception path, the ATPG tool will not continue to propagate the X state backward, so there is no need to add Test Point control, and you only need to mask the untested jump fault (hide or shield) at the end point during ATPG testing; and both "-from" and "-through" need to use the method of this application to insert TestPoint to prevent the ATPG tool from continuing to propagate the X state backward.

[0049] Therefore, based on the characteristics of the Timing Exception statement, for the process of inserting the TestPoint in the Timing Exception path, you can refer to Figure 2 Illustration: First determine whether there is a Timing Exception path. If so, further determine whether the Timing Exception path setting has only one option; if there is only one statement, determine whether it is a "-to" statement. If it is not a "-to" statement, that is, "-from" or "-through" or a combination of the two, insert the Test Point after the circuit with the Timing Exception set; for the case where there is only one "-to", hide the Timing Exception circuit (mask) so that the data it captures is X but the data of the shift operation (shift) is controllable. If there are multiple statements, insert the Test Point after the last path set by a non-"-to" statement.

[0050] By inserting test points in the integrated circuit design, the signals propagating from the starting control point can be effectively controlled. These test points serve as key locations for signal monitoring, ensuring that in the automatic test vector generation (ATPG) process, the indeterminate (X-state) signals are effectively managed to prevent them from continuing to propagate backward to subsequent parts of the circuit.

[0051] In addition, inserting test points avoids inaccurate test results and difficulties in fault diagnosis that may be caused by unstable signals, and ensures that only stable and reliable signals are passed to subsequent stages of the circuit, thereby improving the efficiency and accuracy of the automatic test vector generation process, while also enhancing the overall test coverage and fault detection capabilities of the circuit.

[0052] In summary, the present application can reduce the running time of Transition ATPG of circuits containing Timing Exception, reduce the number of Patterns of Transition ATPG, and improve the coverage of Transition ATPG. It has wide applicability, and the technical implementation is clear and has strong operability.

[0053] The following is a schematic description with reference to the accompanying drawings.

[0054] refer to Figure 1 As shown, an embodiment of the present specification provides a circuit structure of a test point (Test Point), and the circuit structure of the test point (Test Point) includes: an uplink scan cell (ScanCell), an AND gate (AND Gate) and a multiplexer (MUX).

[0055] First of all, the scan unit is the core part of the test circuit, responsible for capturing and shifting test data during the test process. The SI (Scan Input) end of the scan unit ScanCell is connected to the output Q end of the previous linked register to form a scan link. Since the Scan cell is linked, its SI signal is controllable. In the shift phase, its value is the value shifted in, and in the capture phase, it captures the value of its own Q end. This design allows the test data to be smoothly transmitted in the circuit, ensuring the accuracy and integrity of the test signal.

[0056] In addition, the SE end (Scan Enable) of the scanning unit Scan Cell is used as the enable to control ScanCell. The SE end is connected to the ScanEnable signal. During the shift operation phase, the SE signal is high level "1" and low level "0" during capture, allowing data to be moved in from the previous register; during the capture operation phase, the SE signal is low level, at this time the scanning unit will capture the value of its own Q end. This mechanism ensures that the circuit can flexibly respond to different operation requirements in different test phases.

[0057] And, the input terminal D of the scanning unit Scan Cell is connected to the output terminal of the AND gate; the output terminal Q of the scanning unit Scan Cell is connected to an input terminal of the AND gate;

[0058] AND gate is a logic gate whose output is high only when both of its inputs are high. In this test circuit, one input of the AND gate is connected to the output Q of the scan cell, and the other input of the AND gate receives the TestMode signal or other control signal. When the TestMode signal is high level "1", a loop is formed from the Q of the register to the output of the AND gate and then to the end of the Test Point, and the output Q of the scan cell ScanCell affects the test point end through the AND gate. This design allows the circuit to flexibly adjust the signal path according to the state of the control signal in the test mode, thereby improving the testability of the test.

[0059] In addition, the multiplexer (MUX) has the function of signal selection in the circuit, and can select one from multiple inputs to be passed to the output according to the selection signal. Among them, the S end of the multiplexer (MUX) is connected to the TpSelect signal, which is used to control which path the MUX selects for signal transmission. The I0 end is connected to TpIn, which is the data input of the original path, and the I1 end is connected to the output end of the AND gate, which is the data input of the test point path. By controlling the state of the TpSelect signal, the MUX can choose to pass the data of the original path (I0) or the test point path (I1) to the output. This selection mechanism enables the circuit to select different signal paths as needed during the test process, thereby effectively controlling the flow of signals.

[0060] In addition, when processing the timing violation path, when the TpSelect signal is high level "1", the MUX selects the test point path, allowing the logic control signal from the scan unit to be transmitted to the test point end through the AND gate, which can effectively prevent the indeterminate state in the original path from propagating to the subsequent circuit. This control mechanism not only improves the accuracy of the test, but also reduces the number of test vectors, thereby reducing the test cost.

[0061] In general, Figure 1 The test point circuit structure in the circuit realizes flexible control of the signal path during the circuit test. When dealing with timing violations, the structure can effectively control the propagation of indeterminate states and improve the accuracy and efficiency of the test. This innovative design not only provides strong support for the testability of integrated circuits, but also lays the foundation for subsequent circuit testing and fault diagnosis.

[0062] In some embodiments, when performing the design for testability process, the design data is first analyzed to obtain all timing violation paths in the circuit to be tested. These paths may include false paths, multi-cycle paths, etc., which do not meet the standard timing requirements and need to be processed in subsequent tests to ensure chip performance. Timing violation paths refer to paths whose timing requirements are relaxed or ignored due to performance optimization or design requirements in circuit design. If these paths are not processed correctly, they will cause some problems in the automatic test vector generation (ATPG) process, such as increasing the number of test vectors, reducing test coverage, and extending the test run time.

[0063] Specifically, for problems caused during the automatic test vector generation (ATPG) process, several timing violation paths of the circuit to be tested are first obtained. That is, the first step is to determine whether there are timing violation paths in the circuit design. This step is basic, because only when the existence of timing violations is confirmed can corresponding measures be taken to deal with it. Next, the process will adopt different processing methods for different types of timing violations.

[0064] Among them, two commonly used statements for setting timing violations are mentioned: set_false_path and set_multicycle. Both statements will affect the values ​​captured by the ScanCell during Transition ATPG. Timing violation paths refer to those paths that do not meet normal timing requirements due to specific reasons in circuit design. If these paths are not properly handled, errors will be introduced during the test process, resulting in inaccurate test results.

[0065] Further, the method requires determining the path setting options of each timing violation path corresponding to the capture path according to the capture path corresponding to each timing violation path during the test process. The path setting options are a set of parameters used to characterize the path information of the capture path. The timing violation statement can set three options: -from, -through and -to, and these options can be set individually or in combination.

[0066] Specifically, for each timing violation path, it is necessary to determine its corresponding capture path during the test process, and set the corresponding path options accordingly to ensure the effectiveness and accuracy of the test. The capture path refers to the path in which the test vector is transmitted to the inside of the circuit through the scan chain during the test and the signal is captured at a specific node. For each timing violation path, different path options can be set according to its starting point, path point, and end point in the capture path, including -from, -through, and -to. Among them, the -from option is used to identify the starting point of the capture path, the -through option is used to identify the path point in the path, and the -to option is used to identify the end point of the path. These path options together characterize the complete information of the capture path, providing an important basis for subsequent test point insertion and test strategy formulation.

[0067] For example, if a timing violation path starts from the clock input of a Scan Cell, passes through the output of a logic gate, and finally reaches the data input of another Scan Cell, the corresponding path options may include -from, -through, and -to. In this way, when ATPG generates vectors, the timing violation requirements can be met, thereby improving the accuracy and reliability of the test.

[0068] In addition, after determining the path setting options, the method enters the critical test point insertion processing stage. For each timing violation path, if the corresponding capture path contains more than one path setting options, then the test point is inserted after the last timing violation path that does not belong to the "-to" setting option. This is because the "-to" option is usually used to mark the end point of the path, and after the end point, the ATPG tool will no longer propagate the indeterminate state (X state) further, so no additional test point control is required.

[0069] It should be noted that if there is only one path setting option in the capture path corresponding to the timing violation path, and this option does not belong to the "-to" setting option, then the test point is inserted after the timing violation path. This processing can ensure that during the test, the signal starting from the path starting point or the waypoint can be effectively controlled and observed, thereby improving the accuracy and efficiency of the test.

[0070] On the contrary, if the only path setting option is "-to", the end point of the timing violation path will be masked, because the masked path will not affect the test results, thus avoiding unnecessary test point insertion.

[0071] Different test point insertion methods are used for different settings. For the -to statement, since it is set at the end point of the timing violation path, the ATPG tool will not continue to propagate the indeterminate state (X state) backwards. Therefore, there is no need to add test point control to the end point position, which simplifies the processing flow, reduces unnecessary test point insertion, reduces the total number of test points, and avoids test point insertion occupying too much circuit area.

[0072] Then, if the timing violation path setting has only one option, the process will determine whether the option is a -to statement. If it is not a -to statement, that is, it is -from or -through, the test point will be inserted after the circuit that sets the timing violation. This processing method allows more precise control of these paths during the test process, thereby improving the accuracy and efficiency of the test. For the case where there is only one -to, the circuit with the timing violation is masked so that the captured data is X but the shift data is controllable. This method ensures that during the test process, even at the end point of the timing violation path, a certain degree of control over the data flow can be maintained.

[0073] It should be noted that if there are multiple timing violation statements, the test point is inserted after the path set by the last non-to statement. This processing method ensures that in the case of multiple timing violation paths, the test point can effectively control and observe the circuit status, thereby improving the test coverage.

[0074] In summary, Figure 2 The presented flow is a systematic approach for inserting test points based on timing violations in circuit design to improve testability and coverage. This approach ensures that the circuit state can be effectively controlled and observed during the test process by flexibly handling different timing violation settings.

[0075] This method can effectively control and manage the timing violation paths in the integrated circuit, reduce the propagation of uncertain states during the test process, and reduce the difficulty of ATPG tools in deriving transition patterns. This not only improves the coverage of transitions, reduces the running time, and reduces the number of patterns, but also has a minimal impact on the chip area. It can reduce the number of test vectors, shorten the test running time, and improve the test coverage, thereby optimizing the entire test process, reducing test costs, and ultimately improving chip reliability.

[0076] The following uses a circuit example to illustrate the method of inserting test points in the present application when facing different violation paths.

[0077] like Figure 3As shown in the figure, the test circuit consists of four scan cells, an AND gate, combinational logic and sequential logic. This circuit is designed to pass data through different capture paths during the automatic test pattern generation (ATPG) test process to facilitate testing and diagnosis of circuit functions and performance.

[0078] During the process of inserting test points, when determining the path setting options of the capture path corresponding to the timing violation path, first, determine the capture path and its path setting options corresponding to each timing violation path during the test process. These capture paths refer to the paths through which the test vector propagates and is captured inside the circuit. Then, based on the capture process existing in the capture path, that is, the specific propagation node of the test vector in the circuit, determine each path option setting corresponding to the capture process.

[0079] In addition, these corresponding path setting options include "-from", "-through" and "-to", which are used to identify the starting point, waypoint and end point of the captured path respectively.

[0080] Through analysis, in this circuit, data can be transmitted through three main capture paths:

[0081] The first capture path is from the D end to the Q end of scancell1, then passes through the combinational logic, and finally is transmitted to the D end and Q end of scancell3.

[0082] The second capture path is that the data is transmitted from the D end to the Q end of scancell1, passes through the A end and Z end of AND gate and1, and is transmitted to the D end and Q end of scancell4.

[0083] The third capture path is that the data is transmitted from the D end to the Q end of scancell2, and then through the B end and Z end of AND gate and1, and transmitted to the D end and Q end of scancell4.

[0084] In summary, the design of these paths allows different parts of the circuit to be observed and controlled during the test process, thereby effectively detecting and isolating potential fault points. Each ScanCell in the circuit can be individually controlled in test mode to capture and shift test data to detect stuck-at faults and transition faults.

[0085] Further, for Figure 3 The three capture paths in the circuit structure form six different timing violation (Timing Exception) settings, which reflect different timing conditions that may exist in circuit design.

[0086] The six types of timing violation settings that exist are as follows:

[0087] The path starting from the clock terminal (CP) of ScanCell1: set_false_path-from scancell1 / CP(1).

[0088] Path through the output terminal (Z) of AND gate and1: set_false_path-through and1 / Z(2).

[0089] The path ending at the data end (D) of scancell3 and scancell4: set_false_path-to[listscancell3 / D scancell4 / D](3).

[0090] Also include the path starting from the CP of scancell1 and passing through the Z of and1: set_false_path-fromscancell1 / CP-through and1 / Z(4).

[0091] Path starting from CP of scancell1 and scancell2: set_false_path-from[listscancell1 / CP scancell2 / CP](5).

[0092] Contains a path starting from scancell1’s CP, passing through and1’s Z, and ending at scancell4’s D: set_false_path-from scancell1 / CP-through and1 / Z-to scancell4 / D(6).

[0093] These timing violation settings are useful when dealing with timing issues in circuits. If a path is marked as a timing violation, it means that the path may not meet the timing requirements in normal timing analysis, but it still needs to be considered during testing and verification. By inserting test points on these paths, it is possible to ensure that the data on these paths can be controlled and observed during the test process, thereby improving the accuracy and efficiency of the test.

[0094] The following is a schematic explanation of these six situations.

[0095] For the settings of type (1) Timing Exception, please refer to Figure 4 and Figure 5The path of Timing Exception is from scancell1 to scancell3 and scancell4, and affects the subsequent circuits. Figure 2 The program flow chart of this statement only has "-from", so Test Point1 should be inserted after scancell1 to prevent the subsequent circuit from capturing X-state data from scancell1. For the specific insertion position of Test Point, refer to Figure 5 .

[0096] Figure 4 and Figure 5 In the setting, the timing violation path starts from the clock terminal (CP) of the scanning cell ScanCell1 and extends to the scanning cells ScanCell3 and ScanCell4.

[0097] exist Figure 4 In the example, since the timing violation path contains only one path setting option “-from”, which is the CP starting from scancell1, a test point needs to be inserted immediately after scancell1.

[0098] Figure 5 The specific insertion position and method of the test point are explained. By inserting the test point after the scan cell scancell1, it can be ensured that during the test process, any data transmitted from the scan cell scancell1 can be effectively controlled and monitored. For the timing violation path with only the -from option, the starting point of the timing violation path is defined by the instruction set_false_path-from X, where X represents the starting point of the path. The timing violation path is transmitted from the D end to the Q end of the first scan cell ScanCell1, and then transmitted to the D end and Q end of the third scan cell ScanCell3 through the combinational logic, and transmitted to the D end and Q end of the fourth scan cell ScanCell4 through the A end and Z end of the AND gate. The test point is inserted after the first scan cell ScanCell1.

[0099] For the setting of the second type of Timing Exception, please refer to Figure 6 and Figure 7 Among them, the timing paths passing through and1 / Z are all Timing Exception paths. Figure 2 The solution flow chart shows that the statement only has "-through", so Test Point2 should be inserted after and1. The specific solution is as follows Figure 7 shown.

[0100] This path passes through the output terminal Z of the AND gate AND. In this configuration, any timing path passing through and1 / Z is defined as a timing violation, which means that these paths may not meet the timing requirements in normal timing analysis, but still need special attention during testing.

[0101] The path of the timing violation is transmitted from the D end to the Q end of the first scanning unit ScanCell1, and then transmitted to the D end and Q end of the fourth scanning unit ScanCell4 through the A end and the Z end of the AND gate;

[0102] And, the path of the timing violation is transmitted from the D end of the second scanning unit ScanCell2 to the Q end, and then after passing through the B end and the Z end of the AND gate, it is transmitted to the D end and the Q end of the fourth scanning unit ScanCell4, and the test point is inserted after the AND gate.

[0103] Among them, since the timing violation path only contains one path setting option "-through", indicating that it only affects the output of the AND gate (that is, and1), a test point needs to be inserted immediately after the AND gate. This design allows the path after the AND gate to be monitored during the test process, ensuring that any data transmitted from and1 / Z can be effectively controlled and observed.

[0104] Figure 7 The diagram shows that the test point is precisely placed after the AND gate in order to capture and analyze the data passing from that point. This strategy helps improve the accuracy of the test because it allows the test engineer to observe and verify the transmission path of the data after the AND gate and the impact of these paths on the subsequent circuits.

[0105] By inserting a test point after the AND gate, the indeterminate data can be prevented from propagating backwards, thus avoiding possible test errors. This method also helps to reduce the number of test vectors required during the test vector generation (ATPG) process, shorten the test time, and improve the test coverage. The insertion of test points is a critical step because it directly affects the generation of test vectors and test coverage.

[0106] For the settings of the third type of Timing Exception, please refer to Figure 8 and Fig. 9 This statement only has "-to". The values ​​captured by scancell3 and scancell4 are both in the X state, but because the circuits behind these two scancells are not on the path of the Timing Exception, the X state will not continue to propagate backwards. Therefore, these two scancells can be directly masked out. The solution is as follows Fig. 9 shown.

[0107] Since only the paths are set with the "-to" option, in this configuration, the endpoints of the timing violation paths are the data input terminals (D) of the third scancell scancell3 and the fourth scancell scancell4. Since the endpoints of these paths are marked as timing violations, this means that in normal timing analysis, these paths may not meet the timing requirements, but during the test, since they are at the end points of the paths, the values ​​captured by them will not continue to propagate backwards, so the end points of these paths will not affect the subsequent circuits, so the X states on these paths will not propagate further, thereby avoiding errors during the test. This setting allows designers to ignore the transition failure tests at the end points of the paths set with the "-to" option during the test because they will not have a negative impact on the test of subsequent circuits.

[0108] Therefore, the two scan cells are directly masked, where the mask operation is to not add test point control and ignore the data captured from the two scan cells during the automatic vector generation process. This method can simplify the test process, reduce the number of test vectors required, and shorten the test time. By masking these paths, unnecessary testing of these paths can be avoided during the ATPG process, thereby improving the test efficiency.

[0109] In addition, this approach can also reduce the complexity that may arise during the testing process because it avoids including paths that may cause errors in the test vectors. By focusing on those paths that are really important, the accuracy and reliability of the test can be improved.

[0110] In general, Figure 8 and Fig. 9 An effective strategy is provided for handling timing violation paths that are set only with the "-to" option. By identifying the endpoints of these paths and masking them out, the test process can be optimized, reducing test time and resource consumption. This approach helps improve the test efficiency of integrated circuits while ensuring the accuracy and reliability of test results. With this strategy, potential problems can be effectively identified and isolated during the design and verification phases, thereby improving the performance and reliability of the final product. This test point insertion method based on timing violation paths provides a practical solution for the testability design of integrated circuits and helps to meet the increasingly complex timing challenges.

[0111] For the settings of the (4) Timing Exception, please refer to Fig.10 . This sentence contains "-from" and "-through". Figure 2If you add a Test Point after the last option path other than "-to", you need to add a Test Point after and1. The solution is the same as (2). Please refer to the above solution. Figure 7 The relevant indicative content will suffice.

[0112] Fig.10 The illustrated path includes both "-from" and "-through" options. In this setting, the timing violation path starts from the clock terminal CP of the first scanning unit ScanCell1, passes through the output terminal Z of the AND gate AND Gate1, and affects the subsequent circuit. Therefore, since the path setting includes the "-from" and "-through" options, but lacks the "-to" option, it means that the starting point and the path point of the path need to be paid attention to in the test. The reason is: the inclusion of -through and -from indicates that the data from the starting point and the data from the path point will propagate indeterminate states, which means that the indeterminate state has no end point and will continue to propagate, so it is necessary to control the end point of the X state by inserting test points to prevent it from propagating out.

[0113] Therefore, similar to the above Figure 7 , a test point can be added after the last path that is not a "-to" option. Therefore, a test point needs to be added after AND1 to ensure that the data passing through AND1 / Z starting from the first scancell scancell1 can be effectively controlled and monitored. This design allows test engineers to observe and verify the transmission of data on this path during the test process, while preventing X-state data from propagating backwards, thereby improving the accuracy and efficiency of the test.

[0114] By inserting a test point after the AND gate, the indeterminate data can be prevented from propagating backward, thus avoiding possible test errors. In addition, this approach also helps to reduce the number of test vectors required in the test vector generation ATPG process, shorten the test time, and improve the test coverage. The insertion of test points is a critical step because it directly affects the generation of test vectors and test coverage.

[0115] In conclusion, Fig.10 and Figure 7 An effective strategy for handling timing violation paths with "-from" and "-through" options is demonstrated. By inserting test points at critical locations, the data flow in the circuit can be effectively controlled and monitored, thereby improving the quality and efficiency of testing. This approach helps improve the quality of chips shipped, and discovers and fixes potential problems during the design and verification phases, ultimately improving product reliability and performance. Through this meticulous circuit design and test point insertion strategy, integrated circuits are able to maintain efficient and stable performance in the face of complex timing challenges.

[0116] For the settings of the fifth type of Timing Exception, please refer to Fig.11 This statement only has "-from", and the data from scancell1 and scancell2 are both in X state. Figure 2 The solution flow chart should insert Test Point after scancell1 and scancell2 to prevent the subsequent circuit from capturing X-state data from scancell1 and scancell2. The solution is as follows Fig.12 shown.

[0117] In this setting, the starting point of the timing violation path is the clock terminal CP of the two scan cells, the first scan cell scanCell1 and the second scan cell scanCell2, and the path setting only contains the "-from" option, and does not contain the "-through" or "-to" option, which means that the data from the first scan cell scancell1 and the second scan cell scancell2 are both in the X state, that is, in an indeterminate state. This state may cause errors in the test process because the indeterminate data may affect the accuracy of the test results.

[0118] In order to solve this problem, it is necessary to insert test points after the first scanning unit scancell1 and the second scanning unit scancell2 to control and monitor the data transmitted from these two starting points.

[0119] Fig.12 A specific solution is provided, showing how to insert test points after the first scan cell scancell1 and the second scan cell scancell2. By inserting test points after these two scan cells, the subsequent circuit can be effectively prevented from capturing indeterminate data from the first scan cell scancell1 and the second scan cell scancell2. This strategy helps improve the accuracy of the test because it allows test engineers to observe and verify the transmission paths of data after it is transmitted from the first scan cell scancell1 and the second scan cell scancell2, as well as the impact of these paths on subsequent circuits.

[0120] When implementing this test point insertion strategy, the overall structure and logic of the circuit needs to be considered. The insertion of test points should not interfere with normal circuit operation, while ensuring that sufficient control and observation capabilities can be provided in test mode. In addition, the design of test points should also take into account their impact on circuit performance and area to ensure that while improving testability, it will not negatively affect other aspects of the circuit.

[0121] In conclusion, Fig.11 and Fig.12Provides a clear guide showing how to handle timing violation paths with multiple starting points in integrated circuit design. By inserting test points at key locations, the data flow in the circuit can be effectively controlled and monitored, thereby improving the quality and efficiency of testing. This approach not only helps to improve the quality of chips shipped, but also discovers and fixes potential problems during the design and verification phase, ultimately improving product reliability and performance. Through this meticulous circuit design and test point insertion strategy, integrated circuits can maintain efficient and stable performance in the face of complex timing challenges.

[0122] For the settings of the (6) Timing Exception, please refer to Fig.13 The sentence contains "-from", "-through", and "-to". Figure 2 In the flowchart of the solution, TestPoint is added after the last non-"-to" option path, so its processing method is consistent with that of (4), such as Figure 7 shown.

[0123] The path includes the complete path setting options "-from", "-through" and "-to". This configuration involves a path starting from the clock terminal CP of the first scanning unit ScanCell1, passing through the output terminal Z of the AND gate AND Gate1, and finally reaching the data input terminal D of the scanning unit 4. This timing violation path includes all three path setting options, indicating that the starting point, the waypoint and the end point of the path need to be paid special attention to.

[0124] In addition, since the "-to" option is included in the path settings, it means that the end point of the path will not continue to propagate the indeterminate state, so the main focus is on the starting point and waypoints of the path.

[0125] according to Figure 2 For this case, a test point should be added after the last non-"-to" option path. Therefore, a test point needs to be added after and1 to ensure that the data starting from scancell1, passing through and1 / Z, and finally reaching scancell4 can be effectively controlled and monitored. This design allows test engineers to observe and verify the transmission of data on this path during the test process, while preventing X-state data from propagating backwards, thereby improving the accuracy and efficiency of the test.

[0126] Similar to Figure 7 As shown in the figure, in this solution, the test point is precisely placed after the AND gate in order to capture and analyze the data transmitted from this point. This strategy helps improve the accuracy of the test because it allows the test engineer to observe and verify the transmission path of the data after the AND gate 1 and the impact of these paths on the subsequent circuits.

[0127] Still taking the setting of type (1) as an example to illustrate why this method can reduce the difficulty of ATPG derivation, when running ATPG in the conventional way, because the Timing Exception is set, the value captured by the A end of the AND gate is X, and this X will propagate backward. On the one hand, because the value captured by the A end is X, the Z port is also X, the A port and the Z port cannot be tested, and the value of the B port cannot be transmitted, so the B port cannot be tested. On the other hand, the ATPG tool needs to process the X state that is subsequently propagated, which takes a certain amount of time and pattern quantity. When using the method in this application, the Test Point can control the A end of and1 to 1, so that the faults of the B and Z ends can be tested, and the X state will not continue to propagate backward, which reduces the difficulty of ATPG derivation of the pattern.

[0128] It should be noted that even if set_false_path is replaced with set_multicycle, the processing method of the present application is still effective, indicating that the method of the present application has wide applicability and can adapt to different timing violation settings.

[0129] To verify the effectiveness of this method, this application uses an actual project circuit that contains 1.1 million registers and 293 timing violations.

[0130] Table 1 below is a comparison result between the conventional method and the present application.

[0131] Table 1 Comparison of results between conventional method and patent method

[0132]

[0133] In the case of condition one, that is, the coverage of Transition is limited to a maximum of 85%, the results show that the coverage of the two methods is similar, both around 85%. However, using the method of the present application, the running time of ATPG is reduced from 30 hours, 2 minutes and 45 seconds to 5 hours, 51 minutes and 13 seconds, and the number of test vectors is also reduced by 8078. Under condition two, that is, releasing the coverage limit, the coverage can be increased to 92.48%, and the running time and the number of test vectors are also significantly reduced. These results show that the method of the present application can not only improve the coverage of Transition ATPG and reduce the running time, but also reduce the number of test vectors required, while the impact on the chip area is only 0.01%.

[0134] Table 1 shows the comparison of the results of the conventional method and the method of the present application when executing ATPG in Transition mode. These comparison results highlight the significant advantages of the method of the present application in integrated circuit testing. Under the following condition, that is, when the coverage of Transition is limited to a maximum of 85%, the ATPG running time using the method of the present application is significantly reduced from 30 hours, 2 minutes and 45 seconds to 5 hours, 51 minutes and 13 seconds, a reduction of about 79.94%. At the same time, the number of test vectors is also reduced by 8078, a reduction of 88.55%. Although the coverage is similar due to restrictions, both around 85%, the improvement in time and resource efficiency of the method of the present application is obvious.

[0135] Under condition 2, that is, releasing the coverage restriction, this method not only increases the coverage to 92.48%, but also further reduces the running time and the number of test vectors. Specifically, the running time is reduced to 35 hours, 9 minutes and 11 seconds, a reduction of about 9.89%, and the number of test vectors is reduced to 7668, a reduction of about 22.18%. These data show that the method of this application effectively improves the efficiency and performance of the test without sacrificing coverage.

[0136] In addition, although the insertion of test points may have a certain impact on the chip area, the area increase caused by the method of the present application is only 0.01%, and this small increase is almost negligible in practical applications. Overall, the data in Table 1 strongly proves that the method of the present application not only improves the coverage of Transition ATPG and reduces the running time when processing circuits containing timing violation paths, but also reduces the number of test vectors, while having little impact on the chip area, thereby providing an efficient solution for the testability design of integrated circuits.

[0137] The inventive method of the present application significantly reduces the difficulty of deriving transition test vectors by ATPG tools by cutting off the timing violation path from the source and controlling the propagation of the X state. This method not only improves the test coverage, but also shortens the test run time, reduces the number of test vectors, and has minimal impact on the chip area. Therefore, the method of the present application is applicable to the transition ATPG of circuits containing timing violation settings, and provides an effective solution for the testability design of integrated circuits. Through this method, designers can more effectively handle complex timing violation paths, improve the test quality and efficiency of circuits, and thus improve the performance and reliability of the final product.

[0138] In some embodiments, the system will review each timing violation path to determine whether a test point has been inserted, which can prevent repeated insertion of test points on the same timing violation path. If the system determines that a test point already exists on a path, it will skip the path and no longer insert additional test points. On the contrary, if the system detects that a test point has not been inserted on a timing violation path, it will set options such as "-from", "-through" or "-to" according to the previously determined path, and accurately insert test points at the appropriate location.

[0139] In some embodiments, timing violation paths are those paths that are relaxed or ignored in standard timing analysis, which are critical to the performance and reliability of the circuit. These timing violation paths mainly include false paths and multicycle paths (MCP for short).

[0140] Specifically, false paths refer to paths that do not affect timing performance in circuit design. They may be non-critical paths that are intentionally introduced due to design optimization, circuit structure characteristics, or test requirements. In actual timing analysis, the timing requirements of these paths can be ignored to reduce timing constraints in the design, thereby improving the flexibility and efficiency of the design. In circuit design, false paths are usually described using the set_false_path statement, which tells the timing analysis tool to ignore these specific paths to avoid them affecting the timing analysis results.

[0141] On the other hand, a multi-cycle path refers to a path that requires multiple clock cycles to complete data transmission in the circuit operation. These paths usually involve complex logic operations or long-distance signal transmission, so the stable propagation of data cannot be completed in one clock cycle. The existence of loop paths has an important impact on the performance and reliability of the circuit because they may cause data delays or timing conflicts. In circuit design, loop paths are usually described using the set_multicycle statement, which allows the maximum number of clock cycles for the specified path to be provided with appropriate timing margins for these paths.

[0142] In general, false paths and multicycle paths are the two main types of timing violation paths. By using the set_false_path and set_multicycle statements, the characteristics of these paths can be accurately described, thereby optimizing the design process and test strategy while ensuring circuit performance. The use of these statements enables designers to effectively manage and control timing violation paths in complex circuit designs to ensure circuit reliability and efficiency. Correctly handling these timing violation paths is crucial to improving the performance and reliability of integrated circuits, because they directly affect the timing analysis, testing, and verification results of the circuit.

[0143] Based on the same inventive concept, after completing the test point insertion, the testability design of the integrated circuit is significantly improved, so the present application also provides an integrated circuit testability processing method.

[0144] refer to Fig.14 Schematically, a method for processing integrated circuit testability includes:

[0145] Step S202, performing a serial scan chain operation on the circuit to be tested, wherein the circuit to be tested is a circuit to be tested in which test points are inserted according to the integrated circuit test point insertion method as described in any of the examples given in this application. The test point insertion process can be described with reference to the aforementioned examples and will not be described in detail.

[0146] Step S204: After the chaining result is obtained, an automatic test vector may be generated according to the chaining result.

[0147] Step S206: carrying out preset integrated circuit test items according to the automated test vectors.

[0148] It should be noted that the integrated circuit test items can be determined according to the circuit requirements and are not specifically limited.

[0149] By inserting test points into the violation paths based on the present application, the derivation difficulty, running time, etc. of vector generation can be reduced, and the coverage rate can be improved, so the generated vectors can be beneficial to the integrated circuit project testing.

[0150] Based on the same inventive concept, the present application also provides an integrated circuit test point insertion device corresponding to the aforementioned method example.

[0151] refer to Fig.15 Schematically, an integrated circuit test point insertion device comprises:

[0152] A violation path module 101 is used to obtain a plurality of timing violation paths of the circuit to be tested;

[0153] The path setting module 103 is used to determine the path setting options of the capture path corresponding to each timing violation path according to the capture path corresponding to each timing violation path in the test process; wherein the path setting options are used to characterize the path information of the capture path, and the path setting options include any of the following single options or a composite option of a combination of multiple options: -from, -through, -to, wherein -from is used to characterize the path starting point of the capture path, -through is used to characterize the path passing point of the capture path, and -to is used to characterize the path end point of the capture path;

[0154] The insertion module 105 is used to insert a test point into each timing violation path, wherein the insertion process includes: if the capture path corresponding to the timing violation path contains more than one path setting options, then insert a test point after the last timing violation path that does not belong to the "-to" setting option; if there is only one path setting option in the capture path corresponding to the timing violation path, and the path setting option does not belong to the "-to" setting option, then insert a test point after the timing violation path, otherwise the end point of the timing violation path is masked during automatic vector generation.

[0155] Based on the same inventive concept, the present application also provides an integrated circuit testability processing device corresponding to the aforementioned method example.

[0156] refer to Fig.16 Schematically, an integrated circuit testability processing device comprises:

[0157] A scanning module 301 is used to perform a series scan chain on the circuit to be tested, wherein the circuit to be tested is a circuit to be tested in which a test point is inserted according to the integrated circuit test point insertion method as described in any embodiment of the present application;

[0158] Vector module 303, used to generate automatic test vectors according to the chaining results;

[0159] The testing module 305 is used to carry out preset integrated circuit testing items according to the automated testing vectors.

[0160] Based on the same inventive concept, the present application also provides an electronic device, including:

[0161] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute: an integrated circuit test point insertion method as described in any embodiment of the present application, or an integrated circuit testability processing method as described in any embodiment of the present application.

[0162] Based on the same inventive concept, the present application also provides a computer storage medium, characterized in that the computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by the processor, they execute: an integrated circuit test point insertion method as described in any embodiment of the present application, or an integrated circuit testability processing method as described in any embodiment of the present application.

[0163] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0164] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An integrated circuit test point insertion method, characterized in that: include: Obtaining several timing violation paths of the circuit to be tested; According to the capture path corresponding to each timing violation path in the test process, determine the path setting options of the capture path corresponding to each timing violation path; wherein the path setting options are used to characterize the path information of the capture path, and the path setting options include any of the following single options or a composite option of a combination of multiple options: -from, -through, -to, wherein -from is used to characterize the path starting point of the capture path, -through is used to characterize the path passing point of the capture path, and -to is used to characterize the path end point of the capture path; A test point is inserted into each timing violation path, wherein the insertion process includes: if the capture path corresponding to the timing violation path contains more than one path setting option, a test point is inserted after the last timing violation path that does not belong to the "-to" setting option; if there is only one path setting option in the capture path corresponding to the timing violation path, and the path setting option does not belong to the "-to" setting option, a test point is inserted after the timing violation path, otherwise the end point of the timing violation path is masked during automatic vector generation.

2. The integrated circuit test point insertion method according to claim 1, characterized in that: When determining the path setting options of the capture path corresponding to each timing violation path, first determine the capture path of the timing violation path in the test process, and then determine the path setting options corresponding to each capture process based on the capture process in the capture path.

3. The integrated circuit test point insertion method according to claim 1, characterized in that: When inserting a test point, first determine whether the timing violation path has been inserted with a test point. If so, do not insert the test point again. If not, insert the test point.

4. The integrated circuit test point insertion method according to claim 1, characterized in that: The types of timing violation paths include false paths or multicycle paths. False paths are described using the set_false_path statement and multicycle paths are described using the set_multicycle statement.

5. The integrated circuit test point insertion method according to any one of claims 1 to 4, characterized in that: The test point includes a scan cell, an AND gate AND and a data selector MUX; The terminals of the scan cell are connected as follows: the SI terminal is connected to the output Q terminal of the last linked register, the SE terminal is connected to the ScanEnable signal, the input terminal D is connected to the output terminal of the AND gate AND, and the output terminal Q is connected to an input terminal of the AND gate AND; The other input end of the AND gate is connected to a test TestMode or other control signal, wherein the TestMode or other control signal has a value of 1 in the scan mode, so as to form a loop from the Q end of the scan cell to the output of the AND gate and then to the D end of the scan cell; The ports of the data selector MUX are connected as follows: the S terminal is connected to the scan chip select signal TpSelect, the I0 terminal is connected to the original path, and the I1 terminal is connected to the output terminal of the AND gate AND, so that when TpSelect is controlled, the data selector MUX is controlled to select the test point path or the original path.

6. A method for processing integrated circuit testability, characterized in that: include: Performing a series scan chain operation on the circuit to be tested, wherein the circuit to be tested is a circuit to be tested in which a test point is inserted according to the integrated circuit test point insertion method according to any one of claims 1 to 5; Generate automated test vectors based on the chaining results; Carry out preset integrated circuit test items based on automated test vectors.

7. An integrated circuit test point insertion device, characterized in that: include: A violation path module, used for obtaining a plurality of timing violation paths of the circuit to be tested; A path setting module is used to determine the path setting options of the capture path corresponding to each timing violation path according to the capture path corresponding to each timing violation path in the test process; wherein the path setting options are used to characterize the path information of the capture path, and the path setting options include any of the following single options or a composite option of a combination of multiple options: -from, -through, -to, wherein -from is used to characterize the path starting point of the capture path, -through is used to characterize the path passing point of the capture path, and -to is used to characterize the path end point of the capture path; The insertion module is used to insert a test point into each timing violation path, wherein the insertion process includes: if the capture path corresponding to the timing violation path contains more than one path setting option, then the test point is inserted after the last timing violation path that does not belong to the "-to" setting option; if there is only one path setting option in the capture path corresponding to the timing violation path, and the path setting option does not belong to the "-to" setting option, then the test point is inserted after the timing violation path, otherwise the end point of the timing violation path is shielded during automatic vector generation.

8. An integrated circuit testability processing device, characterized in that: include: A scanning module, used for performing a series scan chain operation on the circuit to be tested, wherein the circuit to be tested is a circuit to be tested in which a test point is inserted according to the integrated circuit test point insertion method according to any one of claims 1 to 5; Vector module, used to generate automated test vectors based on scan results; The test module is used to carry out preset integrated circuit test items based on automated test vectors.

9. An electronic device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: the integrated circuit test point insertion method as described in any one of claims 1-5, or the integrated circuit testability processing method as described in claim 6.

10. A computer storage medium, characterized in that: The computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by the processor, they perform: the integrated circuit test point insertion method as described in any one of claims 1-5, or the integrated circuit testability processing method as described in claim 6.

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