Low-cost HDMI video optical transmission device and transmission method based on FPGA

Abstract

The invention relates to a low-cost HDMI (High Definition Multimedia Interface) video optical transmission device and a transmission method based on an FPGA (Field Programmable Gate Array), which are characterized in that the FPGA is used for encoding and decoding HDMI video signals, and a professional video encoding and decoding chip is replaced; meanwhile, a brand-new video transmission frame architecture is designed, effective video data are framed into data frames for transmission at a transmitting end, frame identifiers are set in the data frames, the data frames are deframed into video data according to the frame identifiers at a video recovery end, and according to different resolutions, an IP core of a local clock of an FPGA is used for dynamic adjustment to adapt to various resolutions. Video signals such as line and field signals are output, and a professional pixel clock recovery chip and a DDR3 cache chip are replaced; the whole scheme is high in transmission efficiency, small in transmission delay, capable of achieving real-time transmission, low in hardware system cost, small in size and suitable for application and popularization.

Description

Technical Field

[0001] The present invention relates to the field of video transmission, and in particular to a video optical transmission device and a transmission method. Background Art

[0002] The traditional method of video signal transmission is to use cables as the medium. However, during the transmission process, factors such as cable impedance and length lead to signal quality degradation. When the video is restored at the receiving end, the image is noisy and cannot meet the requirements. Therefore, the transmission medium currently used is mostly optical fiber. However, the following problems exist during the use of ordinary video optical terminals: The video recovery end uses a traditional caching method: DDR3 dynamically caches approximately three frames of images, resulting in significant video transmission delays and failing to meet the low-latency requirements of applications such as target tracking. Each TMDS high-speed differential signal is transmitted using one optical fiber, resulting in at least four optical fibers required for one video channel. A wavelength division multiplexer and de-wavelength division multiplexer are required to achieve single-fiber transmission, resulting in low transmission efficiency. The video transmitter needs to use a professional video decoding interface chip, the video recovery end needs to use a professional video encoding chip, and a professional pixel clock recovery chip to match the pixel clock of the video source end. The solution is costly and large in size. Summary of the Invention

[0003] In view of the defects of the prior art, the present invention provides a low-cost HDMI video optical transmission device and transmission method based on FPGA, which has the advantages of high transmission efficiency, small transmission delay and low hardware cost.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is: A low-cost HDMI video optical transmission device based on FPGA. Both the transmitting end and the receiving end of the optical transmission device adopt FPGA chips. The transmitting end includes a video decoding module, a video de-jitter reconstruction module, a video framing module, a high-speed serial transceiver GTX and a high-speed optical module. The receiving end includes a high-speed optical module, a high-speed serial transceiver GTX, a video deframing module, a dynamic clock reconfiguration module, a video timing reconstruction module and a video encoding module. The transmitting end and the receiving end are connected via optical fiber communication. The video framing module is used to frame valid video data into data frames for transmission and set frame identifiers in the data frames; the video deframing module is used to deframe the data frames to obtain video data according to the frame identifiers.

[0005] The video decoding module deserializes and byte-aligns the HDMI serial data, and performs data channel synchronization processing on the three sets of HDMI RGB differential data. After the synchronization is completed, the data is output as a line signal HS, a field signal VS, a data valid signal DE, and video data DATA according to the decoding rules of the HDMI protocol.

[0006] The video de-jitter reconstruction module performs video de-jitter and timing establishment on the line signal HS, field signal VS, data valid signal DE, and video data DATA decoded by the FPGA through de-jitter filtering and image caching.

[0007] The data frame output by the video framing module includes a field end information code, a DE header information code, and a resolution information code.

[0008] The video framing module and the video deframing module use asynchronous FIFO, the write clock of the video framing module FIFO is the video pixel clock, and the read clock is the user clock of the high-speed serial transceiver GTX; the write clock of the video deframing module FIFO is the user clock of the high-speed serial transceiver GTX, and the read clock is the pixel clock multiplied by the local crystal oscillator.

[0009] The dynamic clock reconfiguration module configures clock parameters according to the timing relationship of DRP by calling the clock IP core, and dynamically multiplies the frequency according to different resolutions to achieve the required pixel clock.

[0010] The video encoding module performs TMDS encoding on the field signal, line signal, and data valid signal output by the video timing reconstruction module according to the HDMI protocol, performs parallel-to-serial conversion on the encoded data, and outputs the TMDS high-speed differential signal to the HDMI connector after the conversion.

[0011] The present invention also provides a low-cost HDMI video optical transmission method based on FPGA, which introduces an HDMI video signal at the transmitting end, performs video decoding, de-jitter reconstruction, and framing processing through FPGA, uses a high-speed serial transceiver GTX to perform data parallel-to-serial conversion, and connects to a high-speed optical module to complete electrical-to-optical conversion. The receiving end is connected to a receiving end through an optical interface and an optical fiber. The receiving end sends the optical signal to the high-speed optical module, and then connects to the high-speed serial transceiver GTX. The high-speed serial data stream is converted into a parallel data stream, and the data stream is subjected to video deframing, dynamic clock reconfiguration, video timing reconstruction, and video encoding processing by FPGA, and then outputs the HDMI video signal.

[0012] The video decoding process is as follows: deserialize the HDMI serial data to obtain the correct deserialized data; according to the HDMI protocol, it fixedly transmits control characters when the field is idle, and achieves byte alignment by determining whether the control characters are stably received; after byte alignment, the three groups of HDMI RGB differential data are synchronized; after synchronization, the data is decoded according to the HDMI protocol rules to output the line signal HS, field signal VS, data valid signal DE, and video data DATA.

[0013] The specific process of video de-jittering and reconstruction is as follows: First, the resolution of the horizontal signal HS and the field signal VS is detected, and the corresponding timing information is output according to the different resolutions according to the VESA standard; Two dual-port RAMs are used to perform ping-pong storage of video data. The first-level RAM stores the odd-numbered lines of video data for each frame, and the second-level RAM stores the even-numbered lines of video data for each frame. The data valid signal DE output by the video decoder is used as the write enable for the RAM. During the process, the high-level time of the data valid signal DE is determined. If the high-level time does not match the corresponding line valid time at the resolution, the line data is considered to be erroneous and the error flag DE-ERR is output. According to the above-mentioned resolution detection results, a delay of 1 line is generated to generate the line signal HS2, field signal VS2, and data valid signal DE2 that comply with the VESA standard. The RAM to be read is selected according to the above-mentioned error flag DE-ERR, and the data of the error line is filled by reading the data of the previous line.

[0014] During the video framing and deframing process, an asynchronous FIFO is used to solve the cross-clock domain problem. During the framing process, the FIFO's write clock is the video pixel clock, and the read clock is the user clock of the high-speed serial transceiver GTX. During the deframing process, the FIFO's write clock is the user clock of the high-speed serial transceiver GTX, and the read clock is the pixel clock multiplied by the local crystal oscillator.

[0015] The specific processing of video framing is as follows: When the rising edge of the data valid signal DE and the falling edge of the field valid signal VS are detected, the FIFO write enable is turned on and the corresponding fixed identifier is written; when the low level count of the field valid signal VS reaches the set value, the FIFO write enable is turned on and data containing resolution information and fixed identifiers is written; when the high level of the data valid signal DE is detected, the FIFO write enable is turned on and video data is written; at other times, the FIFO write enable is turned off; when the FIFO is not empty, the read enable is turned on and the predetermined length data read out is put into the GTX send data. When the FIFO is read empty, the GTX send data sends a fixed K code identifier.

[0016] During the video framing process, 8'hff in the video data is replaced with 8'hfe, and 8'hff is used as a fixed identifier for the resolution information.

[0017] The specific processing of video deframing is as follows: According to the video framing architecture at the transmitter, when a fixed mark of resolution information appears in the parallel data stream converted by the high-speed serial transceiver GTX at the receiver, the video resolution information is parsed and the required clock frequency is multiplied using the local crystal oscillator according to the different resolution information. When the K code mark appears in the GTX parallel data stream, the FIFO write enable is turned off; otherwise, the write enable is turned on to write the video data.

[0018] During video de-framing, the valid line information is obtained according to the parsed resolution information. When the FIFO readable number is greater than the number of valid lines, the FIFO read enable is turned on; if the data read out by the FIFO is detected to be 24'h00ff00, it means that the falling edge of the field valid signal is detected, the output field valid signal and data valid signal are set low, and the FIFO read enable is turned off; if the data read out by the FIFO is detected to be 24'hff0000, it means that the rising edge of the data valid signal is detected, the field valid signal is set high, and then the FIFO readable number is judged again. If it is greater than the number of valid lines, the FIFO read enable is turned on and the data valid signal is set high. Otherwise, the FIFO read enable is turned off and the data valid signal is set low.

[0019] The video timing reconstruction process is as follows: When the rising edge of the field valid signal in the deframed data is detected, the field enable is set high. When the falling edge of the field valid signal is detected, the field enable is set low. If the high level of the field valid signal is not detected for more than 1 frame, the field enable is set low. When the field enable is high and the data valid signal in the deframed data is high, the deframed video data is sent to the synchronous FIFO; When the rising edge of the field valid signal in the deframed data is detected, according to the current resolution, the VESA standard timing signal at the resolution is delayed by 1 line to generate the line, field, and data valid signals. The data valid signal is used as the read enable of the synchronous FIFO, and the data read out is the valid video data.

[0020] In the optical transmission method, the FPGA obtains the communication status of the optical path through the following three methods: Method 1: The IIC interface obtains the received optical power of the optical module in real time. When the received optical power is lower than the set threshold, it is considered that the optical path communication is abnormal. Method 2: Error indication of DC balance signal and polarity signal of 8B / 10B encoding and decoding of high-speed serializer GTX; Method 3: Detect K28.5 synchronization code every 10ms. If no K28.5 synchronization code is detected, the optical communication is abnormal. When an optical path communication anomaly is detected, a rolling color bar at the current resolution is output to inform the user of the current optical path status.

[0021] According to the above technical solution, the present invention can achieve the following beneficial effects: 1. The present invention uses FPGA to decode and encode video signals, replacing professional video interface chips. The entire solution only consists of a power chip, FPGA, and an optical module core chip, which greatly reduces the cost, size, and power consumption of the product. The device panel only has an HDMI video interface, a power interface, and an optical fiber interface. The interface is simple and easy to use, the structure is small, and the hardware cost is low, which is convenient for field operations and commercial promotion.

[0022] 2. The present invention performs de-jitter filtering and image caching on the input video signal to avoid the phenomenon of image flickering at the video output end caused by glitch signals introduced by the video source due to poor video transmission quality, thereby improving the fault tolerance and reliability design of the transmission solution.

[0023] 3. This invention designs a brand-new video transmission architecture. At the video recovery end, an FPGA local clock IP core is used to dynamically adjust to various resolutions according to different resolutions, outputting video signals such as lines and fields, replacing the DDR3 cache chip or pixel clock recovery chip at the video receiving end under traditional solutions. A single optical fiber is used to transmit HDMI videos with a resolution of 1080P@60Hz and below. The transmission delay from the video signal source to the recovery end is controlled at around 1ms. The low latency feature is suitable for fields such as real-time tracking, while reducing cost, size, and power consumption.

[0024] 4. Design a customized frame structure transmission, uniquely identify the video information, ensure correct timing reconstruction at the receiving end, and only transmit video data when DE is valid, thereby improving the reliability of the communication system and bandwidth utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The HDMI video optical transmission architecture of the embodiment of the present invention; Figure 2 HDMI byte alignment process during video decoding; Figure 3 RGB data channel synchronization process. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0027] like Figure 1 As shown, the transmission architecture of an FPGA-based HDMI video optical transmission device of this embodiment is shown. The optical transmission device includes a transmitter and a receiver. Both the transmitter and the receiver use FPGA chips, and the transmitter and the receiver are connected via optical fiber communication.

[0028] The transmitter introduces the video signal through the HDMI connector, uses a diode for hot-swap protection, and then connects to the HR BANK of the FPGA chip. In this embodiment, the FPGA chip is selected based on logic resources and cost considerations, such as Xilinx's XC7A200T-2FGG484. After the FPGA performs video decoding, video de-jitter reconstruction, and video framing on the HDMI video, the high-speed serial transceiver GTX is used to convert the parallel data stream into a high-speed serial data stream, which is then connected to a high-speed optical module for electro-optical conversion. The optical fiber is output through the FC optical interface and connected to the receiving end.

[0029] The receiving end sends the optical signal into the high-speed optical module through the FC optical interface, and then connects to the FPGA high-speed serial transceiver GTX. The high-speed serial data stream is converted into a parallel data stream. The receiving end performs video deframing, dynamic clock reconfiguration, video timing reconstruction, and video encoding on the parallel data stream, and then outputs the video signal through the HDMI connector through hot-swap protection diodes.

[0030] Specifically, the functional modules of the transmitter include a video decoding module, a video de-jitter reconstruction module, and a video framing module.

[0031] The video decoding module is used to decode the data, as follows: (1) Deserialize the HDMI serial data through the primitives IDELAY2 and ISERDES2. The serial-to-parallel ratio of HDMI is 1:10. Cascading ISERDES2 achieves a 1:10 conversion. The reference clock of IDELAY2 is 200M, i.e. 1 tap is 78ps. IDELAY2 selects VAR_LOAD mode to facilitate dynamic adjustment of data delay and obtain correct data after deserialization. (2) According to the HDMI protocol, it transmits 4 10-bit control characters when it is idle, and byte alignment is achieved by judging whether the control characters are stably received. For the specific control process, please refer to the attached Figure 2 : (3) HDMI has three sets of RGB differential data. Due to factors such as PCB wiring, the three sets of data cannot be guaranteed to be completely synchronized. Therefore, data channel synchronization processing is required for the three sets of RGB differential data; (4) After synchronization is completed, the data is output according to the 8B10B decoding rules of the HDMI protocol, and the line signal HS, field signal VS, data valid signal DE, and video data DATA are output.

[0032] The process of data channel synchronization is as follows: Figure 3 , taking red data processing as an example to illustrate the synchronization processing flow: 1) Determine whether the byte alignment of the three sets of RGB data has been completed after deserialization. Otherwise, wait until the byte alignment is completed. If the byte alignment is completed, proceed to the next step; 2) Write the R channel data into the dual-port RAM and start reading the RAM at the same time, and determine whether there is any control character in the read data. If not, continue to execute this step. If yes, proceed to the next step. 3) Mark the rising edge of the control character POS, R channel data is ready. When POS is high and the G and B data are ready, it indicates that the three channel data are synchronized, otherwise proceed to the next step; 4) Close the read, cache the prepared channel data first, and determine whether the G and B channel data are ready. If not, continue with this step. If yes, continue with step 2); Follow the above steps until the data of the three channels are synchronized.

[0033] The function of the video de-jitter reconstruction module is to de-jitter and establish the timing of the line signal HS, field signal VS, data valid signal DE, and video data DATA after TMDS decoding by the FPGA. The specific processing is as follows: (1) First, the resolution of the horizontal signal HS and the field signal VS is detected. According to the VESA standard, the corresponding timing information is output according to the different resolutions, such as field front porch, field effective, line front porch, line effective, etc.; (2) Use two dual-port RAMs to perform ping-pong storage on the video data. To meet the maximum resolution of 1920*1080, the RAM size is set to 4Kb; the first-level RAM stores the odd-numbered lines of video data for each frame, and the second-level RAM stores the even-numbered lines of video data for each frame. The write enable of the RAM is the data valid signal DE1 output by the video decoding module. At the same time, the high-level time of the data valid signal DE is judged. When the high-level time does not match the corresponding line valid time at the resolution, the line data is considered to be wrong and the error flag DE-ERR is output; (3) According to the above-mentioned resolution detection result, a delay of one line is used to generate a line signal HS2, a field signal VS2, and a data valid signal DE2 that comply with the VESA standard. The data of the first-level RAM or the second-level RAM is determined based on the above-mentioned error flag DE-ERR. For example, if a DE valid time error occurs in the current third line of data, the data of the second-level RAM, i.e., the second line, should be read to fill the data of the third line.

[0034] The video processed by the above method is stable, which can avoid problems such as video flickering caused by incorrect high and low level timing or incorrect number of signal edges of line signals and data valid signals caused by poor video signal quality.

[0035] The function of the video framing module is to frame the field signal VS, data valid signal DE, resolution information, etc. after preliminary processing of video decoding and de-jittering.

[0036] During the video framing process, an asynchronous FIFO is used to solve the cross-clock domain problem. The write clock of the video framing module FIFO is the video pixel clock, and the read clock is the user clock of the high-speed serial transceiver GTX.

[0037] During the video framing process, since 8'hff values ​​exist in RGB video data, the RGB video data is processed. For example, when 8'hff appears in the red video data, it is replaced with 8'hfe. Similarly, in the blue and green video data, 8'hff in the video data is replaced with 8'hfe. This ensures that there is no 8'hff in RGB, that is, 8'hff is used as a special identifier.

[0038] The specific processing of video framing is as follows: When the rising edge of the data valid signal DE is detected, the FIFO write enable is turned on and the fixed marker 24'hff0000 is written; when the falling edge of the field valid signal VS is detected, the FIFO write enable is turned on and the fixed marker 24'h00ff00 is written; when the low level count of the field valid signal VS is detected to be equal to 10, the FIFO write enable is turned on and the fixed marker {resolution information, 8'hff} containing the resolution information is written; when the high level of the data valid signal DE is detected, the FIFO write enable is turned on and the video data is written; at other times, the FIFO write enable is turned off; when the FIFO is not empty, the read enable is turned on and the read 24-bit data is put into the GTX transmit data. When the FIFO is read empty, the GTX transmit data is fixedly sent with the K code marker, which is fixed to K28.5 in this example.

[0039] To save bandwidth utilization of the high-speed serial transceiver GTX, only 24 bits are used to transmit video data. In this embodiment, the high-speed serial transceiver GTX selects a line rate of 6.25 Gbps, an encoding mode of 8B / 10B, a synchronization code of K28.5, a pre-encoding bit width of 32 bits, and a post-encoding bit width of 40 bits. Based on this, the GTX user clock is calculated to be 156.25 MHz, which is greater than the 1080P pixel clock of 148.5 MHz. Since video transmission only occupies 24 bits, the remaining 8 bits of data can be used by the user to transmit other signals, which can effectively improve bandwidth utilization.

[0040] The receiving end functional modules include: video deframing module, dynamic clock reconfiguration module, video timing reconstruction module, and video encoding module.

[0041] During the video deframing process, an asynchronous FIFO is also used to solve the cross-clock domain problem. The write clock of the video deframing module FIFO is the user clock of the high-speed serial transceiver GTX, and the read clock is the pixel clock multiplied by the local crystal oscillator.

[0042] The specific processing of the video de-framing module is as follows: According to the video framing architecture at the transmitter, when 8'hff appears in the lower 8 bits of the parallel data stream converted by the high-speed serial transceiver GTX at the receiver, the video resolution information is parsed. When the K28.5 synchronization code appears in the GTX parallel data stream, the FIFO write enable is turned off. Otherwise, the write enable is turned on to write the video data.

[0043] To ensure that the video data read from the FIFO is continuous, the video data needs to be cached. When the FIFO's readable number is greater than the number of valid lines, the FIFO read enable is turned on, and the valid line information can be obtained according to the resolution information analyzed above; when it is detected that the data read from the FIFO is 24'h00ff00, it means that the falling edge of the field valid signal is detected, the output field valid signal and data valid signal are set low, and the FIFO read enable is turned off; when it is detected that the data read from the FIFO is 24'hff0000, it means that the rising edge of the data valid signal is detected, the field valid signal is set high, and the FIFO's readable number is judged at the same time. If it is greater than the number of valid lines, the FIFO read enable is turned on and the data valid signal is set high. Otherwise, the FIFO read enable is turned off and the data valid signal is set low.

[0044] Since the FIFO only buffers valid video when the transmitter frames the video, even if the pixel clock at the receiver deviates from the pixel clock at the transmitter, the FIFO will not be full and data will not be lost.

[0045] After the above-mentioned video deframing processing, the dynamic clock reconfiguration module calls the clock IP core and selects DynamicReconfig. It configures the clock parameters according to the timing relationship of the DRP (dynamically reconfigurable processor) and dynamically multiplies the frequency to achieve the required pixel clock according to different resolutions.

[0046] The processing flow of the video timing reconstruction module is as follows: (1) When the rising edge of the field valid signal output by the above-mentioned de-framing module is detected, the field enable is set high; when the falling edge of the field valid signal is detected, the field enable is set low; when the high level of the field valid signal is not detected for more than 1 frame, the field enable is set low; (2) When the field enable is high and the data valid signal output by the above-mentioned de-framing module is high, the video data output by the above-mentioned de-framing module is sent to the synchronous FIFO; (3) When the rising edge of the field valid signal output by the above-mentioned de-framing module is detected, according to the current resolution, the VESA standard timing signal at the resolution is generated by delaying 1 line, the line, field, and data valid signals, and the data valid signal is used as the read enable of the synchronous FIFO. The data read out is the valid video data.

[0047] The functions of the video encoding module are as follows: performing TMDS encoding on the field signal, line signal, and data valid signal output by the video timing reconstruction module according to the HDMI protocol, and performing a 10:1 parallel-to-serial conversion on the encoded 10-bit data; cascading two OSERDES2 primitive modules, with the sampling mode set to DDR; and outputting the TMDS high-speed differential signal to the HDMI connector after conversion.

[0048] In addition, the FPGA obtains the communication status of the optical link in three ways. When an optical path anomaly is detected, it outputs a fixed scrolling color bar at the current resolution to inform the user of the current optical path status: Method 1: The IIC interface obtains the received optical power of the optical module in real time. When the received optical power is lower than the set threshold, it is considered that the optical path communication is abnormal. Method 2: 8B / 10B encoding and decoding DC balance signal and polarity signal error indication of the high-speed serializer GTX; Method 3: Check the K28.5 synchronization code every 10ms. If no synchronization code is detected, the optical path is abnormal.

[0049] According to the above transmission scheme, the transmission delay is calculated: according to the data stream of video transmission, the transmitter's video de-jitter timing reconstruction module delays 1 line of RAM data reading + the receiver's video de-framing module FIFO storage 1 line + the video timing reconstruction module delays 1 line of FIFO data reading + other logical processing delays (estimated based on 1 line) = 4 lines. Based on the maximum resolution of 1080P, the delay is approximately 30μs, and the minimum resolution of 640*480@60Hz is approximately 76μs. It can be seen that the transmission delay is very small, which is very suitable for low-latency solutions in the field of real-time tracking.

[0050] The solution of this embodiment uses FPGA to transmit the video signal in a simple and reliable frame structure. At the video transmitting end, a frame structure including a field end information code, a DE header information code, and a resolution information code with a unique frame type identifier is designed. Only video data when DE is valid is transmitted, thereby improving bandwidth utilization and communication transmission reliability. At the video recovery end, based on the resolution information code, a local crystal oscillator is used to multiply the required clock frequency, and the video field signal and DE signal are recovered by deframing. Then, based on the resolution information, the video timing is reconstructed to restore stable line, field, DE and other signals.

[0051] The HDMI video optical transmission device and transmission method using the above transmission architecture have the following characteristics: (1) Supports real-time transmission of HDMI video at 1080P@60Hz and below, based on dynamic re-clocking to adapt to different display devices and thus have the characteristics of resolution adaptation; (2) Use the logic resources of FPGA to decode and encode the video signal, replacing the professional encoding and decoding chip. The entire solution only has a power chip, FPGA chip, and optical module core chip. The panel interface is simple and easy to use. The structural size can be achieved at 65mm*65mm. The hardware cost is controlled at around 100 yuan, which is convenient for field operations and commercial promotion.

[0052] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A low-cost HDMI video optical transmission device based on FPGA, characterized in that: The transmitting end and receiving end of the optical transmission equipment both use FPGA chips. The transmitting end includes a video decoding module, a video de-jitter reconstruction module, a video framing module, a high-speed serial transceiver GTX and a high-speed optical module. The receiving end includes a high-speed optical module, a high-speed serial transceiver GTX, a video de-framing module, a dynamic clock reconfiguration module, a video timing reconstruction module and a video encoding module. The transmitting end and the receiving end are connected via optical fiber communication. The video framing module is used to frame valid video data into data frames for transmission and set a frame identifier in the data frame; the video de-framing module is used to de-frame the data frame to obtain video data according to the frame identifier.

2. The low-cost HDMI video optical transmission device based on FPGA according to claim 1, characterized in that: The video decoding module deserializes and byte-aligns the serial data of HDMI, and performs data channel synchronization processing on the three groups of differential data of RGB of HDMI. After the synchronization is completed, the data outputs the line signal HS, the field signal VS, the data valid signal DE, and the video data DATA according to the decoding rules of the HDMI protocol.

3. The low-cost HDMI video optical transmission device based on FPGA according to claim 1, characterized in that: The video de-jittering and reconstruction module performs video de-jittering and timing establishment on the line signal HS, field signal VS, data valid signal DE, and video data DATA decoded by the FPGA through de-jittering filtering and image caching.

4. The low-cost HDMI video optical transmission device based on FPGA according to claim 1, characterized in that: The data frame output by the video framing module includes a field end information code, a DE header information code, and a resolution information code.

5. The low-cost HDMI video optical transmission device based on FPGA according to claim 1, characterized in that: The video framing module and the video deframing module use asynchronous FIFO, the write clock of the video framing module FIFO is the video pixel clock, and the read clock is the user clock of the high-speed serial transceiver GTX; the write clock of the video deframing module FIFO is the user clock of the high-speed serial transceiver GTX, and the read clock is the pixel clock multiplied by the local crystal oscillator.

6. The low-cost HDMI video optical transmission device based on FPGA according to claim 1, characterized in that: The dynamic clock reconfiguration module configures clock parameters according to the timing relationship of DRP by calling the clock IP core, and realizes the required pixel clock according to dynamic frequency multiplication of different resolutions.

7. The low-cost HDMI video optical transmission device based on FPGA according to claim 1, characterized in that: The video encoding module performs TMDS encoding on the field signal, line signal and data valid signal output by the video timing reconstruction module according to the HDMI protocol, performs parallel-to-serial conversion on the encoded data, and outputs the TMDS high-speed differential signal to the HDMI connector after the conversion.

8. A low-cost HDMI video optical transmission method based on FPGA, characterized in that: The HDMI video signal is introduced at the transmitting end. After video decoding, de-jitter reconstruction and framing processing are performed through FPGA, the high-speed serial transceiver GTX is used to convert the data into serial and parallel data, and it is connected to the high-speed optical module to complete the electro-optical conversion. It is connected to the receiving end through the optical interface and optical fiber. The receiving end sends the optical signal to the high-speed optical module, and then connects to the high-speed serial transceiver GTX. The high-speed serial data stream is converted into a parallel data stream, and the data stream is processed by FPGA for video deframing, dynamic clock reconfiguration, video timing reconstruction and video encoding, and then the HDMI video signal is output.

9. The low-cost HDMI video optical transmission method based on FPGA according to claim 8, characterized in that: The video decoding process is as follows: Deserialize the serial data of HDMI to obtain the correct data after deserialization; according to the HDMI protocol, it transmits a fixed control character when the field is idle, and realizes byte alignment by judging whether the control character is stably received; after byte alignment, synchronize the three groups of RGB differential data of HDMI; After synchronization is completed, the data is output according to the decoding rules of the HDMI protocol, and the line signal HS, field signal VS, data valid signal DE, and video data DATA are output.

10. The low-cost HDMI video optical transmission method based on FPGA according to claim 9, characterized in that: The specific process of video de-jittering and reconstruction is as follows: First, the resolution of the horizontal signal HS and the field signal VS is detected, and the corresponding timing information is output according to the different resolutions according to the VESA standard; Use 2 dual-port RAMs to perform ping-pong storage on video data; The first-level RAM stores the odd-numbered lines of video data for each frame of image, and the second-level RAM stores the even-numbered lines of video data for each frame of image. The data valid signal DE output by the video decoder is used as the write enable of the RAM. During the process, the high-level time of the data valid signal DE is judged. When the high-level time does not match the corresponding line valid time under the resolution, it is considered that the line data is wrong, and the error mark DE-ERR is output; According to the above-mentioned resolution detection result, a delay of 1 line is used to generate a line signal HS2, a field signal VS2, and a data valid signal DE2 that comply with the VESA standard. The RAM to be read is selected according to the above-mentioned error flag DE-ERR, and the data of the error line is filled by reading the data of the previous line.

11. The low-cost HDMI video optical transmission method based on FPGA according to claim 9, characterized in that: During the video framing and deframing process, asynchronous FIFO is used to solve the cross-clock domain problem. During the framing process, the write clock of the FIFO is the video pixel clock, and the read clock is the user clock of the high-speed serial transceiver GTX; during the deframing process, the write clock of the FIFO is the user clock of the high-speed serial transceiver GTX, and the read clock is the pixel clock of the local crystal multiplier.

12. The low-cost HDMI video optical transmission method based on FPGA according to claim 11, characterized in that: The specific processing of video framing is as follows: When the rising edge of the data valid signal DE and the falling edge of the field valid signal VS are detected, the FIFO write enable is turned on and the corresponding fixed mark is written; when the low level count of the field valid signal VS reaches the set value, the FIFO write enable is turned on and the data containing the resolution information and the fixed mark is written; when the high level of the data valid signal DE is detected, the FIFO write enable is turned on and the video data is written; At other times, the FIFO write enable is turned off; when the FIFO is not empty, the read enable is turned on, and the read data of the predetermined length is put into the GTX send data. When the FIFO is empty, the GTX send data is fixed to send the K code mark.

13. The low-cost HDMI video optical transmission method based on FPGA according to claim 12, characterized in that: During the video framing process, 8'hff in the video data is replaced by 8'hfe, and 8'hff is used as a fixed identifier of the resolution information.

14. The low-cost HDMI video optical transmission method based on FPGA according to claim 12, characterized in that: The specific processing of video de-framing is as follows: According to the video framing architecture of the transmitting end, when a fixed mark of resolution information appears in the parallel data stream converted by the high-speed serial transceiver GTX at the receiving end, the video resolution information is parsed out, and the required clock frequency is multiplied by the local crystal oscillator according to different resolution information; When a K code mark is detected in the GTX parallel data stream, the FIFO write enable is turned off, otherwise the write enable is turned on to write the video data.

15. The low-cost HDMI video optical transmission method based on FPGA according to claim 14, characterized in that: During the video de-framing process, the valid line information is obtained according to the parsed resolution information. When the readable number of the FIFO is greater than the number of valid lines, the FIFO read enable is turned on; if it is detected that the data read out of the FIFO is 24'h00ff00, it means that the falling edge of the field valid signal is detected, the output field valid signal and the data valid signal are set low, and the FIFO read enable is turned off; if it is detected that the data read out of the FIFO is 24'hff0000, it means that the rising edge of the data valid signal is detected, the field valid signal is set high, and then the readable number of the FIFO is judged again. If it is greater than the number of valid lines, the FIFO read enable is turned on and the data valid signal is set high, otherwise the FIFO read enable is turned off and the data valid signal is set low.

16. The low-cost HDMI video optical transmission method based on FPGA according to claim 9, characterized in that: The video timing reconstruction process is as follows: When the rising edge of the field valid signal in the deframed data is detected, the field enable is set high; when the falling edge of the field valid signal is detected, the field enable is set low; when the high level of the field valid signal is not detected for more than 1 frame, the field enable is set low; When the field enable is high and the data valid signal in the deframed data is high, the deframed video data is sent to the synchronous FIFO; When the rising edge of the field valid signal in the deframed data is detected, according to the current resolution, a delay of 1 line is generated to generate the VESA standard timing signal at the resolution, the line, field, and data valid signals. The data valid signal is used as the read enable of the synchronous FIFO, and the data read out is the valid video data.

17. The low-cost HDMI video optical transmission method based on FPGA according to claim 9, characterized in that: In the optical transmission method, FPGA obtains the communication status of the optical path in the following three ways: Method 1: The IIC interface obtains the received optical power of the optical module in real time. When the received optical power is less than the set threshold, it is considered that the optical path communication is abnormal; Method 2: 8B / 10B encoding and decoding DC balance signal and polarity signal error indication of high-speed serializer GTX; Method 3: Check the K28.5 synchronization code every 10ms. If the code is not detected, the optical communication is abnormal. When an optical path communication anomaly is detected, a rolling color bar at the current resolution is output to prompt the user of the current optical path status.

Images