Semiconductor device, preparation method thereof and storage system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method thereof and a storage system, and relates to the technical field of semiconductor devices. The semiconductor device includes a first memory particle, a second memory particle, and a functional layer. The functional layer comprises a functional circuit and is provided with a first side. The first storage particles and the second storage particles are located on the first side of the functional layer, and the first storage particles and the second storage particles are mixed and bonded with the functional layer. In the embodiment of the invention, the first storage particles and the second storage particles are respectively mixed and bonded with the functional layer, so that the first storage particles and the second storage particles can be respectively and electrically connected with the functional circuit in a mixed bonding manner, and the distance between the first storage particles and the second storage particles is shortened; the transmission bandwidth between the first storage particles and the second storage particles is improved, the integration level of the semiconductor device is improved, and miniaturization of the semiconductor device is facilitated.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a manufacturing method and a storage system thereof. Background Art

[0002] In the related art, the transmission bandwidth between two storage particles is relatively small, which affects the transmission speed of data between the two storage particles. Summary of the invention

[0003] The embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and a storage system, which are intended to solve the technical problem of small transmission bandwidth between two storage particles.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, an embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first storage particle, a second storage particle, and a functional layer. The functional layer includes a functional circuit. The functional layer has a first side, the first storage particle and the second storage particle are located on the first side of the functional layer, and the first storage particle and the second storage particle are hybrid-bonded to the functional layer, respectively.

[0006] In the embodiment of the present disclosure, the first storage particle and the second storage particle are arranged on the first side of the functional layer, so that the first storage particle and the second storage particle can be located on the same side of the functional layer, thereby improving the structural regularity of the semiconductor device. The first storage particle and the second storage particle are arranged to be hybrid-bonded with the functional layer respectively, so that the first storage particle and the second storage particle can be electrically connected to the functional circuit respectively by hybrid bonding, so that the functional circuit can control the first storage particle and the second storage particle to perform operations such as writing and reading data, thereby enabling the semiconductor device to realize the storage function.

[0007] Furthermore, by providing the first storage particle and the second storage particle to be hybrid-bonded with the functional layer respectively, the distance between the first storage particle and the second storage particle can be reduced, the transmission path of data when being transmitted between the first storage particle and the second storage particle can be shortened, the transmission bandwidth between the first storage particle and the second storage particle can be increased, and high-speed transmission of data between the first storage particle and the second storage particle can be achieved. Furthermore, by reducing the distance between the first storage particle and the second storage particle, the integration of the semiconductor device can be improved, the volume of the semiconductor device can be reduced, and the miniaturization of the semiconductor device can be facilitated.

[0008] In addition, the first storage particles and the second storage particles are respectively hybrid-bonded with the functional layer, thereby achieving high integration among the first storage particles, the second storage particles and the functional circuit, improving the integration of the semiconductor device and facilitating the miniaturization of the semiconductor device.

[0009] That is, the embodiments of the present disclosure configure the first storage particles and the second storage particles to be hybrid-bonded with the functional layer, respectively, so as to realize a semiconductor device with high integration and high bandwidth.

[0010] In some possible implementations, the first storage particle includes a flash memory storage particle, and the second storage particle includes a memory storage particle.

[0011] In some possible implementations, the first storage particle includes a 3D NAND storage particle, and the second storage particle includes a 3D Fe RAM storage particle.

[0012] In some possible implementations, the storage capacity of the first storage particle is greater than the storage capacity of the second storage particle, and the read and write speed of the second storage particle is greater than the read and write speed of the first storage particle.

[0013] In some possible implementations, the first storage particle includes a first dielectric layer and a first bonding metal, the first bonding metal is located in the first dielectric layer, and the end surface of the first bonding metal is exposed to the first dielectric layer. The second storage particle includes a second dielectric layer and a second bonding metal, the second bonding metal is located in the second dielectric layer, and the end surface of the second bonding metal is exposed to the second dielectric layer. The functional layer includes a third dielectric layer, a third bonding metal, and a fourth bonding metal. The third bonding metal and the fourth bonding metal are located in the third dielectric layer, and the end surfaces of the third bonding metal and the fourth bonding metal are exposed to the third dielectric layer. The third bonding metal and the fourth bonding metal are electrically connected to the functional circuit, respectively. The first bonding metal is mixedly bonded to the third bonding metal, and the second bonding metal is mixedly bonded to the fourth bonding metal.

[0014] In some possible embodiments, the functional layer has a second side, and the second side is arranged opposite to the first side. The semiconductor device also includes a packaging substrate, and the packaging substrate is located on the second side of the functional layer. The packaging substrate includes a substrate body, a metal ball and a pin. The metal ball is located between the functional layer and the substrate body, and the metal ball electrically connects the substrate body to the functional circuit. The pin is located on a side of the substrate body away from the functional layer, and the pin is electrically connected to the substrate body.

[0015] On the other hand, an embodiment of the present disclosure provides a method for preparing a semiconductor device. The method for preparing a semiconductor device includes: providing a first storage particle and a second storage particle. Providing a functional layer, the functional layer including a functional circuit. The functional layer has a first side, and the first storage particle and the second storage particle are located on the first side of the functional layer. The first storage particle and the second storage particle are mixed and bonded to the functional layer respectively.

[0016] In some possible implementations, the first storage particle includes a flash memory storage particle, and the second storage particle includes a memory storage particle.

[0017] In some possible implementations, the first storage particle includes a 3D NAND storage particle, and the second storage particle includes a 3D Fe RAM storage particle.

[0018] In some possible implementations, the storage capacity of the first storage particle is greater than the storage capacity of the second storage particle, and the read and write speed of the second storage particle is greater than the read and write speed of the first storage particle.

[0019] In some possible implementations, the first storage particle includes a first dielectric layer and a first bonding metal, the first bonding metal is located in the first dielectric layer, and the end surface of the first bonding metal is exposed to the first dielectric layer. The second storage particle includes a second dielectric layer and a second bonding metal, the second bonding metal is located in the second dielectric layer, and the end surface of the second bonding metal is exposed to the second dielectric layer. The functional layer includes a third dielectric layer, a third bonding metal, and a fourth bonding metal. The third bonding metal and the fourth bonding metal are located in the third dielectric layer, and the end surfaces of the third bonding metal and the fourth bonding metal are exposed to the third dielectric layer. The third bonding metal and the fourth bonding metal are electrically connected to the functional circuit, respectively. The first storage particle and the second storage particle are respectively mixedly bonded to the functional layer, including: mixing bonding the first bonding metal with the third bonding metal, and mixing bonding the second bonding metal with the fourth bonding metal.

[0020] In some possible implementations, the first storage particles and the second storage particles are respectively mixed and bonded with the functional layer, including: providing a carrier substrate. Placing the first storage particles and the second storage particles on one side of the carrier substrate. Under the support of the carrier substrate, the first storage particles and the second storage particles are respectively mixed and bonded with the functional mother layer. Under the support of the carrier substrate, after the first storage particles and the second storage particles are respectively mixed and bonded with the functional mother layer, the method further includes: removing the carrier substrate. Cutting the motherboard to form a bare chip. The motherboard includes a functional mother layer and the first storage particles and the second storage particles mixed and bonded with the functional mother layer. The bare chip includes a functional layer formed by cutting the functional mother layer, and the first storage particles and the second storage particles mixed and bonded with the energy layer.

[0021] In some possible embodiments, the functional layer has a second side, and the second side is arranged opposite to the first side. After cutting the motherboard to form the bare chip, it also includes: providing a packaging substrate. The packaging substrate is located on the second side of the functional layer. The bare chip is packaged on the packaging substrate. The packaging substrate includes a substrate body, a metal ball and a pin. The metal ball is located between the functional layer and the substrate body, and the metal ball electrically connects the substrate body to the functional circuit. The pin is located on the side of the substrate body away from the functional layer, and the pin is electrically connected to the substrate body.

[0022] In some possible implementations, before placing the first storage particles and the second storage particles on one side of the carrier substrate, the method further includes: forming an adhesive layer on the surface of one side of the carrier substrate. Placing the first storage particles and the second storage particles on one side of the carrier substrate includes: placing the first storage particles and the second storage particles on the adhesive layer.

[0023] In some possible implementations, providing a first storage particle and a second storage particle includes: providing a first wafer and a second wafer. Forming a plurality of first storage units on the first wafer, and forming a plurality of second storage units on the second wafer. Cutting the first wafer to form a first storage particle including the first storage unit. Cutting the second wafer to form a second storage particle including the second storage unit.

[0024] In another aspect, an embodiment of the present disclosure provides a storage system, which includes the semiconductor device and a controller as described above, and the controller is coupled to the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0026] Figure 1 A structural block diagram of an electronic device provided for some embodiments of the present disclosure;

[0027] Figure 2 A structural diagram of a semiconductor device provided for some embodiments of the present disclosure;

[0028] Figure 3 A top view of a semiconductor device provided for some embodiments of the present disclosure;

[0029] Figure 4 for Figure 3 Cross-sectional view along AA direction;

[0030] Figure 5 A structural block diagram of a storage system provided for some embodiments of the present disclosure;

[0031] Figure 6 A structural block diagram of a storage system provided for some other embodiments of the present disclosure;

[0032] Figure 7 A structural diagram of a die provided for some embodiments of the present disclosure;

[0033] Figure 8 for Figure 7 A partial enlarged view of the middle M region;

[0034] Fig. 9 A flowchart of steps of a method for preparing a semiconductor device provided in some embodiments of the present disclosure;

[0035] Fig.10 A flowchart of steps of a method for preparing a semiconductor device provided in some other embodiments of the present disclosure;

[0036] Fig.11 A structural diagram of a first wafer provided for some embodiments of the present disclosure;

[0037] Fig.12 A structural diagram of a second wafer provided for some embodiments of the present disclosure;

[0038] Fig.13 A positional relationship diagram of a first storage particle and a first carrier provided for some embodiments of the present disclosure;

[0039] Fig.14 A positional relationship diagram of a second storage particle and a second carrier provided in some embodiments of the present disclosure;

[0040] Fig.15 A structural diagram of a third wafer provided for some embodiments of the present disclosure;

[0041] Fig.16 A flowchart of steps of a method for preparing a semiconductor device provided in some embodiments of the present disclosure;

[0042] Fig.17 A positional relationship diagram of a first storage particle and a machine platform provided for some embodiments of the present disclosure;

[0043] Fig.18 A positional relationship diagram of a second storage particle and a machine platform provided in some embodiments of the present disclosure;

[0044] Fig.19 A positional relationship diagram of the first storage particles, the second storage particles and the carrier substrate provided for some embodiments of the present disclosure;

[0045] Fig. 20 A top view of a first storage particle, a second storage particle, and a carrier substrate provided for some embodiments of the present disclosure;

[0046] Fig.21 for Fig. 20 Cross-sectional view along direction BB;

[0047] Fig. 22 A diagram showing the positional relationship among storage particles, a supporting substrate and a functional layer provided for some embodiments of the present disclosure;

[0048] Fig.23 A positional relationship diagram of storage particles, a supporting substrate and a functional layer provided for other embodiments of the present disclosure;

[0049] Fig.24 A structural diagram of a motherboard provided for some embodiments of the present disclosure;

[0050] Fig.25 The structural diagram of the bare die provided for some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0055] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing.

[0056] Figure 1 A structural block diagram of an electronic device provided for some embodiments of the present disclosure.

[0057] like Figure 1 As shown, an embodiment of the present disclosure provides an electronic device 300. For example, the electronic device 300 may be an electronic device with a storage function, such as a computer, a mobile phone, a computer, an electronic watch, etc. It is understandable that the embodiment of the present disclosure does not further limit the type of the electronic device 300.

[0058] In some examples, such as Figure 1 As shown, the electronic device 300 may include a memory system 200 capable of storing data. The memory system 200 may include a semiconductor device 100 and a controller 210 , and the controller 210 may be coupled to the semiconductor device 100 .

[0059] The semiconductor device 100 may be a three-dimensional semiconductor device, such as a three-dimensional memory, for storing data. For example, the semiconductor device 100 may be a 3D Memory. The controller 210 is coupled to the semiconductor device 100 so that the controller 210 can control the semiconductor device 100 .

[0060] In some examples, the memory system 200 may include multiple semiconductor devices 100 , and the controller 210 may be coupled to the multiple semiconductor devices 100 . In other examples, the memory system 200 may include multiple semiconductor devices 100 and multiple controllers 210 , and one controller 210 may be coupled to one or more semiconductor devices 100 .

[0061] Figure 2 A structural diagram of a semiconductor device provided for some embodiments of the present disclosure.

[0062] In some examples, such as Figure 2 As shown, the semiconductor device 100 may include a first memory particle 101 and a second memory particle 102. For example, the memory particle (English name: die, including the first memory particle 101 and the second memory particle 102) may be a three-dimensional memory particle.

[0063] The storage type of the first storage particle 101 and the storage type of the second storage particle 102 may be the same or different. Figure 2 As shown, the semiconductor device 100 may include a first storage particle 101 and a second storage particle 102. In other examples, the semiconductor device 100 may also include a plurality of first storage particles 101 and a plurality of second storage particles 102. It can be understood that the number of the first storage particles 101 and the number of the second storage particles 102 may be the same or different.

[0064] In the related art, the semiconductor device 100 may be packaged individually or by using micro bump (English: Micro Bump) technology to complete 2.5D (English: Dimensional) packaging.

[0065] For example, in the packaging method of separate packaging, the first storage particle 101 and the second storage particle 102 can be packaged separately using a packaging substrate and other structures to form a first storage chip and a second storage chip, and then the first storage chip and the second storage chip are electrically connected to the circuit chip respectively. For example, a control circuit can be provided in the circuit chip, and the first storage chip and the second storage chip are electrically connected to the circuit chip respectively, so that the first storage chip and the second storage chip can be electrically connected to the control circuit in the circuit chip.

[0066] However, packaging the first storage particle 101 and the second storage particle 102 separately will result in a larger distance between the first storage particle 101 and the second storage particle 102, increase the transmission path when data is transmitted between the first storage particle 101 and the second storage particle 102, affect the transmission speed of data between the first storage particle 101 and the second storage particle 102, and reduce the transmission bandwidth between the first storage particle 101 and the second storage particle 102. In addition, packaging the first storage particle 101 and the second storage particle 102 separately will also reduce the integration of the semiconductor device 100, which is not conducive to the miniaturization of the semiconductor device 100. In addition, packaging the first storage particle 101 and the second storage particle 102 separately will also increase the cost of the semiconductor device 100.

[0067] When performing 2.5D packaging, refer to Figure 2 The first storage particle 101 and the second storage particle 102 can be electrically connected to the peripheral circuit 141 located in the circuit layer 140 through the micro-bump structure 103, and then the first storage particle 101, the second storage particle 102 and the circuit layer 140 are packaged as a whole using a packaging substrate and other structures.

[0068] However, when the micro-bump structure 103 is used to perform 2.5D packaging on the first storage particle 101 and the second storage particle 102, the distance between the first storage particle 101 and the second storage particle 102 is also large, which increases the transmission path when data is transmitted between the first storage particle 101 and the second storage particle 102, affects the transmission speed of data between the first storage particle 101 and the second storage particle 102, and reduces the transmission bandwidth between the first storage particle 101 and the second storage particle 102. In addition, the integration of the semiconductor device 100 will be reduced, which is not conducive to the miniaturization of the semiconductor device 100.

[0069] It can be seen that, whether the packaging method of separate packaging is adopted or the 2.5D packaging is realized by using the micro-bump technology, the distance between the first storage particle 101 and the second storage particle 102 is large, which reduces the speed of data transmission between the first storage particle 101 and the second storage particle 102, resulting in a small transmission bandwidth between the first storage particle 101 and the second storage particle 102. In addition, it will also affect the integration of the semiconductor device 100, which is not conducive to the miniaturization of the semiconductor device 100.

[0070] Figure 3 A top view of a semiconductor device provided for some embodiments of the present disclosure. Figure 4 for Figure 3 Cross-sectional view along the AA direction.

[0071] Based on this, an embodiment of the present disclosure provides a semiconductor device 100. Figure 3 and Figure 4 As shown, the semiconductor device 100 may include a first storage particle 101, a second storage particle 102 and a functional layer 110. It can be understood that the above embodiments of the present disclosure have illustrated the first storage particle 101 and the second storage particle 102, which will not be described again.

[0072] In some examples, such as Figure 4 As shown, the functional layer 110 may include a functional circuit 111, and the first storage particle 101 and the second storage particle 102 may be electrically connected to the functional circuit 111. For example, the functional layer 110 may include a circuit functional layer 115, and the functional circuit 111 may be located in the circuit functional layer 115.

[0073] like Figure 4As shown, the functional circuit 111 may include a read / write circuit 111a and a control (English: Controller) circuit 111b. The read / write circuit 111a is used to control the storage particles (including the first storage particles 101 and the second storage particles 102) to perform operations such as writing and reading data. In some examples, the read / write circuit 111a may include a CMOS (English full name: Complementary Metal Oxide Semiconductor, Chinese name: Complementary Metal Oxide Semiconductor) circuit.

[0074] The control circuit 111b may be electrically connected to the read / write circuit 111a to control the read / write circuit 111a. In some examples, the control circuit 111b may also be electrically connected to other circuits (eg, a power supply circuit) other than the read / write circuit 111a.

[0075] In some examples, the functional circuit 111 (including the read / write circuit 111a and the control circuit 111b) and the storage particles (including the first storage particles 101 and the second storage particles 102) can be electrically connected one by one, and one functional circuit 111 controls one storage particle. In other examples, one functional circuit 111 can be electrically connected to at least two storage particles, that is, the first storage particle 101 and the second storage particle 102 can share the same functional circuit 111, so as to reduce the number of functional circuits 111 and reduce the cost of the semiconductor device 100.

[0076] In some examples, such as Figure 3 and Figure 4 As shown, the functional layer 110 has a first side, the first storage particles 101 and the second storage particles 102 are located on the first side of the functional layer 110 , and the first storage particles 101 and the second storage particles 102 are hybrid bonded to the functional layer 110 respectively.

[0077] It can be understood that the first storage particles 101 and the second storage particles 102 are both located on the first side of the functional layer 110 , that is, the first storage particles 101 and the second storage particles 102 are located on the same side of the functional layer 110 , which improves the structural regularity of the semiconductor device 100 .

[0078] The first storage particle 101 and the second storage particle 102 are respectively hybrid-bonded to the functional layer 110 to realize Die to Wafer Bonding (Chinese: storage particle and wafer hybrid bonding), so that the first storage particle 101 and the second storage particle 102 can be electrically connected to the functional circuit 111 respectively by hybrid bonding, so that the functional circuit 111 can control the first storage particle 101 and the second storage particle 102 to perform operations such as reading and writing data.

[0079] In the embodiment of the present disclosure, the first storage particle 101 and the second storage particle 102 are arranged on the first side of the functional layer 110, so that the first storage particle 101 and the second storage particle 102 can be located on the same side of the functional layer 110, thereby improving the structural regularity of the semiconductor device 100. The first storage particle 101 and the second storage particle 102 are arranged to be hybrid-bonded with the functional layer 110, respectively, so that the first storage particle 101 and the second storage particle 102 can be electrically connected to the functional circuit 111 respectively by hybrid bonding, so that the functional circuit 111 can control the first storage particle 101 and the second storage particle 102 to perform operations such as writing and reading data, thereby enabling the semiconductor device 100 to realize the storage function.

[0080] Furthermore, the first storage particle 101 and the second storage particle 102 are respectively hybrid-bonded with the functional layer 110, which can reduce the distance between the first storage particle 101 and the second storage particle 102, shorten the transmission path of data when being transmitted between the first storage particle 101 and the second storage particle 102, increase the transmission bandwidth between the first storage particle 101 and the second storage particle 102, and realize high-speed transmission of data between the first storage particle 101 and the second storage particle 102. Furthermore, reducing the distance between the first storage particle 101 and the second storage particle 102 can also improve the integration of the semiconductor device 100, reduce the volume of the semiconductor device 100, and facilitate the miniaturization of the semiconductor device 100.

[0081] In addition, the first storage particles 101 and the second storage particles 102 are mixed and bonded with the functional layer 110 respectively, which can achieve high integration among the first storage particles 101, the second storage particles 102 and the functional circuit 111, improve the integration of the semiconductor device 100, and facilitate the miniaturization of the semiconductor device 100.

[0082] It can be understood that the embodiment of the present disclosure arranges the first storage particles 101 and the second storage particles 102 to be hybrid-bonded with the functional layer 110 , respectively, so as to realize a semiconductor device 100 with high integration and high bandwidth.

[0083] In some examples, the first storage particle 101 may include a flash storage particle, and the second storage particle 102 may include a memory storage particle.

[0084] For example, the storage capacity of flash memory (English: Flash) storage particles is greater than the storage capacity of memory storage particles, and the read and write speed of memory storage particles is greater than the read and write speed of flash memory storage particles.

[0085] It can be understood that the first storage particles 101 include flash memory storage particles, and the second storage particles 102 include memory storage particles, so that the flash memory storage particles and the memory storage particles can be hybrid-bonded with the functional layer 110 respectively, so that the semiconductor device 100 can achieve heterogeneous integration based on the Xtacking architecture.

[0086] In this way, the flash memory storage particles and the memory storage particles can be combined with each other to make up for each other's shortcomings, so that the semiconductor device 100 can take into account the advantages of both the flash memory storage particles and the memory storage particles, that is, the semiconductor device 100 can have a larger storage capacity and a faster read and write speed, thereby improving the storage performance of the semiconductor device 100 and reducing the loading and refreshing of the L2P table (full name: Logical to Physical, Chinese name: Logical-Physical Conversion Table).

[0087] For example, cold data (i.e., data with low usage frequency) can be stored in flash storage particles, and hot data (i.e., data with high usage frequency) can be stored in memory storage particles. In this way, cold data and hot data can be retrieved by accessing the semiconductor device 100, which reduces unnecessary transfer between cold data and hot data and improves the endurance of the semiconductor device 100.

[0088] In some examples, the memory storage particles can be used as a cache to replace the DRAM (Dynamic Random Access Memory) in the storage system 200, so that the semiconductor device 100 can have its own high-performance cache performance, improve the storage performance of the semiconductor device 100, and increase the advantages of the semiconductor device 100 in high-end application scenarios (such as artificial intelligence, storage and computing integration, etc.).

[0089] It can be understood that by using memory storage particles as cache to replace the DRAM in the storage system 200, there is no need to set up additional DRAM in the storage system 200. On the one hand, it can reduce the number of devices in the storage system 200, which is conducive to the miniaturization of the storage system 200, that is, it is conducive to the miniaturization of the electronic device 300; on the other hand, due to the high cost of DRAM, compared with setting up separately packaged DRAM, setting memory storage particles instead of DRAM can reduce the cost of the storage system 200, thereby reducing the cost of the electronic device 300.

[0090] In addition, since the distance between the memory storage particles and the flash memory storage particles is shorter and the data transmission speed is higher, setting the memory storage particles instead of DRAM can improve the data processing speed of the storage system 200 and improve the performance of the storage system 200.

[0091] In some examples, the first storage particle 101 may include a 3D NAND storage particle, and the second storage particle 102 may include a 3D Fe RAM storage particle (Chinese name: three-dimensional ferroelectric storage particle).

[0092] For example, the storage capacity of 3D NAND storage particles is greater than the storage capacity of 3D FeRAM storage particles, and the read and write speed of 3D FeRAM storage particles is greater than the read and write speed of 3D NAND storage particles.

[0093] It can be understood that the first storage particles 101 are configured to include 3D NAND storage particles, and the second storage particles 102 are configured to include 3D Fe RAM storage particles, so that the 3D NAND storage particles and the 3D Fe RAM storage particles can be hybrid-bonded with the functional layer 110 respectively, so that the semiconductor device 100 can achieve heterogeneous integration based on the Xtacking architecture.

[0094] In this way, 3D NAND storage particles and 3D Fe RAM storage particles can be combined with each other to make up for each other's shortcomings, so that the semiconductor device 100 can take into account the advantages of 3D NAND storage particles and 3DFe RAM storage particles, that is, the semiconductor device 100 can have a larger storage capacity and a faster read and write speed, improve the performance of the semiconductor device 100, and reduce the loading and refreshing of the L2P table (English full name: Logical to Physical, Chinese name: Logical-Physical Conversion Table).

[0095] For example, cold data (i.e., data with low usage frequency) can be stored in 3D NAND storage particles, and hot data (i.e., data with high usage frequency) can be stored in 3D Fe RAM storage particles. In this way, cold data and hot data can be retrieved by accessing the semiconductor device 100, which reduces unnecessary transfer between cold data and hot data and improves the endurance of the semiconductor device 100.

[0096] In some examples, the 3D Fe RAM storage particles, as SLC (full name: Single-Level Cell, Chinese name: single-layer unit flash memory), have the advantage of high speed and can be used as a cache of the semiconductor device 100 to replace the DRAM (full name: Dynamic Random Access Memory, Chinese name: dynamic random access memory) in the storage system 200, to achieve a high-performance memory product of 3D NAND storage particles + 3D FeRAM storage particles, and increase the advantages of the semiconductor device 100 in high-end application scenarios (such as artificial intelligence, storage and computing integration, etc.).

[0097] It can be understood that by using 3D Fe RAM storage particles as cache to replace the DRAM in the storage system 200, there is no need to set up additional DRAM in the storage system 200. On the one hand, the number of devices in the storage system 200 can be reduced, which is conducive to the miniaturization of the storage system 200, that is, it is conducive to the miniaturization of the electronic device 300; on the other hand, due to the high cost of DRAM, compared with setting up separately packaged DRAM, setting up 3D Fe RAM storage particles instead of DRAM can reduce the cost of the storage system 200, thereby reducing the cost of the electronic device 300.

[0098] In addition, since the distance between the 3D Fe RAM storage particles and the 3D NAND storage particles is shorter and the data transmission speed is higher, setting 3D Fe RAM storage particles instead of DRAM can increase the data processing speed of the storage system 200 and improve the performance of the storage system 200.

[0099] In some examples, the storage capacity of the first storage particle 101 is greater than the storage capacity of the second storage particle 102 , and the read and write speed of the second storage particle 102 is greater than the read and write speed of the first storage particle 101 .

[0100] It can be understood that the first storage particle 101 and the second storage particle 102 are respectively hybrid-bonded with the functional layer 110, so that the semiconductor device 100 can achieve heterogeneous integration based on the Xtacking architecture. In this way, the first storage particle 101 and the second storage particle 102 can be combined with each other to make up for each other's shortcomings, so that the semiconductor device 100 can take into account the advantages of the first storage particle 101 and the second storage particle 102, that is, the semiconductor device 100 can have a larger storage capacity and a faster read and write speed, improve the storage performance of the semiconductor device 100, and reduce the loading and refreshing of the L2P table (English full name: Logical to Physical, Chinese name: Logical Physical Conversion Table).

[0101] For example, cold data (i.e., data with low usage frequency) can be stored in the first storage particle 101, and hot data (i.e., data with high usage frequency) can be stored in the second storage particle 102. In this way, cold data and hot data can be retrieved by accessing the semiconductor device 100, which reduces unnecessary transfer between cold data and hot data and improves the endurance of the semiconductor device 100.

[0102] In some examples, the second storage particle 102 can be used as a cache to replace the DRAM (full name: Dynamic Random Access Memory, Chinese name: dynamic random access memory) in the storage system 200, so that the semiconductor device 100 can have its own high-performance cache performance, improve the storage performance of the semiconductor device 100, and increase the advantages of the semiconductor device 100 in high-end application scenarios (such as artificial intelligence, storage and computing integration, etc.).

[0103] It can be understood that by using the second storage particle 102 as a cache to replace the DRAM in the storage system 200, there is no need to set up an additional DRAM in the storage system 200. On the one hand, it can reduce the number of devices in the storage system 200, which is beneficial to the miniaturization of the storage system 200, that is, it is beneficial to the miniaturization of the electronic device 300; on the other hand, due to the high cost of DRAM, compared with setting up a separately packaged DRAM, setting up the second storage particle 102 to replace the DRAM can reduce the cost of the storage system 200, thereby reducing the cost of the electronic device 300.

[0104] In addition, since the distance between the second storage particle 102 and the first storage particle 101 is shorter and the data transmission speed is higher, providing the second storage particle 102 instead of DRAM can increase the data processing speed of the storage system 200 and improve the performance of the storage system 200.

[0105] Figure 5 A structural block diagram of a storage system provided for some embodiments of the present disclosure. Figure 6 A structural block diagram of a storage system provided for some other embodiments of the present disclosure.

[0106] In the related art, the storage system 200 needs to set up DRAM to store the mapping table, and set up a part of the area in the 3D NAND storage chip as SLC BLK (Chinese: single-layer unit flash memory storage block) to store system information and thermal data of the electronic device 200.

[0107] In the embodiment of the present disclosure, a semiconductor device 100 is provided to include a first storage particle 101 and a second storage particle 102, and the first storage particle 101 may be a 3D NAND storage particle, and the second storage particle 102 may be a 3D Fe RAM storage particle, so that the semiconductor device 100 can store a mapping table, system information, thermal data, etc. For example, Figure 5 As shown, the 3D Fe RAM storage particles in the semiconductor device 100 can replace DRAM to store the mapping table. At this time, the dynamic random access memory controller (English: DRAM Controller) can be electrically connected to the 3D Fe RAM storage particles in the semiconductor device 100.

[0108] For example, Figure 6 As shown, the 3D NAND storage particles in the semiconductor device 100 can replace the 3D NAND storage chip to store system information and thermal data of the electronic device 200. At this time, the NADN controller (English: NADAController) can be electrically connected to the 3D NAND storage particles in the semiconductor device 100. In some examples, a part of the area in the 3D NAND storage particle can be used as an SLC BLK to store system information and thermal data.

[0109] It can be understood that 3D Fe RAM storage particles are set instead of DRAM to store mapping tables, and 3D NAND storage particles are set instead of 3D NAND storage chips to store system information and thermal data of the electronic device 200. In this way, there is no need to set up additional DRAM to store mapping tables, nor is there a need to set up additional 3D NAND storage chips to store system information and thermal data, which simplifies the structure of the storage system 200, reduces the cost of the storage system 200, and facilitates the miniaturization of the storage system 200.

[0110] Figure 7 A structural diagram of a die provided for some embodiments of the present disclosure. Figure 8 for Figure 7 A partial enlarged view of the middle M area.

[0111] In some examples, such as Figure 7 and Figure 8 As shown, the first storage particle 101 may include a first dielectric layer 1011 and a first bonding metal 1012 . The first bonding metal 1012 may be located in the first dielectric layer 1011 , and an end surface of the first bonding metal 1012 is exposed to the first dielectric layer 1011 .

[0112] The first dielectric layer 1011 may be an insulating dielectric layer, which plays a role of electrical isolation. For example, the material of the first dielectric layer 1011 may be a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0113] In some examples, such as Figure 7 As shown, the first storage particle 101 may include a first dielectric layer 1011 and a first storage function layer 1013, and the first dielectric layer 1011 and the first storage function layer 1013 are stacked. The first bonding metal 1012 is located in the first dielectric layer 1011. A first storage unit may be provided in the first storage function layer 1013, so that the first storage particle 101 can realize a storage function. The first bonding metal 1012 may be electrically connected to the first storage unit.

[0114] The number of the first bonding metals 1012 may be one or more. When the number of the first bonding metals 1012 is multiple, the multiple first bonding metals 1012 may be arranged in an array. For example, the shape of the first bonding metal 1012 is a cylinder, a truncated cone, a prism, or a truncated cone. The shapes of the multiple first bonding metals 1012 may be the same or different.

[0115] In some examples, the material of the first bonding metal 1012 may include copper. In other examples, the material of the first bonding metal 1012 may also include other conductive metals other than copper, such as gold, silver, iron, or aluminum. When there are multiple first bonding metals 1012, the materials of the multiple first bonding metals 1012 may be the same or different.

[0116] It can be understood that the end surface of the first bonding metal 1012 is exposed to the first dielectric layer 1011 , so that other components (such as the third bonding metal 113 ) can be mixed-bonded with the first bonding metal 1012 through the exposed end surface of the first bonding metal 1012 .

[0117] In some examples, such as Figure 7 As shown, the first bonding metal 1012 may include a first bonding portion 1012a and a first connecting portion 1012b, wherein one end surface of the first bonding portion 1012a is exposed to the first dielectric layer 1011, and is used for mixed bonding with other components (e.g., the third bonding metal 113). One end of the first connecting portion 1012b is electrically connected to the first bonding portion 1012a, and the other end is electrically connected to the first storage function layer 1013 (the first storage unit). In this way, other components (e.g., the third bonding metal 113) can be electrically connected to the first storage function layer 1013 through the first bonding metal 1012.

[0118] like Figure 7 and Figure 8As shown, the second storage particle 102 may include a second dielectric layer 1021 and a second bonding metal 1022 . The second bonding metal 1022 may be located in the second dielectric layer 1021 , and an end surface of the second bonding metal 1022 is exposed to the second dielectric layer 1021 .

[0119] The second dielectric layer 1021 may be an insulating dielectric layer, which plays a role of electrical isolation. For example, the material of the second dielectric layer 1021 may be a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0120] In some examples, such as Figure 7 As shown, the second storage particle 102 may include a second dielectric layer 1021 and a second storage function layer 1023, and the second dielectric layer 1021 and the second storage function layer 1023 are stacked. The second bonding metal 1022 is located in the second dielectric layer 1021. A second storage unit may be provided in the second storage function layer 1023, so that the second storage particle 102 can realize a storage function. The second bonding metal 1022 may be electrically connected to the second storage unit.

[0121] The number of the second bonding metal 1022 may be one or more. When the number of the second bonding metal 1022 is multiple, the multiple second bonding metals 1022 may be arranged in an array. For example, the shape of the second bonding metal 1022 may be a cylinder, a truncated cone, a prism, or a truncated cone. The shapes of the multiple second bonding metals 1022 may be the same or different. The shape and number of the second bonding metal 1022 and the first bonding metal 1012 may be the same or different.

[0122] In some examples, the material of the second bonding metal 1022 may include copper. In other examples, the material of the second bonding metal 1022 may also include other conductive metals other than copper, such as gold, silver, iron, or aluminum. When there are multiple second bonding metals 1022, the materials of the multiple second bonding metals 1022 may be the same or different. The material of the first bonding metal 1012 may be the same as or different from the material of the second bonding metal 1022.

[0123] It can be understood that the end surface of the second bonding metal 1022 is exposed to the second dielectric layer 1021 , so that other components (such as the fourth bonding metal 114 ) can be mixed-bonded with the second bonding metal 1022 through the exposed end surface of the second bonding metal 1022 .

[0124] In some examples, such as Figure 7 and Figure 8As shown, the second bonding metal 1022 may include a second bonding portion 1022a and a second connecting portion 1022b, and one end surface of the second bonding portion 1022a is exposed to the second dielectric layer 1021 for mixed bonding with other components (e.g., the fourth bonding metal 114). One end of the second connecting portion 1022b is electrically connected to the second bonding portion 1022a, and the other end is electrically connected to the second storage function layer 1023 (the second storage unit). In this way, other components (e.g., the fourth bonding metal 114) can be electrically connected to the second storage function layer 1023 through the second bonding metal 1022.

[0125] like Figure 7 and Figure 8 As shown, the functional layer 110 may include a third dielectric layer 112, a third bonding metal 113, and a fourth bonding metal 114. The third bonding metal 113 and the fourth bonding metal 114 are located in the third dielectric layer 112, and the end surfaces of the third bonding metal 113 and the fourth bonding metal 114 are exposed to the third dielectric layer 112. The third bonding metal 113 and the fourth bonding metal 114 are electrically connected to the functional circuit 111, respectively.

[0126] like Figure 7 As shown, the first bonding metal 1012 is mixedly bonded with the third bonding metal 113 , and the second bonding metal 1022 is mixedly bonded with the fourth bonding metal 114 .

[0127] The third dielectric layer 112 may be an insulating dielectric layer, which plays a role of electrical isolation. For example, the material of the third dielectric layer 112 may be a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0128] In some examples, such as Figure 7 As shown, the functional layer 110 may include a third dielectric layer 112 and a circuit functional layer 115, and the third dielectric layer 112 and the circuit functional layer 115 are stacked. The functional circuit 111 may be located in the circuit functional layer 115. The third bonding metal 113 and the fourth bonding metal 114 may be located in the third dielectric layer 112, and the third bonding metal 113 and the fourth bonding metal 114 are electrically connected to the functional circuit 111 located in the circuit functional layer 115, respectively.

[0129] The number of the third bonding metal 113 may be one or more, and the number of the fourth bonding metal 114 may also be one or more. The number of the third bonding metal 113 and the number of the fourth bonding metal 114 may be the same or different. In some examples, the number of the third bonding metal 113 is the same as the number of the first bonding metal 1012, and the number of the fourth bonding metal 114 is the same as the number of the second bonding metal 1022. It can be understood that the third bonding metal 113 and the fourth bonding metal 114 can be arranged in an array in the third dielectric layer 112.

[0130] For example, the shape of the third bonding metal 113 may be a cylinder, a truncated cone, a prism or a truncated pyramid, etc. The shape of the fourth bonding metal 114 may be a cylinder, a truncated cone, a prism or a truncated pyramid, etc. The shape of the third bonding metal 113 and the shape of the fourth bonding metal 114 may be the same or different.

[0131] For example, the material of the third bonding metal 113 may include copper; the material of the third bonding metal 113 may also include other conductive metals other than copper, such as gold, silver, iron, or aluminum. When there are multiple third bonding metals 113, the materials of the multiple third bonding metals 113 may be the same or different. The material of the fourth bonding metal 114 may include copper; the material of the fourth bonding metal 114 may also include other conductive metals other than copper, such as gold, silver, iron, or aluminum. When there are multiple fourth bonding metals 114, the materials of the multiple fourth bonding metals 114 may be the same or different. The material of the third bonding metal 113 may be the same as or different from the material of the fourth bonding metal 114.

[0132] It can be understood that the end surfaces of the third bonding metal 113 and the fourth bonding metal 114 are both exposed to the third dielectric layer 112, so that the first bonding metal 1012 is exposed to the end surface of the first dielectric layer 1011, and can be mixedly bonded with the end surface of the third bonding metal 113 exposed to the third dielectric layer 112, that is, the first storage particles 101 can be mixedly bonded with the functional layer 110; and, the second bonding metal 1022 is exposed to the end surface of the second dielectric layer 1021, and can be mixedly bonded with the end surface of the fourth bonding metal 114 exposed to the third dielectric layer 112, that is, the second storage particles 102 can be mixedly bonded with the functional layer 110.

[0133] In some examples, such as Figure 7As shown, the third bonding metal 113 may include a third bonding portion 113a and a third connecting portion 113b, and one end surface of the third bonding portion 113a is exposed to the third dielectric layer 112, and is used for mixed bonding with the first bonding metal 1012 (first bonding portion 1012a). One end of the third connecting portion 113b is electrically connected to the third bonding portion 113a, and the other end is electrically connected to the functional circuit 111 located in the circuit function layer 115. In this way, the first storage particle 101 and the functional circuit 111 can be electrically connected through the first bonding metal 1012 and the third bonding metal 113.

[0134] In some examples, such as Figure 7 and Figure 8 As shown, the fourth bonding metal 114 may include a fourth bonding portion 114a and a fourth connecting portion 114b, and one end surface of the fourth bonding portion 114a is exposed to the third dielectric layer 112, and is used for mixed bonding with the second bonding metal 1022 (second bonding portion 1022a). One end of the fourth connecting portion 114b is electrically connected to the fourth bonding portion 114a, and the other end is electrically connected to the functional circuit 111 located in the circuit function layer 115. In this way, the second storage particle 102 and the functional circuit 111 can be electrically connected through the second bonding metal 1022 and the fourth bonding metal 114.

[0135] It can be understood that the first bonding metal 1012 and the third bonding metal 113 are mixed bonded, and the second bonding metal 1022 and the fourth bonding metal 114 are mixed bonded, so that the first storage particles 101 and the second storage particles 102 can be mixed bonded with the functional layer 110 respectively, thereby reducing the mutual influence between the first storage particles 101 and the second storage particles 102 when they are mixed bonded with the functional layer 110.

[0136] Moreover, the first bonding metal 1012 and the third bonding metal 113 can not only play the role of mixed bonding, but also play the role of data transmission, that is, data can be transmitted between the functional circuit 111 and the first storage particle 101 through the first bonding metal 1012 and the third bonding metal 113, which shortens the data transmission path, improves the data transmission speed, and increases the transmission bandwidth between the functional circuit 111 and the first storage particle 101.

[0137] The second bonding metal 1022 and the fourth bonding metal 114 can not only play the role of mixed bonding, but also play the role of data transmission, that is, data can be transmitted between the functional circuit 111 and the second storage particle 102 through the second bonding metal 1022 and the fourth bonding metal 114, which shortens the data transmission path, improves the data transmission speed, and increases the transmission bandwidth between the functional circuit 111 and the second storage particle 102.

[0138] In some examples, the functional layer 110 has a second side, and the second side is disposed opposite to the first side. Figure 4 The semiconductor device 100 may further include a packaging substrate 120 , which is located on the second side of the functional layer 110 . That is, the packaging substrate 120 is located on a side of the functional layer 110 away from the first storage particles 101 and the second storage particles 102 .

[0139] For example, the first storage particle 101 and the second storage particle 102 can be mixed and bonded with the functional layer 110 to form a bare chip 131 (see Figure 7 ), the packaging substrate 120 is used to package the bare die 131. It can be understood that the packaging substrate 120 can play a role in protecting the bare die 131.

[0140] In some examples, such as Figure 4 As shown, the package substrate 120 may include a substrate body 121, a metal ball 122, and a pin 123. The metal ball 122 is located between the functional layer 110 and the substrate body 121, and the metal ball 122 electrically connects the substrate body 121 with the functional circuit 111. The pin 123 is located on a side of the substrate body 121 away from the functional layer 110, and the pin 123 is electrically connected to the substrate body 121.

[0141] It can be understood that the substrate body 121 can protect the bare chip 131. The metal ball 122 is located between the substrate body 121 and the functional layer 110, so that the substrate body 121 and the functional circuit 111 can be electrically connected through the metal ball 122. For example, the number of the metal balls 122 can be multiple, and the multiple metal balls 122 can be arranged in an array.

[0142] like Figure 4 As shown, the pin 123 is located on the side of the substrate body 121 away from the functional layer 110, and is electrically connected to the substrate body 121, so that the pin 123 can be electrically connected to the functional circuit 111 and the storage particles (including the first storage particles 101 and the second storage particles 102) through the substrate body 121 and the metal ball 122. In this way, the electronic components outside the semiconductor device 100 can be electrically connected to the functional circuit 111 and the storage particles through the pin 123, thereby improving the convenience of use of the semiconductor device 100. For example, the number of pins 123 can be multiple, and the multiple pins 123 can be arranged in an array.

[0143] On the other hand, embodiments of the present disclosure provide a method for manufacturing a semiconductor device. In some examples, the method for manufacturing a semiconductor device can be used to manufacture the semiconductor device 100 as described above.

[0144] Fig. 9A flow chart of the steps of a method for preparing a semiconductor device provided in some embodiments of the present disclosure.

[0145] In some examples, such as Fig. 9 As shown, the method for preparing a semiconductor device includes:

[0146] Step S101: providing a first storage particle and a second storage particle.

[0147] For example, the storage particles (including the first storage particles 101 and the second storage particles 102) may be three-dimensional storage particles. The storage type of the first storage particles 101 and the storage type of the second storage particles 102 may be the same or different. In some examples, a plurality of first storage particles 101 and a plurality of second storage particles 102 may be provided.

[0148] It is understandable that the above embodiments of the present disclosure have illustrated the first storage particle 101 and the second storage particle 102, which will not be described in detail. The following is an example of a method for preparing the first storage particle 101 and a method for preparing the second storage particle 102.

[0149] Fig.10 A flowchart of steps of a method for preparing a semiconductor device provided in some other embodiments of the present disclosure. Fig.11 A structural diagram of a first wafer provided for some embodiments of the present disclosure. Fig.12 A structural diagram of a second wafer provided for some embodiments of the present disclosure.

[0150] In some examples, such as Fig.10 As shown, providing a first storage particle and a second storage particle (that is, step S101) includes:

[0151] Step S1011, providing a first wafer and a second wafer.

[0152] For example, the material of the wafer (first wafer 151 or second wafer 152) may include silicon or doped silicon. The material of the first wafer 151 and the material of the second wafer 152 may be the same or different. The size of the first wafer 151 and the size of the second wafer 152 may be the same or different.

[0153] Step S1012, forming a plurality of first storage units on the first wafer, and forming a plurality of second storage units on the second wafer.

[0154] For example, the first storage unit 1511 may be a three-dimensional storage unit. Fig.11 As shown, a plurality of first storage units 1511 may be arranged in an array. The second storage unit 1521 may be a three-dimensional storage unit. Fig.12 As shown, a plurality of second storage units 1521 may be arranged in an array.

[0155] It can be understood that the number of the first storage units 1511 formed on the first wafer 151 and the number of the second storage units 1521 formed on the second wafer 152 may be the same or different.

[0156] Fig.13 A diagram showing the positional relationship between the first storage particles and the first carrier provided for some embodiments of the present disclosure. Fig.14 A positional relationship diagram of the second storage particles and the second carrier is provided for some purposes of the present invention.

[0157] Step S1013 , cutting the first wafer to form first storage particles including first storage units.

[0158] For example, Fig.13 As shown, the first wafer 151 can be placed on the first carrier 161, and then the first wafer 151 is cut and split by laser cutting (English: Wafer Dicing), so that the multiple first storage units 1511 can be separated from each other to form a first storage particle 101 including the first storage unit 1511. It can be understood that the first storage particle 101 can include one first storage unit 1511; the first storage particle 101 can also include multiple first storage units 1511.

[0159] It can be understood that the first carrier 161 can support the first wafer 151, reduce the risk of the first wafer 151 breaking during cutting, and improve the reliability of the method for preparing the semiconductor device.

[0160] Step S1014, cutting the second wafer to form second storage particles including second storage units.

[0161] For example, Fig.14 As shown, the second wafer 152 can be placed on the second carrier 162, and then the second wafer 152 can be cut and split by laser cutting, so that the plurality of second storage units 1521 can be separated from each other to form a second storage particle 102 including the second storage unit 1521. It can be understood that the second storage particle 102 can include one second storage unit 1521; the second storage particle 102 can also include a plurality of second storage units 1521.

[0162] It can be understood that the second carrier 162 can support the second wafer 152, reduce the risk of the second wafer 152 breaking during cutting, and improve the reliability of the method for preparing the semiconductor device.

[0163] It can be understood that the steps of cutting the first wafer 151 and the steps of cutting the second wafer 152 are performed separately, that is, the first wafer 151 can be cut first to form the first storage particle 101, and then the second wafer 152 can be cut to form the second storage particle 102; or, the second wafer 152 can be cut first to form the second storage particle 102, and then the first wafer 151 can be cut to form the first storage particle 101; or, the first wafer 151 and the second wafer 152 can be cut at the same time, so that the first wafer 151 can form the first storage particle 101, and the second wafer 152 can form the second storage particle 102.

[0164] After providing the first storage particle 101 and the second storage particle 102 (that is, after step S101), the method for preparing the semiconductor device further includes:

[0165] Step S102, providing a functional layer, the functional layer including a functional circuit. The functional layer has a first side, and the first storage particles and the second storage particles are located on the first side of the functional layer.

[0166] It can be understood that the first storage particles 101 and the second storage particles 102 are located on a first side of the functional layer 110 , that is, the first storage particles 101 and the second storage particles 102 are located on the same side of the functional layer 110 , which improves the structural regularity of the semiconductor device 100 .

[0167] Fig.15 A structural diagram of a third wafer provided for some embodiments of the present disclosure.

[0168] In some examples, the method of providing the functional layer 110 (ie, step S102) includes:

[0169] Step S1021, providing a third wafer.

[0170] For example, the material of the third wafer 153 may include silicon or doped silicon. The materials of the first wafer 151, the second wafer 152 and the third wafer 153 may be the same or different. The sizes of the first wafer 151, the second wafer 152 and the third wafer 153 may be the same or different.

[0171] Step S1022, forming a functional circuit in the third wafer to form a functional mother layer.

[0172] like Fig.15 As shown, a plurality of functional circuits 111 may be formed on the third wafer 153, and the plurality of functional circuits 111 may be arranged in an array. It can be understood that the functional layer 110 is a part of the functional mother layer 110a.

[0173] After providing the functional layer 110 (that is, after step S102), the method for preparing the semiconductor device further includes:

[0174] Step S103 , hybrid bonding the first storage particles and the second storage particles to the functional layer respectively.

[0175] The first storage particle 101 and the second storage particle 102 are respectively hybrid-bonded with the functional layer 110 (functional mother layer 110a) to realize Die to Wafer Bonding (Chinese: storage particle and wafer hybrid bonding), so that the first storage particle 101 and the second storage particle 102 can be electrically connected to the functional circuit 111 respectively by hybrid bonding, so that the functional circuit 111 can control the first storage particle 101 and the second storage particle 102 to perform operations such as reading and writing data.

[0176] Furthermore, the first storage particle 101 and the second storage particle 102 are respectively hybrid-bonded with the functional layer 110, which can reduce the distance between the first storage particle 101 and the second storage particle 102, shorten the transmission path of data when being transmitted between the first storage particle 101 and the second storage particle 102, increase the transmission bandwidth between the first storage particle 101 and the second storage particle 102, and realize high-speed transmission of data between the first storage particle 101 and the second storage particle 102. Furthermore, reducing the distance between the first storage particle 101 and the second storage particle 102 can also improve the integration of the semiconductor device 100, reduce the volume of the semiconductor device 100, and facilitate the miniaturization of the semiconductor device 100.

[0177] In addition, the first storage particles 101 and the second storage particles 102 are mixed and bonded with the functional layer 110 respectively, which can achieve high integration among the first storage particles 101, the second storage particles 102 and the functional circuit 111, improve the integration of the semiconductor device 100, and facilitate the miniaturization of the semiconductor device 100.

[0178] In some examples, the first storage particle 101 includes a flash storage particle, and the second storage particle 102 includes a memory storage particle. In some examples, the first storage particle 101 includes a 3D NAND storage particle, and the second storage particle 102 includes a 3D Fe RAM storage particle. In some examples, the storage capacity of the first storage particle 101 is greater than the storage capacity of the second storage particle 102, and the storage speed of the second storage particle 102 is greater than the storage speed of the first storage particle 101.

[0179] Such a configuration enables the first storage particle 101 and the second storage particle 102 to be combined with each other, so that the semiconductor device 100 can achieve heterogeneous integration based on the Xtacking architecture to make up for the shortcomings of each other, so that the semiconductor device 100 can take into account the advantages of flash memory storage particles and the advantages of memory storage particles, that is, the semiconductor device 100 can have a larger storage capacity and a faster read and write speed, improve the performance of the semiconductor device 100, and reduce the loading and refreshing of the L2P table (full name in English: Logical to Physical, Chinese name: Logical-Physical Conversion Table).

[0180] For example, cold data (i.e., data with low usage frequency) can be stored in the first storage particle 101, and hot data (i.e., data with high usage frequency) can be stored in the second storage particle 102. In this way, cold data and hot data can be retrieved by accessing the semiconductor device 100, which reduces unnecessary transfer between cold data and hot data and improves the endurance of the semiconductor device 100.

[0181] In some examples, the second storage particle 102 can be used as a cache to replace the DRAM (full name: Dynamic Random Access Memory, Chinese name: dynamic random access memory) in the storage system 200, so that the semiconductor device 100 can have its own high-performance cache performance, improve the storage performance of the semiconductor device 100, and increase the advantages of the semiconductor device 100 in high-end application scenarios (such as artificial intelligence, storage and computing integration, etc.).

[0182] It can be understood that by using the second storage particle 102 as a cache to replace the DRAM in the storage system 200, there is no need to set up an additional DRAM in the storage system 200. On the one hand, it can reduce the number of devices in the storage system 200, which is beneficial to the miniaturization of the storage system 200, that is, it is beneficial to the miniaturization of the electronic device 300; on the other hand, due to the high cost of DRAM, compared with setting up a separately packaged DRAM, setting up the second storage particle 102 to replace the DRAM can reduce the cost of the storage system 200, thereby reducing the cost of the electronic device 300.

[0183] In addition, since the distance between the second storage particle 102 and the first storage particle 101 is shorter and the data transmission speed is higher, providing the second storage particle 102 instead of DRAM can increase the data processing speed of the storage system 200 and improve the performance of the storage system 200.

[0184] In some examples, the first storage particle 101 may include a first dielectric layer 1011 and a first bonding metal 1012, the first bonding metal 1012 may be located in the first dielectric layer 1011, and an end surface of the first bonding metal 1012 is exposed to the first dielectric layer 1011. The second storage particle 102 may include a second dielectric layer 1021 and a second bonding metal 1022, the second bonding metal 1022 may be located in the second dielectric layer 1021, and an end surface of the second bonding metal 1022 is exposed to the second dielectric layer 1021.

[0185] The functional layer 110 may include a third dielectric layer 112, a third bonding metal 113, and a fourth bonding metal 114. The third bonding metal 113 and the fourth bonding metal 114 are located in the third dielectric layer 112, and the end surfaces of the third bonding metal 113 and the fourth bonding metal 114 are exposed to the third dielectric layer 112. The third bonding metal 113 and the fourth bonding metal 114 are electrically connected to the functional circuit 111, respectively.

[0186] It can be understood that the above embodiments of the present disclosure have illustrated the materials, structures, and positional relationships of the first dielectric layer 1011, the first bonding metal 1012, the second dielectric layer 1021, the second bonding metal 1022, the third dielectric layer 112, the third bonding metal 113, and the fourth bonding metal 114, which will not be described in detail here. The following is an example of how the first bonding metal 1012, the second bonding metal 1022, the third bonding metal 113, and the fourth bonding metal 114 are formed.

[0187] In some examples, a first sub-dielectric layer may be formed on one side of the first storage function layer 1013, a first connecting portion 1012b may be formed in the first sub-dielectric layer, and the first connecting portion 1012b may be electrically connected to the first storage function layer 1013 (first storage unit). Afterwards, a second sub-dielectric layer may be formed on a side of the first sub-dielectric layer away from the first storage function layer 1013, a first bonding portion 1012a may be formed in the second sub-dielectric layer, and the first bonding portion 1012a may be electrically connected to the first connecting portion 1012b. It is understandable that the material of the first sub-dielectric layer and the material of the second sub-dielectric layer may be the same to form the first dielectric layer 1011.

[0188] In some examples, a third sub-dielectric layer may be formed on one side of the second storage functional layer 1023, a second connecting portion 1022b may be formed in the third sub-dielectric layer, and the second connecting portion 1022b may be electrically connected to the second storage functional layer 1023 (second storage unit). Afterwards, a fourth sub-dielectric layer may be formed on a side of the third sub-dielectric layer away from the second storage functional layer 1023, a second bonding portion 1022a may be formed in the fourth sub-dielectric layer, and the second bonding portion 1022a may be electrically connected to the second connecting portion 1022b. It is understandable that the material of the third sub-dielectric layer and the material of the fourth sub-dielectric layer may be the same to form the second dielectric layer 1021.

[0189] In some examples, a fifth sub-dielectric layer may be formed on one side of the circuit function layer 115, and a third connecting portion 113b and a fourth connecting portion 114b may be formed in the fifth sub-dielectric layer, and the third connecting portion 113b and the fourth connecting portion 114b may be electrically connected to the functional circuit 111, respectively. Afterwards, a sixth sub-dielectric layer may be formed on one side of the fifth sub-dielectric layer away from the circuit function layer 115, and a third bonding portion 113a and a fourth bonding portion 114a may be formed in the sixth sub-dielectric layer, and the third bonding portion 113a may be electrically connected to the third connecting portion 113b, and the fourth bonding portion 114a may be electrically connected to the fourth connecting portion 114b. It is understandable that the fifth sub-dielectric layer and the sixth sub-dielectric layer may be made of the same material to form the third dielectric layer 112.

[0190] The first storage particles 101 and the second storage particles 102 are respectively mixed and bonded with the functional layer 110 (that is, step S103), including:

[0191] The first bonding metal 1012 and the third bonding metal 113 are mixed-bonded, and the second bonding metal 1022 and the fourth bonding metal 114 are mixed-bonded.

[0192] It can be understood that the first bonding metal 1012 and the third bonding metal 113 are mixed and bonded, so that the first storage particle 101 can be mixed and bonded with the functional layer 110; the second bonding metal 1022 and the fourth bonding metal 114 are mixed and bonded, so that the second storage particle 102 can be mixed and bonded with the functional layer 110. In this way, the first storage particle 101 and the second storage particle 102 can be mixed and bonded with the functional layer 110 respectively.

[0193] Moreover, the first bonding metal 1012 and the third bonding metal 113 can not only play the role of mixed bonding, but also play the role of data transmission, that is, data can be transmitted between the functional circuit 111 and the first storage particle 101 through the first bonding metal 1012 and the third bonding metal 113, which shortens the data transmission path, improves the data transmission speed, and increases the transmission bandwidth between the functional circuit 111 and the first storage particle 101.

[0194] The second bonding metal 1022 and the fourth bonding metal 114 can not only play the role of mixed bonding, but also play the role of data transmission, that is, data can be transmitted between the functional circuit 111 and the second storage particle 102 through the second bonding metal 1022 and the fourth bonding metal 114, which shortens the data transmission path, improves the data transmission speed, and increases the transmission bandwidth between the functional circuit 111 and the second storage particle 102.

[0195] Fig.16 A flow chart of the steps of a method for preparing a semiconductor device provided in some other embodiments of the present disclosure. Fig.17 A positional relationship diagram of the first storage particles and the machine platform provided for some embodiments of the present disclosure. Fig.18 A positional relationship diagram of the second storage particles and the machine platform provided for some embodiments of the present disclosure. Fig.19 A positional relationship diagram of the first storage particles, the second storage particles and the supporting substrate provided for some embodiments of the present disclosure. Fig. 20 A top view of first storage particles, second storage particles and a supporting substrate provided for some embodiments of the present disclosure. Fig.21 for Fig. 20 Cross-sectional view along direction BB.

[0196] In some examples, such as Fig.16 As shown, the first storage particles 101 and the second storage particles 102 are respectively mixed and bonded with the functional layer 110 (that is, step S103), including:

[0197] Step S1031, providing a carrier substrate.

[0198] It can be understood that the carrier substrate 163 can be a wafer substrate (English: Carrier Wafer), or a glass substrate or a substrate made of other materials.

[0199] Step S1032 , placing the first storage particles and the second storage particles on one side of the carrier substrate.

[0200] For example, Fig.17 As shown, after the first wafer 151 is cut and the first storage particles 101 including the first storage units 1511 are formed, the first storage particles 101 can be picked up by the machine 400 and placed on one side of the supporting substrate 163. Fig.18 As shown, after the second wafer 152 is cut and the second storage particles 102 including the second storage units 1521 are formed, the second storage particles 102 can be picked up by the machine 400 and placed on one side of the supporting substrate 163 .

[0201] It can be understood that a plurality of first storage particles 101 and a plurality of second storage particles 102 may be placed on the carrier substrate 163 , and the plurality of first storage particles 101 and the plurality of second storage particles 102 may be placed on the same side of the carrier substrate 163 .

[0202] In some examples, such as Fig.19 As shown, the first storage particles 101 and the second storage particles 102 may be arranged alternately on the carrier substrate 163. In other examples, the first storage particles 101 and the second storage particles 102 may also be arranged on the carrier substrate 163 in other set orders.

[0203] For example, the machine 400 can pick up the storage particles (including the first storage particles 101 and the second storage particles 102) by bonding, or can pick up the storage particles by vacuum suction. The embodiment of the present disclosure does not further limit the method of picking up the storage particles by the machine.

[0204] In some examples, before cutting the first wafer 151 and the second wafer 152, a protective layer 165 may be formed on the surface of the first wafer 151 and the surface of the second wafer 152. Fig.17 and Fig.18 As shown, after cutting the first wafer 151 and the second wafer 152, the protective layer 165 can cover the surface of the first storage particle 101 and the surface of the second storage particle 102. In this way, in the process of picking up the storage particles (including the first storage particles 101 and the second storage particles 102), the machine 400 will not directly contact the storage particles, so that the protective layer 165 can protect the storage particles, reduce the risk of damage to the storage particles caused by the picking process, and improve the reliability of the method for preparing the semiconductor device.

[0205] It can be understood that after the first storage particles 101 and the second storage particles 102 are placed on one side of the carrier substrate 163, the protective layer 165 can be removed. Fig.19 and Fig. 20 As shown, the surfaces of the first storage particles 101 and the second storage particles 102 can be exposed, thereby preventing the protective layer 165 from affecting the subsequent preparation process.

[0206] In some examples, before placing the first storage particle 101 and the second storage particle 102 on one side of the carrier substrate 163 (that is, before step S1032), the method for preparing the semiconductor device further includes:

[0207] An adhesive layer is formed on one surface of the supporting substrate.

[0208] It is understandable that the adhesive layer 164 can play a role of adhesion. For example, the adhesive layer 164 can be formed on one side of the support substrate 163 by coating.

[0209] Placing the first storage particle 101 and the second storage particle 102 on one side of the carrier substrate 163 (that is, in step S1032), including:

[0210] The first storage particles and the second storage particles are placed on the adhesive layer.

[0211] like Fig. 20 and Fig.21 As shown, the first storage particle 101 and the second storage particle 102 are placed on the adhesive layer 164, that is, the first storage particle 101 and the second storage particle 102 are placed on the side of the adhesive layer 164 away from the carrier substrate 163, so that the adhesive layer 164 can bond the first storage particle 101 and the second storage particle 102 to the carrier substrate 163, thereby reducing the risk of relative movement between the first storage particle 101 and the second storage particle 102 and the carrier substrate 163, and improving the reliability of the semiconductor device manufacturing method.

[0212] Fig. 22 A positional relationship diagram of storage particles, a supporting substrate and a functional layer provided for some embodiments of the present disclosure. Fig.23 A diagram showing the positional relationship among storage particles, a supporting substrate and a functional layer provided for some other embodiments of the present disclosure. Fig.24 A structural diagram of a motherboard provided for some embodiments of the present disclosure. Fig.25 The structural diagram of the bare die provided for some other embodiments of the present disclosure.

[0213] After placing the first storage particle 101 and the second storage particle 102 on one side of the carrier substrate 163 (that is, in step S1032), the method for preparing the semiconductor device further includes:

[0214] Step S1033 , under the support of the carrier substrate, the first storage particles and the second storage particles are mixed and bonded with the functional mother layer respectively.

[0215] It can be understood that the supporting substrate 163 can support and protect the first storage particles 101 and the second storage particles 102. Fig.21 and Fig. 22As shown, after placing the first storage particles 101 and the second storage particles 102 on one side of the carrier substrate 163, the carrier substrate 163 can be flipped over so that the storage particles (including the first storage particles 101 and the second storage particles 102) away from the side of the carrier substrate 163 can be mixed and bonded with the functional mother layer 110a, thereby improving the convenience of mixed bonding of the first storage particles 101 and the second storage particles 102 with the functional mother layer 110a respectively.

[0216] Moreover, under the support of the supporting substrate 163, the first storage particles 101 and the second storage particles 102 are respectively hybrid-bonded to the functional mother layer 110a, thereby reducing the risk of damage to the first storage particles 101 or the second storage particles 102 caused by the hybrid bonding process and improving the reliability of the semiconductor device manufacturing method.

[0217] In some examples, a plurality of first storage particles 101 and a plurality of second storage particles 102 may be placed on the carrier substrate 163. In this way, under the support of the carrier substrate 163, the plurality of first storage particles 101 and the plurality of second storage particles 102 can be mixed and bonded with the functional mother layer 110a together, without the need to mix and bond the first storage particles 101 and the second storage particles 102 with the functional mother layer 110a separately, thereby improving the convenience of the semiconductor device preparation method.

[0218] After the first storage particles 101 and the second storage particles 102 are mixed and bonded with the functional mother layer 110a respectively under the support of the carrier substrate 163 (that is, after step S1033), the method for preparing the semiconductor device further includes:

[0219] Step S201, removing the carrier substrate.

[0220] like Fig.23 As shown, after the first storage particles 101 and the second storage particles 102 are respectively mixed and bonded with the functional mother layer 110a, the carrier substrate 163 and the adhesive layer 164 can be separated (English: Carrier substrate Debonding) to remove the carrier substrate 163 to prevent the carrier substrate 163 from affecting the subsequent preparation process.

[0221] For example, Fig.24 As shown, after removing the carrier substrate 163 , the adhesive layer 164 may be removed (English: Adhesive layer removal) to prevent the adhesive layer 164 from affecting subsequent preparation processes.

[0222] In some examples, such as Fig.25As shown, after removing the carrier substrate 163 and the adhesive layer 164 , the structure consisting of the functional layer 110 and the plurality of first storage particles 101 and the plurality of second storage particles 102 mixed and bonded with the functional layer 110 can be called a motherboard 132 .

[0223] Step S202, cutting the motherboard to form a bare chip. The motherboard includes a functional mother layer and first and second storage particles mixed and bonded with the functional mother layer. The bare chip includes a functional layer formed by cutting the functional mother layer, and first and second storage particles mixed and bonded with the functional layer.

[0224] For example, Fig.24 and Fig.25 As shown, the functional mother layer 110a in the motherboard 132 can be cut by laser cutting to form a bare chip 131. The bare chip 131 includes a functional layer 110 formed after cutting the functional mother layer 110a, and first storage particles 101 and second storage particles 102 mixed and bonded with the functional layer 110.

[0225] It can be understood that the motherboard 132 is cut so that the bare chips 131 can be independent of each other, thereby avoiding mutual influence between different bare chips 131 and improving the reliability of the method for preparing the semiconductor device.

[0226] In some examples, the functional layer has a second side, and the second side is arranged opposite to the first side. After cutting the motherboard 132 to form the bare chip 131 (that is, after step S202), the method for preparing the semiconductor device further includes:

[0227] A packaging substrate is provided, wherein the packaging substrate is located on the second side of the functional layer.

[0228] The bare chip is packaged on a packaging substrate. The packaging substrate includes a substrate body, metal balls and pins. The metal balls are located between the functional layer and the substrate body, and the metal balls electrically connect the substrate body to the functional circuit. The pins are located on the side of the substrate body away from the functional layer, and the pins are electrically connected to the substrate body.

[0229] It can be understood that the packaging substrate can play the role of packaging the bare die (see Figure 4 The metal ball 122 is located between the substrate body 121 and the functional layer 110, so that the substrate body 121 and the functional circuit 111 can be electrically connected through the metal ball 122. For example, the number of the metal balls 122 can be multiple, and the multiple metal balls 122 can be arranged in an array.

[0230] The pin 123 is located on a side of the substrate body 121 away from the functional layer 110, and is electrically connected to the substrate body 121, so that the pin 123 can be electrically connected to the functional circuit 111 and the storage particles (including the first storage particles 101 and the second storage particles 102) through the substrate body 121 and the metal ball 122. In this way, the electronic components outside the semiconductor device 100 can be electrically connected to the functional circuit 111 and the storage particles through the pin 123, thereby improving the convenience of use of the semiconductor device 100. For example, the number of pins 123 can be multiple, and the multiple pins 123 can be arranged in an array.

[0231] In summary, the embodiments of the present disclosure have at least the following beneficial effects:

[0232] In the embodiment of the present disclosure, the first storage particle 101 and the second storage particle 102 are arranged on the first side of the functional layer 110, so that the first storage particle 101 and the second storage particle 102 can be located on the same side of the functional layer 110, thereby improving the structural regularity of the semiconductor device 100. The first storage particle 101 and the second storage particle 102 are arranged to be hybrid-bonded with the functional layer 110, respectively, so that the first storage particle 101 and the second storage particle 102 can be electrically connected to the functional circuit 111 respectively by hybrid bonding, so that the functional circuit 111 can control the first storage particle 101 and the second storage particle 102 to perform operations such as writing and reading data, thereby enabling the semiconductor device 100 to realize the storage function.

[0233] Furthermore, the first storage particle 101 and the second storage particle 102 are respectively hybrid-bonded with the functional layer 110, which can reduce the distance between the first storage particle 101 and the second storage particle 102, shorten the transmission path of data when being transmitted between the first storage particle 101 and the second storage particle 102, increase the transmission bandwidth between the first storage particle 101 and the second storage particle 102, and realize high-speed transmission of data between the first storage particle 101 and the second storage particle 102. Furthermore, reducing the distance between the first storage particle 101 and the second storage particle 102 can also improve the integration of the semiconductor device 100, reduce the volume of the semiconductor device 100, and facilitate the miniaturization of the semiconductor device 100.

[0234] In addition, the first storage particles 101 and the second storage particles 102 are mixed and bonded with the functional layer 110 respectively, which can achieve high integration among the first storage particles 101, the second storage particles 102 and the functional circuit 111, improve the integration of the semiconductor device 100, and facilitate the miniaturization of the semiconductor device 100.

[0235] That is, the embodiment of the present disclosure arranges the first storage particles 101 and the second storage particles 102 to be hybrid-bonded with the functional layer 110 , respectively, so as to realize a semiconductor device 100 with high integration and high bandwidth.

[0236] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: first storage particles and second storage particles; The functional layer comprises a functional circuit; the functional layer has a first side, the first storage particles and the second storage particles are located on the first side of the functional layer, and the first storage particles and the second storage particles are hybrid-bonded to the functional layer respectively.

2. The semiconductor device according to claim 1, wherein: The first storage particles include flash memory storage particles, and the second storage particles include memory storage particles.

3. The semiconductor device according to claim 1, wherein: The first storage particles include 3D NAND storage particles, and the second storage particles include 3D Fe RAM storage particles.

4. The semiconductor device according to claim 1, wherein: The storage capacity of the first storage particle is greater than the storage capacity of the second storage particle, and the reading and writing speed of the second storage particle is greater than the reading and writing speed of the first storage particle.

5. The semiconductor device according to claim 1, wherein: The first storage particle includes a first dielectric layer and a first bonding metal, wherein the first bonding metal is located in the first dielectric layer, and an end surface of the first bonding metal is exposed to the first dielectric layer; The second storage particle includes a second dielectric layer and a second bonding metal, the second bonding metal is located in the second dielectric layer, and an end surface of the second bonding metal is exposed to the second dielectric layer; The functional layer includes a third dielectric layer, a third bonding metal and a fourth bonding metal; the third bonding metal and the fourth bonding metal are located in the third dielectric layer, and end surfaces of the third bonding metal and the fourth bonding metal are exposed to the third dielectric layer; the third bonding metal and the fourth bonding metal are electrically connected to the functional circuit respectively; The first bonding metal and the third bonding metal are mixed-bonded, and the second bonding metal and the fourth bonding metal are mixed-bonded.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The functional layer has a second side, and the second side is arranged opposite to the first side; The semiconductor device further comprises a packaging substrate, wherein the packaging substrate is located on the second side of the functional layer; The packaging substrate includes a substrate body, a metal ball and a pin; the metal ball is located between the functional layer and the substrate body, and the metal ball electrically connects the substrate body with the functional circuit; the pin is located on a side of the substrate body away from the functional layer, and the pin is electrically connected to the substrate body.

7. A method for preparing a semiconductor device, characterized in that: include: providing first storage particles and second storage particles; providing a functional layer, the functional layer comprising a functional circuit; The functional layer has a first side, and the first storage particles and the second storage particles are located on the first side of the functional layer; The first storage particles and the second storage particles are respectively mixed and bonded with the functional layer.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: The first storage particles include flash memory storage particles, and the second storage particles include memory storage particles.

9. The method for preparing a semiconductor device according to claim 7, characterized in that: The first storage particles include 3D NAND storage particles, and the second storage particles include 3D Fe RAM storage particles.

10. The method for preparing a semiconductor device according to claim 7, characterized in that: The storage capacity of the first storage particle is greater than the storage capacity of the second storage particle, and the reading and writing speed of the second storage particle is greater than the reading and writing speed of the first storage particle.

11. The method for preparing a semiconductor device according to claim 7, characterized in that: The first storage particle comprises a first dielectric layer and a first bonding metal, the first bonding metal is located in the first dielectric layer, and an end surface of the first bonding metal is exposed to the first dielectric layer; the second storage particle comprises a second dielectric layer and a second bonding metal, the second bonding metal is located in the second dielectric layer, and an end surface of the second bonding metal is exposed to the second dielectric layer; the functional layer comprises a third dielectric layer, a third bonding metal and a fourth bonding metal; the third bonding metal and the fourth bonding metal are located in the third dielectric layer, and an end surface of the third bonding metal and the fourth bonding metal is exposed to the third dielectric layer; the third bonding metal and the fourth bonding metal are electrically connected to the functional circuit respectively; The step of hybrid bonding the first storage particles and the second storage particles to the functional layer respectively comprises: The first bonding metal and the third bonding metal are mixed-bonded, and the second bonding metal and the fourth bonding metal are mixed-bonded.

12. The method for preparing a semiconductor device according to claim 7, characterized in that: The step of hybrid bonding the first storage particles and the second storage particles to the functional layer respectively comprises: providing a carrier substrate; Placing the first storage particles and the second storage particles on one side of the carrier substrate; Under the support of the carrier substrate, the first storage particles and the second storage particles are mixed and bonded with the functional mother layer respectively; After the first storage particles and the second storage particles are mixed and bonded with the functional mother layer respectively under the support of the carrier substrate, the method further includes: removing the carrier substrate; The motherboard is cut to form bare chips; the motherboard includes the functional mother layer and the first storage particles and the second storage particles mixed and bonded with the functional mother layer; the bare chip includes a functional layer formed by cutting the functional mother layer, and the first storage particles and the second storage particles mixed and bonded with the functional layer.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: The functional layer has a second side, and the second side is arranged opposite to the first side; after the motherboard is cut to form the bare chip, the method further includes: Providing a packaging substrate; the packaging substrate is located on the second side of the functional layer; The bare chip is packaged on the packaging substrate; the packaging substrate includes a substrate body, a metal ball and a pin; the metal ball is located between the functional layer and the substrate body, and the metal ball electrically connects the substrate body with the functional circuit; the pin is located on a side of the substrate body away from the functional layer, and the pin is electrically connected to the substrate body.

14. The method for preparing a semiconductor device according to claim 12, characterized in that: Before placing the first storage particles and the second storage particles on one side of the carrier substrate, the method further includes: forming an adhesive layer on one side surface of the carrier substrate; Placing the first storage particles and the second storage particles on one side of the carrier substrate includes: The first storage particles and the second storage particles are placed on the adhesive layer.

15. The method for preparing a semiconductor device according to any one of claims 7 to 14, characterized in that: The providing the first storage particle and the second storage particle comprises: providing a first wafer and a second wafer; forming a plurality of first storage units on the first wafer, and forming a plurality of second storage units on the second wafer; Cutting the first wafer to form the first storage particles including the first storage units; The second wafer is cut to form the second storage grains including the second storage units.

16. A storage system, characterized in that: include: Semiconductor devices; The semiconductor device is a semiconductor device as claimed in any one of claims 1 to 6; A controller is coupled to the semiconductor device.

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