Electricity storage device

Abstract

A power storage device (50) is provided with: a cell (60); a relay 53 for cutting off the current of the cell 60; a bypass circuit 120 connected in parallel with the relay 53; and a management device (150). The bypass circuit (120) includes two FETs (121, 123) connected back to back. When an abnormality of the cell (60) is detected, the management device (150) turns off the relay (53) (OPEN), turns on one of the two FETs (121, 123) (CLOSE) and turns off the other (OPEN), and makes it possible to discharge or charge the cell (60) through a path passing through a parasitic diode of the FETs. The management device (150) closes (CLOSE) the relay (53) and the other FET (121, 123) that is OFF (OPEN) when the current I and the energization time T of the FETs (121, 123) reach a predetermined condition or the temperature of the FETs (121, 123) reach a predetermined condition when discharging or charging is performed through a path that passes through the parasitic diode, and the management device (150) also closes (CLOSE) the relay (53) and the other FETs (121, 123) that are OFF (OPEN) when the current I and the energization time T of the FETs (121, 123) reach the predetermined condition.

Description

Technical Field

[0001] The present invention relates to a technique for protecting FETs. Background Art

[0002] One of the battery protection devices is a relay. When an abnormality such as over-discharge or over-charge is detected, the battery can be protected by disconnecting the relay to cut off the current. Patent document 1 below discloses that a bypass circuit is provided in parallel with the relay. The bypass circuit is composed of two FETs connected back to back.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: (Japanese) Patent Publication No. 2021-34297 Summary of the invention

[0006] Problems to be solved by the invention

[0007] Consider using a bypass circuit to control charging and discharging when the relay is in the OPEN state.

[0008] Specifically, the parasitic diodes of the first FET and the second FET connected back to back are in opposite directions, the direction of the parasitic diode of the first FET is set to a charging direction, and the direction of the parasitic diode of the second FET is set to a discharging direction.

[0009] In this case, when the relay is in the open state, when the first FET is closed (CLOSE) and the second FET is opened (OPEN), only discharge can be performed through the path passing through the parasitic diode of the second FET.

[0010] Therefore, for example, when overcharging is detected, the relay is opened (OPEN), the first FET is closed (CLOSE), and the second FET is opened (OPEN), so that charging is limited and only discharging is performed through a path via the parasitic diode of the second FET.

[0011] However, since the parasitic diode generates heat when current is passed through it, if a current exceeding an allowable value flows through the parasitic diode for a period of time exceeding a predetermined period, there is a possibility that the FET may fail.

[0012] In addition, in the case of overdischarge, the relay is opened (OPEN), the first FET is opened (OPEN), and the second FET is closed (CLOSE), thereby limiting the discharge and only charging is performed through the path via the parasitic diode of the first FET. In this case, the same problem also exists.

[0013] An object of the present invention is to suppress FET failure caused by heat generation of a parasitic diode.

[0014] Means for solving problems

[0015] The power storage device includes: a cell; a relay for cutting off the current of the cell; a bypass circuit connected in parallel with the relay; and a management device. The bypass circuit includes two FETs connected back to back.

[0016] When an abnormality of the cell is detected, the management device opens the relay, closes one of the two FETs, and opens the other, thereby enabling discharge or charge of the cell through a path passing through the parasitic diode of the FET.

[0017] When discharging or charging is performed through the path via the parasitic diode, when the current I and the power-on time T of the FET reach specified conditions or when the temperature of the FET reaches specified conditions, the management device closes (CLOSE) the relay and the other FET that is open (OPEN).

[0018] When discharging or charging is performed through the path passing through the parasitic diode, when the current I and the power-on time T of the FET reach specified conditions or when the temperature of the FET reaches specified conditions, the management device maintains the relay open (OPEN) and closes (CLOSE) the other open (OPEN) FET.

[0019] Effects of the Invention

[0020] This technology can suppress FET failure caused by heat generation of a parasitic diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a side view of the car.

[0022] Figure 2 This is an exploded perspective view of a battery.

[0023] Figure 3 It is a single floor plan.

[0024] Figure 4 yes Figure 3 AA line cross-section diagram.

[0025] Figure 5 It is a block diagram showing the electrical structure of a battery.

[0026] Figure 6 It is an IT characteristic.

[0027] Figure 7 It is a diagram showing the current path of a battery.

[0028] Figure 8 It is a diagram showing the current path of a battery.

[0029] Fig. 9 It is an IT characteristic.

[0030] Fig.10 It is a flow chart of FET protection processing.

[0031] Fig.11 It is a flow chart of FET protection processing.

[0032] Fig.12 It is a diagram showing the current path of a battery.

[0033] Fig.13 It is a diagram showing the current path of a battery.

[0034] Fig.14 It is a flow chart of FET protection processing.

[0035] Fig.15 It is a block diagram showing the electrical structure of a battery.

[0036] Fig.16 It is a block diagram showing the electrical structure of a battery. DETAILED DESCRIPTION

[0037] The outline of the power storage device will be described.

[0038] (1) A power storage device according to one embodiment of the present invention includes: a cell; a relay for interrupting a current in the cell; a bypass circuit connected in parallel to the relay; and a management device. The bypass circuit includes two FETs connected back to back.

[0039] When an abnormality of the cell is detected, the management device opens the relay, closes one of the two FETs, and opens the other, thereby enabling discharge or charge of the cell through a path passing through the parasitic diode of the FET.

[0040] When discharging or charging is performed through the path via the parasitic diode, when the current I and the power-on time T of the FET reach specified conditions or when the temperature of the FET reaches specified conditions, the management device closes (CLOSE) the relay and the other FET that is open (OPEN).

[0041] The power storage device of (1) above has the following effects. When the relay is in the open (OPEN) state, the FET on one side is opened (OPEN), and the single cell is discharged or charged through the path through the parasitic diode of the open (OPEN) FET. At this time, when there is a risk of FET failure caused by the heat of the parasitic diode, if the relay and the open (OPEN) FET are closed (CLOSE) at the same time, the FET without contacts is closed (CLOSE) earlier than the relay with contacts. By closing (CLOSE) the FET, the current that can be passed through the bypass circuit increases compared to before closing (CLOSE), so that the heating of the FET can be suppressed and the failure of the FET can be suppressed. After the FET is closed (CLOSE), the contacts of the relay are closed (CLOSE) with a delay, but after the contacts of the relay are closed (CLOSE), the current that can be passed through increases further, and most of the current flows through the relay, so that the failure of the FET can be further suppressed.

[0042] (2) A power storage device according to one embodiment of the present invention includes a cell, a relay for interrupting a current in the cell, a bypass circuit connected in parallel to the relay, and a management device. The bypass circuit includes two FETs connected back to back.

[0043] When an abnormality of the cell is detected, the management device opens the relay, closes one of the two FETs, and opens the other, thereby enabling discharge or charge of the cell through a path passing through the parasitic diode of the FET.

[0044] When discharging or charging is performed through the path via the parasitic diode, when the current I and the power-on time T of the FET reach specified conditions or when the temperature of the FET reaches specified conditions, the management device maintains the relay in an open state (OPEN) and closes (CLOSE) the other open (OPEN) FET.

[0045] The power storage device of (2) above has the following effects. When the relay is in the disconnected (OPEN) state, the FET on one side is disconnected (OPEN), and the single cell is discharged or charged through the path through the parasitic diode of the disconnected (OPEN) FET. At this time, when there is a risk of FET failure caused by the heat of the parasitic diode, by closing (CLOSE) the disconnected (OPEN) FET, the current that can be passed through the bypass circuit is increased compared to before the FET is closed (CLOSE). By increasing the current that can be passed through, the heat of the FET can be suppressed, and the failure of the FET can be suppressed. In addition, the relay is maintained in the disconnected (OPEN) state, so that the action sound such as the clicking sound accompanying the opening and closing of the contacts is not generated. Therefore, for example, by applying the present technology to a power storage device mounted on a car, it is possible to expect an effect as a countermeasure against unpleasant sounds (Japanese: unpleasant sounds) while riding in the car.

[0046] (3) In the power storage device described in (1) or (2) above, the abnormality of the cell may be overcharge or overdischarge. In this configuration, the cell can be protected from overcharge and overdischarge and a FET failure countermeasure can be taken.

[0047] (4) In the power storage device described in any one of (1) to (3) above, the power storage device can also be used for engine starting. Since the power storage device for engine starting discharges a large current, if cranking is performed with the relay controlled to be disconnected (OPEN), a large current flows through the parasitic diode of the bypass circuit, and the possibility of FET failure is high. In particular, when overcharged, the single cell voltage tends to become high and the cranking current tends to become large, so the possibility of FET failure is high. By applying the present technology to a power storage device for engine starting that discharges a large current, even if the power storage device is in an overcharged state, it is possible to suppress FET failure and provide a cranking current.

[0048] In the case of overdischarge, the voltage of the cell is low and the current is likely to be low. By turning on the two FETs, the resistance value of the bypass circuit can be reduced, and the voltage drop of the power storage device can be suppressed. Therefore, it is possible to suppress startup failure caused by voltage drop and insufficient current.

[0049] <Implementation method 1>

[0050] 1. Battery 50 Description

[0051] like Figure 1 As shown, the vehicle 10 is equipped with an engine 20 and a battery 50 used for starting the engine 20. The battery 50 is an example of a "power storage device." The vehicle 10 may also be equipped with a power storage device or a fuel cell for driving the vehicle.

[0052] like Figure 2 As shown, the battery 50 includes a battery pack 60, a circuit board unit 65, and a housing 71. The housing 71 includes a main body 73 made of a synthetic resin material and a cover 74. The main body 73 is a bottomed cylindrical shape, and includes a bottom portion 75 and four side portions 76. An opening 77 is formed at the upper end of the main body 73 through the four side portions 76.

[0053] The housing 71 houses the battery pack 60 and the circuit board unit 65. The circuit board unit 65 is a circuit board 100 on which various components (such as the relay 53, Figure 5 The bypass circuit 120 and the management device 150 shown in FIG. Figure 2 As shown, the circuit board unit 65 is disposed adjacent to, for example, the upper side of the battery pack 60. Alternatively, the circuit board unit 65 may be disposed adjacent to the side of the battery pack 60.

[0054] The cover 74 closes the opening 77 of the main body 73. An outer peripheral wall 78 is provided around the cover 74. The cover 74 has a protrusion 79 which is generally T-shaped when viewed from above. A positive external terminal 51 is fixed to one corner of the front part of the cover 74, and a negative external terminal 52 is fixed to the other corner. The circuit substrate unit 65 may be accommodated in the cover 74 (for example, in the protrusion 79) instead of the main body 73 of the housing 71.

[0055] The battery pack 60 is composed of a plurality of cells 62. Figure 4 As shown, the cell 62 is obtained by accommodating an electrode body 83 and a non-aqueous electrolyte in a rectangular parallelepiped (prismatic) case 82. The cell 62 is, for example, a lithium ion secondary battery cell. The case 82 has a case body 84 and a cover 85 that closes an opening on the top thereof.

[0056] Although the details are not shown, the electrode body 83 is an electrode body in which a separator composed of a porous resin film is arranged between a negative electrode plate obtained by coating an active material on a substrate composed of copper foil and a positive electrode plate obtained by coating an active material on a substrate composed of aluminum foil. They are all strip-shaped, and the negative electrode plate and the positive electrode plate are staggered on opposite sides of the width direction relative to the separator, and are wound into a flat state so as to be accommodated in the shell body 84. The electrode body 83 may also be a stacked type instead of a wound type.

[0057] A positive terminal 87 is connected to the positive electrode plate via a positive electrode collector 86, and a negative terminal 89 is connected to the negative electrode plate via a negative electrode collector 88. The positive electrode collector 86 and the negative electrode collector 88 have a flat base portion 90 and a leg portion 91 extending from the base portion 90. A through hole is formed in the base portion 90. The leg portion 91 is connected to the positive electrode plate or the negative electrode plate.

[0058] The positive terminal 87 and the negative terminal 89 are composed of a terminal main body 92 and a shaft 93 protruding downward from the center portion below the terminal main body 92 and the shaft 93 of the positive terminal 87 are integrally formed of aluminum (a single material). In the negative terminal 89, the terminal main body 92 is made of aluminum and the shaft 93 is made of copper, and they are assembled. The terminal main bodies 92 of the positive terminal 87 and the negative terminal 89 are arranged at both ends of the cover 85 via gaskets 94 made of insulating material, such as Figure 3 As shown, the gasket 94 is exposed to the outside.

[0059] The cover 85 has a pressure relief valve 95. The pressure relief valve 95 is located between the positive terminal 87 and the negative terminal 89. The pressure relief valve 95 is a safety valve. The pressure relief valve 95 opens to reduce the internal pressure of the case 82 when the internal pressure of the case 82 exceeds a limit.

[0060] Figure 5 1 is a block diagram showing the electrical configuration of the battery 50 . The battery 50 includes a battery pack 60 , a relay 53 , a voltage detection unit 54 , a current sensor 55 , a temperature sensor 58 , a bypass circuit 120 , and a management device 150 .

[0061] An engine starting device 160 , an electric load 170 such as auxiliary equipment, and a vehicle generator 180 are electrically connected to the battery 50 .

[0062] When the amount of power generated by the vehicle generator 180 is greater than the amount of power consumed by the electrical load 170 during the driving of the engine 20, the battery 50 is charged by the vehicle generator 180. When the amount of power generated by the vehicle generator 180 is less than the amount of power consumed by the electrical load 170, the battery 50 is discharged to compensate for the shortfall.

[0063] When the engine 20 is stopped, the vehicle generator 180 stops generating electricity. When the power generation is stopped, the battery 50 is not charged and is only discharged to the electrical load 170.

[0064] The battery pack 60 includes, for example, 12 cells 62 (see Figure 2 ), 3 are connected in parallel and 4 are connected in series. Figure 5 The three cells 62 connected in parallel are represented by one battery symbol. The cell is not limited to a prismatic cell, and may be a cylindrical cell or a pouch cell having a laminated film casing.

[0065] The battery pack 60, the relay 53, and the current sensor 55 are connected in series via the power supply line 57P and the power supply line 57N. The power supply lines 57P and 55N can use a busbar BSB (see FIG. 1 ) which is a plate-shaped conductor made of a metal material such as copper. Figure 2 ).

[0066] like Figure 5 As shown, the power supply line 57P connects the positive external terminal 51 and the positive electrode of the battery pack 60. The power supply line 57N connects the negative external terminal 52 and the negative electrode of the battery pack 60.

[0067] External terminals 51 and 52 are terminals for connecting battery 50 to automobile 10 (engine starter 160, electric load 170, vehicle generator 180). Battery 50 can be electrically connected to engine starter 160, electric load 170 and vehicle generator 180 via external terminals 51 and 52.

[0068] The current sensor 55 is provided on the negative power supply line 57N. The current sensor 55 may also be a metal plate-shaped resistor (shunt resistor). The current sensor 55 measures the current I of the battery pack 60 based on the voltage Vr across the resistor. The current sensor 55 can distinguish between discharge and charge based on the polarity (positive or negative) of the voltage Vr across the resistor.

[0069] The voltage detection unit 54 measures the cell voltage Vs of each cell 62 and the total voltage Vt of the battery pack 60. The temperature sensor 58 is attached to the battery pack 60 and detects the temperature of the battery pack 60 or its surroundings.

[0070] The relay 53 is provided on the positive power supply line 57P. The relay 53 is preferably a self-holding switch such as a latch relay. This embodiment uses a latch relay.

[0071] The relay 53 is a normally-closed type and is controlled to be closed (CLOSE) in normal conditions. When there is some abnormality in the battery 50, the current I of the battery pack 60 can be cut off by switching the relay 53 from closed (CLOSE) to open (OPEN).

[0072] The bypass circuit 120 includes a first FET 121 and a second FET 123. In this embodiment, P-channel FETs are used for the first FET 121 and the second FET 123. FET is a field effect transistor.

[0073] like Figure 5 As shown, the first FET 121 connects the source S to one end (point A) of the relay 53 , and the second FET 123 connects the source S to the other end (point B) of the relay 53 .

[0074] The drains of the first FET 121 and the second FET 123 are connected to each other, which is a back-to-back connection. The back-to-back connection is to connect the drains of the FETs to each other or the sources to each other.

[0075] The first FET 121 has a parasitic diode D1, and the second FET 123 has a parasitic diode D2. The parasitic diode D1 sets the charging direction to a forward direction, and the parasitic diode D2 sets the discharging direction to a forward direction, which is an opposite direction.

[0076] The gate G of the first FET 121 and the gate G of the second FET 123 are connected to the management device 150 via signal lines L1 and L2. The management device 150 can control the FETs 121 and 123 individually by sending control signals to the FETs 121 and 123 via the signal lines L1 and L2.

[0077] The bypass circuit 120 is connected in parallel with the relay 53. In the relay disconnected (OPEN) state, by closing the first FET 121 (CLOSE) and opening the second FET 123 (OPEN), the battery pack 60 can pass through the path through the bypass circuit 120 (the path through the source-drain of the first FET 121 and the parasitic diode D2 of the second FET 123: refer to Figure 8 ) is discharged to the vehicle 10. In this case, charging is blocked by the parasitic diode D2.

[0078] In the relay disconnected (OPEN) state, by opening the first FET 121 (OPEN) and closing the second FET 123 (CLOSE), the path through the bypass circuit 120 (the path through the source-drain of the second FET 123 and the parasitic diode D1 of the first FET: refer to Fig.13 ) charges the battery pack 60. In this case, the discharge is blocked by the parasitic diode D1.

[0079] The management device 150 is mounted on the circuit board 100 (see Figure 2 ),like Figure 5 As shown, the CPU 151 , the memory 153 , and the timing unit 155 are provided.

[0080] The management device 150 monitors the state of the battery 50 based on the outputs of the voltage detection unit 54, the current sensor 55, and the temperature sensor 58. That is, the management device 150 monitors the temperature, the current I, and the total voltage Vt of the battery pack 60.

[0081] The memory 153 stores a monitoring program for the battery 50, an execution program for the FET protection process, and data required for executing these programs. The program may be stored in a recording medium such as a CD-ROM and used, transferred, loaned, etc. The program may also be distributed using telecommunication lines.

[0082] The timing unit 155 is used to measure the energization time of the first FET 121 and the second FET 123 .

[0083] 2. FET IT characteristics

[0084] like Figure 6 F1 shown is the IT characteristic of the FET, where the horizontal axis is the conduction time T and the vertical axis is the current I. Specifically, it is the IT characteristic of the FET when the second FET 123 is turned off (OPEN) and the current flows through the parasitic diode D2.

[0085] The area below the boundary line F1 is a safe operation area in which the second FET 123 safely operates. In the area above the boundary line F1, there is a possibility that the second FET 123 may fail due to heat generation of the parasitic diode D2.

[0086] For example, when the current value is 100A, if it is less than 30ms, the second FET 123 is in the safe operating region and operates safely, but if it is more than 30ms, it is out of the safe operating region and there is a possibility of failure. The IT characteristics of the first FET 121 and the second FET 123 are the same.

[0087] 3. Overcharge protection and heating of parasitic diodes

[0088] like Figure 7 As shown, in normal conditions, the relay 53, the first FET 121, and the second FET 123 are all controlled to be closed (CLOSE). The contact resistance of the relay 53 is smaller than the on-resistance of the first FET 121 and the second FET 123, and most of the current I passes through the relay 53. The total voltage Vt of the battery pack 60 increases by charging and decreases by discharging.

[0089] If the total voltage Vt of the battery pack 60 exceeds the upper limit during charging, the management device 150 determines that it is overcharged and switches the relay 53 from closed to open. In addition, the first FET 121 remains closed and the second FET 123 is switched from closed to open.

[0090] By closing the first FET 121 (CLOSE) and opening the second FET 123 (OPEN), as shown in FIG. Figure 8 As shown, after overcharge is detected, discharge can also be performed through a path passing through the source and drain of the first FET 121 and the parasitic diode D2 of the second FET 123 .

[0091] If a large discharge current flows through the parasitic diode D2 and exceeds the safe operating region of the IT characteristic, the second FET 123 may fail due to heat generation of the parasitic diode D2 .

[0092] In order to suppress the failure of the second FET 123 , it is conceivable to close the relay 53 (CLOSE) to reduce the current of the second FET 123 .

[0093] However, since the relay 53 is a mechanical contact 53A, the operation time is long, and it takes time to switch the contact 53A after the command is sent from the management device 150. Therefore, when a relatively large current is discharged in the parasitic diode D2, there is a possibility that the second FET 123 fails before the contact 53A is closed.

[0094] In this embodiment, after overcurrent is detected, when there is a possibility that the second FET 123 fails during the discharge process through the path via the parasitic diode D2, an instruction to switch from open (OPEN) to closed (CLOSE) is sent from the management device 150 to the relay 53, and at the same time, an instruction to switch from open (OPEN) to closed (CLOSE) is sent to the second FET 123.

[0095] Since the second FET 123 is a semiconductor switch, the operating time is shorter than that of the mechanical switch relay 53. The operating time is the time from when a command is sent to a switch until the state of the switch is actually switched.

[0096] If commands are sent to the relay 53 and the second FET 123 simultaneously, the second FET 123 is closed (CLOSE) within several tens of nanoseconds, and thereafter, the contact of the relay is closed (CLOSE) with a delay.

[0097] Since the allowable current between the drain and source of the second FET 123 is greater than the allowable current of the parasitic diode D2, the current that can flow through the bypass circuit 120 can be increased in the period of several dozen milliseconds after the second FET 123 is closed until the contact 53A of the relay 53 is closed. Therefore, the failure of the second FET 123 caused by heat generation can be suppressed.

[0098] Fig. 9 F0 to F3 shown are IT characteristics in which the horizontal axis represents the energization time T and the vertical axis represents the current I.

[0099] Specifically, F1 is an IT characteristic when the relay 53 is opened (OPEN), the first FET 121 is closed (CLOSE), the second FET 123 is opened (OPEN), and the current flows through the parasitic diode D2. F2 is an IT characteristic when the relay 53 is opened (OPEN), the first FET 121 and the second FET 123 are closed (CLOSE), and the current flows between the source and drain of the first FET 121 and the second FET 123. F3 is an IT characteristic when the relay 53 is closed (CLOSE), the first FET 121 and the second FET 123 are closed (CLOSE), and the current flows between the contacts of the relay 53.

[0100] The safe operating area widens in the order of F3, F2, and F1, and the allowable current decreases in the order of the relay 53, the source-drain of the second FET 123, and the parasitic diode D2 of the second FET 123. Specifically, in the case of T = 100 ms, the allowable current of the relay 53 is about 2000A, the allowable current of the drain-source of the second FET 123 is 150A, and the allowable current of the parasitic diode of the second FET 123 is about 30A.

[0101] F0 is an IT determination line for switching the relay 53 and the second FET 123 from open (OPEN) to closed (CLOSE) in order to protect the FET.

[0102] Fig.10 FET protection processing is a flowchart of the FET protection processing. After the relay 53 is cut off in response to overcharge detection, the FET protection processing is as follows: Figure 8 As shown, the operation is performed in a case where only discharge (limited charge) is possible through the path via the parasitic diode D2 of the second FET 123 .

[0103] At the start of the FET protection process, the relay 53 is OPEN, the first FET 121 is CLOSE, and the second FET 123 is OPEN (refer to Figure 8 ).

[0104] The FET protection process consists of four steps S10 to S40. The management device 150 determines the IT condition of the second FET 123 in S10. Specifically, the operating point P determined by the current I and the energization time T of the second FET 123 is compared with the Fig. 9 The IT condition is compared with the IT determination line F0 shown in FIG. 1 to determine whether the operating point P of the second FET 123 is below the IT determination line F0. The IT condition is an example of a predetermined condition of the present invention.

[0105] When the operating point P of the second FET 123 is located below the IT determination line F0 , the management device 150 maintains the first FET 121 closed (CLOSE) and maintains the second FET 123 open (OPEN).

[0106] When the operating point P of the second FET 123 exceeds the IT determination line F0 and moves to the upper side, the process proceeds to S20 , and the management device 150 simultaneously sends a switching signal from OPEN to CLOSE to the relay 53 and the second FET 123 .

[0107] Since the operation time of the FET is shorter than the operation time of the relay 53, the second FET 123 is closed first (CLOSE) (S30). The allowable current between the drain and source of the second FET 123 is greater than the allowable current of the parasitic diode D2. For example, in the case of T = 100 ms, the allowable current between the drain and source is about 150A, and the allowable current of the parasitic diode D2 of the second FET 123 is about 30A.

[0108] Therefore, after the second FET 123 is closed, the current that can flow through the bypass circuit 120 can be increased. Therefore, it is possible to suppress a malfunction of the second FET 123 caused by heat generation.

[0109] After the second FET 123 is closed, the relay 53 is closed with a delay (S40). When the relay 53 is closed, most of the discharge current flows through the relay 53, so the current of the bypass circuit 120 is reduced, and the heat generation of the second FET 123 is further suppressed.

[0110] <Implementation method 2>

[0111] Fig.11 FIG. 4 is a flowchart of the FET protection process of the second embodiment. The FET protection process is the same as that of the first embodiment. After the relay 53 is disconnected in response to the overcharge detection, Figure 8 As shown, the first FET 121 is controlled to be closed (CLOSE), the second FET 123 is controlled to be open (OPEN), and only discharge (limited charge) is enabled through the path via the parasitic diode D2 of the second FET 123.

[0112] Similar to the first embodiment, the management device 150 turns off (OPEN) the relay 53 by detecting overcharge, and then determines whether the operating point P of the bypass circuit 120 is below the IT determination line F0 ( S10 ).

[0113] When the operating point P of the second FET 123 exceeds the IT determination line F0 ( S10 : YES), the management device 150 does not send a switching signal to the relay 53 , but only sends a switching signal from OPEN to CLOSE to the second FET 123 ( S23 ).

[0114] like Fig.12 As shown, the second FET 123 switches from open (OPEN) to closed (CLOSE) in response to the switching signal (S33), and the relay 53 remains open (OPEN) (S43).

[0115] The drain-source allowable current of the second FET 123 is greater than the allowable current of the parasitic diode D2. For example, in the case of T = 100 ms, the drain-source allowable current is about 150A, and the allowable current of the parasitic diode D2 of the second FET 123 is about 30A.

[0116] By closing the second FET 123 and increasing the allowable current, it is possible to suppress a malfunction of the second FET 123 compared to a case where the current continues to flow through the parasitic diode D2 .

[0117] When charging is detected after the second FET 123 is closed (after S33 ), the management device 150 can cut off the charging by switching the second FET 123 from closed (CLOSE) to open (OPEN).

[0118] Embodiment 2 performs FET protection processing only by the second FET 123, so the number of operations of the relay 53 can be reduced compared to embodiment 1 which performs FET protection processing using the second FET 123 and the relay 53. By reducing the number of operations of the relay 53, an effect as a countermeasure against unpleasant sounds during riding can be expected.

[0119] <Implementation method 3>

[0120] In the first embodiment, when overcharging is detected, the relay 53 is opened (OPEN), the first FET 121 is closed (CLOSE), and the second FET 123 is opened (OPEN). Figure 8 As shown, only discharge is enabled through the path (parasitic diode D2 ) passing through the bypass circuit 120 .

[0121] When over-discharge is detected (when the total voltage Vt of the battery pack 60 is lower than the lower limit voltage), the relay 53 may be opened (OPEN), the first FET 121 may be opened (OPEN), and the second FET 123 may be closed (CLOSE), as shown in FIG. Fig.13As shown, only charging is enabled through the path passing through the bypass circuit 120 (parasitic diode D1).

[0122] If a large charging current flows through the parasitic diode D1 and exceeds the safe operating region of the IT characteristic, the first FET 121 may fail due to heat generation of the parasitic diode D1 .

[0123] Fig.14 FET protection processing is a flowchart of the FET protection processing. After the relay 53 is cut off in response to over-discharge detection, the FET protection processing is as follows: Fig.13 As shown, the relay 53 is opened (OPEN), the first FET 121 is opened (OPEN), the second FET 123 is closed (CLOSE), and only charging (limited discharge) is possible through the path via the parasitic diode D1 of the first FET 121.

[0124] After the relay 53 is turned OFF (OPEN) by detecting overcharge, the management device 150 determines whether the operating point P of the first FET 121 is Fig. 9 The lower side of the IT determination line F0 shown (S10).

[0125] When the operating point P of the first FET 121 exceeds the IT determination line F0, the management device 150 transmits a switching signal to the relay 53 and the first FET 121 (S25).

[0126] Since the operation time of the FET is shorter than the operation time of the relay 53, the first FET 121 is closed first (CLOSE) (S35). The allowable current between the drain and source of the first FET 121 is greater than the allowable current of the parasitic diode D2. Therefore, after the first FET 121 is closed (CLOSE), the current that can be passed through the bypass circuit 120 can be increased. Therefore, the failure of the first FET 121 caused by heat can be suppressed.

[0127] After the first FET 121 is closed, the relay 53 is closed with a delay (S45). After the relay 53 is closed, since most of the discharge current flows through the relay 53, the current of the bypass circuit 120 decreases, and the heating of the first FET 121 is further suppressed.

[0128] <Implementation method 4>

[0129] The management device 150 may use the bypass circuit 120 to perform failure detection of the relay 53. Failure detection may be performed during a period when the battery 50 is not in use, such as when the vehicle is parked.

[0130] The failure detection process will be described below.

[0131] After the contact 53A of the relay 53 is switched from closed (CLOSE) to open (OPEN), the first FET 121 is closed (CLOSE), and the second FET 123 is opened (OPEN), and the management device 150 detects Figure 5 The voltage at point B is shown.

[0132] When relay 53 operates normally (when contact 53A is open), the voltage at point B is lower than the voltage at the positive electrode of battery pack 60 (voltage at point A) by the voltage drop of parasitic diode D2 .

[0133] When an abnormality occurs in the relay 53 (when the contact 53A is not opened), the voltage at the point B becomes the same potential as the voltage at the positive electrode of the battery pack 60 (the voltage at the point A). Therefore, based on the voltage at the point B, a closing (CLOSE) fault (a fault in which the relay 53 is fixed in the closed state and does not open) can be detected.

[0134] When it is confirmed that the relay 53 is normally opened (OPEN), the relay 53 is closed (CLOSE) and the voltage at the point B is detected by the management device 150 .

[0135] When the relay 53 operates normally (when the contact 53A is closed (CLOSE)), the voltage at the point B becomes the same potential as the voltage at the positive electrode of the battery pack 60 (the voltage at the point A).

[0136] When an abnormality occurs in the relay 53 (when the contact 53A is not closed), the voltage at the point B becomes lower than the voltage at the positive electrode of the battery pack 60 (the voltage at the point A) by the voltage drop of the parasitic diode D2. Therefore, based on the voltage at the point B, an open fault (a fault in which the relay 53 is fixed in open and not closed) can be detected.

[0137] Thus, the fault of relay 53 can be diagnosed using bypass circuit 120. Since the fault diagnosis of relay 53 is performed using bypass circuit 120, even when bypass circuit 120 fails or there is a possibility of failure, the fault diagnosis can be avoided.

[0138] A case where a failure may occur in the bypass circuit 120 is, for example, a case where a FET protection operation is performed due to heat generation of the parasitic diodes D1 and D2 .

[0139] <Implementation method 5>

[0140] Fig.15 2 is a block diagram of the battery 200. The battery 200 is different from the battery 50 of the first embodiment in that the relay 53 is replaced by a current interruption device 210.

[0141] The current cutoff device 210 is composed of a first FET 211 and a second FET 213 connected back to back.

[0142] When the battery 200 is overcharged, the first FET 211 is closed (CLOSE) and the second FET 123 is opened (OPEN), so that charging can be limited by the parasitic diode D2 and discharge can be performed from the battery 200 to the vehicle 10 .

[0143] When discharging through the path via the parasitic diode D2, when the operating point P of the second FET 213 exceeds the IT determination line F0, the management device 150 can suppress the failure of the second FET 213 caused by the heat of the parasitic diode D2 by closing the second FET 213.

[0144] In addition, the first FET 211 may be set as a protection object. That is, by opening (OPEN) the first FET 211 and closing (CLOSE) the second FET 123, when the battery 200 is charged through the path via the parasitic diode D1, when the operating point P of the first FET 211 exceeds the IT determination line F0, the first FET 211 is closed (CLOSE), thereby suppressing the failure of the first FET 211 caused by the heat of the parasitic diode D1.

[0145] <Other embodiments>

[0146] The present invention is not limited to the embodiments described in the above description and drawings, and for example, the following embodiments are also included in the technical scope of the present invention.

[0147] (1) The cell (electricity storage cell that can be repeatedly charged and discharged) 62 is not limited to a lithium-ion secondary battery cell, but may be other non-aqueous electrolyte secondary battery cells. The cell 62 is not limited to a plurality of cells connected in series and parallel, but may be a series connection or a single cell. A capacitor may also be used instead of a secondary battery cell. A secondary battery cell and a capacitor are examples of a cell.

[0148] (2) In the above embodiment, the battery 50 is mounted on the automobile 10, but it can also be mounted on a mobile object other than a vehicle such as a ship or an aircraft. In addition, it is not limited to a mobile object, and can also be used for fixed-position applications such as a power storage device for absorbing fluctuations in a distributed power generation system and a UPS (uninterruptible power supply).

[0149] (3) In the above embodiment, the relay 53 is arranged on the positive power supply line 57P, and the current sensor 55 is arranged on the negative power supply line 57N. Alternatively, the current sensor 55 may be arranged on the positive power supply line 57P, and the relay 53 may be arranged on the negative power supply line 57N. In addition, in the above embodiment, a P-channel FET is used in the bypass circuit 120, but an N-channel FET may also be used.

[0150] (4) In the above-mentioned first embodiment, when the operating point P of the second FET 123 exceeds the IT determination line F0, the process moves to S20, and the management device 150 simultaneously sends a switching signal from opening (OPEN) to closing (CLOSE) to the relay 53 and the second FET 123. If the second FET 123 can be closed (CLOSE) before the contact 53A of the relay 53 is closed (CLOSE), it is not necessary to send the switching signal at the same time. The switching signal may be sent to the relay 53, and then the switching signal may be sent to the second FET 123.

[0151] (5) In the first embodiment, the IT condition of the second FET 123 is determined (S10), and the FET protection process (S20 to S40) is executed. The execution of the FET protection process (S20 to S40) can be based on the current I and the energization time T of the second FET 123, or can be determined based on other conditions.

[0152] (6) In the above-mentioned first embodiment, the IT condition (S10) of the second FET 123 is determined, and the FET protection process (S20 to S40) is executed. Alternatively, the temperature condition (S10) of the second FET 123 may be determined, and the FET protection process (S20 to S40) may be executed. That is, the FET protection process (S20 to S40) may be executed when the temperature of the second FET 123 exceeds the threshold value. In this case, a temperature sensor 125 may be added to the bypass circuit 120 to measure the temperature of the first FET 121 and the second FET 123. Fig.16 ).

[0153] DESCRIPTION OF REFERENCE NUMERALS 50 battery (power storage device) 53 relay

[0154] 55 Current Sensor

[0155] 60 battery pack

[0156] 62 monomer 120 bypass circuit 121 first FET

[0157] 123 Second FET

[0158] 150 Management Devices

Claims

1. An electric storage device, comprising: monomer; Relay, cuts off the current of the monomer; a bypass circuit connected in parallel with the relay; as well as Management device, The bypass circuit includes two FETs connected back to back. When the management device detects an abnormality in the monomer, The relay is opened (OPEN), one of the two FETs is closed (CLOSE), and the other is opened (OPEN), so that the discharge or charge of the cell is possible through the path through the parasitic diode of the FET. When discharging or charging is performed through the path via the parasitic diode, when the current I and the power-on time T of the FET reach specified conditions or when the temperature of the FET reaches specified conditions, the management device closes (CLOSE) the relay and the other FET that is open (OPEN).

2. An electric storage device comprising: monomer; Relay, cuts off the current of the monomer; a bypass circuit connected in parallel with the relay; as well as Management device, The bypass circuit includes two FETs connected back to back. When the management device detects an abnormality in the monomer, The relay is opened (OPEN), one of the two FETs is closed (CLOSE), and the other is opened (OPEN), so that the discharge or charge of the cell is possible through the path through the parasitic diode of the FET. When discharging or charging is performed through the path passing through the parasitic diode, when the current I and the power-on time T of the FET reach specified conditions or when the temperature of the FET reaches specified conditions, the management device maintains the relay in an open state (OPEN) and closes (CLOSE) the other open (OPEN) FET.

3. The power storage device according to claim 1 or claim 2, wherein: The abnormality of the cell is overcharge or overdischarge.

4. The power storage device according to claim 1 or claim 2, which is used for engine starting.

5. An electric storage device comprising: monomer; A current cut-off device cuts off the current of the monomer; as well as Management device, The current cutoff device includes two FETs connected back to back, When the management device detects an abnormality in the monomer, By closing (CLOSE) one of the two FETs and opening (OPEN) the other, the discharge or charge of the cell is enabled through a path passing through the parasitic diode of the FET. When discharging or charging is performed through the path passing through the parasitic diode, when the current I and the power-on time T of the FET reach specified conditions or when the temperature of the FET reaches specified conditions, the management device closes (CLOSE) the other FET that was opened (OPEN).

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