Method and apparatus for managing sensor data

Abstract

The embodiment of the invention relates to a method and device for managing sensor data. Systems, apparatuses, articles, and methods are disclosed. An example apparatus includes interface circuitry configured to connect with a field device, the field device including a first sensor, the field device being powered by a power source; computer readable instructions; and programmable circuitry powered by the power source, the computer readable instructions causing the programmable circuitry to: obtain a first measurement value from the field device using a first communication protocol, the first measurement value corresponding to the first sensor; acquiring a second measurement value from a second sensor separate from the field device without using the first communication protocol; and wirelessly transmitting the first measurement value and the second measurement value to the controller using a second communication protocol.

Description

Technical Field

[0001] The present disclosure relates generally to field devices and, more particularly, to methods and apparatus for managing sensor data. Background Art

[0002] A manufacturing or design environment may include a variety of actuators (e.g., valves, motors, engines, gears, fans, etc.). Actuators can apply mechanical forces of different types, strengths, and frequencies based on the needs of the application. In some examples, multiple actuators are mechanically and / or logically connected to each other. In order to manage such a complex system, field devices can monitor and / or control one or more actuators. Field devices can use standardized protocols to achieve external communication so that other field devices and the main controller can interpret the data regardless of the type of connected actuator. Summary of the invention

[0003] For a method and apparatus for managing sensor data, an example apparatus includes an interface circuit system configured to connect to a field device, the field device including a first sensor, the field device being powered by a power supply; computer-readable instructions; and a programmable circuit system powered by the power supply, the computer-readable instructions causing the programmable circuit system to: obtain a first measurement value from the field device using a first communication protocol, the first measurement value corresponding to the first sensor; obtain a second measurement value from a second sensor separate from the field device without using the first communication protocol; and wirelessly transmit the first measurement value and the second measurement value to a controller using a second communication protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an example environment including a sensor coordinator device and field devices;

[0005] Figure 2 is used for Figure 1 A block diagram of an example implementation of a 4-20 milliamp (mA) current loop for powering a field device and a sensor coordinator device;

[0006] Figure 3 yes Figure 1 A block diagram of an example implementation of a sensor coordinator device;

[0007] Figure 4 yes Figure 1 A block diagram of an example implementation of a field device;

[0008] Figure 5 It means that the exemplary programmable circuit system can be executed, instantiated and / or performed to implement Figure 3 example machine readable instructions and / or a flowchart of example operations of a sensor coordinator device;

[0009] Figure 6 It means that Figure 3 Flowcharts of example machine-readable instructions and / or example operations executed, instantiated, and / or performed by example programmable circuitry of a sensor coordinator device;

[0010] Figure 7 is a block diagram of an example processing platform including programmable circuitry structured to execute, instantiate and / or perform example machine-readable instructions and / or perform Figure 5 Example operation to achieve Figure 3 Sensor coordinator device;

[0011] Figure 8 yes Figure 7 A block diagram of an example implementation of a programmable circuit system;

[0012] Fig. 9 yes Figure 7 A block diagram of another example implementation of a programmable circuit system; and

[0013] Fig.10 is a block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers) for distributing software, instructions and / or firmware (e.g., corresponding to Figure 5 and Figure 6 Example machine-readable instructions of the present invention are distributed to client devices associated with end users and / or consumers (e.g., for licensing, sale, and / or use), retailers (e.g., for sale, resale, licensing, and / or sub-licensing), and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers and / or other end users, such as direct purchasing customers).

[0014] In general, the same reference numbers will be used to refer to the same or like parts throughout the drawings(s) and accompanying written description. The drawings are not necessarily to scale. DETAILED DESCRIPTION

[0015] As used in this patent, stating that any part (e.g., a layer, film, region, area, or plate) is in any way on another part (e.g., positioned on another part, located on another part, disposed on another part, or formed on another part, etc.) indicates that the referenced part is in contact with the other part, or that the referenced part is located above the other part with one or more intermediate parts in between.

[0016] As used herein, unless otherwise specified, connection references (e.g., attachment, coupling, connection, and engagement) may include intermediate members between elements to which the connection reference refers, and / or relative motion between these elements. Thus, a connection reference does not necessarily infer that two elements are directly connected to each other and / or have a fixed relationship to each other. As used herein, a statement that any part is "in contact" with another part means that there is no intermediate part between the two parts.

[0017] Unless otherwise specifically stated, descriptors such as "first," "second," and "third" as used herein do not in any way infer or indicate any meaning of priority, physical order, arrangement in a list, and / or ordering, but are merely used as labels and / or arbitrary names to distinguish elements to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to by a different descriptor (such as "second" or "third") in the claims. In this case, it should be understood that these descriptors are only used to clearly identify these elements in the context of the discussion (e.g., within the claims), where these elements may otherwise share the same name.

[0018] As used herein, "approximately" and "about" modify the subject matter / values ​​thereof to recognize that variations can exist in real-world applications. For example, "approximately" and "approximately" can modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections that will be understood by one of ordinary skill in the art. For example, "approximately" and "approximately" can indicate that such dimensions may be within a tolerance range of + / - 10%, unless otherwise stated in the following description.

[0019] As used herein, "substantially real time" means occurring in a nearly instantaneous manner, recognizing that there can be real-world delays in computation time, transmission, etc. Thus, unless otherwise specified, "substantially real time" means real time + 1 second.

[0020] As used herein, the phrase "in communication" includes variations thereof, covers direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but instead includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals and / or one-time events.

[0021] As used herein, "programmable circuitry" is defined as including (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) that are constructed to perform specific operation(s) and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that are programmable with instructions for performing specific function(s) and / or operation(s) and include one or more semiconductor-based logic devices (e.g., electronic hardware implemented by one or more transistors). Examples of programmable circuit systems include a programmable microprocessor such as a central processor unit (CPU) that can execute a first instruction to perform one or more operations and / or functions, a field programmable gate array (FPGA) that can be programmed with a second instruction for causing configuration and / or structuring of the FPGA to instantiate one or more operations and / or functions corresponding to the first instruction, a graphics processor unit (GPU) that can execute a first instruction to perform one or more operations and / or functions, a digital signal processor (DSP) that can execute a first instruction to perform one or more operations and / or functions, an XPU that can execute a first instruction to perform one or more operations and / or functions, a network processing unit (NPU) one or more microcontrollers, and / or an integrated circuit such as an application specific integrated circuit (ASIC). For example, the XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof), and an orchestration technology (e.g., (multiple) application programming interfaces (APIs)), which can assign (multiple) computing tasks to any one (multiple) of the multiple types of programmable circuit systems that are suitable and can be used to perform (multiple) computing tasks.

[0022] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), etc.

[0023] An example communication protocol used by field devices is the Highway Addressable Remote Transducer protocol. is a two-way communication protocol that supports communication between two HART-enabled devices (e.g., a field device and a host controller). In some examples, the two HART-enabled devices send and receive data over a wired connection using 4-20 milliamps (mA) of current. In other examples, the two HART-enabled devices also implement Communication protocol to send and receive without a wired connection data. and Communication protocols are often used in industrial environments because systems supporting one or both protocols are simple, reliable, and minimally expensive to implement.

[0024] and The communication protocol describes the data generated by a HART-enabled device. For example, a field device may include one or more internal sensors for monitoring actuators. If both devices are HART-enabled, the field devices can use or Provides internal sensor readings to the main controller.

[0025] Although and Communication is established between field devices and the host controller, but these protocols cannot be used by non-HART-enabled devices. For example, suppose an application requires that an actuator be measured using a third-party sensor that is not implemented within the field device connected to the actuator. The designer or manufacturer must implement both: (1) a HART-enabled field device to obtain the internal sensor readings and control the actuator, and (2) a separate communication system to obtain the third-party sensor readings. This additional communication system will increase the cost and complexity of the system, limiting the use of HART-enabled devices to some, but not all, applications.

[0026] The example methods, devices, and systems described herein use and The sensor coordinator device includes analog and digital terminals to connect to both third-party sensors and HART-enabled devices using analog terminals, digital terminals, and wireless interface circuitry. The sensor coordinator device includes a processor for packaging data recorded from third-party sensors into or The sensor coordinator device also includes an event manager circuit system that monitors one or more thresholds so that messages received from HART-enabled devices or readings from third-party sensors can trigger actions to be performed by the sensor coordinator device or a connected HART-enabled device. Thus, the example sensor coordinator device described herein enables the use of or WirelessHART to realize complex drive and measurement systems.

[0027] Figure 1 is a block diagram of an example environment including an example sensor coordinator device described in accordance with the teachings of the present disclosure. Figure 1 The environment of FIG. 1 includes an example field device 102 , an example sensor coordinator device 106 , example sensors 108A, 108B, 108C, and 108D (collectively, sensors 108 ), and a controller 110 .

[0028] The field device 102 is a HART-enabled device that is connected to both the sensor coordinator device 106 and one or more actuators 104. The field device 102 measures, monitors and / or controls the actuators 104. The field device 102 also communicates with the sensor coordinator device 106 via a wired The sensor coordinator device 106 communicates with the field device 102 through a protocol to exchange data. Examples of data exchanged between the field device 102 and the sensor coordinator device 106 may include, but are not limited to, measurements, performance indicators, instructions, etc. Examples of the field device 102 include, but are not limited to, a remote terminal unit (RTU), a programmable logic controller (PLC), a human-machine interface (HMI), etc. Figure 1 The example includes an instance of field device 102. In other examples, the environment implements a different number of field devices 102. Figure 4 The field device 102 is discussed further.

[0029] Actuator 104 applies mechanical force to perform a task. The size, cost, complexity, and functionality of actuator 104 can vary depending on the needs of the application. In some examples, the actuator is Figure 1 In other examples, the actuators themselves are Figure 1 The actuator 104 may be implemented as a variety of components, including but not limited to pumps, motors, engines, valves, mechanical arms, levers, pulleys, pistons, gears, springs, etc. The actuator 104 applies mechanical force based on instructions received from the field device 102. A single field device 102 may be connected to any number of actuators 104.

[0030] According to the teachings of the present disclosure, the sensor coordinator device 106 communicates with both HART-enabled devices and non-HART-enabled devices. For example, the sensor coordinator device 106 may have a The first connection of the field device 102 of the protocol to the implementation The second connection of the controller 110 of the protocol, and to the controller not using The sensor coordinator device 106 may be configured to receive a set of third connections to the sensors 108 of the HART-enabled protocol. In some examples, the sensor coordinator device 106 may perform actions based on data received from the HART-enabled devices. Additionally or alternatively, the sensor coordinator device 106 may cause the HART-enabled devices to perform actions based on input from the sensors 108 and internal logic within the sensor coordinator device 106. Figure 1 The example environment includes one instance of the sensor coordinator device 106 (e.g., one sensor coordinator device). In other examples, the field devices 102 and / or the controller 110 can communicate with multiple instances of a sensor coordinator device 106. Figure 3 The sensor coordinator device 106 is discussed further.

[0031] Sensor 108 measures Figure 1 The sensor 108 can measure any type of physical phenomenon. For example, the sensor 108A measures temperature, the sensor 108B measures voltage and current, the sensor 108C measures sound, and the sensor 108D measures position / orientation. Figure 1 Four sensors are shown, but the sensor coordinator device 106 may be connected to any number of sensors 108 .

[0032] As used herein, the sensor 108 may be referred to as an external sensor because the sensor is not implemented in or directly connected to the field device 102. Similarly, as used above and herein, the sensor 108 may be referred to as a third-party sensor because the sensor may be designed and manufactured independently of the HART-enabled devices (e.g., the field device 102 and the sensor coordinator device 106).

[0033] The controller 110 communicates wirelessly with the sensor coordinator device 106 to obtain Figure 1 For example, the controller 110 may obtain measurements from both the sensor 108 and internal sensors of the field device 102. The controller 110 may then use these measurements to generate a user interface including a virtual instrument panel.

[0034] The controller 110 also communicates wirelessly with the sensor coordinator device 106 to Figure 1 108A. The controller 110 may provide instructions to other components within the environment of the sensor 108A. For example, the controller 110 may instruct the sensor coordinator device 106 to change the sampling rate of the sensor 108A to a specific value. In such an example, the controller 110 may determine the new value of the sampling rate based on: (a) logic implemented by the programmable circuit system within the controller 110, and / or (b) external input (e.g., input obtained via the user interface described above).

[0035] exist Figure 1 In some examples, the controller 110 communicates with the field devices 102 indirectly via the sensor coordinator device 106. In other examples, the controller 110 additionally or alternatively communicates directly with the field devices 102. In some examples, the controller 110 is referred to as a primary controller and the field devices 102 are referred to as secondary controllers.

[0036] The controller 110 may include any type of programmable circuitry. Examples of programmable circuitry include, but are not limited to, a programmable microprocessor, a field programmable gate array (FPGA) that can instantiate instructions, a central processor unit (CPU), a graphics processor unit (GPU), a digital signal processor (DSP), an XPU or a microcontroller and an integrated circuit, such as an application specific integrated circuit (ASIC).

[0037] Figure 1 The example of describes an implementation in which the controller 110 employs both the field devices 102 and the sensor coordinator device 106 to monitor and control the environment. In other examples, the controller 110 may employ only the sensor coordinator device 106 (eg, without accompanying field devices) to monitor and control the environment.

[0038] exist Figure 1 In the example environment of , the field device 102 is HART-enabled and the sensor 108 is not HART-enabled. Figure 1 In the example of FIG. 1 , field devices 102, actuators 104, sensor coordinator devices 106, and sensors 108 are located at a first location within an environment (e.g., a production floor of a manufacturing plant), and controller 110 is located at a second location within the environment (e.g., a control room within the manufacturing plant). Therefore, implementing two separate communication protocols within the environment may require a large amount of wiring (e.g., from the production floor to the control room) and a large amount of logic running on controller 110 to independently handle the two protocols.

[0039] Advantageously, the sensor coordinator device 106 enables the controller 110 to exchange data with both the field devices 102 and the sensors 108 via a single wireless communication protocol. Thus, the sensor coordinator device 106 supports the controller 110 with less cost and complexity than alternative solutions that use multiple communication protocols and / or multiple wires to directly connect the controller 110 to the sensors 108 and the field devices 102.

[0040] Figure 2 is used for Figure 1 A block diagram of an example implementation of a 4-20 milliamp (mA) current loop for powering field devices and a sensor coordinator device. Figure 2 Included are a power source 202 , a field device 102 , and a sensor coordinator device 106 .

[0041] The 4-20mA current loop is used to provide both power and data within a single electrical connection. Generally speaking, a 4-20mA current loop includes a power supply, a transmitter, and a receiver connected in series with each other. Figure 2 In the example of FIG. 1 , the power supply 202 provides power to both the field device 102 and the sensor coordinator device 106 . The power supply 202 may be implemented within the controller 110 or controlled by the controller 110 . It is a bidirectional protocol, so both the field device 102 and the sensor coordinator device 106 can act as a transmitter and a receiver. It is also a half-duplex protocol, so at any point in time, one of the field device 102 or the sensor coordinator device 106 is acting as a transmitter while the other is acting as a receiver.

[0042] The power supply of the 4-20mA current loop provides a voltage used by the transmitter and receiver to perform operations. The transmitter uses the voltage to generate a signal with a current between 4mA and 20mA. The receiver then interprets the amount of current (e.g., amperage) as data encoded by the transmitter. In particular, 4mA corresponds to 0% of the maximum value encoded by the transmitter, and 20mA corresponds to 100% of the minimum value.

[0043] For example, assume that the field device 102 is transmitting the joint angle of the robot arm with a maximum value of 180°, and the current of the signal used to transmit the reading is 12 mA. In such an example, the sensor coordinator device 106 determines that the joint angle parameter is 90° because

[0044] exist Figure 2 In , power and power consumption are modeled as voltage gain and voltage drop, respectively. For example, power supply 202 generates a voltage labeled V SOURCE Due to the transmission loss between the power supply 202 and the field device 102, the voltage first drops to V TRANSMITDue to the power consumption of the field device 102, the voltage drops a second time, V FIELD If the voltage available to the field device 102 is less than V FIELD , the field device 102 may fail or fail to power on.

[0045] Generally speaking, industry may produce field devices 102 such that for various applications, there are:

[0046] V SOURCE ≥V TRANSMIT +V FIELD .

[0047] In some examples, V SOURCE With the sum V TRANSMIT +V FIELD The difference between is called overhead. For example, consider an alternative 4-20mA loop that includes only field devices and power supply 202. If V SOURCE is 20V, V TRANSMIT is 5V, V FIELD If the MOSFET is 10V, the alternative 4-20mA loop has a 5V overhead that is not consumed.

[0048] Advantageously, the sensor coordinator device 106 is configured to use Figure 2 The overhead voltage within the 4-20mA loop of the sensor coordinator device 106 powers itself and the sensor 108. That is, the sensor coordinator device 106 can power itself and the sensor 108 at a voltage drop of V COORDINATOR Small enough to operate where:

[0049] V SOURCE ≥V TRANSMIT +V FIELD +V COORDINATOR

[0050] Even though the field device 102 may not know V COORDINATOR Designed for situations where

[0051] Figure 3 yes Figure 1 106. Figure 3 The sensor coordinator device 106 may be instantiated (e.g., created, validated for any length of time, materialized, implemented, etc.) by a programmable circuit system (such as a central processing unit (CPU)) executing a first instruction. Additionally or alternatively, Figure 3The sensor coordinator device 106 may be instantiated (e.g., created as an instance, validated for any length of time, embodied, implemented, etc.) by: (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA), which is structured and / or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. It should be understood that, therefore, Figure 3 Some or all of the circuitry of may be instantiated at the same or different times. For example, Figure 3 Some or all of the circuitry of can be instantiated in one or more threads that execute concurrently on hardware and / or serially on hardware. In addition, in some examples, Figure 3 Some or all of the circuit systems may be implemented by a microprocessor circuit system executing instructions and / or an FPGA circuit system performing operations to implement one or more virtual machines and / or containers. Figure 3 The example includes field devices 102, sensor coordinator device 106, sensors 108, and controller 110. The sensor coordinator device 106 includes an example bus 300, an example digital terminal 302, an example analog terminal 304, an example memory 306, an example wireless interface circuit system 308, an example sensor 310, an example data logger circuit system 312, an example event manager circuit system 314, and an example protocol converter circuit system 316.

[0052] Bus 300 refers to one or more physical connections (eg, interconnects, copper traces, etc.) that enable communication between internal components of sensor coordinator device 106. Bus 300 may be implemented using one or more communication systems that meet predetermined threshold power and latency requirements.

[0053] Digital terminal 302 refers to one or more physical endpoints configured to send / receive digital signals to / from an external source. Similarly, analog terminal 304 refers to one or more physical endpoints configured to send / receive analog signals to / from an external source. Examples of terminals include, but are not limited to, pins, ports, copper pads, leads of electronic components, etc.

[0054] In the examples described herein, the digital terminals 302 and the analog terminals 304 are used to exchange data with the sensors 108. A given sensor 108A can be connected to one or both of the digital terminals 302 and the analog terminals 304. Both the digital terminals 302 and the analog terminals 304 can exchange any type of data. In some examples, the digital terminals 302 exchange discrete data (e.g., instructions or commands), while the analog terminals 304 exchange continuous data (e.g., sensor measurements).

[0055] The analog terminals 304 are also connected to the field device 102 to use the wired For example, the field device 102 may use the pins in the analog terminal 304 to transmit a signal with a current between 4 mA and 20 mA, as described above in conjunction with Figure 2 described.

[0056] The memory 306 stores data used by other components of the sensor coordinator device 106. For example, the memory 306 can store data, including but not limited to sensor measurements received via the digital terminal 302 and / or the analog terminal 304, parameters used by the event manager circuit system 314, configurations used by the protocol converter circuit system 316 to convert messages, etc. The memory 306 can be implemented as any type of memory. For example, the memory 306 can be a volatile memory or a non-volatile memory. The volatile memory can be implemented by a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), and / or any other type of RAM device. The non-volatile memory can be implemented by flash memory and / or any other desired type of memory device.

[0057] Wireless interface circuitry 308 communicates with controller 110 using radio frequency transmissions over a free space medium (e.g., without wires). Wireless interface circuitry 308 may include any communication protocol suitable for wireless communication with controller 110. Examples of wireless communication protocols include, but are not limited to Low energy consumption, etc. The wireless interface circuit system 308 may include a transceiver, an antenna, and / or other hardware components required to implement one or more of the above communication protocols. In some examples, the wireless interface circuit system 308 is instantiated by a programmable circuit system that executes wireless interface instructions and / or is configured to perform operations such as Figure 5 and Figure 6 A flowchart represents the operations.

[0058] In some examples, the sensor coordinator device 106 includes components for communicating wirelessly. For example, the components for wireless communication can be implemented by the wireless interface circuit system 308. In some examples, the wireless interface circuit system 308 can be implemented by a device such as Figure 7 For example, the wireless interface circuit system 308 may be implemented by executing, for example, Figure 5 At least those machine executable instructions implemented by block 514 Figure 8 In some examples, the wireless interface circuit system 308 may be instantiated by a hardware logic circuit system, which may be an ASIC, XPU, or other processor configured and / or structured to perform operations corresponding to machine-readable instructions. Fig. 9The wireless interface circuit system 308 is implemented by the FPGA circuit system 900 of the present invention. Additionally or alternatively, the wireless interface circuit system 308 can be instantiated by any other combination of hardware, software and / or firmware. For example, the wireless interface circuit system 308 can be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured and / or structured to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0059] Sensor(s) 310 refers to one or more sensors implemented within the package of sensor coordinator device 106. Like sensor 108, sensor 310 may be referred to as third-party sensors and / or external sensors because they are designed and implemented separately from field device 102. In some examples, sensor 310 may not be accessible via Protocol for transmission.

[0060] The data logger circuit system 312 obtains measurements from the sensors 108 and the sensors 310. For example, the sensor 108A can generate an output voltage (Vsensor) that is provided to the sensor coordinator device 106 via a pin within the analog terminal 304. In such an example, the data logger circuit system 312 can sample Vsensor, filter the noise in the sample, and convert the filtered output into a measurement. The data logger circuit system 312 can determine when and how often to sample Vsensor, which filtering and conversion techniques to use, and so on. The data logger circuit system 312 also stores the measurements in the memory 306 via the bus 300. In some examples, the data logger circuit system 312 is instantiated by a programmable circuit system that executes data logger instructions and / or is configured to perform operations such as Figure 5 and Figure 6 A flowchart represents the operations.

[0061] In some examples, the sensor coordinator device 106 includes components for recording. For example, the components for recording can be implemented by the data logger circuit system 312. In some examples, the data logger circuit system 312 can be implemented by, for example, Figure 7 For example, the data logger circuit system 312 may be implemented by executing, for example, Figure 5 At least those machine executable instructions implemented by block 508 Figure 8In some examples, the data recorder circuit system 312 can be instantiated by hardware logic circuit system, which can be an ASIC, XPU or other processor configured and / or structured to perform operations corresponding to machine-readable instructions. Fig. 9 FPGA circuit system 900 is implemented. Additionally or alternatively, data logger circuit system 312 can be instantiated by any other combination of hardware, software, and / or firmware. For example, data logger circuit system 312 can be implemented by at least one or more hardware circuits (e.g., processor circuit system, discrete and / or integrated analog and / or digital circuit system, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.), which are configured and / or structured to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0062] The event manager circuitry 314 identifies triggers and manages the actions of other components within the sensor coordinator device 106 based on the triggers. As used above and herein, a trigger refers to a change in input to the sensor coordinator device 106 that prompts an action to occur. An action may refer to a combination of Figure 3 Any of the operations described in this article. Figure 5 Examples of triggers and actions are discussed further below. In some examples, event manager circuitry 314 is instantiated by programmable circuitry that executes event manager instructions and / or is configured to perform functions such as Figure 5 and Figure 6 A flowchart represents the operations.

[0063] In some examples, the sensor coordinator device 106 includes components for management. For example, the components for management can be implemented by the event manager circuit system 314. In some examples, the event manager circuit system 314 can be implemented by, for example, Figure 7 For example, the event manager circuitry 314 may be implemented by executing, for example, Figure 5 At least those machine executable instructions implemented by blocks 504-518 Figure 8 In some examples, event manager circuitry 314 may be instantiated by hardware logic circuitry, which may be an ASIC, XPU, or other processor configured and / or structured to perform operations corresponding to machine-readable instructions. Fig. 9FPGA circuit system 900 is implemented. Additionally or alternatively, event manager circuit system 314 can be instantiated by any other combination of hardware, software and / or firmware. For example, event manager circuit system 314 can be implemented by at least one or more hardware circuits (e.g., processor circuit system, discrete and / or integrated analog and / or digital circuit system, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.), which are configured and / or structured to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0064] The protocol converter circuitry 316 places the information into a format defined by the communication protocol. For example, the protocol converter circuitry 316 packages the measurements from the sensor 108 into Low energy grouping or The protocol converter circuitry 316 also implements wired protocol to encode information within two signals superimposed on a single physical 4-20mA connection.

[0065] Protocol converter circuitry 316 may perform any number of data manipulation operations to produce information in a desired format. Data manipulation operations that may be used for protocol conversion include, but are not limited to, addition, subtraction, reordering, packing, etc. In some examples, protocol converter circuitry 316 is instantiated by programmable circuitry that executes protocol converter instructions and / or is configured to perform operations such as Figure 5 and Figure 6 A flowchart represents the operations.

[0066] In some examples, the sensor coordinator device 106 includes components for converting. For example, the components for converting can be implemented by the protocol converter circuit system 316. In some examples, the protocol converter circuit system 316 can be implemented by, for example, Figure 7 For example, the protocol converter circuit system 316 may be implemented by executing, for example, Figure 5 At least those machine executable instructions implemented by block 512 Figure 8 In some examples, the protocol converter circuit system 316 can be instantiated by a hardware logic circuit system, which can be an ASIC, XPU or other processor configured and / or structured to perform operations corresponding to machine-readable instructions. Fig. 9The protocol converter circuit system 316 may be implemented by any other combination of hardware, software, and / or firmware. Additionally or alternatively, the protocol converter circuit system 316 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the protocol converter circuit system 316 may be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured and / or structured to execute some or all of the machine-readable instructions and / or to execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0067] Audio / visual output 318 may refer to any hardware component that emits audio or light. For example, audio / visual output 318 may be implemented by devices including, but not limited to, speakers, safety stack lights, beacon lights, screens, etc. Figure 3 In the example block diagram of , the audio / visual output 318 is implemented within the package of the sensor coordinator device 106. In other examples, one or more components of the audio / visual output 318 may be implemented external to the sensor coordinator device 106.

[0068] In some examples, some or all of the audio / visual outputs 318 may be referred to as peripheral output components. Similarly, in some examples, the sensor coordinator device 106 implements or is connected to Figure 4 Peripheral input components not shown (e.g., keyboard, touch screen, emergency stop button, etc.).

[0069] The sensor coordinator device 106 provides notifications using audio / visual output 318. The notifications may provide any type of information to a user of the sensor coordinator device 106. In some examples, the notification is an alert that notifies the user of unexpected behavior (e.g., an error, a failure, an outage, etc.). In some examples, the notification is a status update (e.g., all systems are OK, a measurement has been completed, etc.).

[0070] In some examples, the sensor coordinator device 106 includes a component for notification. For example, the component for notification can be implemented by an audio / visual output 318. In some examples, the audio / visual output 318 can be implemented by a device such as Figure 7 For example, the audio / visual output 318 may be implemented by executing, for example, Figure 5 At least those machine executable instructions implemented by block 518 Figure 8In some examples, the audio / visual output 318 may be instantiated by a hardware logic circuit system, which may be an ASIC, XPU, or other processor configured and / or structured to perform operations corresponding to machine-readable instructions. Fig. 9 FPGA circuit system 900 is implemented. Additionally or alternatively, the audio / visual output 318 can be instantiated by any other combination of hardware, software, and / or firmware. For example, the audio / visual output 318 can be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured and / or structured to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0071] Figure 4 yes Figure 1 A block diagram of an example implementation of a field device. Figure 4 The field device 102 may be instantiated (e.g., created as an instance, made effective for any length of time, materialized, realized, etc.) by a programmable circuit system (such as a central processing unit (CPU)) executing a first instruction. Additionally or alternatively, Figure 4 The field device 102 may be instantiated (e.g., created as an instance, validated for any length of time, materialized, implemented, etc.) by: (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA), which is constructed and / or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. It should be understood that, therefore, Figure 4 Some or all of the circuitry of may be instantiated at the same or different times. For example, Figure 4 Some or all of the circuitry of can be instantiated in one or more threads that execute concurrently on hardware and / or serially on hardware. In addition, in some examples, Figure 4 Some or all of the circuit systems of the can be implemented by microprocessor circuit systems executing instructions and / or FPGA circuit systems performing operations to implement one or more virtual machines and / or containers. Field device 102 includes bus 400, digital terminal 402, analog terminal 404, memory 406, (multiple) sensor 408, data logger circuit system 410 and event manager circuit system 412.

[0072] and Figure 3Like the digital and analog terminals of the present invention, the digital terminal 402 and the analog terminal 404 refer to physical endpoints configured to send / receive signals to / from an external source. The digital terminal 402 is connected to the actuator 104. In some examples, the digital terminal 402 is also connected to a peripheral component (now shown). The analog terminal 404 is connected to both the actuator 104 and the sensor coordinator device 106.

[0073] The memory 406 stores data used by the other components of the field device 102. The memory 406 may be implemented by any type of volatile or non-volatile memory.

[0074] Sensors 408 measure physical phenomena of the surrounding environment (e.g., actuator 104). Sensors 408 may be referred to as internal sensors because they are implemented within the package of field device 102. In particular, sensors 408 are implemented as one or more subsystems within field device 102 that use The protocol communicates with the rest of the field device 102 .

[0075] Figure 1 Sensor 108, Figure 3 The sensor 310 and Figure 4 Each of sensors 408 may include any type of sensor. In some examples, a designer or manufacturer of sensor coordinator device 106 may add functionality by implementing sensor 310 using a sensor type not included in sensor 408. Similarly, a user of sensor coordinator device 106 may add functionality by connecting sensor 108 with a sensor type not included in sensor 408 or sensor 310. In some examples, one or more of sensors 108, 310, and 408 include a common sensor type.

[0076] Within one or more subsystems implementing sensor 408, data logger circuitry 410 performs a voltage logger operation by measuring the voltage, filtering the noise, and converting the voltage to a The data logger circuitry 312 may determine when and how often to sample the various sensor voltages, which filtering and conversion techniques to use, and so forth.

[0077] and Figure 3 Like the event manager circuitry 314 , the event manager circuitry 412 identifies triggers and manages actions of other components within the sensor coordinator device 106 based on the triggers. Figure 4The event manager circuitry 412 may identify an internal trigger from the sensor 408 or from input received via a peripheral component (e.g., a keyboard, a touch screen, etc.) implemented within the field device 102. Additionally or alternatively, the field device 102 performs an operation based on input received from an external source (e.g., the sensor coordinator device 106).

[0078] As with audio / visual output 318 , audio / visual input 414 may refer to any hardware component that emits audio or light. Audio / visual output 414 may provide any type of notification to a user of field device 102 .

[0079] Without the sensor coordinator device 106, industries seeking to use a single communication protocol to measure / control the environment are limited to sensors 408 implemented within field devices 102 (e.g., capable of communicating via Advantageously, the sensor coordinator device 106 implements a protocol converter circuitry 316 that is connected to sensors that are not enabled third-party sensors (e.g., sensor 108 and sensor 310), and converting the sensor outputs to a single communication protocol (e.g., Thus, an environment including the sensor coordinator device 106 can support more types of sensors using a single communication protocol than an environment using only the field device 102. For example, DVC6200 is a valve controller and an example implementation of field device 102 . DVC6200 can collect internal pressure and travel readings (e.g., sensor 408 measures pressure and travel). In the presence of sensor coordinator device 106, using The DVC6200 system can acquire other measurements to measure the valve, including but not limited to vibration, temperature, audio, etc.

[0080] Although Figure 3 An example manner of implementing the sensor coordinator device 106 is shown in FIG. Figure 3 One or more of the elements, processes, and / or devices shown may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. In addition, the example bus 300, the example digital terminal 302, the example analog terminal 304, the example memory 306, the example wireless interface circuit system 308, the example sensor 310, the example data logger circuit system 312, the example event manager circuit system 314, the example protocol converter circuit system 316, and / or (more generally) Figure 3The example sensor coordinator device 106 may be implemented in hardware alone or in combination with software and / or firmware. Thus, for example, the example bus 300, the example digital terminal 302, the example analog terminal 304, the example memory 306, the example wireless interface circuit system 308, the example sensor 310, the example data logger circuit system 312, the example event manager circuit system 314, the example protocol converter circuit system 316, and / or (more generally) Figure 3 Any of the example sensor coordinator devices 106 may be implemented by programmable circuitry in combination with machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPUs), digital signal processor(s) (DSPs), ASIC(s), programmable logic device(s) (PLDs), and / or field programmable logic devices (FPLDs) (such as FPGAs). In addition, Figure 3 An example sensor coordinator device 106 may include in addition to or in lieu of Figure 3 One or more elements, processes and / or devices of those shown, and / or may include more than one of any or all of the elements, processes or devices shown.

[0081] Figure 5 and Figure 6 1 and ... Figure 3 The example operations may be performed by the programmable circuit system to implement and / or initialize the sensor coordinator device 106. Figure 3 The sensor coordinator device 106 of the machine readable instructions may be one or more executable programs or (multiple) parts of one or more executable programs for execution by the programmable circuit system, such as the following in combination Figure 7 The programmable circuit system 712 shown in the example programmable circuit system platform 700 discussed below; and / or may be a combination of the following Figure 8 and / or Fig. 9 One or more functions or portions of functions to be performed by the example programmable circuit system (e.g., FPGA) discussed. In some examples, machine-readable instructions cause operations, tasks, etc. to be performed and / or executed in an automatic manner in the real world. As used herein, "automation" means without human involvement.

[0082] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical disks (e.g., Blu-ray disks, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, read-only memory (ROMs), solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by programmable circuit systems located in one or more hardware devices, but the entire program and / or portions thereof may also be executed and / or instantiated and / or embodied in dedicated hardware by one or more hardware devices other than programmable circuit systems instead. The machine-readable instructions may be distributed among multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that can facilitate communication between a server and an endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. In addition, although reference is made to Figure 5 The flowchart(s) shown describe example procedures, but may also be implemented using Figure 3Many other methods of the example sensor coordinator device 106 of the example sensor coordinator device 106. For example, the execution order of the blocks of the (multiple) flowcharts can be changed, and / or some of the described blocks can be changed, eliminated or combined. Additionally or alternatively, any or all of the blocks in the flowchart can be implemented by one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are constructed to perform corresponding operations without executing software or firmware. The programmable circuit system can be distributed in different network locations and / or located locally in one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.). For example, the programmable circuit system can be a CPU and / or FPGA located in the same package (e.g., in the same integrated circuit (IC) package or in two or more separate housings), one or more sub-processors in a single machine, multiple processors distributed between multiple servers in a server rack, multiple sub-processors distributed between one or more server racks, etc., and / or any (multiple) combinations thereof.

[0083] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), or a data structure (e.g., as part(s) of instructions, code, code representation, etc.) that may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., located at the same or different locations of a network or collection of networks (e.g., in the cloud, an edge device, etc.) , server). The machine-readable instructions may need to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, redistributed, compiled, etc., in order to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and / or stored on separate computing devices, where the parts, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations that together may form a program as described herein.

[0084] In another example, the machine-readable instructions may be stored in a state that can be read by the programmable circuit system, but a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., may need to be added in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions (e.g., stored settings, data inputs, recorded network addresses, etc.) may need to be configured before the machine-readable instructions and / or (multiple) corresponding programs can be executed in whole or in part. Therefore, as used herein, a machine-readable, computer-readable and / or machine-readable medium may include (multiple) instructions and / or programs, regardless of the specific format or state of (multiple) machine-readable instructions and / or programs.

[0085] The machine-readable instructions described herein may be represented in any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented in any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0086] As mentioned above, Figure 5The example operations of can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transient computer-readable and / or machine-readable media. As used herein, the terms non-transient computer-readable medium, non-transient computer-readable storage medium, non-transient machine-readable medium, and / or non-transient machine-readable storage medium are explicitly defined to include any type of computer-readable storage device and / or storage disk, and exclude propagation signals and transmission media. Examples of such non-transient computer-readable media, non-transient computer-readable storage media, non-transient machine-readable media, and / or non-transient machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage device or storage disk, wherein information is stored therein for any duration (e.g., long-term, permanent, short-term, temporary buffering, and / or caching of information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware to retain information over a period of time, but exclude propagating signals and transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuit system, which may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or manufactured to perform computer-readable instructions and machine-readable instructions, etc.

[0087] "Include" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim employs any form of "include" or "comprise" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or used in any type of claim statement, it should be understood that additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or statement. As used herein, when the phrase "at least" is used as a transitional term, such as in the preamble of a claim, it is open-ended, just as the terms "comprising" and "including" are open-ended. For example, when used in a form such as A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or performance of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A and B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of a process, instruction, action, activity, and / or step, the phrase "at least one of A or B" is intended to refer to an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0088] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude the plural. As used herein, the term "a" or "an" object refers to one or more of that object. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. In addition, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, these features may also be combined together, and being included in different examples or claims does not mean that the combination of features is not feasible and / or not advantageous.

[0089] Figure 5 is a flow chart representing example machine-readable instructions and / or example operations 500 that may be executed, instantiated, and / or performed by programmable circuitry to implement the sensor coordinator device 106. When the event manager circuitry 314 optionally observes a change in an input, Figure 5 The example machine readable instructions and / or example operations 500 begin. (Block 502). The input may come from any source connected to the event manager circuit system 314, including but not limited to sensors 108 and 310, memory 306, field devices 102, controllers 110, etc. Therefore, the type of change identified in block 502 may depend on the source of the input. The change may include but is not limited to a change in voltage generated by one of the sensors 108 or 310, a new value stored in an address of the memory 306, a digital message received from the controller 110, a 4-20mA analog message received from the field device 102, etc.

[0090] The event manager circuit system 314 determines whether the change satisfies a trigger. (Block 504). As used herein, a trigger refers to any condition that causes the sensor coordinator device 106 to perform an action when satisfied. The type of trigger can vary based on the type of change observed in block 502. For example, a first trigger can be satisfied when the output voltage Vsensor received from one of the sensors 108 or 310 exceeds a threshold voltage. A second trigger can be satisfied when the amount of data stored in a portion of the memory 306 exceeds a threshold capacity (e.g., 850 kilobytes in a 1 megabyte cache are filled with sensor measurements). A third trigger can be satisfied when a message from a field device 102 or controller 110 has a specific message. In an example where block 502 is not implemented and the event manager circuit system 314 does not observe a change in the input, the fourth trigger can be satisfied by a certain amount of time. The event manager circuit system 314 can additionally or alternatively check other triggers based on the input and operation of the sensor coordinator device 106. If the event manager circuitry 314 determines that the change does not satisfy the trigger (block 504: NO), control returns to block 502 where the event manager circuitry 314 optionally observes another change in the input.

[0091] If the event manager circuitry 314 determines that the change does satisfy the trigger (block 504: yes), the event manager circuitry 314 determines whether the trigger causes recording. (block 506). Each trigger corresponds to at least one action that is performed or executed by the sensor coordinator device 106 when the trigger condition is satisfied. In some examples, the action is to record sensor data. If the trigger does not cause recording (block 506: no), control passes to block 510. If the trigger does cause recording (block 506: yes), the event manager circuitry 314 causes the data recorder circuitry 312 to record data. (block 508). The data may correspond to a measurement value recorded from the sensor 108 or the sensor 310. In such an example, the source of the measurement is defined by the action corresponding to the trigger.

[0092] The event manager circuitry 314 determines whether the trigger causes a transmission. (Block 510). If the trigger does not cause a transmission (Block 510: No), control passes to block 516. If the trigger does cause a transmission (Block 510: Yes), the event manager circuitry 314 causes the protocol converter circuitry 316 to convert the data based on a communication protocol. (Block 512). The type of communication protocol may depend on the device that will receive the converted data, which is defined by the action corresponding to the trigger. For example, if the action describes a transmission to the field device 102, the protocol converter circuitry 316 converts the data to a wired protocol. Similarly, if the action describes a transmission to the controller 110, the protocol converter circuitry 316 converts the data to a wireless communication protocol used by the controller 110 (e.g., or Low energy consumption).

[0093] The event manager circuit system 314 causes the sensor coordinator device 106 to transmit the converted data. (Block 514). The event manager circuit system 314 uses the action corresponding to the trigger as a basis for determining which component of the sensor coordinator device 106 performs the transmission. For example, if the action describes a transmission to the field device 102, the protocol converter circuit system 316 causes the analog terminal 304 to transmit the converted data through the wired connection. Similarly, if the action describes a transmission to the controller 110, the event manager circuit system 314 causes the wireless interface circuit system 308 to transmit a message.

[0094] The event manager circuitry 314 determines whether the trigger causes a notification. (Block 516). If the trigger does not cause a notification (Block 516: No), control proceeds to block 520. If the trigger does cause a notification (Block 516: Yes), the event manager circuitry 314 causes one or more components within the audio / visual output 318 to provide a notification. (Block 518). In some examples, the notification may be achieved by a light, screen, or speaker turning on. In some examples, the notification will be achieved by a light changing color, a screen updating a graphical component, or a speaker changing tone. The notification may additionally or alternatively be achieved by different combinations of audio and visual signals.

[0095] The event manager circuitry 314 determines whether the sensor coordinator device 106 is still powered on (block 520). If the sensor coordinator device 106 is still powered on (block 520: yes), control returns to block 502, where the event manager circuitry 314 optionally observes additional changes in inputs. When the sensor coordinator device 106 is no longer powered on, the machine-readable instructions and / or operations end (block 520: no).

[0096] exist Figure 5 In the example flow chart of , for simplicity, the event manager circuit system 314 checks and performs actions (eg, recording, transmitting, notifying) in series. In practice, the event manager circuit system 314 may check and / or perform one or more actions in parallel.

[0097] Figure 5 The example flowchart of provides examples of some actions that can be performed after the trigger is satisfied. In some examples, the trigger causes the sensor coordinator device 106 to perform Figure 5For example, the trigger may also cause the event manager to change a value in memory 306, change a configuration to modify the performance of the programmable circuit system, and so on.

[0098] The first action prompted by the first trigger may also satisfy the condition of the second trigger, thereby prompting the second action. Advantageously, the event manager circuit system 314 can combine triggers in this way to form a complex logical workflow. For example, it is assumed that the passage of a set amount of time satisfies the first trigger. In response, the event manager circuit system 314 causes the data recorder circuit system 312 to start recording the measured value from the sensor 108A. The measured value begins to change the value in the memory 306, which satisfies the second trigger. In response, the event manager circuit system 314 causes the audio / visual output 318 to turn off the green light and turn on the yellow light (for example, to indicate that the sensor coordinator device 106 has been switched from standby mode to measurement mode). The data recorder circuit system 312 changes the flag in the memory when the measurement is completed, which satisfies the third trigger and causes the event manager circuit system 314 to access the new measured value. If the new value is within the expected range, the fourth trigger is satisfied. In response to the fourth trigger, the event manager circuit system 314 causes the audio / visual output 318 to turn off the yellow light and turn on the green light. Alternatively, if the new value is not within the expected range, the fifth trigger is satisfied. In response to the fifth trigger, the event manager circuit system 314 causes the audio / visual output 318 to turn off the yellow light and turn on the red light (e.g., to indicate that an error has occurred). In response to the fifth trigger, the event manager circuit system 314 also causes the protocol converter circuit system 316 to package the new value into group (eg, so errors can be reported to controller 110).

[0099] The above example is one implementation of a logical workflow supported by the sensor coordinator device 106. In general, a logical workflow may include any number of triggers and operations. The triggers and operations that form the logical workflow may be connected in any manner. One or more instructions within the logical workflow may be pre-programmed into the sensor coordinator device 106, received from the field device 102, or received from the controller 110.

[0100] Figure 6 It means that Figure 3 Flowchart of example machine readable instructions and / or example operations executed, instantiated, and / or performed by an example programmable circuit system of a sensor coordinator device. The machine readable instructions and / or operations 600 begin when one or more of the analog terminals 304 obtain a first measurement from the field device 102, the first measurement corresponding to a first sensor in the sensor 408. (Block 602). Figure 6 In the example, the first communication protocol is wired protocol because the field device 102 is HART enabled and has a wired connection with the sensor coordinator device 106.

[0101] The event manager circuitry 314 causes the data logger circuitry 312 to acquire a second measurement from a second sensor separate from the field device 102 without using the first communication protocol. (Block 604). The second sensor may be one of the sensors 108 or one of the sensors 310. The data logger circuitry 312 may determine configuration parameters (e.g., sampling rate, filtering technique, etc.) for acquiring the second measurement.

[0102] Event manager circuitry 314 causes wireless interface circuitry 308 to wirelessly transmit the first measurement and the second measurement to controller 110 using a second communication protocol. (Block 606). The second communication protocol may be implemented as To achieve wireless transmission, the event manager circuit system 314 causes the protocol converter circuit system 316 to convert the first measurement value from the wired The protocol is converted to a second communication protocol, and the second measurement value is packaged into one or more packets formatted in the second communication protocol.

[0103] Event manager circuitry 314 may cause operations of 604 and 606 in response to any number or types of triggers. In some examples, the output of block 602 satisfies a trigger that causes execution of block 604, and the output of block 604 satisfies a trigger that causes execution of block 606. In other examples, the triggers that cause execution of blocks 604 and 606 are unrelated.

[0104] The machine readable instructions and / or operations 600 are combined Figure 5 Example Implementation of Described Logical Workflow. Sensor coordinator device 106 may implement other logical workflows in accordance with the teachings of the present disclosure.

[0105] Figure 7 is a block diagram of an example programmable circuit system platform 700 that is structured to execute and / or instantiate Figure 5 Example machine readable instructions and / or example operations to implement Figure 3 The sensor coordinator device 106 of the programmable circuit system platform 700 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, such as an iPad TMtablet computer (e.g., tablet computer), personal digital assistant (PDA), internet appliance, DVD player, CD player, digital video recorder, Blu-ray player, game console, personal video recorder, set-top box, headsets (e.g., augmented reality (AR) headsets, virtual reality (VR) headsets, etc.) or other wearable device, or any other type of computing and / or electronic device.

[0106] The programmable circuit system platform 700 of the illustrated example includes a programmable circuit system 712. The programmable circuit system 712 of the illustrated example is hardware. For example, the programmable circuit system 712 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired series or manufacturer. The programmable circuit system 712 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 712 implements the data recorder circuit system 312, the event manager circuit system 314, and the protocol converter circuit system 316.

[0107] The programmable circuit system 712 of the illustrated example includes a local memory 713 (e.g., cache, registers, etc.). The programmable circuit system 712 of the illustrated example communicates with main memory 714, 716 (including volatile memory 714 and non-volatile memory 716) via a bus 718. The volatile memory 714 can be implemented by a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), and / or any other type of RAM device. The non-volatile memory 716 can be implemented by a flash memory and / or any other desired type of memory device. Access to the main memory 714, 716 of the illustrated example is controlled by a memory controller 717. In some examples, the memory controller 717 can be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired series or manufacturer, or any other type of circuit system for managing data flow in and out of the main memory 714, 716. In this example, the local memory 713, the main memory 714, and / or the main memory 716 implement the memory 306.

[0108] The programmable circuit system platform 700 of the illustrated example also includes an interface circuit system 720. The interface circuit system 720 may be implemented by hardware that complies with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, Interface 720 implements digital terminal 302 , analog terminal 304 , and wireless interface circuit system 308 .

[0109] In the example shown, one or more input devices 722 are connected to the interface circuitry 720. The input device(s) 722 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuitry 712. The input device(s) 722 may be implemented by, for example, sensors 108, sensors 310, keyboards, buttons, mice, touch screens, trackpads, trackballs, etc., and / or speech recognition systems.

[0110] One or more output devices 724 are also connected to the interface circuit system 720 of the illustrated example. The output device(s) 724 may be implemented as, for example, an audio / visual output 318 (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switch (IPS) display, a touch screen, a speaker, etc.). Thus, the interface circuit system 720 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit system, such as a GPU.

[0111] The interface circuitry 720 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate data exchange with external machines (e.g., any type of computing device) over the network 726. Communications may be through, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

[0112] The programmable circuit system platform 700 of the illustrated example also includes one or more mass storage disks or devices 728 for storing firmware, software and / or data. Examples of such mass storage disks or devices 728 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0113] Can be Figure 5 and Figure 6 The machine-readable instructions 732 implemented by the machine-readable instructions may be stored in the mass storage device 728, in the volatile memory 714, in the non-volatile memory 716, and / or on at least one removable, non-transitory computer-readable storage medium (such as a CD or DVD).

[0114] Figure 8 yes Figure 7 712 of the programmable circuit system 712. In this example, Figure 7The programmable circuit system 712 is implemented by the microprocessor 800. For example, the microprocessor 800 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit system). The microprocessor 800 executes Figure 5 and Figure 6 Some or all of the machine readable instructions of the flowchart to effectively Figure 2 The circuit system is instantiated as a logic circuit to perform operations corresponding to these machine-readable instructions. In some such examples, Figure 3 The circuit system is instantiated by the hardware circuits of the microprocessor 800 in combination with machine-readable instructions. For example, the microprocessor 800 can be implemented by a multi-core hardware circuit system such as a CPU, DSP, GPU, XPU, etc. Although it can include any number of example cores 802 (for example, 1 core), the microprocessor 800 of this example is a multi-core semiconductor device including N cores. The cores 802 of the microprocessor 800 can operate independently, or can cooperate to execute machine-readable instructions. For example, the machine code corresponding to a firmware program, an embedded software program, or a software program can be executed by one of the cores 802, or can be executed by multiple cores in the core 802 at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more cores in the core 802. The software program may correspond to a program executed by Figure 5 and Figure 6 A flowchart may represent a portion or all of machine-readable instructions and / or operations.

[0115] The core 802 can communicate via a first example bus 804. In some examples, the first bus 804 can be implemented by a communication bus to implement communications associated with (multiple) cores in the core 802. For example, the first bus 804 can be implemented by at least one of an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 804 can be implemented by any other type of computing or electrical bus. The core 802 can obtain data, instructions, and / or signals from one or more external devices via an example interface circuit system 806. The core 802 can output data, instructions, and / or signals to one or more external devices via the interface circuit system 806. Although the core 802 of this example includes an example local memory 820 (e.g., a level 1 (L1) cache, which can be split into an L1 data cache and an L1 instruction cache), the microprocessor 800 also includes an example shared memory 810, which can be shared by the core (e.g., a level 2 (L2 cache)) for high-speed access to data and / or instructions. Data and / or instructions may be transferred (eg, shared) by writing to and / or reading from the shared memory 810. The local memory 820 of each core in the core 802 and the shared memory 810 may be a plurality of levels of cache memory and main memory (eg, Figure 7 The cache memory is a part of a storage device hierarchy of main memory 714, 716 of the main memory 714, 716. Generally, memory at higher levels in the hierarchy has lower access times and smaller storage capacities than memory at lower levels. Changes to various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0116] Each core 802 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit system. Each core 802 includes a control unit circuit system 814, an arithmetic and logic (AL) circuit system (sometimes referred to as an ALU) 816, a plurality of registers 818, a local memory 820, and a second example bus 822. Other structures may exist. For example, each core 802 may include a vector unit circuit system, a single instruction multiple data (SIMD) unit circuit system, a load / store unit (LSU) circuit system, a branch / jump unit circuit system, a floating point unit (FPU) circuit system, etc. The control unit circuit system 814 includes a semiconductor-based circuit structured to control (e.g., coordinate) data movement within the corresponding core 802. The AL circuit system 816 includes a semiconductor-based circuit structured to perform one or more mathematical and / or logical operations on data within the corresponding core 802. The AL circuit system 816 of some examples performs integer-based operations. In other examples, the AL circuit system 816 also performs floating-point operations. In other examples, AL circuitry 816 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating-point operations. In some examples, AL circuitry 816 may be referred to as an arithmetic logic unit (ALU).

[0117] Registers 818 are semiconductor-based structures for storing data and / or instructions, such as the results of one or more of the operations performed by the AL circuit system 816 of the corresponding core 802. For example, registers 818 may include vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Registers 818 may include vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Figure 8 As shown, the registers 818 are arranged in a memory bank. Alternatively, the registers 818 may be organized in any other arrangement, format, or structure, such as by being distributed throughout the core 802 to reduce access time. The second bus 822 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0118] Each core 802 and / or more generally the microprocessor 800 may include additional and / or alternative structures in addition to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more aggregation / common grid stops (CMSs), one or more shifters (e.g., (multiple) barrel shifters), and / or other circuit systems. The microprocessor 800 is a semiconductor device that is manufactured to include many transistors that are connected to implement the above structures in one or more integrated circuits (ICs) housed in one or more packages.

[0119] The microprocessor 800 may include and / or collaborate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, the accelerator is implemented by a logic circuitry to perform certain tasks faster and / or more efficiently than a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as described herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be mounted on the microprocessor 800, in the same chip package as the microprocessor 800, and / or in one or more packages separate from the microprocessor 800.

[0120] Fig. 9 yes Figure 7 900. In this example, programmable circuit system 712 is implemented by FPGA circuit system 900. For example, FPGA circuit system 900 can be implemented by an FPGA. FPGA circuit system 900 can be used, for example, to perform operations that can otherwise be performed by executing corresponding machine-readable instructions. Figure 8 However, once configured, the FPGA circuit system 900 instantiates operations and / or functions corresponding to the machine-readable instructions in hardware, and therefore, can generally perform these operations / functions faster than a general-purpose microprocessor executing corresponding software to perform the operations / functions.

[0121] More specifically, Figure 8 The microprocessor 800 (which can be programmed to execute Figure 5 and Figure 6 Compared to a general-purpose device in which some or all of the machine-readable instructions are represented by a flowchart, but whose interconnections and logic circuitry are fixed after manufacture, Fig. 9 The example FPGA circuit system 900 includes interconnect and logic circuit systems, which can be configured, structured, programmed and / or interconnected in different ways after manufacturing to instantiate, for example, Figure 5 and Figure 6The flowcharts represent some or all of the operations / functions corresponding to the machine-readable instructions. In particular, FPGA circuit system 900 can be considered as an array of logic gates, interconnects, and switches. The switches can be programmed to change the way the logic gates are connected to each other through the interconnects, effectively forming one or more dedicated logic circuits (unless and until FPGA circuit system 900 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on the data received by the input circuit system. These operations can correspond to Figure 5 and Figure 6 Thus, FPGA circuit system 900 can be configured and / or structured to effectively communicate with Figure 5 and Figure 6 Some or all of the operations / functions corresponding to the machine-readable instructions of the flowchart are instantiated as dedicated logic circuits to perform the operations / functions corresponding to these software instructions in a dedicated manner similar to an ASIC. Therefore, the FPGA circuit system 900 can execute the operations / functions corresponding to these software instructions faster than a general-purpose microprocessor. Figure 5 and Figure 6 Some or all of the machine-readable instructions correspond to operations / functions.

[0122] exist Fig. 9 In some examples, the FPGA circuit system 900 is configured and / or structured in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file can be compiled and / or generated based on instructions of a hardware description language (HDL) (such as Lucid, very high speed integrated circuit (VHSIC) hardware description language, or Verilog). For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions of the HDL; the code / program can be translated into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) can be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some examples, Fig. 9 The FPGA circuit system 900 can access and / or load a binary file to cause Fig. 9 The FPGA circuit system 900 is configured and / or structured to perform one or more operations / functions. For example, a binary file may be obtained by Fig. 9 The FPGA circuit system 900 can be accessed by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions to cause Fig. 9 Configuration and / or structuring of the FPGA circuit system 900 or (multiple) parts thereof.

[0123] In some examples, the binary file is compiled, generated, transformed, and / or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform can translate a first instruction (e.g., code or program) corresponding to one or more operations / functions of a high-level language (e.g., C, C++, Python, etc.) into a second instruction corresponding to one or more operations / functions of the HDL. In some such examples, the binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instruction. In some examples, Fig. 9 The FPGA circuit system 900 can access and / or load a binary file to cause Fig. 9 The FPGA circuit system 900 is configured and / or structured to perform one or more operations / functions. For example, a binary file may be obtained by Fig. 9 The FPGA circuit system 900 can be accessed by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions to cause Fig. 9 Configuration and / or structuring of the FPGA circuit system 900 or (multiple) parts thereof.

[0124] Fig. 9 The FPGA circuit system 900 includes an example input / output (I / O) circuit system 902 for obtaining and / or outputting data from / to an example configuration circuit system 904 and / or external hardware 906. For example, the configuration circuit system 904 can be implemented by an interface circuit system that can obtain a binary file that can be implemented by a bitstream, data, and / or machine-readable instructions to configure the FPGA circuit system 900 or (multiple) portions thereof. In some such examples, the configuration circuit system 904 can obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), etc. and / or any (multiple) combination thereof. In some examples, the external hardware 906 can be implemented by an external hardware circuit system. For example, the external hardware 906 can be implemented by Figure 8 It is implemented by the microprocessor 800.

[0125] FPGA circuitry 900 also includes an array of example logic gate circuitry 908, a plurality of example configurable interconnects 910, and example storage circuitry 912. Logic gate circuitry 908 and configurable interconnects 910 are configurable to instantiate a plurality of example logic gate circuitry 908, and a plurality of example storage circuitry 912. Figure 5 and Figure 6One or more operations / functions corresponding to at least some of the machine-readable instructions and / or other desired operations. Fig. 9 The logic gate circuit system 908 shown is manufactured in the form of blocks or groups. Each block includes a semiconductor-based electrical structure that can be configured as a logic circuit. In some examples, the electrical structure includes a logic gate (e.g., And gate, Or gate, Nor gate, etc.) that provides a basic building block for the logic circuit. An electrically controlled switch (e.g., transistor) is present in each of the logic gate circuit systems 908 to implement the configuration of the electrical structure and / or logic gate to form a circuit for performing the desired operation / function. The logic gate circuit system 908 may include other electrical structures, such as a lookup table (LUT), a register (e.g., a trigger or latch), a multiplexer, etc.

[0126] The configurable interconnect 910 of the illustrated example is a conductive path, trace, via, or the like, which may include an electrically controlled switch (e.g., a transistor) whose state may be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit systems 908, thereby programming a desired logic circuit.

[0127] The storage circuit system 912 of the illustrated example is structured to store (multiple) results of one or more of the operations performed by the corresponding logic gates. The storage circuit system 912 can be implemented by registers, etc. In the illustrated example, the storage circuit system 912 is distributed between the logic gate circuit system 908 to facilitate access and increase execution speed.

[0128] Fig. 9 The example FPGA circuit system 900 also includes an example special operation circuit system 914. In this example, the special operation circuit system 914 includes a special circuit system 916, which can be called to implement common functions to avoid programming these functions on site. Examples of such special circuit systems 916 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory, and multiplier accumulator circuit systems. There may be other types of special circuit systems. In some examples, the FPGA circuit system 900 may also include an example general programmable circuit system 918, such as an example CPU 920 and / or an example DSP 922. There may be other general programmable circuit systems 918, such as GPUs, XPUs, etc., which may be programmed to perform other operations in addition or alternatively.

[0129] although Figure 8 and Fig. 9 Shows Figure 7These are two example implementations of the programmable circuit system 712, but many other approaches are also contemplated. For example, the FPGA circuit system may include an onboard CPU, such as Figure 8 One or more of the example CPUs 920. Thus, Figure 7 The programmable circuit system 712 may additionally be configured by combining at least Figure 8 An example microprocessor 800 and Fig. 9 In some such hybrid examples, Figure 8 One or more cores 802 may execute Figure 5 and Figure 6 The flowchart represents a first portion of machine-readable instructions to perform (multiple) first operations / functions, Fig. 9 The FPGA circuit system 900 can be configured and / or structured to perform the same as that Figure 5 , Figure 6 The second portion of the computer readable instructions represented by the flowchart may correspond to (a plurality of) second operations / functions, and / or the ASIC may be configured and / or structured to perform the same Figure 5 and Figure 6 The third portion of the machine-readable instructions represented by the flowchart corresponds to (multiple) third operations / functions.

[0130] It should be understood, therefore, Figure 3 Some or all of the circuitry of may be instantiated at the same or different times. For example, Figure 8 The same and / or different portions of the microprocessor 800 may be programmed to execute portions of the machine-readable instructions at the same and / or different times. In some examples, Fig. 9 The same and / or different portions of the FPGA circuit system 900 may be configured and / or structured to perform operations / functions corresponding to the portions of the machine-readable instructions at the same and / or different times.

[0131] In some examples, Figure 3 Some or all of the circuitry of can be instantiated, for example, in one or more threads that execute concurrently and / or serially. Figure 8 The microprocessor 800 can execute machine-readable instructions in one or more threads of execution concurrently and / or serially. In some examples, Fig. 9 The FPGA circuit system 900 can be configured and / or structured to perform operations / functions concurrently and / or serially. In addition, in some examples, Figure 3 Some or all of the circuitry in the Figure 8 The microprocessor 800 is implemented within one or more virtual machines and / or containers.

[0132] In some examples, Figure 7 The programmable circuit system 712 can be in one or more packages. For example, Figure 8 The microprocessor 800 and / or Fig. 9 The FPGA circuit system 900 can be in one or more packages. In some examples, the XPU can be composed of Figure 7 The XPU may be implemented by a programmable circuit system 712, which may be in one or more packages. For example, the XPU may include a CPU in a package (e.g., Figure 8 Microprocessor 800, Fig. 9 CPU 920, etc.), a DSP in another package (e.g., Fig. 9 DSP 922 in another package), a GPU in another package, and an FPGA in another package (e.g., Fig. 9 FPGA circuit system 900).

[0133] Fig.10 A block diagram is shown in FIG. 1 , which shows an example software distribution platform 1005 for distributing software such as Figure 7 The example software distribution platform 1005 may be implemented by any computer server, data facility, cloud service, etc. that is capable of storing software and transmitting it to other computing devices. The third party may be a customer of the entity that owns and / or operates the software distribution platform 1005. For example, the entity that owns and / or operates the software distribution platform 1005 may be a software (such as a hardware device owned and / or operated by a third party from the owner and / or operator of the software distribution platform). Figure 7 The third party may be a consumer, user, retailer, original equipment manufacturer, etc., who purchases and / or licenses the software for use and / or resale and / or sublicense. In the example shown, the software distribution platform 1005 includes one or more servers and one or more storage devices. The storage device stores the machine-readable instructions 732, which may correspond to the above-described Figure 5 and Figure 6The example machine-readable instructions of the example software distribution platform 1005 are one or more servers in communication with the example network 1010, which may correspond to the Internet and / or any one or more of the above-described example networks. In some examples, one or more servers respond to a request to transfer software to a requesting party as part of a commercial transaction. The delivery, sale, and / or payment of the license of the software may be processed by one or more servers of the software distribution platform and / or a third-party payment entity. The server enables a purchaser and / or licensor to download the machine-readable instructions 732 from the software distribution platform 1005. For example, with Figure 5 and Figure 6 The software corresponding to the example machine-readable instructions of the example programmable circuit system platform 700 can be downloaded to the example programmable circuit system platform 700, which will execute the machine-readable instructions 732 to implement the sensor coordinator device 106. In some examples, one or more servers of the software distribution platform 1005 periodically provide, transmit and / or force software updates (e.g., Figure 7 Example machine readable instructions 732) to ensure that improvements, patches, updates, etc. are distributed and applied to the software at the end-user device. Although referred to as software above, alternatively, the distributed "software" may also be firmware.

[0134] It can be understood from the above that the use of and The disclosed systems, apparatus, articles of manufacture, and methods improve the efficiency of using computing devices by packaging data recorded from third-party sensors into or The protocol and monitors one or more thresholds so that changes in input (e.g., messages received from HART-enabled devices, readings from third-party sensors, new values ​​in memory, etc.) can trigger actions to be performed by the sensor coordinator device 106 or a connected HART-enabled device. Thus, the disclosed systems, apparatus, articles, and methods are intended to provide one or more improvements in the operation of a machine such as a computer or other electronic device and / or mechanical device.

[0135] Disclosed herein are example methods, apparatus, systems, and articles of manufacture for managing sensor data.Additional examples and combinations thereof include the following.

[0136] Example 1 includes an apparatus, comprising:

[0137] an interface circuit system configured to connect to a field device, the field device including a first sensor, the field device being powered by a power supply;

[0138] computer readable instructions; and

[0139] Programmable circuitry, powered by a power source, and computer-readable instructions causing the programmable circuitry to:

[0140] obtaining a first measurement from the field device using a first communication protocol, the first measurement corresponding to a first sensor;

[0141] acquiring a second measurement from a second sensor separate from the field device without using the first communication protocol; and

[0142] The first measurement and the second measurement are wirelessly transmitted to the controller using a second communication protocol.

[0143] Example 2 includes the apparatus according to Example 1, wherein the power supply, the field device, and the apparatus form a 4-20 milliamp (mA) current loop.

[0144] Example 3 includes the apparatus of Example 1, wherein the first communication protocol is a wired high-speed addressable remote transducer protocol.

[0145] Example 4 includes the apparatus of Example 1, wherein the second communication protocol is Bluetooth Low Energy (BLE) protocol.

[0146] Example 5 includes the apparatus of Example 1, wherein the second communication protocol is a wireless high-speed addressable remote transducer protocol.

[0147] Example 6 includes the apparatus of Example 1, wherein the programmable circuitry records the second measurement in response to an instruction from the field device.

[0148] Example 7 includes the apparatus of Example 1, wherein the computer readable instructions cause the programmable circuitry to transmit the first measurement value and the second measurement value in response to an instruction from the field device.

[0149] Example 8 includes the apparatus of Example 1, wherein the computer readable instructions cause the programmable circuit system to transmit instructions to the field device, the instructions causing the field device to: (a) record a first measurement from the first sensor, and (b) transmit the first measurement to the apparatus.

[0150] Example 9 includes the apparatus of Example 1, wherein the computer readable instructions cause the programmable circuitry to trigger an audio or visual notification based on the first measurement and the second measurement.

[0151] Example 10 includes the apparatus of Example 1, wherein the programmable circuit system includes one or more of the following:

[0152] at least one of a central processing unit, a graphics processing unit, or a digital signal processor, the at least one of the central processing unit, the graphics processing unit, or the digital signal processor having control circuitry for controlling movement of data within the programmable circuitry, arithmetic and logic circuitry for performing one or more first operations corresponding to the machine-readable data, and one or more registers for storing results of the one or more first operations, the machine-readable data in the device;

[0153] a field programmable gate array (FPGA), the FPGA comprising logic gate circuitry, a plurality of configurable interconnects, and storage circuitry, the logic gate circuitry and the plurality of configurable interconnects being used to perform the one or more second operations, the storage circuitry being used to store results of the one or more second operations; or

[0154] An application specific integrated circuit (ASIC) includes logic gate circuitry for performing one or more third operations.

[0155] Example 11 includes a non-transitory machine-readable storage medium including instructions for causing a programmable circuit system to at least:

[0156] obtaining a first measurement from a field device using a first communication protocol, the first measurement corresponding to a first sensor within the field device, the field device being powered by a power supply;

[0157] acquiring a second measurement from a second sensor separate from the field device without using the first communication protocol; and

[0158] The first measurement and the second measurement are wirelessly transmitted to the controller using a second communication protocol.

[0159] Example 12 includes the non-transitory machine-readable storage medium of Example 11, wherein the power supply, the field device, and the non-transitory machine-readable storage medium form a 4-20 milliamp (mA) current loop.

[0160] Example 13 includes the non-transitory machine-readable storage medium of Example 11, wherein the programmable circuitry records the second measurement in response to an instruction from the field device.

[0161] Example 14 includes the non-transitory machine-readable storage medium of Example 11, wherein the instructions cause the programmable circuitry to transmit the first measurement value and the second measurement value in response to the instruction from the field device.

[0162] Example 15 includes a non-transitory machine-readable storage medium according to Example 11, wherein the instructions cause the programmable circuit system to transmit instructions to the field device, the instructions causing the field device to: (a) record a first measurement value from the first sensor, and (b) transmit the first measurement value to the non-transitory machine-readable storage medium.

[0163] Example 16 includes the non-transitory machine-readable storage medium according to Example 11, wherein the instructions cause the programmable circuit system to trigger an audio or visual notification based on the first measurement value and the second measurement value.

[0164] Example 17 includes a method comprising:

[0165] obtaining, with the programmable circuit system, a first measurement from a field device using a first communication protocol, the first measurement corresponding to a first sensor within the field device, the field device being powered by a power supply;

[0166] acquiring, using the programmable circuitry and without using the first communication protocol, a second measurement from a second sensor separate from the field device; and

[0167] The first measurement and the second measurement are wirelessly transmitted to the controller using the programmable circuitry and a second communication protocol.

[0168] Example 18 includes the method of Example 17, wherein the power supply, the field device, and the programmable circuitry form a 4-20 milliamp (mA) current loop.

[0169] Example 19 includes the method of Example 17, further comprising recording the second measurement value in response to an instruction from the field device.

[0170] Example 20 includes the method of Example 17, further comprising transmitting the first measurement value and the second measurement value in response to an instruction from the field device.

[0171] The following claims are incorporated into this specification by reference. Although certain example systems, devices, articles, and methods are disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods that fully fall within the scope of the claims of this patent.

Claims

1. A device comprising: an interface circuit system configured to connect to a field device, the field device including a first sensor, the field device being powered by a power supply; computer readable instructions; as well as A programmable circuit system powered by the power supply, wherein the computer readable instructions cause the programmable circuit system to: obtaining a first measurement from the field device using a first communication protocol, the first measurement corresponding to the first sensor; acquiring a second measurement from a second sensor separate from the field device without using the first communication protocol; as well as The first measurement and the second measurement are wirelessly transmitted to a controller using a second communication protocol.

2. The apparatus of claim 1, wherein the power supply, the field device, and the apparatus form a 4-20 mA current loop.

3. The apparatus of claim 1, wherein the first communication protocol is a wired high-speed addressable remote transducer protocol.

4. The apparatus according to claim 1, wherein the second communication protocol is Low energy BLE protocol.

5. The apparatus of claim 1, wherein the second communication protocol is a wireless high-speed addressable remote transducer protocol.

6. The apparatus of claim 1, wherein the programmable circuitry records the second measurement in response to an instruction from the field device.

7. The apparatus of claim 1, wherein the computer-readable instructions cause the programmable circuitry to transmit the first measurement and the second measurement in response to instructions from the field device.

8. The apparatus of claim 1, wherein the computer-readable instructions cause the programmable circuit system to transmit instructions to the field device, the instructions causing the field device to: (a) record the first measurement from the first sensor, and (b) transmit the first measurement to the apparatus.

9. The apparatus of claim 1, wherein the computer-readable instructions cause the programmable circuitry to trigger an audio or visual notification based on the first measurement and the second measurement.

10. The apparatus of claim 1, wherein the programmable circuitry comprises one or more of: at least one of a central processing unit, a graphics processing unit, or a digital signal processor, the at least one of the central processing unit, the graphics processing unit, or the digital signal processor having control circuitry for controlling movement of data within the programmable circuitry, arithmetic and logic circuitry for performing one or more first operations corresponding to machine-readable data, and one or more registers for storing results of the one or more first operations, the machine-readable data in the apparatus; A field programmable gate array (FPGA), the FPGA comprising a logic gate circuit system, a plurality of configurable interconnects, and a storage circuit system, the logic gate circuit system and the plurality of configurable interconnects being used to perform one or more second operations, the storage circuit system being used to store results of the one or more second operations; or The application specific integrated circuit ASIC includes a logic gate circuit system for performing one or more third operations.

11. A non-transitory machine-readable storage medium comprising instructions for causing a programmable circuit system to at least: obtaining a first measurement from a field device using a first communication protocol, the first measurement corresponding to a first sensor within the field device, the field device being powered by a power supply; acquiring a second measurement from a second sensor separate from the field device without using the first communication protocol; as well as The first measurement and the second measurement are wirelessly transmitted to a controller using a second communication protocol. 12 . The non-transitory machine-readable storage medium of claim 11 , wherein the power supply, the field device, and the non-transitory machine-readable storage medium form a 4-20 mA current loop.

13. The non-transitory machine-readable storage medium of claim 11, wherein the programmable circuitry records the second measurement in response to a change in an input satisfying a trigger.

14. The non-transitory machine-readable storage medium of claim 11, wherein the instructions cause the programmable circuitry to transmit the first measurement value and the second measurement value in response to a change in an input satisfying a trigger.

15. The non-transitory machine-readable storage medium of claim 11, wherein the instruction causes the programmable circuit system to transmit an instruction to the field device, the instruction causing the field device to: (a) record the first measurement value from the first sensor, and (b) transmit the first measurement value to the non-transitory machine-readable storage medium.

16. The non-transitory machine-readable storage medium of claim 11, wherein the instructions cause the programmable circuitry to trigger an audio or visual notification based on the first measurement value and the second measurement value.

17. A method comprising: obtaining, with the programmable circuit system, a first measurement from a field device using a first communication protocol, the first measurement corresponding to a first sensor within the field device, the field device being powered by a power source; acquiring, using the programmable circuitry and without using the first communication protocol, a second measurement from a second sensor separate from the field device; as well as The first measurement and the second measurement are wirelessly transmitted to a controller using the programmable circuitry and a second communication protocol.

18. The method of claim 17, wherein the power supply, the field device, and the programmable circuitry form a 4-20 mA current loop.

19. The method of claim 17, further comprising recording the second measurement in response to an instruction from the field device.

20. The method of claim 17, further comprising transmitting the first measurement and the second measurement in response to an instruction from the field device.

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