A high-reliability clock synchronization method for micro PNT systems based on CSAC

Abstract

The present invention provides a high-reliability clock synchronization method for a micro PNT system based on CSAC. First, the 1pps signal of the CSAC and the 1pps signal of the GNSS are acquired in real time to calculate the clock difference signal. When the GNSS signal is valid, it is determined whether the clock difference signal is greater than a preset threshold. If it is greater than the threshold, the coarse adjustment function of the chip-level atomic clock is enabled. Otherwise, the following fine adjustment operation is performed. If the 1pps signal of the GNSS fails, the system will automatically enable the clock hold function, and predict and maintain the time accuracy of the CSAC through the extended Kalman filter method, ensuring that a high time synchronization accuracy can be maintained during the period when the GNSS signal is lost. Once the GNSS signal is restored, the system will exit the clock hold mode and re-synchronize with the GNSS. The present invention solves the clock synchronization problem between CSAC and GNSS, thereby ensuring high-precision time synchronization of the system and significantly enhancing the reliability of the system.

Description

Technical Field

[0001] The present invention relates to the field of aviation navigation, and in particular to a high-reliability clock synchronization method for a micro PNT system based on CSAC. Background Art

[0002] The application value of atomic clock timing technology in positioning, communications, and navigation is becoming increasingly prominent. Chip-Scale Atomic Clocks (CSACs), the core of micro-PNT systems, are becoming a key technology supporting various applications due to their small size, low power consumption, and high precision.

[0003] In recent years, China has continuously advanced positioning and timing technologies based on high-precision atomic clocks during the construction and improvement of the Beidou Navigation Satellite System (BDS). CSAC-assisted GNSS systems have demonstrated significant advantages, particularly in complex environments such as drones, autonomous driving, and communication systems, where high-precision and continuous timing is crucial. Compared to traditional crystal oscillators, atomic clocks offer exceptionally high long-term stability and short-term accuracy, effectively improving the reliability and continuity of positioning and time synchronization even when satellite navigation signals are poor or intermittent.

[0004] Against this backdrop, domestic research institutes and enterprises have gradually accelerated research and breakthroughs in micro-PNT technologies. By using the GNSS system to calibrate and synchronize CSACs, combined with various clock calibration algorithms, such as Kalman filtering and adaptive algorithms, they can effectively eliminate long-term stability issues caused by the atomic clock's inherent frequency offset. Furthermore, to address complex environments where GNSS signals cannot provide a continuous and stable time reference, a series of adaptive timekeeping and synchronization algorithms have been designed. These algorithms enable CSACs to maintain high time accuracy even in the event of GNSS failure, thereby ensuring the continuity of the timing system.

[0005] Therefore, designing and implementing an adaptive time synchronization method based on atomic clocks not only meets the urgent domestic demand for high-precision timing technology, but also provides technical support and solutions for the development of future Micro-PNT systems. Summary of the Invention

[0006] The purpose of the present invention is to provide a high-reliability clock synchronization method for a micro PNT system based on CSAC to solve the clock synchronization problem between CSAC and GNSS, ensure high-precision time synchronization of the system, and improve the reliability of the system to achieve the purpose of accurate time synchronization.

[0007] To achieve the above objectives, the present invention provides a high-reliability clock synchronization method for a micro PNT system based on CSAC.

[0008] Therefore, the present invention adopts the above-mentioned high-reliability clock synchronization method for micro PNT systems based on CSAC, and the technical effects are as follows:

[0009] (1) The method provided by the present invention comprehensively considers the method of adjusting the clock signal of CSAC under different conditions. It can predict the clock difference between CSAC and GNSS when the GNSS signal fails, and perform time synchronization based on the clock difference prediction value, which greatly improves the robustness of the system and ensures the high precision of time synchronization.

[0010] (2) The present invention designs a high-reliability clock synchronization method for a micro-PNT system based on CSAC, which can predict the CSAC clock error data in combination with the historical data characteristics of CSAC, so that when the time source changes, the system can still maintain high-precision synchronization performance, effectively improving the reliability and stability of the synchronization system.

[0011] (3) The present invention adopts a dynamic adjustment strategy. When GNSS fails or is unavailable, it uses the high precision and short-term retention capability of the atomic clock to reduce the impact of clock source frequency drift, thereby ensuring that the system can still maintain a high time synchronization accuracy when not relying on external timing signals.

[0012] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is an architectural diagram of a high-reliability clock synchronization method for a micro PNT system based on CSAC in the present invention;

[0014] Figure 2 These are the three situations corresponding to the CASC clock error change trends in the fine adjustment mode of the present invention. Figure 2 (A) The absolute value of the CSAC clock error measurement is greater than 1 ns, and the clock error change trend is approaching 0 ns; Figure 2 (B) The CSAC clock error measurement value is within ±1ns, and the absolute value of the CSAC relative frequency deviation is greater than 1×10 -11 s / s; Figure 2 (C) The absolute value of the CSAC clock error measurement is greater than 1 ns, and the clock error change trend is away from 0 ns;

[0015] Figure 3 This is a flow chart of the clock holding algorithm in the present invention. DETAILED DESCRIPTION

[0016] The technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

[0017] Unless otherwise defined, technical or scientific terms used in the present invention shall have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0018] TDC-AS6500, or AS6500, is a high-performance time-to-digital conversion chip produced by ScioSense.

[0019] The MAX913 is a single high-speed, low-power comparator manufactured by Maxim Integrated.

[0020] CSAC is an innovative chip-scale atomic clock (Chip Scale Atomic Clock). It holds a significant position and significance in the field of atomic clocks. With its compact size, low power consumption, and relatively high accuracy, chip-scale atomic clocks have broad application prospects in numerous fields.

[0021] Example 1

[0022] The present invention provides a high-reliability clock synchronization method for a micro PNT system based on CSAC, comprising the following steps:

[0023] S1. Initialize each part of the microcontroller, especially the time-to-digital converter (TDC), and send relevant instructions;

[0024] Initialization of TDC includes:

[0025] S11. Initialize the TDC-AS6500 time interval measurement chip and the MAX913 comparator chip, use the 10 MHz signal output by the CSAC as the external reference clock, and use the MAX913 to shape the clock signal.

[0026] S12. The TDC-AS6500 communicates with the STM32H743IIT6 microcontroller through the SPI serial port to transmit control commands and clock error measurement results. The SPI bus uses the "0b100X_XXXX" instruction format to send the corresponding initialization parameters, where X represents the binary form of the register address. These parameters include the INTERRUPT pin, REFCLK pin, DISABLE pin, and RSTIDX pin.

[0027] S13, TDC-AS6500 identifies measurement events and triggers data acquisition by monitoring the level changes of its INTERRUPT pin. The chip uses an edge-triggered event timing method, using the start pulse of each reference clock cycle as the time reference point. During each trigger event, it accurately measures and calculates the time interval between the measurement channel signal and the rising edge of the reference clock signal in the previous cycle. The measurement results are broken down into two key parameters: the count value within the reference clock cycle (REFID) and the clock error precision measurement value (TSTOP). These parameters are recorded and stored in dedicated registers of CHANNELx for subsequent processing and analysis.

[0028] S2. Use the TDC to monitor and record in real time the 1 pps signal sent by the CSAC to channel STOP1 and the 1 pps signal sent by the GNSS receiver to channel STOP2, and calculate the clock difference Δt between the two 1 pps signals. 12 , thereby obtaining clock error data;

[0029] During each trigger event, accurately measure and calculate the time interval between the measurement channel signal and the rising edge of the reference clock signal in the previous cycle. The specific steps are as follows:

[0030] Time interval calculation: Calculate the time intervals of channel STOP1 and channel STOP2. The specific formula is as follows:

[0031] t stop =TSTOP+REF_DIV×REFID;

[0032] Where, t stop It represents the time interval of a single channel, and REF_DIV represents the frequency division coefficient.

[0033] Time interval difference calculation: Calculate the time interval difference Δt between channel STOP1 and channel STOP2 12 , the calculation formula is as follows:

[0034] Δt 12 =t stop1 -t stop2 ;

[0035] Where, t stop1 Indicates the time interval of the first channel, t stop2 Indicates the time interval of the second channel.

[0036] S3. Determine whether the GNSS signal is disconnected. The 1pps signal output by the GNSS receiver is connected to the STOP2 channel of the TDC chip. The STOP2 measurement result is used to determine whether the GNSS receiver's 1pps signal is disconnected. If the STOP2 measurement result is 0, it indicates that the GNSS 1pps signal is disconnected, and the process proceeds to step S8; otherwise, the process proceeds to step S4 to step S7.

[0037] S4. After executing steps S1 to S3 100 times without any problems, the system is considered to be in a stable state and adjustment judgment begins. To avoid discussing the positive and negative conditions of the clock error data, the clock error value is converted into its absolute value;

[0038] S5. Determine whether the clock difference is greater than 100ns. If so, proceed to step S6; otherwise, proceed to step S7;

[0039] S6. The system enters coarse adjustment mode. If the clock error is greater than 100ns, coarse synchronization is performed using the 1pps synchronization function of the CSAC to reduce the clock error between the CSAC and GNSS system time to within 100ns. The system then returns to step S5.

[0040] S7, the system enters the fine adjustment mode, in which the microcontroller uses a clock control algorithm based on the ping-pong method to accurately adjust the clock. First, the clock error historical data is fitted based on the traditional quadratic clock error model; second, the clock control adjustment value S is calculated based on the fitting results. n (n=1, 2, 3); finally, the CASC is frequency modulated in the opposite direction according to the clock control adjustment amount;

[0041] In fine adjustment mode, the microcontroller uses the ping-pong method to fit the quadratic clock error model. This model provides the key basis for subsequent precise adjustment, as follows:

[0042] While the reference signal is valid, the ping-pong algorithm keeps the CSAC in a free-running state and collects the clock difference between the CSAC and GNSS in real time. When the running time reaches the preset clock steering period, the least squares estimation method is used to analyze and process the historical clock difference data during this period to obtain the estimated values ​​of the secondary clock difference model parameters.

[0043] The quadratic clock error model is as follows:

[0044]

[0045] In this model, b0, b1, and b2 are the clock error model parameters to be fitted, which represent the CSAC initial phase deviation, CSAC initial frequency deviation, and CSAC frequency drift rate, respectively. t0 is the reference time point, and ε x is the random noise term;

[0046] In fine adjustment mode, the microcontroller uses a ping-pong-based clock control algorithm to precisely adjust the clock. This method uses the clock error trend reflected by the CSAC model to classify different situations and determine the corresponding clock control adjustment amount accordingly, as follows:

[0047] When the absolute value of the CSAC clock error measurement is greater than 1 ns and the clock error trend approaches 0 ns, the clock steering adjustment is set to S1, and the formula is as follows:

[0048]

[0049] Where x is the clock difference between CSAC and GNSS system time at the time of clock control operation, T is the control time constant, and β is the attenuation factor.

[0050] When the absolute value of the CSAC clock error measurement is greater than 1 ns, and the clock error trend is moving away from 0 ns, the clock control adjustment amount is set to S2, and the formula is as follows:

[0051]

[0052] Where α1 is the relative frequency deviation of CSAC in the current driving cycle;

[0053] When the clock error measurement value of CSAC is within ±1ns and the absolute value of the relative frequency deviation of CSAC is greater than 1×10 - 11 When s / s, the clock control adjustment amount is set to S3, and the formula is as follows:

[0054]

[0055] When the clock error measurement value of CSAC is within ±1ns and the absolute value of the relative frequency deviation of CSAC is not greater than 1×10 -11 When s / s, no control operation is performed to reduce the frequency adjustment of CSAC, that is, the clock control adjustment amount is set to 0;

[0056] The CSAC is adjusted using the obtained clock control adjustment; the relevant data is sorted and stored.

[0057] S8. When the GNSS signal is disconnected, the system enters the clock hold mode. In this mode, the microcontroller uses the clock hold algorithm to adjust the clock.

[0058] First, based on historical clock error data, the clock error model parameters are estimated using the extended Kalman filter (EKF) algorithm, using the CSAC's phase deviation, frequency deviation, and frequency drift rate as state variables. This results in a CSAC nonlinear clock error model. This model is then used to predict the clock error at the next moment. Finally, the clock holding conditions are established based on the CSAC nonlinear clock error model and its predicted values, and the necessary clock steering operations are performed accordingly.

[0059] The high-reliability clock synchronization method for a micro-PNT system based on CSAC according to claim 1 is characterized in that a clock holding condition is established based on the CSAC nonlinear clock error model and its predicted value, and necessary clock steering operations are performed based on this condition. The specific operations are as follows:

[0060] Clock hold condition judgment: If the absolute value of the clock error prediction value is less than 10ns, and the relative frequency deviation is less than |4×10-11|s / s, and the clock error prediction value shows a decreasing trend (approaching 0ns), then no clock steering operation is performed on the CSAC, and it is allowed to slowly converge in autonomous operation, ensuring that the clock error of the CSAC slowly converges to near 0ns in subsequent control cycles;

[0061] When the absolute value of the predicted clock error is not less than 10 ns, or the relative frequency deviation is not less than |4×10-11| s / s, or the predicted clock error diverges (moves away from 0 ns), necessary clock steering operations are required: using the CSAC's 10,000-second frequency stability as a reference, small adjustments are made to gradually return the CSAC's clock error to near 0 ns.

[0062] After each cycle, the current clock error data is stored and used to update the extended Kalman filter model in the next cycle; if the GNSS signal returns to normal, the system will exit the clock hold mode and continue to use GNSS for 1pps calibration synchronization.

[0063] During the clock maintenance process, the EKF algorithm is used to estimate the clock error model parameters, thereby obtaining the CSAC nonlinear clock error model, whose mathematical form is as follows:

[0064]

[0065] Where x(t) is the clock error of the atomic clock; t is the time difference between the current measurement time and the initial measurement time; a0 is the initial phase deviation of the CSAC; a1 is the initial frequency deviation of the CSAC; a2 is the CSAC frequency drift rate, also known as the aging rate; ε x (t) is the CSAC random noise, a0, a1 and a2 are the deterministic time components that affect the atomic clock error, and ε x (t) is the random variation component that affects the atomic clock error.

[0066] The system performs an EKF process based on historical data, which involves determining the system equations and initializing them, predicting and updating them, and then iterating and predicting them repeatedly. This process gradually infers the current system state. A nonlinear clock error model for the CSAC is then constructed based on this current system state. Based on this rigorous nonlinear clock error model, the system accurately predicts the current CSAC clock error.

[0067] S9. After each adjustment, the system will form an entry with the forecast value obtained in step S7 and the corresponding time, 1pps signal, clock error information, etc., and store the entry additionally and persistently in the historical data list. The relevant results will be saved on the SD card or transferred to the host computer software until the reference signal is restored and the clock hold mode is exited. The CSAC will quickly resynchronize with the GNSS system time and return to S2. Among them, the persistent historical data serves as a log to help users analyze and troubleshoot problems when a fault occurs. On the other hand, the historical data serves as the data set of S8 and serves as a reference for prediction when system data is missing.

[0068] Therefore, the present invention adopts the above-mentioned high-reliability clock synchronization method of a micro PNT system based on CSAC to solve the clock synchronization problem between CSAC and GNSS, ensure high-precision time synchronization of the system, and improve the reliability of the system to achieve the purpose of accurate time synchronization.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solutions of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A high-reliability clock synchronization method for a micro PNT system based on CSAC, characterized in that: The following steps are involved: S1. Initialize each part of the microcontroller, initialize the time-to-digital converter TDC, and send relevant instructions; S2. Use the TDC to monitor and record in real time the 1pps signal sent by the CSAC to channel STOP1 and the 1pps signal sent by the GNSS receiver to channel STOP2, and calculate the clock difference between the two 1pps signals. , thereby obtaining clock error data; S3. Determine whether the GNSS signal is disconnected. The 1pps signal output by the GNSS receiver is connected to the STOP2 channel of the TDC chip. The STOP2 measurement result is used to determine whether the GNSS receiver's 1pps signal is disconnected. If the STOP2 measurement result is 0, it indicates that the GNSS 1pps signal is disconnected, and the process proceeds to step S8. Otherwise, the process proceeds to step S4 to step S7. S4. After executing steps S1 to S3 100 times without any problems, the system enters a stable state. At this time, adjustment begins. To avoid discussing the positive and negative conditions of the clock error data, the clock error value is converted to its absolute value. S5. Determine whether the clock difference is greater than 100ns. If so, proceed to step S6; otherwise, proceed to step S7; S6. The system enters the coarse adjustment mode, the atomic clock's built-in 1 pps coarse synchronization function is activated, and the atomic clock automatically adjusts the clock error, then returns to step S4. S7, the system enters the fine adjustment mode. In this mode, the microcontroller uses a clock control algorithm based on the ping-pong method to accurately adjust the clock. First, the clock error historical data is fitted based on the traditional quadratic clock error model. Second, the clock control adjustment amount is calculated based on the fitting results. Finally, the CASC is frequency modulated in the opposite direction according to the clock control adjustment amount. S8. When the GNSS signal is disconnected, the system enters the clock hold mode. In this mode, the microcontroller uses a clock hold algorithm to adjust the clock. First, based on the historical clock error data, the extended Kalman filter (EKF) algorithm is used to estimate the clock error model parameters, thereby obtaining a CSAC nonlinear clock error model. Then, the CSAC nonlinear clock error model is used to predict the clock error at the next moment; Finally, the clock maintenance conditions are established based on the CSAC nonlinear clock error model and its predicted values, and the necessary clock steering operations are performed based on this. S9. After each adjustment, the system will combine the obtained forecast value and the corresponding time, 1pps signal, and clock error information into an entry, and store the entry additionally and persistently in the historical data list. The relevant results will be saved on the SD card or transferred to the host computer software. The system will then exit the clock hold mode, and the CSAC will quickly resynchronize with the GNSS system time and return to S2. Among them, the persistent historical data serves as a log to help users analyze and troubleshoot problems when a fault occurs. On the other hand, the historical data serves as the data set of S8 and serves as a reference for prediction when system data is missing.

2. A high-reliability clock synchronization method for a micro PNT system based on CSAC according to claim 1, characterized in that: Initialization of TDC includes: S11. Initialize the TDC-AS6500 time interval measurement chip and the MAX913 comparator chip, use the 10 MHz signal output by the CSAC as the external reference clock, and use the MAX913 to shape the clock signal. S12. The TDC-AS6500 communicates with the STM32H743IIT6 microcontroller through the SPI serial port to transmit control commands and clock error measurement results. The SPI bus uses the "0b100X_XXXX" instruction format to send the corresponding initialization parameters, where X represents the binary form of the register address. These parameters include the INTERRUPT pin, REFCLK pin, DISABLE pin, and RSTIDX pin. S13. The TDC-AS6500 identifies measurement events and triggers data acquisition by monitoring changes in the level of its INTERRUPT pin. The TDC-AS6500 uses edge-triggered event timing, using the start pulse of each reference clock cycle as the time reference point. During each trigger event, the TDC-AS6500 accurately measures and calculates the time interval between the measurement channel signal and the rising edge of the reference clock signal in the previous cycle. The measurement results are broken down into two key parameters: the count value REFID within the reference clock cycle and the precise clock error measurement value TSTOP. These two key parameters are recorded and stored in dedicated registers of CHANNEL x for subsequent processing and analysis.

3. The adaptive time synchronization method based on chip-level atomic clock driving according to claim 2, characterized in that: During each trigger event, accurately measure and calculate the time interval between the measurement channel signal and the rising edge of the reference clock signal in the previous cycle. The specific steps are as follows: Time interval calculation: Calculate the time intervals of channel STOP1 and channel STOP2. The specific formula is as follows: ； Where, Indicates the time interval of a single channel, Indicates the frequency division coefficient; Time interval difference calculation: calculate the time interval difference between channel STOP1 and channel STOP2 The calculation formula is as follows: ； Where, Indicates the time interval of the first channel, Indicates the time interval of the second channel.

4. The adaptive time synchronization method based on chip-level atomic clock driving according to claim 1, characterized in that: The historical clock error data are fitted based on the traditional quadratic clock error model, as follows: During the effective reference signal period, the ping-pong algorithm keeps the CSAC in a free-running state and collects the clock difference between the CSAC and GNSS in real time. When the running time reaches the preset clock steering period, the least squares estimation method is used to analyze and process the historical clock difference data during this period to obtain the estimated values ​​of the secondary clock difference model parameters. The quadratic clock error model is as follows: ； In this model, 、 and That is, the clock error model parameters to be fitted, which represent the CSAC initial phase deviation, CSAC initial frequency deviation and CSAC frequency drift rate, respectively. is the reference time point, is the random noise term.

5. The adaptive time synchronization method based on chip-level atomic clock driving according to claim 1, characterized in that: The clock control adjustment amount is calculated based on the fitting results, as follows: When the absolute value of the CSAC clock error measurement is greater than 1ns, and the clock error trend approaches 0ns, the clock control adjustment amount is set to , the formula is as follows: ； Where, To measure the clock difference between CSAC and GNSS system time at the time of clock control operation, represents the driving time constant, represents the attenuation factor; When the absolute value of the CSAC clock error measurement is greater than 1ns, and the clock error trend is moving away from 0ns, the clock control adjustment amount is set to , the formula is as follows: ； Where, is the relative frequency deviation of CSAC in the current steering cycle; When the CSAC clock error measurement value is between ±1ns and the absolute value of the CSAC relative frequency deviation is greater than When the clock control adjustment is set to , the formula is as follows: ； When the clock error measurement value of CSAC is within ±1ns and the absolute value of the relative frequency deviation of CSAC is not greater than When it is not controlled, in order to reduce the frequency adjustment of the CSAC, that is, the clock control adjustment amount is set to 0; The CSAC is adjusted using the obtained clock control adjustment; the relevant data is sorted and stored.

6. The high-reliability clock synchronization method for a micro PNT system based on CSAC according to claim 1, characterized in that: Based on the CSAC nonlinear clock error model and its predicted value, the clock maintenance conditions are established, and the necessary clock steering operations are performed based on them. The specific operations are as follows: If the absolute value of the clock error prediction value is less than 10ns, and the relative frequency deviation is less than , and the clock error prediction value shows a decreasing trend, then, no clock steering operation is performed on CSAC, and it is allowed to converge slowly under autonomous operation, ensuring that the clock error of CSAC converges slowly to around 0ns in the subsequent control cycle; When the absolute value of the clock error prediction value is not less than 10ns, or the relative frequency deviation is not less than , or if the clock error prediction value shows a divergent state, it is necessary to perform necessary clock steering operations: using the CSAC's 10,000-second frequency stability as a reference, make small fine-tuning to cause the CSAC's clock error to gradually return to around 0 ns.

7. The high-reliability clock synchronization method for a micro PNT system based on CSAC according to claim 1, characterized in that: The EKF algorithm is used to estimate the clock error model parameters, thereby obtaining the CSAC nonlinear clock error model, whose mathematical form is as follows: ； Where, is the clock error of CSAC; is the time difference between the current measurement time and the initial measurement time; is the CSAC initial phase deviation; is the CSAC initial frequency deviation; is the CSAC frequency drift rate, also known as the aging rate; is CSAC random noise, 、 and is the deterministic time component that affects the CSAC clock error, and is the random variation component that affects the CSAC clock error.

8. The high-reliability clock synchronization method for a micro PNT system based on CSAC according to claim 7, characterized in that: The CSAC nonlinear clock error model is used to predict the clock error at the next moment, as follows: The system performs the EKF process based on historical data, which involves determining the system equations and initializing, predicting and updating, and repeating the iterations and predictions, gradually calculating the current system state. It then constructs a nonlinear clock error model for the CSAC based on the current system state, and based on this constructed nonlinear clock error model, obtains the current CSAC clock error prediction. After each cycle, the current clock error data is stored and applied to the model update in the next cycle.

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