Driving circuit and display module

Abstract

The invention discloses a driving circuit and a display module. The driving circuit comprises a clock signal input end, a grid signal output end and a standby transmission unit, the clock signal input end is connected with the grid signal output end; the grid signal output end is used for being connected with a pixel; one end of the standby transmission unit is connected with the clock signal input end, and the other end is connected with the pixel; the clock signal input end is used for receiving a clock signal and controlling the grid signal output end to transmit a grid signal to the pixel according to a preset time sequence through the clock signal so as to drive the pixel to work; and the standby transmission unit is used for communicating the clock signal input end with the pixels when the output of the gate signal output end is abnormal so as to drive the pixels to work. According to the technical scheme, a maintainer can cut off signal connection among the clock signal input end, the grid signal output end and the pixels to relieve suppression on signal output of the standby transmission unit, so that the standby transmission unit can replace the grid signal output end to drive the pixels to work.

Description

Technical Field

[0001] The present application relates to the technical field of drive circuits, and in particular to a drive circuit and a display module. Background Art

[0002] Liquid crystal displays (LCDs) have been widely used in various electronic devices due to their advantages such as low power consumption, high resolution, and thinness. The working principle of LCDs is mainly to rely on the internal driving circuit to send gate signals to pixels, and adjust the arrangement of liquid crystal molecules through the gate signals, thereby controlling the transmittance of each pixel and realizing the picture display of the LCD.

[0003] When the gate signal output of the driving circuit is abnormal, the screen display of the LCD will be affected. How to construct the circuit structure of the driving circuit so as to quickly repair the driving circuit board when the gate signal output of the driving circuit is abnormal has become an urgent problem to be solved in the industry. Summary of the invention

[0004] The purpose of the present application is to provide a driving circuit, aiming to solve the problem in the related art that when the gate signal output of the driving circuit is abnormal, it cannot be quickly repaired.

[0005] To achieve the purpose of the present application, in a first aspect, the present application provides a driving circuit, comprising a clock signal input terminal, a gate signal output terminal and a standby transmission unit; the clock signal input terminal is connected to the gate signal output terminal;

[0006] The gate signal output terminal is used to connect to the pixel; one end of the standby transmission unit is connected to the clock signal input terminal, and the other end is used to connect to the pixel;

[0007] The clock signal input terminal is used to receive a clock signal, and control the gate signal output terminal to transmit a gate signal to the pixel at a preset timing through the clock signal, so as to drive the pixel to work;

[0008] The backup transmission unit is used to connect the clock signal input terminal with the pixel to drive the pixel to work when an abnormality occurs in the output of the gate signal output terminal.

[0009] In a possible implementation, the standby transmission unit includes a level transmission signal output terminal and a first transistor, and the first terminal of the level transmission signal output terminal is connected to the clock signal input terminal;

[0010] The input end of the first transistor is connected to the second end of the level transmission signal output end, and the output end of the first transistor is used to connect to the pixel;

[0011] The level transmission signal output terminal is used to output a pre-charge signal and a pull-down signal to the outside; the first transistor is used to turn on when an abnormality occurs in the output of the gate signal output terminal, so that the clock signal input terminal and the level transmission signal output terminal are connected to the pixel and drive the pixel to work.

[0012] In a possible implementation, the stage transmission signal output terminal is connected to a control terminal of the first transistor, and transmits a first control signal to the control terminal, where the first control signal is used to turn on the first transistor;

[0013] The driving circuit further comprises a level signal input terminal, the level signal input terminal is connected to the control terminal of the first transistor; the level signal input terminal is used to transmit a second control signal to the control terminal, and the second control signal is used to turn off the first transistor;

[0014] Wherein, the current direction of the second control signal at the control end is opposite to that of the first control signal; when the gate signal output end works normally, the driving force of the second control signal at the control end is greater than the driving force of the first control signal at the control end;

[0015] When an abnormality occurs in the output of the gate signal output terminal, the driving force of the second control signal at the control terminal is smaller than the driving force of the first control signal at the control terminal.

[0016] In a possible implementation, the driving force of the second control signal is greater than the driving force of the first control signal;

[0017] The driving circuit further comprises a second transistor, the input end of the second transistor is connected to the level signal input end; the output end of the second transistor is connected to the control end of the first transistor;

[0018] When the gate signal output terminal operates normally, the second transistor is turned on, and when an abnormality occurs in the output of the gate signal output terminal, the second transistor is turned off.

[0019] In a possible implementation, the driving circuit further includes a second transistor and a third transistor; the input end of the second transistor is connected to the level signal input end; the output end of the second transistor is connected to the control end of the first transistor;

[0020] The input terminal and the control terminal of the third transistor are connected to the stage transmission signal output terminal, and the output terminal of the third transistor is connected to the control terminal of the first transistor; the driving force of the third transistor is smaller than the driving force of the second transistor;

[0021] When the gate signal output terminal operates normally, the second transistor is turned on, and when an abnormality occurs in the output of the gate signal output terminal, the second transistor is turned off.

[0022] In a possible implementation, the driving circuit further includes a second transistor and a third transistor; the input end of the second transistor is connected to the level signal input end; the output end of the second transistor is connected to the control end of the first transistor;

[0023] The input terminal and the control terminal of the third transistor are connected to the stage transmission signal output terminal, and the output terminal of the third transistor is connected to the control terminal of the first transistor;

[0024] When the gate signal output terminal operates normally, the second transistor is turned on and the third transistor is turned off; when the output of the gate signal output terminal is abnormal, the second transistor is turned off and the third transistor is turned on.

[0025] In a possible implementation manner, the control terminal of the second transistor is connected to the gate signal output terminal.

[0026] In a possible implementation, the driving force of the second control signal is smaller than the driving force of the first control signal;

[0027] The driving circuit further comprises a third transistor, an input end of the third transistor is connected to the stage transmission signal output end, and an output end of the third transistor is connected to the control end of the first transistor;

[0028] When the gate signal output terminal operates normally, the third transistor is turned off, and when the output of the gate signal output terminal is abnormal, the third transistor is turned on.

[0029] In a second aspect, the present application further proposes a display module, the display module comprising a pixel and a driving circuit; the driving circuit is connected to the pixel to drive the pixel to work; the driving circuit comprises a clock signal input terminal, a gate signal output terminal and a standby transmission unit; the clock signal input terminal is connected to the gate signal output terminal;

[0030] The gate signal output terminal is used to connect to the pixel; one end of the standby transmission unit is connected to the clock signal input terminal, and the other end is used to connect to the pixel;

[0031] The clock signal input terminal is used to receive a clock signal, and control the gate signal output terminal to transmit a gate signal to the pixel at a preset timing through the clock signal, so as to drive the pixel to work;

[0032] The backup transmission unit is used to connect the clock signal input terminal with the pixel to drive the pixel to work when an abnormality occurs in the output of the gate signal output terminal.

[0033] In a possible implementation, the display module includes a plurality of the driving circuits, and among the driving circuits, some of the driving circuits are configured as working circuits, and some of the driving circuits are configured as redundant circuits;

[0034] The working circuit is connected to the pixel to drive the pixel to work; the redundant circuit is used to connect to the pixel to drive the pixel to work when any one of the working circuits fails.

[0035] The technical solution of the present application is to set a spare transmission unit between the clock signal input terminal and the pixel. When the gate signal output terminal normally outputs the gate signal, the signal transmission of the spare transmission unit to the pixel direction is suppressed by the gate signal output terminal. When the gate signal output of the gate signal output terminal is abnormal, the maintenance personnel can eliminate the signal interference of the gate signal output terminal to the pixel after the abnormality by cutting off the signal connection between the clock signal input terminal, the gate signal output terminal and the pixel. At the same time, the suppression of the signal output of the spare transmission unit is released, so that the spare transmission unit can replace the gate signal output terminal to drive the pixel to work, realize the rapid repair of the abnormal display module screen, improve the maintenance efficiency of the display module screen, and improve the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 A schematic diagram of the structure of an embodiment of the driving circuit provided in the present application;

[0038] Figure 2 for Figure 1 A schematic diagram of the structure of the driving circuit after the abnormal signal output at the middle gate signal output terminal is repaired;

[0039] Figure 3 A schematic diagram of the circuit structure of the display module provided in this application;

[0040] Figure 4 for Figure 3 Schematic diagram of the circuit structure after the signal output at the middle gate signal output terminal is abnormal and has been repaired.

[0041] Description of reference numerals:

[0042] 100-display module;

[0043] 10-driving circuit, 10a-first driving circuit, 10b-second driving circuit, 10c-third driving circuit, 10d-fourth driving circuit;

[0044] cl k-clock signal input terminal, Gn-gate signal output terminal;

[0045] 1- standby transmission unit, Zn- level transmission signal output terminal, vgl- level signal input terminal, T1- first transistor, T2- second transistor, T3- third transistor, Zn-1- pull-down signal input terminal, Zn+1- pre-charge signal input terminal;

[0046] 20-pixel, 20a-first pixel, 20b-second pixel, 20c-third pixel;

[0047] CLK1-first clock signal input line, CLK2-second clock signal input line, STV-start signal input line, RST-reset signal input line, D1-first signal output line, D2-second signal output line, D3-third signal output line, D4-fourth signal output line. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0049] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there can be a central component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there can be a central component at the same time.

[0050] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this application and in the specification are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in this application includes any and all combinations of one or more of the related listed items.

[0051] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0052] The present application proposes a display module. In some embodiments, the display module includes a liquid crystal panel and a driving circuit. The driving circuit is used to transmit a gate signal to the liquid crystal panel; the liquid crystal panel is used to display images and videos.

[0053] The liquid crystal panel is composed of multiple pixels, each of which includes liquid crystal molecules, thin film transistors (TFT), pixel electrodes (PXL) and common electrodes (COM). Liquid crystal molecules are used to adjust the transmittance of light, thereby realizing different screen displays. The thin film transistor is connected to the driving circuit and can receive a gate signal from the driving circuit. The gate signal can control the on and off of the thin film transistor. The current of the driving circuit can make the turned-on thin film transistor reach the pixel electrode and form a voltage at the pixel electrode. This voltage forms an electric field with the common electrode and drives the liquid crystal molecules to move. This changes the arrangement of the liquid crystal molecules in the pixel, thereby changing the transmittance of light and realizing image display.

[0054] When the gate signal output of the driving circuit is abnormal, the screen display of the LCD will be affected. In the related art, when the gate signal output of the driving circuit is abnormal, the circuit board where the entire driving circuit is located can only be replaced as a whole, and the driving circuit cannot be quickly repaired.

[0055] To solve the above problems, in the present application, the driving circuit includes a clock signal input terminal, a gate signal output terminal and a backup transmission unit; the clock signal input terminal is connected to the gate signal output terminal; the gate signal output terminal is used to connect to the pixel; one end of the backup transmission unit is connected to the clock signal input terminal, and the other end is used to connect to the pixel; the clock signal input terminal is used to receive a clock signal, and control the gate signal output terminal through the clock signal to transmit the gate signal to the pixel at a preset timing to drive the pixel to work; the backup transmission unit is used to connect the clock signal input terminal and the pixel to drive the pixel to work when an abnormality occurs in the output of the gate signal output terminal.

[0056] The technical solution of the present application is to set a spare transmission unit between the clock signal input terminal and the pixel. When the gate signal output terminal normally outputs the gate signal, the signal transmission of the spare transmission unit to the pixel direction is suppressed by the gate signal output terminal. When the gate signal output of the gate signal output terminal is abnormal, the maintenance personnel can eliminate the signal interference of the gate signal output terminal to the pixel after the abnormality by cutting off the signal connection between the clock signal input terminal, the gate signal output terminal and the pixel. At the same time, the suppression of the signal output of the spare transmission unit is released, so that the spare transmission unit can replace the gate signal output terminal to drive the pixel to work, realize the rapid repair of the abnormal display module screen, improve the maintenance efficiency of the display module screen, and improve the user experience.

[0057] The driving circuit provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0058] Please refer to Figure 1 and Figure 2 The driving circuit 10 includes a clock signal input terminal clk and a gate signal output terminal Gn. The clock signal input terminal clk is used to connect to the clock generator in the display module 100 to receive the clock signal from the clock generator. The driving circuit 10 can generate a control signal according to the clock signal, and control the gate signal output terminal Gn to transmit the gate signal to the pixel 20 at a preset timing to drive the pixel 20 to work.

[0059] The driving circuit 10 further includes a backup transmission unit 1. When the gate signal output terminal Gn normally outputs the gate signal, the signal transmission between the backup transmission unit 1 and the pixel 20 is suppressed. When the gate signal output terminal Gn outputs an abnormality, the output abnormality may be an abnormal connection between the gate signal output terminal Gn and the clock signal input terminal clk (the abnormal connection may be a short circuit, an open circuit or poor contact), or an abnormal connection between the gate signal output terminal Gn and the pixel 20, which is not limited in the present application.

[0060] like Figure 2 As shown, when the gate signal output terminal Gn outputs abnormally, the maintenance personnel can cut off the signal connection between the clock signal input terminal clk, the gate signal output terminal Gn and the pixel 20, and eliminate the signal interference of the abnormal gate signal output terminal Gn on the pixel 20. At the same time, the inhibition of the signal output of the backup transmission unit 1 is released, so that the backup transmission unit 1 can replace the gate signal output terminal Gn to drive the pixel 20 to work, realize the rapid repair of the abnormal screen of the display module 100, improve the maintenance efficiency of the screen of the display module 100, and improve the user experience.

[0061] In one embodiment of the present application, the standby transmission unit 1 includes a level transmission signal output terminal Zn and a first transistor T1, wherein a first end of the level transmission signal output terminal Zn is connected to a clock signal input terminal clk; an input end of the first transistor T1 is connected to a second end of the level transmission signal output terminal Zn, and an output end of the first transistor T1 is used to connect to a pixel 20. The first transistor T1 may be an N-type metal oxide semiconductor (NMOS), a P-type metal oxide semiconductor (PMOS), or a bipolar junction transistor (BJT), and the present application does not limit this.

[0062] When the gate signal output terminal Gn outputs the gate signal normally, the first transistor T1 is turned off, and the connection between the level transfer signal output terminal Zn and the pixel 20 is cut off. The level transfer signal output terminal Zn is only used to transmit the pre-charge signal and the pull-down signal to the lower-level circuit under the control of the clock signal to ensure the correct pre-charge and pull-down operation of the lower-level circuit, thereby realizing precise control and stable operation of the pixel 20.

[0063] When the output of the gate signal output terminal Gn is abnormal, the first transistor T1 is turned on, and the clock signal input terminal c lk, the level transfer signal output terminal Zn and the pixel 20 are connected. In addition to transmitting the pre-charge signal and the pull-down signal to the lower circuit, the level transfer signal output terminal Zn will also replace the gate signal output terminal Gn to transmit the gate signal to the pixel 20 to maintain the normal operation of the pixel 20.

[0064] In this embodiment, the first transistor T1 is used to connect the stage transfer signal output terminal Zn and the pixel 20, thereby structurally multiplexing the stage transfer signal output terminal Zn in the driving circuit 10 for outputting the pre-charge signal and the pull-down signal to the outside, so as to complete the replacement of the gate signal output terminal Gn gate signal output without adding other circuit output terminals and circuit structures, thereby simplifying the layout of the driving circuit 10, improving the circuit integration of the driving circuit 10, and improving the driving efficiency of the driving circuit 10 for the pixel 20.

[0065] It can be understood that in other possible implementations of the present application, other output ports such as data lines or scan lines can also be used to replace the gate signal output terminal Gn to transmit the gate signal to the pixel 20, and the present application does not impose any limitation on this.

[0066] In order to realize the control of closing and turning on the first transistor T1, in one embodiment of the present application, the stage transmission signal output terminal Zn is connected to the control terminal of the first transistor T1, and transmits a first control signal to the control terminal, and the first control signal is used to turn on the first transistor T1. It should be noted that the first control signal can be a high-level electrical signal or a low-level electrical signal. When the first transistor T1 is a transistor such as an NMOS tube that is turned on by a high level and turned off by a low level, the first control signal is a high-level signal; when the first transistor T1 is a transistor such as a PMOS tube that is turned on by a low level and turned off by a high level, the first control signal is a low-level signal, and the present application does not limit this. For example, in the present application, the first transistor T1 is an NMOS tube, and the stage transmission signal output terminal Zn transmits a high-level signal to the first transistor T1 to turn on the first transistor T1.

[0067] The driving circuit 10 also includes a level signal input terminal vgl, which is connected to the control terminal of the first transistor T1; the level signal input terminal vgl is used to transmit a second control signal to the control terminal, and the second control signal is used to turn off the first transistor T1. The second control signal can be a high-level signal or a low-level signal. When the first transistor T1 is a transistor such as an NMOS tube that is turned on at a high level and turned off at a low level, the second control signal is a low-level signal; when the first transistor T1 is a transistor such as a PMOS tube that is turned on at a low level and turned off at a high level, the second control signal is a high-level signal, and this application does not limit this. For example, in this application, the first transistor T1 is an NMOS tube, and the level signal input terminal vgl transmits a low-level signal to the first transistor T1 to turn off the first transistor T1.

[0068] To achieve the switch control of the first transistor T1, in this embodiment, the current direction of the second control signal at the control end of the first transistor T1 is opposite to that of the first control signal. When the gate signal output terminal Gn works normally, the driving force of the second control signal at the control end is greater than the driving force of the first control signal at the control end. When the output of the gate signal output terminal Gn is abnormal, the driving force of the second control signal at the control end is less than the driving force of the first control signal at the control end.

[0069] In this way, when the gate signal output terminal Gn works normally, the low-voltage signal of the control terminal of the first transistor T1 is injected into the level signal input terminal vgl, covering the high-voltage signal of the control terminal of the first transistor T1 injected into the control terminal of the first transistor T1 by the level signal output terminal Zn, the control terminal of the first transistor T1 is in a low-level state, the first transistor T1 is turned off, and the connection between the level signal output terminal Zn and the pixel 20 is cut off.

[0070] When the output of the gate signal output terminal Gn is abnormal, the driving force of the second control signal at the control terminal is less than the driving force of the first control signal at the control terminal. The high-voltage signal injected into the control terminal of the first transistor T1 by the level signal output terminal Zn covers the low-voltage signal injected into the control terminal of the first transistor T1 by the level signal input terminal vgl. The control terminal of the first transistor T1 is in a high-level state, the first transistor T1 is turned on, the level signal output terminal Zn is connected to the pixel 20, and replaces the gate signal output terminal Gn to transmit the gate signal to the pixel 20, and drives the pixel 20 to work.

[0071] There are many ways to adjust the driving force of the first control signal and the second control signal. In one embodiment of the present application, the level signal input terminal vgl is connected to a voltage regulator. By controlling the timing of the level signal input terminal vgl, when the gate signal output terminal Gn works normally, the level signal input terminal vgl increases the current delivered to the control terminal of the first transistor T1 and increases the driving force of the second control signal. When the output of the gate signal output terminal Gn is abnormal, the level signal input terminal vgl reduces the current delivered to the control terminal of the first transistor T1 to reduce the driving force of the second control signal. In this way, the control of turning off and on the first transistor T1 is realized.

[0072] In another possible implementation of the present application, the driving force of the second control signal is greater than the driving force of the first control signal; the driving circuit 10 also includes a second transistor T2, the input end of the second transistor T2 is connected to the level signal input end vgl; the output end of the second transistor T2 is connected to the control end of the first transistor T1; when the gate signal output end Gn works normally, the second transistor T2 is turned on, and the second control signal is injected into the control end of the first transistor T1, and because the driving force of the second control signal is greater than the driving force of the first control signal, the second control signal will cover the first control signal and make the control end of the first transistor T1 in a low level state, thereby turning off the first transistor T1. When the output of the gate signal output end Gn is abnormal, the second transistor T2 is turned off, and at this time, only the first control signal exists in the first transistor T1, and the first transistor T1 is in a high level state and turned on under the action of the first control signal.

[0073] In another possible implementation of the present application, the driving circuit 10 also includes a second transistor T2 and a third transistor T3; the input end of the second transistor T2 is connected to the level signal input end vgl; the output end of the second transistor T2 is connected to the control end of the first transistor T1; the input end and the control end of the third transistor T3 are connected to the level signal output end Zn, and the output end of the third transistor T3 is connected to the control end of the first transistor T1; the driving force of the third transistor T3 is less than the driving force of the second transistor T2.

[0074] When the gate signal output terminal Gn works normally, the second transistor T2 is turned on. At this time, since the driving force of the third transistor T3 is smaller than the driving force of the second transistor T2, the second control signal injected from the second transistor T2 will cover the first control signal injected from the third transistor T3, thereby turning off the first transistor T1.

[0075] When the output of the gate signal output terminal Gn is abnormal, the second transistor T2 is turned off, and at this time, only the first control signal exists in the first transistor T1, and the first transistor T1 is turned on under the action of the first control signal. Compared with only using the second transistor T2 to connect the level signal input terminal vgl and the control terminal of the first transistor T1, the third transistor T3 is added in this embodiment, and the level signal output terminal Zn is connected to the control terminal of the first transistor T1 through the third transistor T3, so as to form a signal isolation between the level signal output terminal Zn and the control terminal of the first transistor T1, thereby avoiding the low-level signal injected into the level signal input terminal vgl from affecting the pre-charge signal and the pull-down signal of the level signal output terminal Zn, thereby improving the stability of the circuit.

[0076] In addition to setting the driving force of the third transistor T3 to be smaller than the driving force of the second transistor T2, in other possible implementations of the present application, the driving force of the third transistor T3 can also be set to be the same as the driving force of the second transistor T2, and the second transistor T2 and the third transistor T3 can be controlled separately, which can also achieve control of turning off and on the first transistor T1.

[0077] Specifically, the driving circuit 10 also includes a second transistor T2 and a third transistor T3; the input end of the second transistor T2 is connected to the level signal input end vgl; the output end of the second transistor T2 is connected to the control end of the first transistor T1; the input end and the control end of the third transistor T3 are connected to the level signal output end Zn, and the output end of the third transistor T3 is connected to the control end of the first transistor T1.

[0078] When the gate signal output terminal Gn works normally, the driving circuit 10 controls the second transistor T2 to turn on, the third transistor T3 to turn off, the control terminal of the first transistor T1 is connected to the level signal input terminal vg1, the second control signal is injected into the control terminal of the first transistor T1, and the first transistor T1 is turned off.

[0079] When the output of the gate signal output terminal Gn is abnormal, the second transistor T2 is turned off, the third transistor T3 is turned on, the control terminal of the first transistor T1 is connected to the stage transfer signal output terminal Zn, the first control signal is injected into the control terminal of the first transistor T1, and the first transistor T1 is turned on.

[0080] Based on the above embodiments, there are many ways to turn on and off the second transistor T2. In one embodiment of the present application, the driving circuit 10 further includes an external signal input terminal, one end of which is connected to the external circuit, and the other end is connected to the control terminal of the second transistor T2. When the gate signal output terminal Gn works normally, the external signal input terminal receives an on signal from the external circuit and transmits it to the control terminal of the second transistor T2, thereby turning on the second transistor T2. When the output of the gate signal output terminal Gn is abnormal, the external signal input terminal receives a off signal from the external circuit and transmits it to the control terminal of the second transistor T2, thereby turning off the second transistor T2.

[0081] In another embodiment of the present application, the control end of the second transistor T2 is connected to the gate signal output terminal Gn. When the gate signal output terminal Gn works normally, the control end of the second transistor T2 receives the high-frequency signal from the gate signal output terminal Gn and turns on the second transistor T2. When the output of the gate signal output terminal Gn is abnormal, the clock signal input terminal clk and the gate signal output terminal Gn signal are cut off, the control end of the second transistor T2 loses the signal from the gate signal output terminal Gn, and the second transistor T2 is turned on. Compared with setting an additional circuit, this embodiment reduces the layout of the circuit line by connecting the control end of the second transistor T2 to the gate signal output terminal Gn, reduces the complexity of the hardware, and improves the reliability and response speed of the system. At the same time, the state of the second transistor T2 is directly controlled by the gate signal, so that the switching process is faster and more efficient, and the normal operation of the display module 100 is effectively guaranteed.

[0082] It can be understood that in addition to setting the second transistor T2, and setting the second transistor T2 and the third transistor T3 at the same time, the third transistor T3 can also be set separately to realize the control of turning off and on the first transistor T1. Specifically, in one embodiment of the present application, the driving force of the second control signal is less than the driving force of the first control signal; the driving circuit 10 also includes a third transistor T3, the input end of the third transistor T3 is connected to the stage transfer signal output end Zn, and the output end of the third transistor T3 is connected to the control end of the first transistor T1. When the gate signal output end Gn works normally, the third transistor T3 is turned off, and the control end of the first transistor T1 only has the second control signal, and is then turned off.

[0083] When an abnormality occurs in the output of the gate signal output terminal Gn, the third transistor T3 is turned on, and the first control signal and the second control signal are simultaneously injected into the control terminal of the first transistor T1. Since the driving force of the second control signal is smaller than the driving force of the first control signal, the first control signal will cover the second control signal, thereby turning on the first transistor T1.

[0084] Please refer to Figure 3 , the display module 100 may include one driving circuit 10, or may include multiple driving circuits 10, and the present application does not limit this. In one possible implementation mode of the present application, the display module 100 includes multiple driving circuits 10, and in each of the driving circuits 10, some of the driving circuits 10 are set as working circuits, and some of the driving circuits 10 are set as redundant circuits. The working circuit is connected to the pixel 20 to maintain the normal operation of the display module 100. The redundant circuit is used to replace the failed working circuit to connect to the pixel 20 when any working circuit fails, and to drive the pixel 20 to work instead of the failed working circuit, thereby eliminating the maintenance of the failed working circuit, reducing the maintenance time of the display module 100 after the working circuit fails, improving the maintenance efficiency of the display module 100, and improving the user experience.

[0085] To facilitate the description of the replacement process of the redundant circuit, it is now assumed that the driving circuit 10 includes a first driving circuit 10a, a second driving circuit 10b, a third driving circuit 10c, and a fourth driving circuit 10d, the pixel 20 includes a first pixel 20a, a second pixel 20b, and a third pixel 20c, and the display module 100 also includes a signal input line and a signal output line, wherein the first driving circuit 10a, the second driving circuit 10b, and the third driving circuit 10c are set as working circuits, and the fourth driving circuit 10d is set as a redundant circuit. One end of the first driving circuit 10a is connected to the signal input line, and the other end is connected to the first pixel 20a, one end of the second driving circuit 10b is connected to the signal input line, and the other end is connected to the second pixel 20b, and one end of the third driving circuit 10c is connected to the signal input line, and the other end is connected to the third pixel 20c. The fourth driving circuit 10d is not connected, or is only connected to the signal input line.

[0086] The signal input lines include first and second clock signal input lines CLK1 and CLK2, a start signal input line STV, a reset signal input line RST, etc. The signal output lines include first, second, third and fourth signal output lines D1, D2, D3 and D4.

[0087] When the display module 100 displays the screen normally, the first driving circuit 10a outputs a gate signal to the first pixel 20a to drive the first pixel 20a to work. The second driving circuit 10b outputs a gate signal to the second pixel 20b to drive the second pixel 20b to work. The third driving circuit 10c outputs a gate signal to the third pixel 20c to drive the third pixel 20c to work.

[0088] Please refer to Figure 4 When the gate signal output terminal Gn of the third drive circuit 10c outputs an abnormal signal, the maintenance personnel will perform the following operations:

[0089] S10 , cutting off the connection between the gate signal output terminal Gn of the third driving circuit 10 c and the third pixel 20 c , and short-circuiting the third pixel 20 c and the third signal output line D3 .

[0090] S20 , short-circuiting the fourth driving circuit 10 d and each signal input line (if the display module 100 has been connected before leaving the factory, this step can be skipped).

[0091] S30, short-circuit the signal output terminal Zn of the second driving circuit 10b with the first signal output line D1; short-circuit the pre-charge signal input terminal Zn+1 with the second signal output line D2;

[0092] S40, short-circuit the level transfer signal output terminal Zn of the fourth drive circuit 10d with the first signal output line D1; short-circuit the pre-charge signal input terminal Zn+1 with the fourth signal output line D4; short-circuit the pull-down signal input terminal Zn-1 with the first signal output line D1; short-circuit the gate signal output terminal Gn with the third signal output line D3; the purpose of this step is to connect the level transfer signal output terminal Zn of the fourth drive circuit 10d with the pre-charge signal input terminal Zn+1 and the pull-down signal input terminal Zn-1 of the first drive circuit 10a and the second drive circuit 10b, so that the fourth drive circuit 10d can replace the third drive circuit 10c to realize the pre-charge and pull-down of the upper and lower circuits.

[0093] S50, short-circuit the gate signal output terminal Gn of the fourth driving circuit 10d and D3. The purpose of this step is to connect the gate signal output terminal Gn of the fourth driving circuit 10d to the third pixel 20c, so that the fourth driving circuit 10d can replace the third driving circuit 10c to output the gate signal for the third pixel 20c.

[0094] After the above steps, the drive circuit can be replaced, thereby realizing the rapid repair of the abnormal display module screen and improving the user experience.

[0095] In the description of the embodiments of the present application, it should be noted that the orientation or positional relationship of terms such as "center", "up", "down", "left", "right", "vertical", "horizontal", "inside" and "outside" are based on the orientation or positional relationship described in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0096] What is disclosed above is only a preferred embodiment of the present application, and it certainly cannot be used to limit the scope of rights of the present application. Ordinary technicians in this field can understand that all or part of the processes of implementing the above embodiment and equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A driving circuit, characterized in that: It includes a clock signal input terminal, a gate signal output terminal and a backup transmission unit; the clock signal input terminal is connected to the gate signal output terminal; The gate signal output terminal is used to connect to the pixel; one end of the standby transmission unit is connected to the clock signal input terminal, and the other end is used to connect to the pixel; The clock signal input terminal is used to receive a clock signal, and control the gate signal output terminal to transmit a gate signal to the pixel at a preset timing through the clock signal, so as to drive the pixel to work; The backup transmission unit is used to connect the clock signal input terminal with the pixel to drive the pixel to work when an abnormality occurs in the output of the gate signal output terminal.

2. The driving circuit according to claim 1, characterized in that: The standby transmission unit comprises a level transmission signal output terminal and a first transistor, wherein the first terminal of the level transmission signal output terminal is connected to the clock signal input terminal; The input end of the first transistor is connected to the second end of the level transmission signal output end, and the output end of the first transistor is used to connect to the pixel; The level transmission signal output terminal is used to output a pre-charge signal and a pull-down signal to the outside; the first transistor is used to turn on when an abnormality occurs in the output of the gate signal output terminal, so that the clock signal input terminal and the level transmission signal output terminal are connected to the pixel and drive the pixel to work.

3. The driving circuit according to claim 2, characterized in that: The stage transmission signal output terminal is connected to the control terminal of the first transistor and transmits a first control signal to the control terminal, wherein the first control signal is used to turn on the first transistor; The driving circuit further comprises a level signal input terminal, the level signal input terminal is connected to the control terminal of the first transistor; the level signal input terminal is used to transmit a second control signal to the control terminal, and the second control signal is used to turn off the first transistor; Wherein, the current direction of the second control signal at the control end is opposite to that of the first control signal; when the gate signal output end works normally, the driving force of the second control signal at the control end is greater than the driving force of the first control signal at the control end; When an abnormality occurs in the output of the gate signal output terminal, the driving force of the second control signal at the control terminal is smaller than the driving force of the first control signal at the control terminal.

4. The driving circuit according to claim 3, characterized in that: The driving force of the second control signal is greater than the driving force of the first control signal; The driving circuit further comprises a second transistor, the input end of the second transistor is connected to the level signal input end; the output end of the second transistor is connected to the control end of the first transistor; When the gate signal output terminal operates normally, the second transistor is turned on, and when an abnormality occurs in the output of the gate signal output terminal, the second transistor is turned off.

5. The driving circuit according to claim 3, characterized in that: The driving circuit further includes a second transistor and a third transistor; the input end of the second transistor is connected to the level signal input end; the output end of the second transistor is connected to the control end of the first transistor; The input terminal and the control terminal of the third transistor are connected to the stage transmission signal output terminal, and the output terminal of the third transistor is connected to the control terminal of the first transistor; the driving force of the third transistor is smaller than the driving force of the second transistor; When the gate signal output terminal operates normally, the second transistor is turned on, and when an abnormality occurs in the output of the gate signal output terminal, the second transistor is turned off.

6. The driving circuit according to claim 3, characterized in that: The driving circuit further includes a second transistor and a third transistor; the input end of the second transistor is connected to the level signal input end; the output end of the second transistor is connected to the control end of the first transistor; The input terminal and the control terminal of the third transistor are connected to the stage transmission signal output terminal, and the output terminal of the third transistor is connected to the control terminal of the first transistor; When the gate signal output terminal operates normally, the second transistor is turned on and the third transistor is turned off; when the output of the gate signal output terminal is abnormal, the second transistor is turned off and the third transistor is turned on.

7. The driving circuit according to any one of claims 4 to 6, characterized in that: The control terminal of the second transistor is connected to the gate signal output terminal.

8. The driving circuit according to claim 3, characterized in that: The driving force of the second control signal is smaller than the driving force of the first control signal; The driving circuit further comprises a third transistor, an input end of the third transistor is connected to the stage transmission signal output end, and an output end of the third transistor is connected to the control end of the first transistor; When the gate signal output terminal operates normally, the third transistor is turned off, and when the output of the gate signal output terminal is abnormal, the third transistor is turned on.

9. A display module, characterized in that: It comprises a pixel and a driving circuit as described in any one of claims 1 to 8; the driving circuit is connected to the pixel to drive the pixel to operate.

10. The display module according to claim 9, wherein: The display module comprises a plurality of driving circuits, and among the driving circuits, some of the driving circuits are configured as working circuits, and some of the driving circuits are configured as redundant circuits; The working circuit is connected to the pixel to drive the pixel to work; The redundant circuit is used to connect to the pixel to drive the pixel to work when any one of the working circuits fails.

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