Heterojunction bipolar transistor, preparation method and radio frequency amplifier

Abstract

The embodiment of the invention provides a heterojunction bipolar transistor, which comprises a semiconductor layer with a first surface; the emitter structure is arranged on the first surface; a passivation layer covering the emitter structure; the base metal comprises a plurality of finger parts which are arranged on the first surface at intervals and are electrically connected with the semiconductor layer; the connecting part is electrically connected with the plurality of finger parts respectively; the connecting part is located on the side, away from the semiconductor layer, of the emitter structure and is isolated from the emitter structure through the passivation layer. According to the heterojunction bipolar transistor, the preparation method and the radio frequency amplifier provided by the embodiment of the invention, the heterojunction area can be reduced while the original size of the emitter structure is ensured, so that the junction capacitance is reduced, and the working frequency of the heterojunction bipolar transistor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a heterojunction bipolar transistor, a preparation method and a radio frequency amplifier. Background Art

[0002] With the development of heterojunction bipolar transistor technology, higher requirements are placed on the high-frequency performance of heterojunction bipolar transistor products. There are two main parameters for evaluating the high-frequency characteristics of heterojunction bipolar transistors, namely the current gain cutoff frequency (ft) and the maximum oscillation frequency (fmax), both of which are inversely proportional to the junction capacitance. Reducing the junction capacitance can effectively improve the high-frequency performance of heterojunction bipolar transistor devices. The traditional method of reducing junction capacitance is to directly reduce the base metal width through photolithography to achieve the effect of reducing junction capacitance; this requires more precise photolithography size control, which will make the photolithography process difficult and reduce the yield.

[0003] Therefore, there is an urgent need to provide a better solution to reduce junction capacitance. Summary of the invention

[0004] Therefore, in order to overcome at least some of the defects in the prior art, the embodiments of the present invention provide a heterojunction bipolar transistor, a preparation method and a radio frequency amplifier, in which the connection portion of the base metal is set on the emitter structure, which can reduce the base step area while ensuring the original size of the emitter structure, thereby reducing the heterojunction area, and further reducing the junction capacitance, thereby increasing the operating frequency of the heterojunction bipolar transistor.

[0005] One embodiment of the present invention provides a heterojunction bipolar transistor, comprising: a semiconductor layer, the semiconductor layer having a first surface; an emitter structure, arranged on the first surface; a passivation layer, covering the emitter structure; a base metal, comprising: a plurality of fingers, the plurality of fingers are arranged on the first surface at intervals from each other and electrically connected to the semiconductor layer; a connecting portion, electrically connected to the plurality of fingers respectively; at least a portion of the connecting portion is located on a side of the emitter structure away from the semiconductor layer and is isolated from the emitter structure by the passivation layer.

[0006] Another embodiment of the present invention provides a method for preparing a heterojunction bipolar transistor, comprising: providing a first basic structure; the first basic structure comprising: a semiconductor layer, the semiconductor layer having a first surface; an emitter structure, arranged on the first surface; a passivation layer, the passivation layer covering the emitter structure; a base metal preparation step: forming a plurality of fingers on one side of the first surface of the first basic structure, so that the plurality of fingers are electrically connected to the semiconductor layer and the emitter structure is located between adjacent fingers among the plurality of fingers; forming a connecting portion on a side of the emitter structure away from the semiconductor layer, so that the connecting portion is isolated from the emitter structure by the passivation layer, and the connecting portion is respectively connected to the plurality of fingers; the plurality of fingers and the connecting portion constitute the base metal.

[0007] An embodiment of the present invention further provides a radio frequency amplifier, comprising the heterojunction bipolar transistor described in the above embodiment.

[0008] The above-mentioned embodiments of the present invention have at least one or more of the following beneficial effects: the connection portion of the base metal is arranged on the emitter structure, and the emitter structure and the connection portion are isolated by a passivation layer to ensure that there is no short circuit. This embodiment can reduce the base step area while ensuring that the size of the emitter structure and the base metal remains basically unchanged compared to the conventional heterojunction bipolar transistor structure, thereby reducing the junction capacitance and improving working efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The specific implementation modes of the present invention will be described in detail below with reference to the accompanying drawings.

[0010] Figure 1 A schematic diagram of the top structure of a heterojunction bipolar transistor provided in an embodiment of the present invention.

[0011] Figure 2 for Figure 1 The structural schematic diagram of the AA section of the heterojunction bipolar transistor shown.

[0012] Figure 3 for Figure 1 Schematic diagram of the structure of the BB cross section of the heterojunction bipolar transistor shown.

[0013] Figure 4 for Figure 1 Schematic diagram of the CC cross-section structure of the heterojunction bipolar transistor shown.

[0014] Figure 5 A schematic top view of the first basic structure in the method for preparing a heterojunction bipolar transistor provided in an embodiment of the present invention.

[0015] Figure 6A schematic diagram of a top view structure after a first mask is formed in the method for preparing a heterojunction bipolar transistor provided in an embodiment of the present invention.

[0016] Figure 7 A schematic diagram of the top view structure after the first opening is formed in the method for preparing a heterojunction bipolar transistor provided in an embodiment of the present invention.

[0017] Figure 8 A schematic diagram of a top view of the structure after a second mask is formed in the method for preparing a heterojunction bipolar transistor provided in an embodiment of the present invention.

[0018] Fig. 9 The first basic structure in the method for preparing a heterojunction bipolar transistor provided in an embodiment of the present invention corresponds to Figure 1 Cross-sectional diagram showing the location of the BB section.

[0019] Fig.10 For the corresponding Figure 1 A schematic diagram of the structure of forming the first mask at the BB cross-section position.

[0020] Fig.11 For the corresponding Figure 1 A schematic diagram of the structure of forming the second mask at the BB cross-section position.

[0021] Fig.12 For the corresponding Figure 1 A schematic diagram of the structure of forming the second mask at the AA cross-section position.

[0022] Fig.13 For the corresponding Figure 1 Schematic diagram of the structure of the deposited base metal material at the BB cross-section position.

[0023] Fig.14 For the corresponding Figure 1 Schematic diagram of the structure of the deposited base metal material at the AA cross-section position.

[0024] Fig.15 A schematic top view of the structure of another heterojunction bipolar transistor provided in an embodiment of the present invention.

[0025] Fig.16 A schematic top view of the structure of another heterojunction bipolar transistor provided in an embodiment of the present invention.

[0026] Fig.17 A schematic top view of the structure of another heterojunction bipolar transistor provided in an embodiment of the present invention.

[0027] Fig.18 It is a cross-sectional view of a heterojunction bipolar transistor in the prior art.

[0028] [Description of Reference Numerals]

[0029] 100. Heterojunction bipolar transistor; 10. Semiconductor layer; 11. First surface; 12. Substrate; 13. Subcollector layer; 14. Etch stop layer; 15. Collector layer; 16. Base layer; 17. Emitter layer; 20. Emitter structure; 201. First end; 202. Second end; 21. Emitter step; 22. Emitter metal; 30. Passivation layer; 31. First sublayer; 311. First opening; 32. Second sublayer; 40. Base metal; 41. Finger; 411: First part; 412: Second part; 42. Connecting part; 50. First mask; 51. First window; 60. Second mask; 61. Second window; 62. Third window; 70. Base metal material; 80. Collector metal. 10a, first semiconductor layer; 11a, upper surface; 21a, first emitter step; 22a, first emitter metal; 20a, first emitter structure; 40a: first base metal. DETAILED DESCRIPTION

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.

[0034] First embodiment

[0035] Reference Figure 1 The first embodiment of the present invention provides a heterojunction bipolar transistor 100, comprising: a semiconductor layer 10, an emitter structure 20 ( Figure 1 The semiconductor layer 10 has a first surface 11. The emitter structure 20 is disposed on the first surface 11. The passivation layer 30 covers the emitter structure 20. Figure 1 and Figure 3 The base metal 40 (indicated by hatching in the figure) includes a plurality of fingers 41, which are arranged on the first surface 11 at intervals and are electrically connected to the semiconductor layer 10. Figure 1 , Figure 2 and Figure 4 The base metal 40 further includes a connecting portion 42, and the connecting portion 42 is electrically connected to the plurality of finger portions 41. Figure 2 and Figure 4 At least a portion of the connecting portion 42 is located on a side of the emitter structure 20 away from the semiconductor layer 10 and is isolated from the emitter structure 20 by the passivation layer 30 .

[0036] Among them, the semiconductor layer 10 is a base step of a heterojunction bipolar transistor structure. For example, the semiconductor layer 10 may specifically include a substrate 12, a sub-collector layer 13, an etching stop layer 14, a collector layer 15, a base layer 16 and an emitter layer 17 stacked in sequence. Among them, the first surface 11 is specifically the surface of the emitter layer 17 away from the base layer 16. The multiple fingers 41 specifically penetrate the emitter layer 17 and the base layer 16 to connect. The specific structure of the semiconductor layer 10 can be set with reference to the epitaxial layer structure of a traditional heterojunction bipolar transistor. A collector metal 80 connected to the collector layer is also provided on the semiconductor layer 10.

[0037] The emitter structure 20 includes an emitter step 21 and an emitter metal 22 sequentially stacked on the first surface 11 .

[0038] The passivation layer 30 is, for example, made of silicon nitride, and the thickness of the passivation layer 30 is, for example, 20 to 80 nm (nanometers). The area where the first surface 11 is exposed outside the emitter structure 20 is the first sub-region, and the passivation layer 30 also covers the first sub-region. For example, the passivation layer 30 can be regarded as a first sub-layer 31 covering the first sub-region and a second sub-layer 32 covering the emitter structure 20. For example, a first opening 311 is provided on the passivation layer 30, and the specific first opening 311 is located in the first sub-region, so that the multiple fingers 41 can be electrically connected to the semiconductor layer 10 through the first opening 311. The second sub-layer 32 covers the top surface of the emitter structure 20 away from the semiconductor layer 10 and the side surface between the top surface of the emitter structure 20 and the semiconductor layer 10. In some embodiments, the side surface of the emitter structure 20 is arranged obliquely to the first surface 11, which can provide better support for the connecting portion 42.

[0039] The passivation layer 30 may also have other openings corresponding thereto, for example, a metal connection opening may be provided at a portion of the emitter structure 20 not covered by the connection portion 42 for metal bonding connection, which is not limited in this embodiment.

[0040] Reference Fig.18 In the prior art, the semiconductor layer of the heterojunction bipolar transistor structure is marked as the first semiconductor layer 10a, the base metal is marked as the first base metal 40a, the emitter metal is marked as the first emitter metal 22a, the emitter structure is marked as the first emitter structure 20a, and the emitter step is marked as the first emitter step 21a. Fig.18In the embodiment, the first base metal 40a and the first emitter structure 20a are adjacently arranged on the upper surface of the first semiconductor layer 10a, that is, in the existing heterojunction bipolar transistor structure, the base metal connecting strip is arranged on the outside of the emitter step layer, and the base metal connecting strip and the emitter step layer need to maintain a certain distance to ensure the reliability of the heterojunction bipolar transistor product. Therefore, in the heterojunction bipolar transistor structure in which the base metal connecting strip and the emitter step layer are arranged on the same layer, the base step area is larger. However, the base step area determines the area of ​​the base-collector heterojunction. In the heterojunction bipolar transistor 100 provided in the above embodiment of the present invention, the connecting portion 42 is arranged on the emitter structure 20, and the emitter structure 20 and the connecting portion 42 are isolated by the passivation layer 30 to ensure that there is no Short circuit, compared with the solution in which the base metal connecting strip is arranged on the outside of the emitter step layer, this embodiment can reduce the base step area while ensuring that the sizes of the emitter structure 20 and the base metal 40 are basically unchanged compared with the conventional heterojunction bipolar transistor structure. The base step area of ​​the heterojunction bipolar transistor 100 provided by the embodiment of the present invention can be reduced by 15% to 25% compared with the base step area of ​​the traditional heterojunction bipolar transistor structure, that is, the base step area of ​​the heterojunction bipolar transistor 100 provided by the embodiment of the present invention can reach 75% to 85% of the base step area of ​​the traditional heterojunction bipolar transistor. Therefore, the structure of the heterojunction bipolar transistor 100 provided by the embodiment of the present invention can reduce the area of ​​the base-collector heterojunction, thereby reducing the junction capacitance and improving the working efficiency.

[0041] In some embodiments, reference Figure 1 , the plurality of fingers 41 are arranged in parallel along a first direction. The connecting portion 42 extends along a second direction perpendicular to the first direction. Figure 1 In the orientation shown, the multiple fingers 41 are arranged horizontally and parallel to each other, and the connecting portion 42 vertically connects the multiple fingers 41. Of course, in other embodiments, the connecting portion 42 only needs to connect the multiple fingers 41, that is, the connecting portion 42 can also be arranged obliquely relative to the multiple fingers 41.

[0042] In some embodiments, the emitter structure 20 has a first end 201 and a second end 202 opposite to each other in a first direction, and the connecting portion 42 may be disposed at a middle position between the first end 201 and the second end 202, or may be disposed near one end (the first end 201 or the second end 202) of the emitter structure 20. In some embodiments, the connecting portion 42 is disposed adjacent to one of the first end 201 and the second end 202. For example Figure 1 The connecting portion 42 shown is disposed adjacent to the first end 201 . In this embodiment, “adjacent to the first end 201 ” means that the connecting portion 42 is closer to the first end 201 than to the second end 202 .

[0043] In some embodiments, the orthographic projection of the emitter structure 20 on the first surface 11 has a first projection edge and a second projection edge that are opposite to each other in the first direction, and the orthographic projection of the connecting portion 42 on the first surface 11 is located between the first projection edge and the second projection edge. The first projection edge is the projection of the first end 201 on the first surface 11, and the second projection edge is the projection of the second end 202 on the first surface 11. That is, the width of the connecting portion 42 in the second direction is located on the emitter structure 20, which can reduce the occupied area of ​​the connecting portion 42. In some embodiments, the distance L1 from the orthographic projection of the connecting portion 42 on the first surface 11 to the first projection edge and the second projection edge is greater than or equal to 0.2 microns. Figure 1 As shown, if the connection portion 42 is disposed closer to the first end 201, the distance from the orthographic projection of the connection portion 42 on the first surface 11 to the edge of the first projection should be greater than or equal to 0.2 microns. If the connection portion 42 is disposed closer to the second end 202, the distance from the orthographic projection of the connection portion 42 on the first surface 11 to the edge of the second projection should be greater than or equal to 0.2 microns.

[0044] Specifically, refer to Fig.15 In some embodiments, the orthographic projection of the edge of the connecting portion 42 close to the first end 201 on the first surface 11 coincides with the first projection edge. Fig.16 , the connecting portion 42 is located between the first end 201 and the second end 202, the lengths of the plurality of fingers 41 and the emitter structure 20 along the first direction are equal, and specifically, the orthographic projections of the edges of the plurality of fingers 41 close to the first end 201 on the first surface 11 are in a straight line with the first projection edge, and the orthographic projections of the edges of the plurality of fingers 41 close to the second end 202 on the first surface 11 are in a straight line with the second projection edge. Fig.17 In some embodiments, the edge of the connecting portion 42 close to the first end 201 and the first projected edge may be arranged close to the edge of the first surface 11 in the first direction.

[0045] In some embodiments, the connecting portion 42 has a first width W1 along the first direction, and the first width W1 is greater than or equal to 1 micrometer.

[0046] In some embodiments, reference Figure 3 Each of the plurality of fingers 41 includes a first portion 411 and a second portion 412, wherein the first portion 411 is disposed in the first opening 311, the second portion 412 is located on a side of the first portion 411 away from the semiconductor layer 10, and the second portion 412 extends to a surface of the first sub-layer 31 adjacent to the first opening 311. Figure 3That is, among the multiple fingers 41, the width of the first portion 411 of each finger 41 in the second direction is smaller than the width of the second portion 412 in the second direction. The first portion 411 is the portion where the multiple fingers 41 are electrically connected to the semiconductor layer 10. The distance between the first portion 411 and the emitter structure 20 will affect the reliability of the product. In this embodiment, by setting the first portion 411 to be narrower than the second portion 412, it is possible to ensure that the first portion 411 and the emitter structure 20 are maintained at a suitable distance, while the second portion 412 can maintain the width of the traditional base metal, thereby not affecting the base resistance. Therefore, compared with the traditional structure, the different settings of the widths of the first portion 411 and the second portion 412 in the multiple fingers 41 can improve the reliability without affecting the base resistance. Second embodiment

[0047] A second embodiment of the present invention provides a method for preparing a heterojunction bipolar transistor, which can be used to prepare the heterojunction bipolar transistor 100 provided in the above embodiment. The method for preparing the heterojunction bipolar transistor includes:

[0048] Step S1: Provide a first basic structure; Figure 5 and Fig. 9 The first basic structure includes: a semiconductor layer 10 , the semiconductor layer 10 has a first surface 11 ; an emitter structure 20 , which is arranged on the first surface 11 ; and a passivation layer 30 , which covers the emitter structure 20 .

[0049] Step S3 (base metal 40 preparation step): a plurality of fingers 41 are formed on one side of the first surface 11 of the first basic structure, so that the plurality of fingers 41 are electrically connected to the semiconductor layer 10 and the emitter structure 20 is located between adjacent fingers 41 among the plurality of fingers 41; a connecting portion 42 is formed on a side of the emitter structure 20 away from the semiconductor layer 10, so that the connecting portion 42 is isolated from the emitter structure 20 by the passivation layer 30, and the connecting portion 42 is respectively connected to the plurality of fingers 41; the plurality of fingers 41 and the connecting portion 42 constitute the base metal 40.

[0050] The description of the semiconductor layer 10, the emitter structure 20 and the passivation layer 30 in the first basic structure of this embodiment can refer to the description in the aforementioned first embodiment. In the heterojunction bipolar transistor 100 provided in this embodiment, by making the connection portion 42 of the formed base metal 40 located on the emitter structure 20 in step S3 and isolated from the emitter structure 20 by the passivation layer 30, the base step area can be reduced while ensuring that the size of the emitter structure 20 and the base metal 40 is basically unchanged compared to the conventional heterojunction bipolar transistor structure, the area of ​​the heterojunction can be reduced, and then the junction capacitance can be reduced, and the working efficiency can be improved.

[0051] Specifically, the area of ​​the first surface 11 exposed outside the emitter structure 20 is the first sub-region. The passivation layer 30 also covers the first sub-region. Figure 6 and Fig.10 , and before step S3, further comprising step S2:

[0052] Step S21: forming a first mask 50 on the passivation layer; the first mask 50 has a plurality of first windows 51, and the orthographic projections of the plurality of first windows 51 on the first surface 11 are located in the first sub-region.

[0053] Step S22 : etching the passivation layer 30 corresponding to the first windows 51 to form a plurality of first openings 311 .

[0054] Step S22: After etching out a plurality of first openings 311, remove the first mask 50 to obtain Figure 7 The structure shown.

[0055] Step S3 specifically includes step S31 (refer to Figure 8 , Fig.11 and Fig.13 ): forming a second mask 60 on the passivation layer 30, the second mask 60 having a second window 61 and a plurality of third windows 62, the plurality of third windows 62 exposing a plurality of first openings 311; the orthographic projection of the second window 61 on the first surface 11 intersects with the orthographic projection of the emitter structure 20 on the first surface 11, and the second window 61 is connected to the plurality of third windows 62;

[0056] Step S32 (refer to Fig.12 and Fig.14 ):Depositing a base metal material 70 on the second mask 60 to form a base metal 40.

[0057] Among them, the formation process of the first mask 50 and the second mask 60 can refer to the traditional photolithography process. The deposition of the base metal material 70 can adopt an evaporation process. In this embodiment, by respectively setting the first mask 50 and the second mask 60, when the base metal material 70 is deposited (indicated by diagonal filling in the figure), since the plurality of third windows 62 expose the plurality of first openings 311, the portion of the base metal material 70 corresponding to the position of the third window 62 can be deposited on the first surface 11 through the first opening 311 and electrically connected to the semiconductor layer 10, forming a plurality of fingers 41; since the orthographic projection of the second window 61 on the first surface 11 intersects with the orthographic projection of the emitter structure 20 on the first surface 11, the portion of the base metal material 70 corresponding to the position of the second window 61 can be deposited on the emitter structure 20, forming a connecting portion 42, and the setting of the passivation layer 30 allows the connecting portion 42 to be separated from the emitter structure 20 to prevent short circuit. Since the second window 61 is connected to the plurality of third windows 62, the connecting portion 42 can be connected to the plurality of fingers 41 respectively. In this embodiment, the structure of the heterojunction bipolar transistor 100 in the first embodiment can be realized by disposing the first mask 50 and the second mask 60, thereby reducing the junction capacitance and improving the power.

[0058] Of course, after step S22 , the base metal material 70 may be deposited by evaporating the base metal 40 in multiple times by respectively setting different masks for the multiple fingers 41 and the connecting parts 42 . The present embodiment is not limited to the above example.

[0059] In some embodiments, in the aforementioned step S32, the orthographic projection of the third window 62 on the first surface 11 covers the first opening 311 and covers the area of ​​the passivation layer 30 adjacent to the first opening 311. Fig.10 and Fig.11 , that is, the width W3 of the third window 62 is greater than the width W2 of the first window 51, so that the formed finger 41 has a first portion 411 located in the first opening 311 and a second portion 412 located on a side of the first portion 411 away from the semiconductor layer 10, and the second portion 412 extends to the surface of the first sublayer 31 adjacent to the first opening 311. Referring to the description in the first embodiment above, compared with the conventional structure, the different settings of the widths of the first portion 411 and the second portion 412 in the plurality of fingers 41 can improve reliability without affecting the base resistance.

[0060] An embodiment of the present invention also provides a radio frequency amplifier, including the heterojunction bipolar transistor 100 described in any one of the aforementioned embodiments. The radio frequency amplifier can be applied to integrated radio frequency switches and filters. The radio frequency amplifier provided in this embodiment has the same beneficial effects as the heterojunction bipolar transistor 100, which will not be repeated here.

[0061] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A heterojunction bipolar transistor, characterized in that: include: a semiconductor layer having a first surface; An emitter structure, disposed on the first surface; a passivation layer covering the emitter structure; The base metal comprises: a plurality of fingers, the plurality of fingers are arranged on the first surface at intervals and are electrically connected to the semiconductor layer; and a connecting portion, which is electrically connected to the plurality of fingers respectively; At least a portion of the connecting portion is located on a side of the emitter structure away from the semiconductor layer and is isolated from the emitter structure by the passivation layer.

2. The heterojunction bipolar transistor according to claim 1, characterized in that: The plurality of fingers are arranged in parallel along a first direction; and the connecting portion extends along a second direction perpendicular to the first direction.

3. The heterojunction bipolar transistor according to claim 2, characterized in that: The orthographic projection of the emitter structure on the first surface has a first projection edge and a second projection edge opposite to each other in a first direction, and the orthographic projection of the connecting portion on the first surface is located between the first projection edge and the second projection edge.

4. The heterojunction bipolar transistor according to claim 3, characterized in that: The distances from the orthographic projection of the connecting portion on the first surface to the first projection edge and the second projection edge are both greater than or equal to 0.2 micrometers.

5. The heterojunction bipolar transistor according to claim 2, characterized in that: The emitter structure has a first end and a second end opposite to each other in the first direction, and the connecting portion is disposed adjacent to one of the first end and the second end.

6. The heterojunction bipolar transistor according to claim 2, characterized in that: The connecting portion has a first width along the first direction, and the first width is greater than or equal to 1 micrometer.

7. The heterojunction bipolar transistor according to claim 1, characterized in that: The passivation layer includes a first sublayer; the first sublayer covers the area of ​​the first surface exposed outside the emitter structure, the first sublayer has a plurality of first openings corresponding to the plurality of fingers, and the plurality of fingers are electrically connected to the semiconductor layer through the corresponding first openings; Each of the plurality of fingers includes a first portion and a second portion, wherein the first portion is disposed in the first opening, the second portion is located at a side of the first portion away from the semiconductor layer, and the second portion extends to a surface of the first sublayer adjacent to the first opening.

8. The heterojunction bipolar transistor according to claim 1, characterized in that: The side surface of the emitter structure is arranged obliquely to the first surface.

9. A method for preparing a heterojunction bipolar transistor, characterized in that: include: providing a first infrastructure; The first basic structure includes: a semiconductor layer, the semiconductor layer having a first surface; an emitter structure, arranged on the first surface; a passivation layer, the passivation layer covering the emitter structure; Base metal preparation steps: forming a plurality of fingers on one side of the first surface of the first basic structure, so that the plurality of fingers are electrically connected to the semiconductor layer and the emitter structure is located between adjacent fingers among the plurality of fingers; forming a connecting portion on a side of the emitter structure away from the semiconductor layer, so that the connecting portion is isolated from the emitter structure by the passivation layer, and the connecting portion is respectively connected to the plurality of fingers; the plurality of fingers and the connecting portion constitute the base metal.

10. A radio frequency amplifier, characterized in that: The radio frequency amplifier comprises a heterojunction bipolar transistor as described in any one of claims 1-8.

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