Preparation method of solar cell, solar cell and photovoltaic module

Abstract

The invention relates to a preparation method of a solar cell, the solar cell and a photovoltaic module. The preparation method of the solar cell comprises the steps that a substrate is provided, the substrate is provided with a first surface and a second surface which are oppositely arranged in the thickness direction perpendicular to the substrate, and at least one of the first surface and the second surface is defined as a target surface; forming a first tunneling layer, a first doped semiconductor layer, a second tunneling layer and a second doped semiconductor layer which are stacked on the target surface of the substrate in the direction away from the substrate to obtain a passivation structure; a plurality of holes are formed in the second tunneling layer; and performing annealing treatment on the passivation structure to increase the size of the hole in the direction parallel to the reference plane. According to the preparation method of the solar cell, the passivation performance of the solar cell can be improved, and the contact performance of the solar cell can also be improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a method for preparing a solar cell, a solar cell and a photovoltaic module. Background Art

[0002] A solar cell is a device that converts sunlight into electrical energy. In related technologies, solar cells usually include a tunneling oxide layer, which can improve the passivation performance of solar cells. However, the setting of the tunneling oxide layer will hinder the transmission and collection of carriers, resulting in poor contact performance of traditional solar cells. Summary of the invention

[0003] Based on this, it is necessary to provide a method for preparing a solar cell, a solar cell and a photovoltaic module to address the above technical problems, which can improve the passivation performance of the solar cell while also improving the contact performance of the solar cell.

[0004] According to a first aspect of the present application, a method for preparing a solar cell is provided, the method for preparing a solar cell comprising:

[0005] Providing a substrate, wherein the substrate has a first surface and a second surface disposed opposite to each other along a thickness direction perpendicular to the substrate, and defining at least one of the first surface and the second surface as a target surface;

[0006] A first tunneling layer, a first doped semiconductor layer, a second tunneling layer and a second doped semiconductor layer are stacked on the target surface of the substrate in a direction away from the substrate to obtain a passivation structure; a plurality of holes are provided on the second tunneling layer;

[0007] Annealing the passivation structure to increase the size of the hole in a direction parallel to a reference plane;

[0008] The reference plane is a plane perpendicular to the thickness direction of the substrate.

[0009] In one embodiment, the process parameters of the annealing treatment include: annealing time is 10min-60min, and annealing temperature is 400℃-900℃.

[0010] In one embodiment, the annealing treatment of the passivation structure specifically includes:

[0011] annealing the passivation structure in an oxygen-free atmosphere;

[0012] Wherein, the oxygen-free gas includes an inert gas or hydrogen.

[0013] In one embodiment, after the passivation structure is annealed, at least a portion of the holes penetrate the second tunneling layer.

[0014] In one embodiment, after the passivation structure is annealed, the sum of the orthographic projection areas of the plurality of holes in a preset region of the reference plane is S1, the area of ​​the preset region of the reference plane is S2, S1=a*S2, 10%≤a≤80%.

[0015] In one embodiment, 15%≤a≤60%.

[0016] In one of the embodiments, before the passivation structure is annealed, the sum of the orthographic projection areas of the plurality of holes in a preset region of the reference plane is S3, the area of ​​the preset region of the reference plane is S2, S3=b*S2, 0%≤b<15%.

[0017] According to a second aspect of the present application, there is provided a solar cell, comprising:

[0018] A substrate, wherein the substrate has a first surface and a second surface disposed opposite to each other along a thickness direction perpendicular to the substrate, and at least one of the first surface and the second surface is defined as a target surface;

[0019] A first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer are stacked on the target surface of the substrate in a direction away from the substrate;

[0020] an anti-reflection layer, disposed on a surface of the second doped semiconductor layer away from the second tunneling layer; and

[0021] A plurality of electrodes are disposed on the anti-reflection layer, and the electrodes are electrically connected to the second doped semiconductor layer;

[0022] The first tunneling layer is a continuous tunneling layer, and the second tunneling layer is a discontinuous tunneling layer.

[0023] In one embodiment, a plurality of holes are provided on the second tunneling layer, and the sum of the orthographic projection areas of the plurality of holes in a preset region of a reference plane is S1, and the area of ​​the preset region of the reference plane is S2, S1=a*S2, 10%≤a≤80%.

[0024] In one embodiment, at least part of the holes are disposed through the second tunneling layer.

[0025] In one embodiment, the thickness of the first tunneling layer is smaller than the thickness of the second tunneling layer.

[0026] In one embodiment, the thickness of the second tunneling layer is 0.2 nm-5 nm.

[0027] In one embodiment, the thickness of the first tunneling layer is 0.5 nm-5 nm.

[0028] In one embodiment, the contact resistivity between the second doped semiconductor layer and the electrode is 0.5 mΩ·cm 2 -5mΩ·cm 2 .

[0029] In one embodiment, the material of the second tunneling layer includes silicon oxide, and the molar mass percentage of oxygen in the second tunneling layer is 5%-45%.

[0030] In one embodiment, the half-peak width of the Raman characteristic peak of the second doped semiconductor layer is 3 cm -1 -20cm -1 ;

[0031] The Raman characteristic peak of the second doped semiconductor layer is 510 cm -1 -520cm -1 The characteristic peak at .

[0032] According to a third aspect of the present application, a photovoltaic assembly is provided, comprising:

[0033] A battery string, wherein the battery string is formed by connecting a plurality of solar cells of any one of the above embodiments;

[0034] An encapsulation layer, the encapsulation layer is used to cover the surface of the battery string;

[0035] A cover plate is used to cover a surface of the packaging layer away from the battery string.

[0036] In the technical solution of the present application, on the one hand, the second tunneling layer can be used to block the downward ablation of the metal paste, thereby improving the passivation performance of the solar cell; on the other hand, the first tunneling layer can suppress the recombination of carriers at the substrate interface, thereby improving the carrier transport and charge collection capabilities; and in the process of annealing the passivation structure, the crystallinity and tensile stress of the first doped semiconductor layer and the second doped semiconductor layer can be improved, thereby increasing the size of multiple holes on the second tunneling layer between the first doped semiconductor layer and the second doped semiconductor layer under the action of tensile stress, which is beneficial to promote the longitudinal transmission of carriers in the first doped semiconductor layer and the second doped semiconductor layer, thereby improving the contact performance of the solar cell; therefore, the preparation method of the solar cell can improve the passivation performance of the solar cell while also improving the contact performance of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic flow chart of a method for preparing a solar cell in an embodiment of the present application is shown.

[0038] Figure 2 A schematic structural diagram of a solar cell in an embodiment of the present application is shown.

[0039] Figure 3 The oxygen element distribution diagram of the passivation structure of one embodiment of the present application before annealing is shown.

[0040] Figure 4 The oxygen element distribution diagram of the passivation structure after annealing treatment in one embodiment of the present application is shown.

[0041] Figure 5 A line scan element distribution diagram of the second tunneling layer before annealing treatment according to an embodiment of the present application is shown.

[0042] Figure 6 A line scan element distribution diagram of the second tunneling layer after annealing treatment according to an embodiment of the present application is shown.

[0043] Figure 7 The Raman spectra of the second doped semiconductor layer before and after annealing treatment in one embodiment of the present application are shown.

[0044] Figure numerals: 100, substrate; 101, first surface; 102, second surface; 200, first tunneling layer; 300, first doped semiconductor layer; 400, second tunneling layer; 410, hole; 500, second doped semiconductor layer; 600, anti-reflection layer; 700, electrode; L1, first energy spectrum; L2, second energy spectrum. DETAILED DESCRIPTION

[0045] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0046] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0047] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0048] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0049] In the present application, unless otherwise clearly specified and limited, if there is a description that a first feature is "above" or "below" a second feature, etc., or similar descriptions appear, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0050] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0051] Figure 1 A schematic diagram of a process for preparing a solar cell in an embodiment of the present application is shown. Figure 2 A schematic structural diagram of a solar cell in an embodiment of the present application is shown.

[0052] See also Figure 1 and Figure 2 , a method for preparing a solar cell provided by an embodiment of the present application comprises:

[0053] S10, providing a substrate 100, wherein the substrate 100 has a first surface 101 and a second surface 102 that are disposed opposite to each other along a thickness direction perpendicular to the substrate 100, and defining at least one of the first surface 101 and the second surface 102 as a target surface.

[0054] The substrate 100 is used to receive incident light and generate photogenerated carriers. In some embodiments, the substrate 100 may be a silicon substrate, and the material of the silicon substrate may include at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, the material of the substrate 100 may also be silicon carbide, an organic material, or a multi-component compound. The multi-component compound may include, but is not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenide, and the like.

[0055] The target surface of the substrate 100 may be configured as a pyramid-shaped velvet surface, so that the reflectivity of the target surface of the substrate 100 to the incident light is lower, thereby increasing the absorption utilization rate of the light.

[0056] The target surface of the substrate 100 can also be set to a non-pyramid velvet surface, such as a stacked step morphology, so that the first tunneling layer 200 located on the target surface of the substrate 100 has a higher density and uniformity, so that the first tunneling layer 200 has a good passivation effect on the target surface of the substrate 100.

[0057] S20, forming a first tunneling layer 200, a first doped semiconductor layer 300, a second tunneling layer 400 and a second doped semiconductor layer 500 stacked on a target surface of the substrate 100 in a direction away from the substrate 100 to obtain a passivation structure. A plurality of holes 410 are provided on the second tunneling layer 400.

[0058] The first surface 101 may be a target surface, and a first tunneling layer 200 , a first doped semiconductor layer 300 , a second tunneling layer 400 and a second doped semiconductor layer 500 that are stacked are formed on the first surface 101 .

[0059] Alternatively, the second surface 102 is a target surface, and a first tunneling layer 200 , a first doped semiconductor layer 300 , a second tunneling layer 400 , and a second doped semiconductor layer 500 that are stacked are formed on the second surface 102 .

[0060] Alternatively, the first surface 101 and the second surface 102 are target surfaces, and a first tunneling layer 200 , a first doped semiconductor layer 300 , a second tunneling layer 400 and a second doped semiconductor layer 500 are stacked and formed on the first surface 101 and the second surface 102 , respectively.

[0061] For example, the first surface 101 is the front surface, the second surface 102 is the back surface, and a first tunneling layer 200 , a first doped semiconductor layer 300 , a second tunneling layer 400 and a second doped semiconductor layer 500 are stacked and formed on the first surface 101 .

[0062] The material of the first tunnel layer 200 and the second tunnel layer 400 may be a dielectric material, for example, any one of silicon oxide, magnesium fluoride, silicon oxide, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide.

[0063] The material of the first doped semiconductor layer 300 and the second doped semiconductor layer 500 may be at least one of silicon carbide, microcrystalline silicon, or polycrystalline silicon.

[0064] S30 , performing annealing treatment on the passivation structure to increase the size of the hole 410 along a direction parallel to a reference plane, where the reference plane is a plane perpendicular to the thickness direction of the substrate 100 .

[0065] On the one hand, the second tunneling layer 400 can be used to block the downward ablation of the metal paste (the metal paste will be subsequently formed on the side of the second doped semiconductor layer 500 away from the substrate 100, and then the electrode 700 described below will be formed on the side of the second doped semiconductor layer 500 away from the substrate 100), thereby improving the passivation performance of the solar cell; on the other hand, the first tunneling layer 200 can suppress the recombination of carriers at the interface of the substrate 100, and the carrier transport and charge collection capabilities can be improved; and in the process of annealing the passivation structure, the crystallinity and tensile stress of the first doped semiconductor layer 300 and the second doped semiconductor layer 500 can be improved, so that under the action of tensile stress, the size of the multiple holes 410 on the second tunneling layer 400 between the first doped semiconductor layer 300 and the second doped semiconductor layer 500 increases, which is beneficial to promote the longitudinal transmission of carriers in the first doped semiconductor layer 300 and the second doped semiconductor layer 500, thereby improving the contact performance of the solar cell; therefore, the preparation method of the solar cell can improve the passivation performance of the solar cell while also improving the contact performance of the solar cell. It should be noted that the size of the hole 410 is at the nanometer level, and the second tunneling layer 400 can still be well utilized to prevent the downward ablation of the metal paste.

[0066] In some embodiments, the process parameters of the annealing treatment include: an annealing time of 10 min-60 min, and an annealing temperature of 400° C.-900° C.

[0067] For example, the annealing time is 10 min, 20 min, 30 min, 40 min, 50 min or 60 min, and the annealing temperature is 400°C, 500°C, 600°C, 700°C, 800°C or 900°C.

[0068] If the annealing temperature is too low or the annealing time is too short, the tensile stress formed between the first doped semiconductor layer 300 and the second doped semiconductor layer 500 will be insufficient, making it difficult to make the second tunneling layer 400 discontinuous; if the annealing temperature is too high or the annealing time is too long, the structure of the first tunneling layer 200 will be affected; for this reason, it is necessary to set the annealing temperature and the annealing time in appropriate ranges, for example, the annealing temperature is set to 400°C-900°C, and the annealing time is set to 10min-60min, which can make the second tunneling layer 400 discontinuous and increase the size of the hole 410, which is beneficial to promote the longitudinal transmission of carriers in the first doped semiconductor layer 300 and the second doped semiconductor layer 500; and the first tunneling layer 200 can maintain its density and continuity, which is beneficial to improve the passivation performance of the solar cell.

[0069] In some embodiments, the step S30 of annealing the passivation structure specifically includes:

[0070] S31, performing annealing treatment on the passivation structure in an oxygen-free gas atmosphere, wherein the oxygen-free gas includes an inert gas or hydrogen.

[0071] The inert gas can be nitrogen or helium.

[0072] Annealing the passivation structure in an oxygen-free atmosphere can well protect the passivation structure.

[0073] In some embodiments, after the passivation structure is annealed, at least a portion of the holes 410 are disposed through the second tunneling layer 400 .

[0074] In this way, the second tunneling layer 400 can be in a discontinuous state, and carriers can be directly transmitted through these through-holes 410. Compared with the second tunneling layer 400 before the annealing treatment, the carrier passing capacity of the second tunneling layer 400 after the annealing treatment is increased, which is beneficial to promote the longitudinal transmission of carriers in the first doped semiconductor layer 300 and the second doped semiconductor layer 500, and further helps to improve the contact performance of the solar cell.

[0075] In some embodiments, after the passivation structure is annealed, the sum of the orthographic projection areas of the plurality of holes 410 in the preset region of the reference plane is S1, the area of ​​the preset region of the reference plane is S2, S1 = a*S2, 10%≤a≤80%.

[0076] Further, 15%≤a≤80%, and further, 15%≤a≤60%.

[0077] Illustratively, a is 10%, 15%, 20%, 30%, 40%, 50%, 60%, 70% or 80%.

[0078] It can be understood that the area of ​​the plurality of holes 410 in the preset area of ​​the reference plane accounts for 10%-80%. It can be seen that the area of ​​the plurality of holes 410 in the preset area of ​​the reference plane accounts for a relatively large proportion, which is beneficial to promote the longitudinal transmission of carriers in the first doped semiconductor layer 300 and the second doped semiconductor layer 500, thereby helping to improve the contact performance of the solar cell.

[0079] In some embodiments, before the passivation structure is annealed, the sum of the orthographic projection areas of the plurality of holes 410 in a preset region of the reference plane is S3, the area of ​​the preset region of the reference plane is S2, S3=b*S2, 0%≤b<15%.

[0080] For example, b is 10.3% (can be combined with Figure 3 to understand), a is 45.1% (can be combined with Figure 4 to understand).

[0081] It can be seen that before the passivation structure is annealed, the area ratio of the multiple holes 410 in the preset area of ​​the reference plane is relatively small. After the passivation structure is annealed, the area ratio of the multiple holes 410 in the preset area of ​​the reference plane is significantly increased. This shows that annealing the passivation structure can significantly increase the area ratio of the multiple holes 410 in the preset area of ​​the reference plane (this is mainly due to the increase in the tensile stress of the first doped semiconductor layer 300 and the second doped semiconductor layer 500), and thus form a discontinuous second tunneling layer 400, which is more conducive to promoting the longitudinal transmission of carriers in the first doped semiconductor layer 300 and the second doped semiconductor layer 500, and thus is more conducive to improving the contact performance of the solar cell.

[0082] like Figure 3 and Figure 4 As shown, after the passivation structure is annealed, the first tunneling layer 200 still has continuity and compactness, which indicates that the tensile stress of the first doped semiconductor layer 300 and the second doped semiconductor layer 500 does not affect the continuity and compactness of the first tunneling layer 200 .

[0083] The present application also provides a solar cell, including a substrate 100 , a first tunneling layer 200 , a first doped semiconductor layer 300 , a second tunneling layer 400 , a second doped semiconductor layer 500 , an anti-reflection layer 600 and an electrode 700 .

[0084] The first tunneling layer 200, the first doped semiconductor layer 300, the second tunneling layer 400 and the second doped semiconductor layer 500 are stacked on the target surface of the substrate 100 in a direction away from the substrate 100, the anti-reflection layer 600 is arranged on the side surface of the second doped semiconductor layer 500 away from the second tunneling layer 400, and a plurality of electrodes 700 are arranged on the anti-reflection layer 600, and the electrodes 700 are electrically connected to the second doped semiconductor layer 500.

[0085] The material of the anti-reflection layer 600 may be a conductive material, for example, the material of the anti-reflection layer 600 is a transparent conductive oxide (TCO), etc. The electrode 700 is electrically connected to the second doped semiconductor layer 500 through the anti-reflection layer 600, so the electrode 700 and the second doped semiconductor layer 500 are indirectly electrically connected.

[0086] Alternatively, the material of the anti-reflection layer 600 is an insulating material, for example, the material of the anti-reflection layer 600 is aluminum oxide, silicon nitride or silicon oxynitride, etc. The electrode 700 passes through the anti-reflection layer 600 and is in electrical contact with the second doped semiconductor layer 500, so the electrode 700 is directly electrically connected to the second doped semiconductor layer 500.

[0087] The first tunneling layer 200 is a continuous tunneling layer, and the second tunneling layer 400 is a discontinuous tunneling layer.

[0088] The second tunneling layer 400 is a discontinuous tunneling layer relative to the first tunneling layer 200, which mainly means that the density of the second tunneling layer 400 is less than that of the first tunneling layer 200, or the porosity of the second tunneling layer 400 is greater than that of the first tunneling layer 200. Of course, it is also allowed that the first tunneling layer 200 is partially discontinuous due to process errors, as long as the first tunneling layer 200 is roughly continuous and has a high density. Since the second tunneling layer 400 is a discontinuous tunneling layer, it is beneficial to promote carriers to pass through the discontinuous area on the second tunneling layer 400, and then to be longitudinally transmitted in the first doped semiconductor layer 300 and the second doped semiconductor layer 500, which is beneficial to improve the contact performance of the solar cell.

[0089] In some embodiments, a plurality of holes 410 are disposed on the second tunneling layer 400, and the sum of the orthographic projection areas of the plurality of holes 410 in a preset region of the reference plane is S1, and the area of ​​the preset region of the reference plane is S2, S1 = a*S2, 10%≤a≤80%.

[0090] The area of ​​the plurality of holes 410 in the preset region of the reference plane accounts for a relatively large proportion, which is beneficial to promote the longitudinal transmission of carriers in the first doped semiconductor layer 300 and the second doped semiconductor layer 500, thereby improving the contact performance of the solar cell.

[0091] In some embodiments, the thickness of the first tunneling layer 200 is less than the thickness of the second tunneling layer 400 .

[0092] The carriers in the first tunneling layer 200 mainly pass through in the form of quantum tunneling. The thickness of the first tunneling layer 200 is set to be smaller than the thickness of the second tunneling layer 400, which is beneficial to improving the passivation performance of the solar cell while improving the contact performance of the solar cell; the carriers in the second tunneling layer 400 mainly pass through the hole 410. The thickness of the second tunneling layer 400 can be set to be greater than the thickness of the first tunneling layer 200. This is beneficial to better utilize the second tunneling layer 400 to block the downward ablation of the metal paste.

[0093] In some embodiments, the thickness of the second tunneling layer 400 is 0.2 nm-5 nm.

[0094] Specifically, the thickness of the second tunnel layer 400 is 2 nm-5 nm. For example, the thickness of the second tunnel layer 400 is 2 nm, 3 nm, 4 nm or 5 nm.

[0095] In this way, more carriers in the second tunneling layer 400 can pass through the hole 410, which is more conducive to promoting the longitudinal transmission of carriers in the first doped semiconductor layer 300 and the second doped semiconductor layer 500 with the help of the hole 410, and is more conducive to improving the contact performance of the solar cell.

[0096] In some embodiments, the thickness of the first tunneling layer 200 is 0.5 nm-5 nm.

[0097] Specifically, the thickness of the first tunnel layer 200 is 0.5 nm-2 nm. For example, the thickness of the first tunnel layer 200 is 0.5 nm, 1 nm, 1.5 nm or 2 nm.

[0098] The first tunneling layer 200 is continuous and dense, and the carriers in the first tunneling layer 200 mainly pass through in a quantum tunneling manner. The first tunneling layer 200 is also used to effectively suppress the recombination of carriers at the interface of the substrate 100, thereby improving the carrier transport and charge collection capabilities.

[0099] In some embodiments, the material of the second tunneling layer 400 includes silicon oxide, and the molar mass percentage of oxygen in the second tunneling layer 400 is 5%-45%.

[0100] For example, the molar mass percentage of oxygen element in the second tunneling layer 400 is 5%, 10%, 15%, 20%, 30%, 40% or 45%.

[0101] Before the passivation structure is annealed, the molar mass percentage of oxygen in the second tunneling layer 400 is 20%-54%. For example, before the passivation structure is annealed, the molar mass percentage of oxygen in the second tunneling layer 400 is 27%, and after the passivation structure is annealed, the molar mass percentage of oxygen in the second tunneling layer 400 is 19% ( Figure 5 In the figure, the energy spectrum corresponding to the oxygen element before the passivation structure is annealed is the first energy spectrum L1; Figure 6 In the figure, the energy spectrum corresponding to the oxygen element after the passivation structure is annealed is the second energy spectrum L2).

[0102] It can be seen that after the passivation structure is annealed, the molar mass percentage of the oxygen element in the second tunneling layer 400 decreases, which also indicates from one aspect that the proportion of the holes 410 in the second tunneling layer 400 increases, thereby forming a non-continuous second tunneling layer 400, which is beneficial to promote the longitudinal transmission of carriers in the first doped semiconductor layer 300 and the second doped semiconductor layer 500, and is more beneficial to improve the contact performance of the solar cell.

[0103] In some embodiments, the sum of the thickness of the second doped semiconductor layer 500 and the thickness of the first doped semiconductor layer 300 is 10 nm-500 nm.

[0104] Optionally, the thickness of the second doped semiconductor layer 500 is greater than or equal to the thickness of the first doped semiconductor layer 300. Due to the greater thickness of the second doped semiconductor layer 500, the effect of the annealing process on the first tunneling layer 200 between the first doped semiconductor layer 300 and the substrate 100 can be reduced, which is beneficial to maintaining the continuity and compactness of the first tunneling layer 200, thereby improving the passivation performance of the solar cell while improving the contact performance of the solar cell.

[0105] In some embodiments, the half-peak width of the Raman characteristic peak of the second doped semiconductor layer 500 is 3 cm -1 -20cm -1 The Raman characteristic peak of the second doped semiconductor layer 500 is 510cm -1 -520cm -1 The characteristic peak at .

[0106] Specifically, before the passivation structure is annealed, the half-peak width of the Raman characteristic peak of the second doped semiconductor layer 500 is 5 cm -1 -25cm -1 The Raman characteristic peak of the second doped semiconductor layer 500 is 515cm -1 -521cm -1 The characteristic peak at .

[0107] For example, before the passivation structure is annealed, the peak position of the Raman characteristic peak of the second doped semiconductor layer 500 is 519.19 cm -1 At , the half-peak width of the Raman characteristic peak of the second doped semiconductor layer 500 is 16.62 cm -1 After the passivation structure is annealed, the peak position of the Raman characteristic peak of the second doped semiconductor layer 500 is 516.17cm -1 At , the half-peak width of the Raman characteristic peak of the second doped semiconductor layer 500 is 14.96 cm -1 ( Figure 7 In the embodiment, before the passivation structure is annealed, the Raman spectrum of the second doped semiconductor layer 500 is indicated as L3, and after the passivation structure is annealed, the Raman spectrum of the second doped semiconductor layer 500 is indicated as L4) 。

[0108] It can be seen that after the passivation structure is annealed, the half-peak width of the Raman characteristic peak of the second doped semiconductor layer 500 is reduced, the Raman characteristic peak of the second doped semiconductor layer 500 is red-shifted, and the peak position of the Raman characteristic peak of the second doped semiconductor layer 500 is less than 520.7 cm-1 This indicates that the crystallization performance of the second doped semiconductor layer 500 can be improved by annealing the passivation structure, and the peak position of the Raman characteristic peak of the second doped semiconductor layer 500 is smaller than 520.7 cm -1 The higher the crystallinity of the second doped semiconductor layer 500, the higher the tensile stress of the second doped semiconductor layer 500. Similarly, by annealing the passivation structure, the crystallinity and tensile stress of the first doped semiconductor layer 300 can also be improved. Under the action of the tensile stress, the second tunneling layer 400 can be in a discontinuous state, which is beneficial to promote the longitudinal transmission of carriers in the first doped semiconductor layer 300 and the second doped semiconductor layer 500, and is more beneficial to improve the contact performance of the solar cell.

[0109] In some embodiments, the contact resistivity between the second doped semiconductor layer 500 and the electrode 700 is 0.5 mΩ·cm 2 -5mΩ·cm 2 .

[0110] In this embodiment, the filling factor of the solar cell is 86.20%, and the conversion efficiency of the solar cell is 26.54%.

[0111] Table 1 Electrical performance parameters of solar cells before and after annealing

[0112]

[0113]

[0114] As can be seen from Table 1 above, after the passivation structure is annealed, the fill factor (FF) and the conversion efficiency (Eta) of the solar cell are significantly improved, and the contact resistivity (ρ c ) and the series resistance are significantly reduced, which indicates that after the passivation structure is annealed, the contact performance between the stacked doped polysilicon and the electrode 700 is greatly improved, and under the condition of maintaining the open circuit voltage (Voc), the fill factor (FF) and conversion efficiency (Eta) of the solar cell can be greatly improved.

[0115] An embodiment of the present application further provides a photovoltaic assembly, including a battery string, an encapsulation layer and a cover plate, wherein the battery string is formed by connecting the solar cells of any of the above embodiments, the encapsulation layer is used to cover the surface of the battery string, and the cover plate is used to cover the surface of the encapsulation layer away from the battery string. The solar cells are electrically connected in the form of a whole piece or multiple pieces to form a plurality of battery strings, and the plurality of battery strings are electrically connected in series and / or in parallel.

[0116] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a solar cell, characterized in that: The method for preparing the solar cell comprises: Providing a substrate, wherein the substrate has a first surface and a second surface disposed opposite to each other along a thickness direction perpendicular to the substrate, and defining at least one of the first surface and the second surface as a target surface; A first tunneling layer, a first doped semiconductor layer, a second tunneling layer and a second doped semiconductor layer are stacked on the target surface of the substrate in a direction away from the substrate to obtain a passivation structure; a plurality of holes are provided on the second tunneling layer; Annealing the passivation structure to increase the size of the hole in a direction parallel to a reference plane; The reference plane is a plane perpendicular to the thickness direction of the substrate.

2. The method for preparing a solar cell according to claim 1, characterized in that: The process parameters of the annealing treatment include: annealing time is 10min-60min, and annealing temperature is 400℃-900℃.

3. The method for preparing a solar cell according to claim 1, characterized in that: The annealing treatment of the passivation structure specifically includes: annealing the passivation structure in an oxygen-free atmosphere; Wherein, the oxygen-free gas includes an inert gas or hydrogen.

4. The method for preparing a solar cell according to claim 1, characterized in that: After the passivation structure is annealed, at least a portion of the holes penetrate the second tunneling layer.

5. The method for preparing a solar cell according to any one of claims 1 to 4, characterized in that: After the passivation structure is annealed, the sum of the orthographic projection areas of the plurality of holes in the preset region of the reference plane is S1, the area of ​​the preset region of the reference plane is S2, S1=a*S2, 10%≤a≤80%.

6. The method for preparing a solar cell according to claim 5, characterized in that: 15％≤a≤60％。 7. The method for preparing a solar cell according to any one of claims 1 to 4, characterized in that: Before the passivation structure is annealed, the sum of the orthographic projection areas of the plurality of holes in the preset region of the reference plane is S3, the area of ​​the preset region of the reference plane is S2, S3=b*S2, 0%≤b<15%.

8. A solar cell, characterized in that: include: A substrate, wherein the substrate has a first surface and a second surface disposed opposite to each other along a thickness direction perpendicular to the substrate, and at least one of the first surface and the second surface is defined as a target surface; A first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer are stacked on the target surface of the substrate in a direction away from the substrate; an anti-reflection layer, disposed on a surface of the second doped semiconductor layer away from the second tunneling layer; and A plurality of electrodes are disposed on the anti-reflection layer, and the electrodes are electrically connected to the second doped semiconductor layer; The first tunneling layer is a continuous tunneling layer, and the second tunneling layer is a discontinuous tunneling layer.

9. The solar cell according to claim 8, characterized in that The second tunneling layer is provided with a plurality of holes, the sum of the orthographic projection areas of the plurality of holes in a preset region of the reference plane is S1, the area of ​​the preset region of the reference plane is S2, S1=a*S2, 10%≤a≤80%.

10. The solar cell according to claim 9, characterized in that: At least a portion of the holes are disposed through the second tunneling layer.

11. The solar cell according to claim 8, characterized in that The thickness of the first tunneling layer is smaller than the thickness of the second tunneling layer.

12. The solar cell according to claim 8, characterized in that: The thickness of the second tunneling layer is 0.2 nm-5 nm.

13. The solar cell according to claim 8, characterized in that The thickness of the first tunneling layer is 0.5 nm-5 nm.

14. The solar cell according to claim 8, characterized in that The contact resistivity between the second doped semiconductor layer and the electrode is 0.5 mΩ·cm 2 -5mΩ·cm 2 .

15. The solar cell according to claim 8, characterized in that The material of the second tunneling layer includes silicon oxide, and the molar mass percentage of oxygen in the second tunneling layer is 5%-45%.

16. The solar cell according to claim 8, characterized in that The half-peak width of the Raman characteristic peak of the second doped semiconductor layer is 3 cm -1 -20cm -1 ; The Raman characteristic peak of the second doped semiconductor layer is 510 cm -1 -520cm -1 The characteristic peak at .

17. A photovoltaic module, characterized in that: include: A battery string, wherein the battery string is formed by connecting a plurality of solar cells according to any one of claims 8 to 16; An encapsulation layer, the encapsulation layer is used to cover the surface of the battery string; A cover plate is used to cover a surface of the packaging layer away from the battery string.

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