Security data synchronization method and device based on WIFI

Abstract

The invention discloses a security data synchronization method and device based on WIFI, and the method comprises the steps: carrying out the business data intercommunication with each device in a plurality of devices at a CPU side of a target device through a multi-thread mechanism, enabling the target device to be connected with the plurality of devices through a switch, enabling the target device and the plurality of devices to be multi-business and high-concurrency devices, and enabling the target device to be connected with the plurality of devices through a switch; the target device receives service data sent by the opposite terminal device and stores the service data in a CPU cache to wait for service processing; when the CPU side calls the FPGA to carry out service processing, determining a service processing queue for the CPU to send data to the FPGA according to the current processing condition of the FPGA; according to different service processing conditions in the FPGA, the number of service cores and the processing performance of a single service core, the size of the multiple sliding windows is automatically adjusted on the CPU side; and deploying a plurality of service cores for each service function in the FPGA according to the concurrent demand of the target equipment in the system and the processing capacity of a single service core in the FPGA.

Description

Technical Field

[0001] The present application relates to the technical field of data synchronization, and more specifically, to a WIFI-based secure data synchronization method and device. Background Art

[0002] For devices with multiple different business functions and concurrent requirements, they usually need to be directly or indirectly connected to multiple devices with different functions through a communication bearer network in the system, and need to communicate with multiple other devices at the same time during the business process. According to the characteristics of the system, the device itself needs to have multiple different business functions at the same time, that is, technically, the central processing unit (CPU) and the field programmable gate array (FPGA) need to cooperate and schedule with each other to achieve the high-speed parallel processing capability of the device.

[0003] At present, for devices with CPU and FPGA architectures, the following methods are generally used when performing concurrent business operations: First, a blocking method is used. After the CPU sends a packet of data to the FPGA, it waits for the FPGA to respond. After the CPU receives the FPGA response, it will send the next packet of data. Although this method can effectively ensure that each packet of data can be stably and reliably operated, it cannot give full play to the high-speed processing characteristics of the architecture.

[0004] The second is to use a non-blocking method, based on the FPGA service processing performance, to calculate the FPGA processing delay for different services, and use the FPGA maximum processing delay as the threshold value to control the CPU to send data at an interval greater than the threshold value. This method can improve the data processing capability, but when the processing delays between different services differ greatly, the CPU must send data at the maximum delay interval, which cannot give full play to the FPGA's high-speed computing capabilities. Summary of the invention

[0005] In response to at least one defect or improvement need in the prior art, the present invention provides a WIFI-based secure data synchronization method and device, which solves the problem that the device cannot meet high performance and multi-concurrency requirements, improves the high-concurrency processing capability when processing a large number of different services at the same time, and ensures that the device meets the usage requirements of high reliability, high concurrency, and low latency.

[0006] To achieve the above-mentioned purpose, according to the first aspect of the present invention, a WIFI-based secure data synchronization method is provided, the method comprising: on the CPU side of the target device, business data intercommunication with each of the multiple devices is performed through a multi-threading mechanism, wherein the target device is connected to the multiple devices through a switch, the target device and the multiple devices are multi-service, high-concurrency devices, and the target device receives the business data sent by the opposite device and stores it in the CPU cache waiting for business processing; when the CPU side calls the FPGA for business processing, the business processing queue for the CPU to send data to the FPGA is determined according to the current processing status of the FPGA; according to different business processing situations inside the FPGA, according to the number of business cores and the processing performance of a single business core, the size of multiple sliding windows is automatically adjusted on the CPU side; according to the concurrency requirements of the target device in the system and the processing capacity of a single business core in the FPGA, multiple business cores are deployed in the FPGA for each business function.

[0007] In an exemplary embodiment, the target device's CPU side uses a multi-threading mechanism to communicate business data with each of the multiple devices separately, including: when the target device communicates with the multiple devices and receives a data packet composed of a specified protocol, the CPU of the target device creates multiple threads respectively, wherein each of the multiple threads independently records the interaction information between the target device and the multiple devices; when a target thread among the multiple threads fails to receive business data from the opposite device within a target time limit, the target thread is closed and the corresponding memory resources in the CPU are released.

[0008] In an exemplary embodiment, when the FPGA is called on the CPU side for business processing, the business processing queue for sending data from the CPU to the FPGA is determined based on the current processing status of the FPGA, including: when multiple threads of the target device receive the business data at the same time, the CPU dynamically adjusts the order of sending the business data to the FPGA based on the current operating status of the FPGA and the performance of processing different businesses.

[0009] In an exemplary embodiment, the automatic adjustment of the size of multiple sliding windows on the CPU side according to the different business processing conditions inside the FPGA, the number of business cores and the processing performance of a single business core includes: the CPU uses a non-blocking method to call the FPGA to perform multiple business processing, and uses a window sliding method to continuously send the business data to be processed to the FPGA; according to the operation conditions of different businesses currently being carried out in the FPGA, the window size for each business is dynamically adjusted according to the processing conditions of each different business under a large window.

[0010] In an exemplary embodiment, after the CPU uses a non-blocking method to call the FPGA to perform multiple business processes and uses a window sliding method to continuously send the business data to be processed to the FPGA, the method also includes: when the CPU calls the FPGA, the window sliding method is used to call the business data, and the CPU sends the business data to the FPGA according to the window size; when the CPU receives the response data from the FPGA, the window is continuously slid in response to the data response from the FPGA, and the next packet of business data to be processed in the business processing queue is sent to the FPGA.

[0011] In an exemplary embodiment, after sending the next packet of to-be-processed business data in the business processing queue to the FPGA, the method further includes: when the target device communicates with the multiple devices, the CPU uses a window sliding method to call the FPGA function for each of the businesses, wherein the number of business cores deployed in the FPGA corresponds to each business, and the number of windows maintained by each business corresponds to the processing performance of a single business core of each business.

[0012] According to the second aspect of the present invention, there is also provided a WIFI-based secure data synchronization device, comprising: a communication unit, for communicating business data with each of the multiple devices through a multi-threading mechanism on the CPU side of the target device, wherein the target device is connected to the multiple devices through a switch, the target device and the multiple devices are multi-service, high-concurrency devices, and the target device receives the business data sent by the opposite device and stores it in the CPU cache waiting for business processing; a determination unit, for determining the business processing queue for sending data from the CPU to the FPGA according to the current processing status of the FPGA when the CPU side calls the FPGA for business processing; an adjustment unit, for automatically adjusting the size of multiple sliding windows on the CPU side according to different business processing situations inside the FPGA, according to the number of business cores and the processing performance of a single business core; a deployment unit, for deploying multiple business cores for each business function in the FPGA according to the concurrency requirements of the target device in the system and the processing capacity of a single business core in the FPGA.

[0013] According to a third aspect of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the above-mentioned WIFI-based secure data synchronization method when running.

[0014] According to a fourth aspect of the present invention, there is also provided an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the above-mentioned WIFI-based secure data synchronization method through the computer program.

[0015] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0016] The present invention provides a secure data synchronization method based on WIFI. Based on the "CPU+FPGA" architecture, the method fully reflects the high concurrent processing capability of the device when processing a large number of different services at the same time, and ensures that the device meets the use requirements of high reliability, high concurrency and low latency by using multiple technical means such as CPU multi-threading mechanism, service queue management and control mechanism, FPGA multi-service core parallel operation mechanism, and FPGA scheduling mechanism based on multiple window sliding method. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A flowchart of an optional WIFI-based secure data synchronization method provided in an embodiment of the present application;

[0019] Figure 2 An optional system deployment diagram provided for an embodiment of the present application;

[0020] Figure 3 An optional multi-threading and data transmission control schematic diagram provided for an embodiment of the present application;

[0021] Figure 4 An optional hardware logic structure design schematic diagram provided for an embodiment of the present application;

[0022] Figure 5 A schematic diagram of an optional calling mechanism of a multiple window sliding method provided in an embodiment of the present application;

[0023] Figure 6 A schematic diagram of another optional calling mechanism of the multiple window sliding method provided in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of another optional calling mechanism of the multiple window sliding method provided in an embodiment of the present application;

[0025] Figure 8 A schematic diagram of the structure of an optional WIFI-based secure data synchronization device provided in an embodiment of the present application;

[0026] Fig. 9 A schematic diagram of the structure of an optional electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0029] According to one aspect of the embodiments of the present application, a secure data synchronization method based on WIFI is provided. Figure 1 The present invention describes a secure data synchronization method based on WIFI provided in an embodiment of the present application.

[0030] Figure 1 is a flow chart of an optional WIFI-based secure data synchronization method provided in an embodiment of the present application, such as Figure 1 As shown, the process of the method may include the following steps:

[0031] S102, the target device CPU communicates service data with each of the multiple devices through a multi-thread mechanism, wherein the target device is connected to the multiple devices through a switch, and the target device and the multiple devices are multi-service, high-concurrency devices. The target device receives service data sent by the opposite device and stores it in the CPU cache to wait for service processing;

[0032] S104, when the CPU side calls the FPGA to perform service processing, the service processing queue for sending data from the CPU to the FPGA is determined according to the current processing status of the FPGA;

[0033] S106, automatically adjusting the size of the multiple sliding windows on the CPU side according to different service processing conditions inside the FPGA, the number of service cores and the processing performance of a single service core;

[0034] S108 , deploying multiple service cores for each service function in the FPGA according to the concurrency requirements of the target device in the system and the processing capability of a single service core in the FPGA.

[0035] The embodiment of the present application provides a secure data synchronization method based on WIFI, which can realize data processing of devices with different services and high concurrency requirements based on the CPU+FPGA architecture, and can be applied to all devices using the architecture and with high concurrency processing requirements. The CPU+FPGA architecture is adopted, in which the CPU is responsible for scheduling the use of the FPGA, and the FPGA is responsible for business processing of the data sent by the CPU. In order to ensure the actual use requirements of the device in high concurrency, short latency, and high-performance usage scenarios, the high-performance concurrent processing capability of the device can be improved by using a multiple sliding window method. The device with the CPU+FPGA architecture schedules the FPGA through the CPU and uses the parallel processing capability of the FPGA to process large amounts of data. For example, in a wireless sensor network, a distributed time synchronization and data synchronization solution can improve the synchronization accuracy and convergence speed of the network. This architecture can ensure that data can be processed and synchronized quickly and securely in high-concurrency scenarios.

[0036] like Figure 2 As shown, when a device with multiple different business functions and concurrent requirements works normally in the system, it needs to communicate with multiple other devices online at any time, or respond to business requests from multiple devices at any time, so it is particularly important to design a highly reliable concurrent device for the device. Optionally, the business processing flow can be managed on the CPU side, multiple business cores can be deployed on the FPGA side for parallel computing, and a multiple window sliding method can be used for the interaction between the CPU and FPGA to ensure the computing power of the device when performing a large number of different business parallel processing.

[0037] Exemplarily, the target device (multi-service, high-concurrency device) can be directly connected to other devices (device 1, device 2...device M) through a switch. When multiple devices are connected, the concurrent use requirements of the devices can be met through software and hardware design, and interconnection with different business functions of different devices can be achieved. The hardware structure of the device adopts a CPU+FPGA design architecture, in which the CPU is mainly used to realize online communication with other devices in the system through an IP network, and can actively initiate services to other devices or respond to service requests initiated by other devices; the FPGA mainly realizes functions such as high-speed computing of specific different services.

[0038] See also Figure 3 and Figure 4 As shown, exemplarily, the target device can adopt the hardware architecture of CPU+FPGA, with the CPU as the main control chip responsible for communicating with external devices, and the FPGA as the computing chip responsible for high-speed computing of the business data sent by the CPU. In order to ensure the high concurrency capability of this device, a multi-threading mechanism is adopted on the CPU side, and different threads independently maintain the interaction process with different external devices; a data control mechanism is adopted on the CPU side, and when multiple threads receive business data at the same time, the order in which different business data packets are sent to the FPGA is adjusted; in terms of CPU calling FPGA, a multi-window sliding method is adopted to maintain different sliding windows for different businesses, effectively improving the calling efficiency of FPGA; a multi-business core mechanism is adopted on the FPGA side to perform high-speed computing of multiple different businesses at the same time.

[0039] Through the above steps S102 to S108, the CPU side of the target device communicates with the business data of each device in the multiple devices through a multi-threading mechanism, wherein the target device is connected to the multiple devices through a switch, and the target device and the multiple devices are multi-service, high-concurrency devices. The target device receives the business data sent by the opposite device and stores it in the CPU cache waiting for business processing; when the CPU side calls the FPGA for business processing, the business processing queue for the CPU to send data to the FPGA is determined according to the current processing status of the FPGA; according to different business processing situations inside the FPGA, the size of multiple sliding windows is automatically adjusted on the CPU side according to the number of business cores and the processing performance of a single business core; according to the concurrency requirements of the target device in the system and the processing capacity of a single business core in the FPGA, multiple business cores are deployed in the FPGA for each business function, which solves the problem that the device cannot meet the high-performance and multi-concurrency requirements, improves the high-concurrency processing capability when processing a large number of different businesses at the same time, and ensures that the device meets the usage requirements of high reliability, high concurrency and low latency.

[0040] In an exemplary embodiment, performing service data intercommunication with each of the multiple devices through a multi-threading mechanism on the CPU side of the target device includes:

[0041] S11, when the target device communicates with multiple devices and receives a data packet composed according to a specified protocol, the CPU of the target device creates multiple threads respectively, wherein each of the multiple threads independently records the interaction information between the target device and the multiple devices;

[0042] S12, when a target thread among the multiple threads fails to receive service data from the opposite device within a target time limit, closing the target thread and releasing corresponding memory resources in the CPU.

[0043] In the present application embodiment, combined Figure 3 and Figure 4 As shown, a multi-thread mechanism (e.g., thread 1, thread 2, ..., thread M) can be used on the CPU side. Optionally, when the target device communicates with other external devices through an IP network or other means, the CPU will always monitor the TCP / UDP data of the corresponding port. When a data packet composed of a specified protocol is received, the CPU will create a new thread according to the intercommunication object, and use a multi-thread mechanism so that each thread can independently record the interaction information with different devices; if a thread has not received data from the opposite device for a long time, the thread will be closed to release CPU memory resources.

[0044] In the multi-threaded design on the CPU side, multiple threads can be created by inheriting the Thread method. Each thread independently maintains the interaction information with different devices. Multiple threads process multiple business information at the same time, and the CPU can manage the threads throughout their life cycle.

[0045] In an exemplary embodiment, when the CPU side calls the FPGA to perform service processing, determining the service processing queue for sending data from the CPU to the FPGA according to the current processing status of the FPGA includes:

[0046] S21, when multiple threads of the target device receive business data at the same time, the CPU dynamically adjusts the order of sending the business data to the FPGA based on the current operation status of the FPGA and the performance of processing different businesses.

[0047] In the embodiment of the present application, the business data control mechanism on the CPU side is further explained. Specifically, the CPU side can adopt a control mechanism for the business data that needs to be processed by this device. When multiple threads receive business data at the same time, the CPU will fully judge the FPGA's current processing capabilities of different businesses such as business function 1 and business function 2 based on the current operation status of the FPGA and the performance of processing different businesses, and dynamically adjust the order of sending business data to the FPGA.

[0048] In the CPU-side business data control design, the CPU can create a data sending queue, record the business information being processed by the FPGA and the business information to be processed, and control the sending order of different business data packets in the queue according to the number of business cores and business processing performance in the FPGA, so as to give full play to the computing power of the equipment while ensuring system performance.

[0049] In an exemplary embodiment, according to different service processing situations inside the FPGA, based on the number of service cores and the processing performance of a single service core, automatically adjusting the size of multiple sliding windows on the CPU side includes:

[0050] S31, the CPU uses a non-blocking method to call the FPGA to process multiple services, and uses a window sliding method to continuously send the service data to be processed to the FPGA;

[0051] S32, according to the running conditions of different services currently being carried out in the FPGA, dynamically adjust the window size for each service according to the processing conditions of each different service under the large window.

[0052] In the embodiment of the present application, a calling mechanism of a multiple window sliding method can be adopted. For example, when the CPU side calls the FPGA to process multiple services, a non-blocking method can be used to call it. According to the computing power of the FPGA, a large amount of business data to be processed is continuously sent to the FPGA using the window sliding method, making full use of the high-speed computing characteristics of the FPGA to improve the multi-service parallel processing capability of the device. At the same time, according to the operation status of different services currently being carried out in the FPGA, the window size for each service is dynamically adjusted again according to the processing status of each different service under a large window.

[0053] In other words, the CPU dynamically adjusts the size of the total window between the CPU and FPGA based on the business type in the data queue and the processing capability of the FPGA, and then dynamically adjusts the number of windows for each business based on the FPGA's ability to simultaneously process the same business, giving full play to the FPGA's high-speed parallel computing characteristics.

[0054] In an exemplary embodiment, after the CPU uses a non-blocking method to call the FPGA to perform multiple business processes and uses a window sliding method to continuously send the business data to be processed to the FPGA, the method further includes:

[0055] S41, when the CPU calls the FPGA, the window sliding method is used to call the business data, and the CPU sends the business data to the FPGA according to the window size;

[0056] S42, when the CPU receives the response data from the FPGA, it continuously slides the window in response to the data response from the FPGA, and sends the next packet of service data to be processed in the service processing queue to the FPGA.

[0057] In the present application embodiment, Figure 5 As shown, when the CPU calls the FPGA, it uses the window sliding method to call data. The CPU can send data to the FPGA according to the window size. As the FPGA responds to data, the window continues to slide, so that the device can give full play to the processing power of the FPGA when performing multi-service processing.

[0058] For example, when the CPU sends data to the FPGA, the window size N can be set to 10. When the device is in high-concurrency processing of multiple services, the CPU controls the number of services being processed inside the FPGA. When the CPU receives the response data from the FPGA, it immediately sends the next packet of service data to be processed in the service processing queue to the FPGA, enabling the device to process service data efficiently.

[0059] In an exemplary embodiment, after sending the next packet of service data to be processed in the service processing queue to the FPGA, the method further includes:

[0060] S51, when the target device communicates with multiple devices, the CPU uses the window sliding method to call the FPGA function for each service, wherein the number of service cores deployed in the FPGA corresponds to each service, and the number of windows maintained by each service corresponds to the processing performance of a single service core of each service.

[0061] In the present application embodiment, combined Figure 6 and Figure 7 As shown in the figure, when the target device communicates with multiple external devices with different business functions, the CPU will use the window sliding method to call the FPGA function for each independent business, set the current window to N, and the windows of the four different businesses are N1, N2, N3, and N4 respectively. For each different business, the number of business cores deployed in the FPGA is different, and the processing performance of a single business core of different businesses is different, so that under a large window, the number of windows maintained for each different business is different. When a business is processed, such as business 2, and the CPU-side data processing queue also does not have this business, the CPU can dynamically adjust the window N to N', and adjust the windows of business 1, business 3, and business 4 respectively.

[0062] The CPU and FPGA can dynamically adjust the size of the window N' between the CPU and FPGA according to the performance and latency of all the services currently being processed. At the same time, in view of the performance and latency of processing different services, under a large window N', the window sizes of N1', N2', and N3' can be dynamically adjusted according to the different services in the CPU queue to be processed and the deployment of the service core in the FPGA, giving full play to the high-speed computing characteristics of the FPGA and effectively improving the processing ability of the device to communicate with multiple other devices for different services at the same time.

[0063] Furthermore, for the use requirements of high concurrency and multi-service intercommunication of equipment, if a single service core is used for service processing, when facing concurrent services, the responsiveness of the entire equipment will be limited by the processing performance of a single service core, affecting the equipment's ability to handle multiple services simultaneously. By integrating multiple service cores in the FPGA, the FPGA's ability to process multiple different services in parallel can be enhanced, effectively solving the problem that the processing capacity and latency of a single service core do not meet system requirements, and improving the equipment's concurrency capability.

[0064] Specifically, the CPU can independently maintain the intercommunication with each different device through multi-threading technology, timely receive the service data sent by the opposite device, and store it in the CPU cache in time, waiting for subsequent service processing, optimize the service processing queue of the CPU to send data to the FPGA, and automatically adjust the order of sending different service data according to the current processing status of the FPGA and the optimal processing capability of the device. Then, according to the different service processing conditions inside the FPGA, the size of multiple sliding windows can be automatically adjusted on the CPU side according to the number of service cores and the processing performance of a single service core, giving full play to the characteristics of FPGA high-speed parallel computing and enhancing the efficiency of CPU scheduling FPGA. According to the concurrent requirements of the device in the system and the processing capacity of a single service core in the FPGA, multiple service cores are deployed in the FPGA for each service function, greatly improving the parallel processing capability of the device, and realizing the reliable processing of multiple services and high concurrency of the device in the system.

[0065] Through this embodiment, multiple different service cores are deployed inside the FPGA to support the multi-service functions of the device; at the same time, multiple sets of the same service cores are deployed according to the service type to improve the parallel computing capability of the device.

[0066] According to another aspect of the embodiments of the present application, a synchronization device for implementing the above-mentioned WIFI-based secure data synchronization method is also provided. Figure 8 is a schematic structural diagram of an optional WIFI-based secure data synchronization device according to an embodiment of the present application, such as Figure 8 As shown, the device may include:

[0067] The communication unit 802 is used to communicate business data with each of the multiple devices through a multi-threading mechanism on the CPU side of the target device, wherein the target device is connected to the multiple devices through a switch, the target device and the multiple devices are multi-service, high-concurrency devices, and the target device receives the business data sent by the opposite device and stores it in the CPU cache to wait for business processing;

[0068] A determining unit 804 is used to determine a service processing queue for sending data from the CPU to the FPGA according to a current processing status of the FPGA when the CPU side calls the FPGA to perform service processing;

[0069] An adjusting unit 806, configured to automatically adjust the size of the multiple sliding windows on the CPU side according to different service processing conditions inside the FPGA, the number of service cores and the processing performance of a single service core;

[0070] The deployment unit 808 is used to deploy multiple service cores for each service function in the FPGA according to the concurrency requirements of the target device in the system and the processing capability of a single service core in the FPGA.

[0071] It should be noted that the communication unit 802 in this embodiment can be used to execute the above step S102, the determination unit 804 in this embodiment can be used to execute the above step S104, the adjustment unit 806 in this embodiment can be used to execute the above step S106, and the deployment unit 808 in this embodiment can be used to execute the above step S108.

[0072] Through the above modules, the CPU side of the target device communicates with the business data of each device in the multiple devices through a multi-threaded mechanism, wherein the target device is connected to the multiple devices through a switch, and the target device and the multiple devices are multi-service, high-concurrency devices. The target device receives the business data sent by the opposite device and stores it in the CPU cache waiting for business processing; when the CPU side calls the FPGA for business processing, the business processing queue for the CPU to send data to the FPGA is determined according to the current processing status of the FPGA; according to the different business processing situations inside the FPGA, the size of the multiple sliding windows is automatically adjusted on the CPU side according to the number of business cores and the processing performance of a single business core; according to the concurrency requirements of the target device in the system and the processing capacity of a single business core in the FPGA, multiple business cores are deployed in the FPGA for each business function, which solves the problem that the device cannot meet the high-performance and multi-concurrency requirements, improves the high-concurrency processing capability when processing a large number of different businesses at the same time, and ensures that the device meets the usage requirements of high reliability, high concurrency and low latency.

[0073] In an exemplary embodiment, the communication unit comprises:

[0074] a creation module, configured to cause the CPU of the target device to create a plurality of threads respectively when the target device communicates with the plurality of devices and receives a data packet composed of a prescribed protocol, wherein each of the plurality of threads independently records interaction information between the target device and the plurality of devices;

[0075] The release module is used to close the target thread and release the corresponding memory resources in the CPU when the target thread among the multiple threads fails to receive the service data of the opposite device within the target time limit.

[0076] In an exemplary embodiment, the determining unit includes:

[0077] The first adjustment module is used for dynamically adjusting the order of sending the service data to the FPGA by the CPU in combination with the current operation status of the FPGA and the performance of processing different services when multiple threads of the target device receive the service data at the same time.

[0078] In an exemplary embodiment, the adjusting unit comprises:

[0079] A sending module, used for the CPU to call the FPGA in a non-blocking manner to perform multiple business processing, and to continuously send the business data to be processed to the FPGA using a window sliding method;

[0080] The second adjustment module is used to dynamically adjust the window size for each service according to the running conditions of different services currently being carried out in the FPGA and the processing conditions of each different service under a large window.

[0081] In an exemplary embodiment, the apparatus further comprises:

[0082] A first calling unit, configured to use a window sliding method to call the service data when the CPU calls the FPGA, and the CPU sends the service data to the FPGA according to the window size;

[0083] The response unit is used for continuously sliding the window in response to the data response of the FPGA when the CPU receives the response data of the FPGA, and sending the next packet of business data to be processed in the business processing queue to the FPGA.

[0084] In an exemplary embodiment, the apparatus further comprises:

[0085] The second calling unit is used for the CPU to use the window sliding method to call the FPGA function for each of the services when the target device communicates with the multiple devices, wherein the number of service cores deployed in the FPGA corresponds to each service, and the number of windows maintained by each service corresponds to the processing performance of a single service core of each service.

[0086] It should be noted here that the examples and scenarios implemented by the above-mentioned modules and corresponding steps are the same, but are not limited to the contents disclosed in the above-mentioned embodiments. It should be noted that the above-mentioned modules as part of the device can run in a hardware environment and can be implemented by software or hardware, wherein the hardware environment includes a network environment.

[0087] According to another aspect of the embodiments of the present application, a storage medium is further provided. Optionally, in this embodiment, the storage medium can be used to execute the program code of any of the above-mentioned secure data synchronization methods based on WIFI in the embodiments of the present application.

[0088] Optionally, in this embodiment, the storage medium is configured to store program codes for executing the following steps:

[0089] S1, the target device CPU communicates with each of the multiple devices through a multi-thread mechanism, wherein the target device is connected to the multiple devices through a switch, and the target device and the multiple devices are multi-service, high-concurrency devices. The target device receives the service data sent by the opposite device and stores it in the CPU cache to wait for service processing;

[0090] S2, when the CPU side calls the FPGA to perform service processing, the service processing queue for sending data from the CPU to the FPGA is determined according to the current processing status of the FPGA;

[0091] S3, according to different business processing situations inside the FPGA, based on the number of business cores and the processing performance of a single business core, the size of multiple sliding windows is automatically adjusted on the CPU side;

[0092] S4, deploy multiple service cores for each service function in the FPGA according to the concurrency requirements of the target device in the system and the processing capacity of a single service core in the FPGA.

[0093] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, which will not be described in detail in this embodiment.

[0094] Among them, computer-readable storage media may include, but are not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0095] According to another aspect of the embodiments of the present application, an electronic device for implementing the above-mentioned WIFI-based secure data synchronization method is also provided. The electronic device may be a server, a terminal, or a combination thereof.

[0096] Fig. 9 is a schematic diagram of the structure of an optional electronic device according to an embodiment of the present application, such as Fig. 9 As shown, it includes a processor 902, a communication interface 904, a memory 906 and a communication bus 908, wherein the processor 902, the communication interface 904, and the memory 906 communicate with each other through the communication bus 908, wherein:

[0097] Memory 906, used to store computer programs;

[0098] The processor 902 is used to implement the following steps when executing the computer program stored in the memory 906:

[0099] S1, the target device CPU communicates with each of the multiple devices through a multi-thread mechanism, wherein the target device is connected to the multiple devices through a switch, and the target device and the multiple devices are multi-service, high-concurrency devices. The target device receives the service data sent by the opposite device and stores it in the CPU cache to wait for service processing;

[0100] S2, when the CPU side calls the FPGA to perform service processing, the service processing queue for sending data from the CPU to the FPGA is determined according to the current processing status of the FPGA;

[0101] S3, according to different business processing situations inside the FPGA, based on the number of business cores and the processing performance of a single business core, the size of multiple sliding windows is automatically adjusted on the CPU side;

[0102] S4, deploy multiple service cores for each service function in the FPGA according to the concurrency requirements of the target device in the system and the processing capacity of a single service core in the FPGA.

[0103] Optionally, the communication bus may be a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 The communication interface is used for communication between the electronic device and other devices.

[0104] The memory may include RAM, or may include non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0105] As an example, the memory 906 may include, but is not limited to, the communication unit 802, the determination unit 804, the adjustment unit 806, and the deployment unit 808 in the WIFI-based secure data synchronization device. In addition, other module units in the WIFI-based secure data synchronization device may also be included but are not limited to, which will not be repeated in this example.

[0106] The above-mentioned processor can be a general-purpose processor, which can include but not be limited to: CPU (Central Processing Unit), NP (Network Processor), etc.; it can also be DSP (Digital Signal Processing), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0107] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment will not be described in detail here.

[0108] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0109] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0110] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0111] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0112] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0113] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, disk or optical disk and other media that can store program code.

[0114] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0115] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

[0116] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A secure data synchronization method based on WIFI, characterized in that: include: The target device CPU communicates with each of the multiple devices through a multi-thread mechanism, wherein the target device is connected to the multiple devices through a switch, the target device and the multiple devices are multi-service, high-concurrency devices, and the target device receives the service data sent by the opposite device and stores it in the CPU cache to wait for service processing; When the CPU side calls the FPGA to perform service processing, the service processing queue for sending data from the CPU to the FPGA is determined according to the current processing status of the FPGA; According to different business processing situations inside the FPGA, the size of multiple sliding windows is automatically adjusted on the CPU side according to the number of business cores and the processing performance of a single business core; According to the concurrency requirements of the target device in the system and the processing capability of a single service core in the FPGA, multiple service cores are deployed in the FPGA for each service function.

2. The secure data synchronization method based on WIFI as claimed in claim 1, characterized in that: The intercommunication of service data with each of the multiple devices by using a multi-thread mechanism on the CPU side of the target device comprises: When the target device communicates with the multiple devices and receives a data packet composed of a specified protocol, the CPU of the target device creates multiple threads respectively, wherein each of the multiple threads independently records the interaction information between the target device and the multiple devices; When a target thread among the multiple threads fails to receive the service data of the opposite device within a target time limit, the target thread is closed and the corresponding memory resources in the CPU are released.

3. The secure data synchronization method based on WIFI as claimed in claim 1, characterized in that: When the CPU side calls the FPGA to perform service processing, determining the service processing queue for sending data from the CPU to the FPGA according to the current processing status of the FPGA includes: When multiple threads of the target device receive the service data simultaneously, the CPU dynamically adjusts the order of sending the service data to the FPGA based on the current operation status of the FPGA and the performance of processing different services.

4. The secure data synchronization method based on WIFI as claimed in claim 1, characterized in that: The automatically adjusting the size of the multiple sliding windows on the CPU side according to different service processing conditions inside the FPGA, the number of service cores and the processing performance of a single service core, includes: The CPU uses a non-blocking method to call the FPGA to perform multiple business processing, and uses a window sliding method to continuously send the business data to be processed to the FPGA; According to the running conditions of different services currently being carried out in the FPGA, the window size for each service is dynamically adjusted according to the processing conditions of each different service under a large window.

5. The secure data synchronization method based on WIFI as claimed in claim 4, characterized in that: After the CPU uses a non-blocking method to call the FPGA to perform multiple business processes and uses a window sliding method to continuously send the business data to be processed to the FPGA, the method further includes: When the CPU calls the FPGA, the window sliding method is used to call the service data, and the CPU sends the service data to the FPGA according to the window size; When the CPU receives the response data from the FPGA, it continuously slides the window in response to the data response from the FPGA, and sends the next packet of service data to be processed in the service processing queue to the FPGA.

6. The secure data synchronization method based on WIFI as claimed in claim 5, characterized in that: After sending the next packet of to-be-processed service data in the service processing queue to the FPGA, the method further includes: When the target device communicates with the multiple devices, the CPU uses the window sliding method to call the FPGA function for each of the services, wherein the number of service cores deployed in the FPGA corresponds to each service, and the number of windows maintained by each service corresponds to the processing performance of a single service core of each service.

7. A secure data synchronization device based on WIFI, characterized in that: include: A communication unit, configured to communicate service data with each of the multiple devices through a multi-thread mechanism on the CPU side of the target device, wherein the target device is connected to the multiple devices through a switch, the target device and the multiple devices are multi-service, high-concurrency devices, and the service data received by the target device and sent by the opposite device is stored in the CPU cache to wait for service processing; A determination unit, configured to determine a service processing queue for sending data from the CPU to the FPGA according to a current processing status of the FPGA when the CPU calls the FPGA to perform service processing; An adjustment unit, configured to automatically adjust the size of the multiple sliding windows on the CPU side according to different service processing conditions inside the FPGA, the number of service cores and the processing performance of a single service core; A deployment unit is used to deploy multiple service cores for each service function in the FPGA according to the concurrency requirements of the target device in the system and the processing capacity of a single service core in the FPGA.

8. The WIFI-based secure data synchronization device according to claim 7, characterized in that: The communication unit comprises: a creation module, configured to cause the CPU of the target device to create a plurality of threads respectively when the target device communicates with the plurality of devices and receives a data packet composed of a prescribed protocol, wherein each of the plurality of threads independently records interaction information between the target device and the plurality of devices; The release module is used to close the target thread and release the corresponding memory resources in the CPU when the target thread among the multiple threads fails to receive the service data of the opposite device within the target time limit.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein the program executes the method according to any one of claims 1 to 6 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to execute the method according to any one of claims 1 to 6 through the computer program.

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