Superconducting quantum chip wiring and optimizing method

Abstract

The invention discloses an automatic wiring and optimizing method for a superconducting quantum chip, and belongs to the field of automatic design of superconducting quantum chips. According to the method, in a modeling stage, a'combined wiring template 'model under a fine-grained grid is adopted, a problem is discretized through a combined wiring template, complex geometric operation of the arc wiring problem in the solving process is avoided, and the search space of an algorithm is greatly reduced; in the legal solution search stage, a single-side wiring algorithm is adopted, a line sequence search problem is extended according to wiring result characteristics of the algorithm, a line sequence tree search framework is designed, and on the basis, the blocking relation between lines is explored, and a series of search optimization strategies are designed; an exchange winding action is adopted to meet the special wire sequence requirement of a read wire; in the wiring optimization stage, an iterative optimization wiring scheme based on space limitation is adopted, and multi-stage target optimization is performed on the overall wiring result on the basis of a legal solution, so that the wiring result meets design requirements.

Description

Technical Field

[0001] The present invention belongs to the field of automatic design of superconducting quantum chips, and more specifically, relates to a superconducting quantum chip wiring and optimization method. Background Art

[0002] In recent years, quantum computers have become one of the most popular research areas. Quantum computers are different from traditional computers and follow the laws of quantum mechanics to perform mathematical operations. Quantum computing is expected to solve some problems that are difficult for traditional computers to solve, and is of great significance in research fields such as cryptography, machine learning, and quantum measurement. At present, the design of quantum computers mainly includes design schemes based on superconducting quantum bits, light quanta, ion traps, and silicon quanta. Among them, superconducting quantum computers have strong performance and controllability, and their core units are superconducting quantum bits (Qubit). Superconducting quantum computers are one of the current mainstream types of quantum computers and have become one of the most important candidates for scalable quantum processors. In 2019, Google's 53-bit superconducting quantum computer "Platanus" achieved quantum superiority for the first time, and then the "Zu Chongzhi" developed by the team of USTC achieved quantum superiority again with 66 quantum bits. The superconducting quantum computer "Condor" released by IBM in 2023 has 1,121 quantum bits, which will increase the quantum bit scale of existing superconducting quantum computers to thousands. The number of bits in superconducting quantum chips has exploded in recent years, and it also determines the overall performance of quantum computers. In the future, general-purpose quantum computers with commercial value are expected to have a quantum bit scale of millions. The design and manufacturing process of integrating a large number of superconducting quantum bits on a quantum chip will become unprecedentedly complex. However, the current layout drawing process of superconducting quantum chips is still highly dependent on human decision-making, mainly manual drawing, supplemented by automated tools, which can no longer meet the design time and quality requirements of chips. Summary of the invention

[0003] In view of the above defects or improvement needs of the prior art, the present invention provides a superconducting quantum chip wiring and optimization method, which can shorten the design cycle of the superconducting quantum chip and improve the design quality and performance of the chip.

[0004] To achieve the above object, according to a first aspect of the present invention, a superconducting quantum chip automatic wiring and optimization method is provided, comprising:

[0005] The layout to be wired is gridded, and under preset constraints, the optimal wiring result of the superconducting quantum chip is obtained by minimizing the number of turns and the total length of the line.

[0006] The optimal wiring result includes the wiring solutions of n read lines and m control lines, each wiring solution includes multiple wiring templates and the type value of each wiring template, the actual line length, the number of grids offset between the template end point and the starting point on the x-axis and y-axis, and the number of grids at d1, d2, and d b The relative coordinates of all grids passed through the range and the starting point, and the turning method of the wiring template relative to the forward direction;

[0007] The preset constraints include:

[0008] Line geometry constraints: The line is composed of multiple wiring templates spliced ​​in sequence; the wiring templates include a straight line template, a turning template and an offset template, the turning template is a 1 / 4 arc, and the offset template is a splicing of arcs corresponding to the inner angles at the diagonal of a parallelogram, the minimum side length of a set of parallel sides of the parallelogram is r, the length of the diagonal is 2r, and the minimum radius of the arc is r; the type values ​​of the straight line template, the turning template, and the offset template are 0, 1, and 2 respectively; the type value is used to simultaneously characterize the type of the wiring template and the number of turns;

[0009] Line connectivity constraints: The endpoints of the read line and the control line correspond to a unique non-empty line solution; in a line solution, the starting point of the first wiring template is the starting point of the line, the end point of the last wiring template is the end point of the line, the starting point of the current wiring template is the end point of the previous wiring template, and the end point of the current wiring template is the starting point of the next wiring template;

[0010] Line spacing constraints: The minimum spacing between control lines or between control lines and read lines is d1, the minimum spacing between read lines is d2, and the minimum spacing between microwave transmission lines and wiring obstacles is d b .

[0011] According to a second aspect of the present invention, there is provided an electronic device, comprising: a computer-readable storage medium and a processor;

[0012] The computer-readable storage medium is used to store executable instructions;

[0013] The processor is used to read the executable instructions stored in the computer-readable storage medium and execute the method as described in the first aspect.

[0014] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to cause a processor to execute the method as described in the first aspect.

[0015] According to a fourth aspect of the present invention, there is provided a computer program product, comprising a computer program or instructions, wherein when the computer program or instructions are executed by a processor, the method according to the first aspect is implemented.

[0016] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0017] 1. The existing academic research and commercial tools cannot solve the experimental examples used in this study, especially for large-scale layouts with a large number of bits and dense lines, even with the use of tool-assisted wiring, it is very difficult. The method provided by the present invention establishes a "combined wiring template" according to the chip to solve the arc wiring and empty bridge layout problems of superconducting quantum chips. The modeling scheme of the combined wiring template is adopted to establish a "combined wiring template" model under a fine-grained grid, which highly discretizes the problem. The problem is discretized through the combined wiring template, avoiding the complex geometric operations in the solution process of the arc wiring problem, and greatly reducing the search space of the algorithm, which provides the possibility for the wiring solution and optimization of high-integration layouts.

[0018] 2. Considering the computational efficiency, as a further optimization of the present invention, a complete wiring process from legal line sequence search to wiring optimization is designed to realize the automatic wiring function of real superconducting chips; in the legal solution search stage, a one-sided wiring algorithm is adopted, and the line sequence search problem is extended according to the wiring result characteristics of the algorithm and a line sequence tree search framework is designed, which efficiently solves the wiring resource competition problem of superconducting quantum chips. The one-sided wiring algorithm has many interesting wiring characteristics, powerful search capabilities, flexible scalability and excellent wiring efficiency in the escape wiring problem; on this basis, the blocking relationship between lines is explored, and a series of search optimization strategies for two-step backtracking and blocking tables are proposed; in addition, an exchange winding action is proposed to further expand the one-sided wiring to meet the special line sequence requirements of the reading line; in the wiring optimization stage, an iterative optimization wiring scheme based on space constraints is designed, and the overall wiring results are optimized at multiple levels based on the legal solution, so that the final wiring results meet the design requirements.

[0019] 3. As a further preference of the present invention, a spatial restriction concept is introduced during wiring optimization to solve the multi-objective optimization problem in superconducting quantum chip wiring. When designing the exchange winding action and the wiring iterative optimization algorithm, the algorithm first marks the space near the legal solution of one or more lines as a local search area, and the new line is routed within the limited area. This method allows the new line to simply inherit the direction characteristics of the previous line, while limiting the scale of the search space, making it possible to use complex and inefficient wiring algorithms. Spatial restriction not only guarantees the search efficiency of iterative wiring optimization, but is also a prerequisite for the implementation of winding actions. In wiring problems with complex wiring rules that need to consider the direction relationship between multiple lines, the spatially restricted wiring algorithm design concept has high flexibility and controllability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of each wiring template provided by an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of a single-side wiring effect provided by an embodiment of the present invention, Figure 2 (a) to (d) are schematic diagrams of the wiring sequence of A, B, the wiring sequence of C, A, B, the wiring sequence of A, C, B, and the wiring sequence of C, B, A, respectively;

[0022] Figure 3 A schematic diagram of line sequence search under two-step backtracking provided by an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of the switching winding action provided by an embodiment of the present invention, Figure 4 (a) to (d) are schematic diagrams of single-sided wiring in the order of B and C, marking the space of lines C and B, single-sided wiring of space marking for read line B, and single-sided wiring for control line C;

[0024] Figure 5 A schematic diagram of a spatial iterative routing optimization process provided by an embodiment of the present invention, Figure 5 (a) to (d) are schematic diagrams of the first, second, and third wiring iterations and the optimal wiring result, respectively. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] The superconducting quantum chip layout design process, also known as the physical design stage of the chip, first needs to place a series of core components such as bits and couplers according to the logic design of the chip. After that, set up microwave transmission lines to connect quantum bits to external pins, and finally complete other design requirements such as solder joints and hole placement. The designed layout must also undergo physical rule verification and post-simulation verification to ensure that the design meets the constraints and meets the requirements. Layouts that do not meet the design requirements will be fed back to the corresponding design process to restart the design and verification. As the scale of chips grows, the design process becomes more and more complex, and the difficulty and time consumption of each design link will increase significantly. At present, the design stage of a large-scale layout in one iteration may take several days. In addition, the effect of manually drawn layouts is also somewhat uncontrollable. It is difficult to verify the design effect during the design process, and it is easy to make mistakes, which in turn increases the number of design iterations and causes a lot of time costs.

[0027] In the layout design stage, automatic wiring is the most difficult, time-consuming and also one of the most important links. Wiring is to plan the specific microwave transmission lines from the reading cavity and control cavity under the quantum bit to the outside of the chip. Each quantum bit generally has a corresponding reading line and control line, so the number of lines is positively correlated with the number of quantum bits. In addition to the increase in design time caused by the number of lines, the superconducting quantum computers currently designed are noisy quantum computers, and their performance is not as stable as the digital circuits used in traditional computers. The core part of the superconducting quantum computer uses microwave transmission lines to transmit signals. The noise and crosstalk generated during the transmission process directly affect the reliability and performance of the calculation. How to design the wiring scheme of the microwave transmission lines in the layout so that the signal can achieve a balance between dissipation and noise is a major challenge.

[0028] The bottleneck of quantum computers at this stage is not only limited to breakthroughs in physical theory, but also tests the design level and manufacturing process level of quantum chips. The traditional quantum chip layout wiring process relies on a lot of manpower, and it is difficult to meet the development needs of superconducting quantum computers in terms of time cost, design quality and reliability. The layout automation wiring capability in the quantum electronic design automation (Q-EDA) design tool is of vital importance to the development of superconducting quantum chips. Efficient automated wiring can not only greatly shorten the design cycle of superconducting quantum chips, but also improve the design quality and performance of chips. It is an indispensable design tool for the design and development of superconducting quantum chips in the future.

[0029] Facing the problem of wiring advanced, highly integrated, large-scale superconducting quantum chips, traditional physical design methodology is still difficult to adapt to its physical design requirements. The main problems are as follows:

[0030] 1) Due to the large differences in design requirements in different scenarios in circuit layout design, the algorithm designs of these studies are often highly targeted, and it is difficult to find a unified solution to solve all wiring problems. Superconducting quantum chips use coplanar waveguide circuits, and to date, there has been no automatic wiring research targeting the characteristics of highly integrated superconducting quantum chips. The biggest difference from conventional circuits is that it uses coplanar waveguides to transmit high-frequency microwave signals. When microwave transmission lines need to turn, arc turns must be used to ensure signal stability and reduce crosstalk. This is also the fundamental difference and difficulty between the automatic wiring problem of superconducting quantum chips and other automatic wiring research.

[0031] 2) The current status of the development of the wiring function of the Q-EDA tools that have been released is mainly based on the expansion of the traditional circuit automatic wiring algorithm and layout tools. It has taken shape, but it is not yet mature. Its algorithm design is less targeted to the arc line characteristics of superconducting quantum chips, and the solutions provided by different companies have certain differences and are not directly compatible with each other. The tools have great restrictions on the design process and parameters, and the functions are very limited.

[0032] 3) Existing Q-EDA tools that support routing have limited routing capabilities, cannot automatically route multiple routes at the same time, and cannot automatically route chip layouts in densely wired scenarios. Public Q-EDA tools have lowered the design threshold for superconducting quantum chip layouts to a certain extent, but are limited by their algorithm design or corporate commercial considerations and cannot currently meet the design requirements of the most cutting-edge chips.

[0033] Based on this, an embodiment of the present invention provides a superconducting quantum chip automatic wiring optimization method, comprising:

[0034] The layout to be wired is gridded, and under preset constraints, the optimal wiring result of the superconducting quantum chip is obtained by minimizing the number of turns and the total length of the line.

[0035] The optimal wiring result includes the wiring solutions of n read lines and m control lines, each wiring solution includes multiple wiring templates and the type value of each wiring template, the actual line length, the number of grids offset between the template end point and the starting point on the x-axis and y-axis, and the number of grids at d1, d2, and d b The relative coordinates of all grids passed within the range and the starting point, and the turning mode of the wiring template relative to the forward direction;

[0036] The preset constraints include:

[0037] Line geometry constraints: The line is composed of multiple wiring templates spliced ​​in sequence; the wiring templates include a straight line template, a turning template and an offset template, the turning template is a 1 / 4 arc, and the offset template is a splicing of arcs corresponding to the inner angles at the diagonal of a parallelogram, the minimum side length of a set of parallel sides of the parallelogram is r, the length of the diagonal is 2r, and the minimum radius of the arc is r; the type values ​​of the straight line template, the turning template, and the offset template are 0, 1, and 2 respectively; the type value is used to simultaneously characterize the type of the wiring template and the number of turns;

[0038] Wire connectivity constraints: The endpoints of the read wire and the control wire correspond to a unique non-empty wire solution; in a wire solution, the starting point of the first wiring template is the starting point of the wire, the end point of the last wiring template is the end point of the wire, and the end point is on the boundary of the layout to be wired that can be used as the end point, and the start point of the current wiring template is the end point of the previous wiring template, and the end point of the current wiring template is the start point of the next wiring template;

[0039] Line spacing constraints: The minimum spacing between control lines or between control lines and read lines is d1, the minimum spacing between read lines is d2, and the minimum spacing between microwave transmission lines and wiring obstacles is d b .

[0040] The method provided by the present invention analyzes the constraints and optimization goals of the problem according to the physical characteristics of the superconducting quantum wiring problem, and establishes a wiring problem mathematical model that is highly correlated and easy to optimize.

[0041] The mathematical model of layout and routing problems mainly considers the following elements:

[0042] 1. Known Information

[0043] 1) Layout boundaries: represent the size of the chip and the area of ​​the wiring

[0044] 2) Escape endpoint: The boundary representing the end point of the wiring.

[0045] 3) Obstacles: Wiring obstacles consisting of resonant cavities, substrates, and some other components through which microwave transmission lines cannot pass.

[0046] 4) Line starting point: the starting point of the control line and the read line.

[0047] 2. Decision variables

[0048] 1) Line solution: The solution of all lines composed of arcs and straight lines of specific curvature.

[0049] 3. Optimization goals

[0050] 1) Minimize the number of turns (Count of Corners, CoC) in the line: The turns in the microwave transmission line will cause signal loss and generate noise, so the more turns in the line, the more unstable the transmission quality and the higher the chip error rate. In addition, the wiring design with fewer turns makes the overall route more beautiful and neat, which is in line with the design habits of manual wiring.

[0051] The neat design also makes it easier for chip designers to make additional design changes and maintenance, while also leaving more effective space for adding other components in subsequent processes;

[0052] 2) Minimize the total wire length (TWL): The length of the line directly affects the transmission quality and loss of the signal. At the same time, a shorter bus length also means that the wiring in the chip occupies less space. Therefore, the bus length is also one of the key indicators for improving the integration of the chip.

[0053] 4. Constraints

[0054] 1) Line geometry constraints: The line must be composed of straight lines or arcs, and the radius of the arc must be greater than or equal to r. When the microwave transmission line needs to be turned, an arc turn should be used. The main purpose is to reduce signal reflection and loss, which is also the biggest feature and difficulty of this wiring problem;

[0055] 2) Line connectivity constraint: All read lines and control line endpoints must correspond to a unique non-empty line solution. i ={s1, s2, ...s m}The starting point of line segment s1 is the endpoint of the line, and line segment s m The end point of is on the boundary of the chip that can be used as the end point. For any j∈[1,m-1], s j The end point and s j+1 The starting points must be the same. Connectivity constraints ensure that the results meet the basic logic requirements of wiring, which is also the basic goal of all wiring problems;

[0056] 3) Line spacing constraints: In a superconducting quantum chip, all lines cannot overlap with obstacles or other lines, and must maintain a certain distance from them. The distance between the line and the obstacle is d b The main factor is the width of the line itself and the precision of the manufacturing process. The spacing requirements d1 and d2 between lines depend not only on the line width and the process, but also because microwave signals are prone to noise and crosstalk between lines, also known as signal coherence. The spacing between read lines is usually larger than the spacing between other lines because the read signal is more sensitive to noise.

[0057] The main symbolic definitions of the mathematical model of the superconducting quantum chip wiring problem are shown in Table 1.

[0058] Table 1 Symbolic definitions of mathematical models for superconducting quantum chip wiring problems

[0059]

[0060]

[0061] The "combined wiring template" used in the method provided in the embodiment of the present invention is as follows: Figure 1 As shown in the figure, the starting and ending points of these routing templates can be perfectly placed on the vertices of the grid, and all routing solutions are specified, which are composed of several continuous routing templates. The contents of a combined routing template are shown in Table 2. Among them, the parameters in Table 1 that need to be known in advance for calculating the routing template include: the minimum spacing between all lines d1, the minimum spacing between read lines d2, and the minimum spacing between lines and obstacles d b , minimum turning radius r.

[0062] Table 2 Main information contained in a wiring template

[0063]

[0064] Under the "Combined Wiring Template", the decision variables for this solution are:

[0065] Rw={r1,r2……r n} (1)

[0066] R C = {r n ,r n+1 ....r n+m} (2)

[0067] r i ={t i1 ,t i2 ,....t io} (3)

[0068] Among them, t i1 ,t i2 ,t io They are the first, second and last wiring templates of the ith line respectively. The parameters contained in each wiring template are shown in Table 2.

[0069] The optimization goal is:

[0070]

[0071]

[0072] In this modeling, the output of the problem can be supplemented as R w and R C , expressed as formula (1) and formula (2), respectively representing n read line solutions and m control line solutions. i It can be expressed as formula (3), which means that the solution of a line consists of several routing templates. The first-level optimization goal of the problem is to minimize the total number of turns COC, which can be expressed as formula (4), which means R C and R W The sum of the types of all the templates t in the solution; the secondary optimization goal is to minimize the total length TWL, expressed as formula (5), representing R C and R W The sum of the len of template t of all solutions in .

[0073] The method provided in the embodiment of the present invention generates a set of wiring templates by combining arc segments and straight line segments according to the accuracy and constraint requirements of the layout. The templates include three types: straight line templates, turning templates, and offset templates. The templates can be screened according to the constraints to meet special requirements such as neat and symmetrical placement of air bridges. The combined wiring template used in this method limits the use of arc lines and converts the wiring problem from an irregular path planning problem in a continuous space to a template splicing problem in a grid. In the design of the combined wiring template, the geometric shapes of all templates are fixed, and the geometric shape information can be abstracted in advance as relative coordinate position information in a fine-grained grid. In the process of solving the wiring using the template, it is only necessary to consider the state of the grid where the template is located, without having to repeatedly perform geometric operations to determine whether constraints such as spacing are met.

[0074] The above mathematical model can be solved by existing methods, such as brute force solution. Considering the computational complexity, as a further preferred embodiment of the present invention, the following method is used to solve and calculate to obtain the optimal wiring result:

[0075] S1, using a single-side routing algorithm to obtain d1 and d2 that meet the line geometry constraints, the line connectivity constraints of a single line, and the line spacing constraints b A solution for a single line with constraints; a tree search method is used to obtain the wiring order between the lines that meet the line connectivity constraints of multiple lines, and after the current read line is routed, if the d2 constraint in the line spacing constraint is violated and the previous line is a control line, the wiring order of the current read line and the control line is exchanged to make the wiring order meet the d2 constraint in the line spacing constraint, thereby meeting all constraints in the line spacing constraint and obtaining a legal solution for the line.

[0076] Specifically, in S1, the legal line sequence and preliminary routing are solved to obtain a legal solution that meets the preset constraints. Among them, the line resource competition problem is converted into a line escape order search problem by using the characteristics of the one-sided routing algorithm results and edge fit, and a tree search framework and pruning strategy are designed to optimize the efficiency of tree search. The methods used specifically include:

[0077] 1. Single-sided wiring algorithm

[0078] like Figure 2 The figure shows the effect of using the unilateral routing algorithm in different sequences. The unilateral routing algorithm simulates the way people plan their walking paths. In reality, when people plan their walking paths in complex city streets and unknown road conditions, they first confirm the general direction of the destination, or obtain the general path through map navigation and other means. When walking, in order to avoid collisions with vehicles and other pedestrians, they always walk along the right hand side as much as possible while trying not to be far away from the end point. On the one hand, pedestrians only know the location and distance of the destination, but cannot know the specific path, but during the walking process, they always have a strong error correction ability to cope with complex scenarios. On the other hand, all vehicles and pedestrians abide by the traffic rules of walking on the right side, ensuring traffic order and efficient use of road space.

[0079] The one-sided routing algorithm sets a virtual routing boundary. The algorithm sets search restrictions or specific space division methods based on the information of the starting point, so that the starting point is at the "edge of space" from the beginning. This design ensures that pedestrians do not stray away from the target when walking or use navigation to obtain a rough path.

[0080] The one-sided routing algorithm dynamically searches for paths along one side of the edge, and can obtain a path that best fits the edge of the space, corresponding to pedestrians walking on the right. In this way, the one-sided routing algorithm avoids the process of using a directional mode to reach the boundary of the space, as well as the maintenance cost of the space boundary containing an arc. That is, the main ways to generate routing for the one-sided routing algorithm include:

[0081] By defining a virtual space, we can set the boundaries for the algorithm to walk.

[0082] Set the boundaries of the algorithm's walking by distance or other reference values;

[0083] By simulating the way people walk, the line can walk along the edge of the space in complex scenes to reach the chip boundary.

[0084] 2. Legal Line Sequence Tree Search

[0085] This method uses a tree search framework to search for line sequences, which fits the characteristics of the one-sided routing algorithm. The advantage of the tree search framework is that each time a new branch is searched or backtracked, only the line is added or deleted at the end of the existing line sequence, which is consistent with the characteristics of the one-sided routing algorithm. Deleting and adding lines at the end of the line sequence will not affect the previous lines. The search process can maximize the use of each routing action and better reuse the routing results.

[0086] That is, based on the current routing algorithm, a wire sequence tree search framework is adopted, and its main contents include:

[0087] Convert the resource competition problem into a wiring order problem;

[0088] The legal line sequence is searched through tree search, and the pruning and backtracking strategies are optimized during the search process through the blocking relationship between lines.

[0089] Figure 3 The figure shows the line sequence tree search process designed by this scheme. This scheme uses the blocking relationship of the circuits in the chip and adopts a two-step backtracking method and a blocking table method. First, the blocking relationship between the circuits is detected two by two. When performing node search and search backtracking, the number of search nodes is reduced according to the blocking relationship.

[0090] 3. Exchange winding action

[0091] The solution uses a swap winding action to achieve the special line sequence requirements of superconducting quantum chips during wiring, that is, the minimum spacing between read lines is d2, reducing signal crosstalk between key lines. For example, when the line sequence is {C, B}, B is the read line, C is the control line, and the spacing between B and other legal read lines that have been laid is less than d2, then it is necessary to swap the winding and adjust the line sequence to {B, C}. Figure 4 This means that line B bypasses line C to realize the wiring process according to the line sequence {B, C}. First, Figure 4 In (a), the single-side winding algorithm is used to lay out lines C and B in reverse order. Then, Figure 4 In (b), the routable space around lines B and C and the routable space around the starting point C are marked, and lines B and C are deleted. Figure 4 In (c), line B is routed along the edge of the marked space. Finally, line C is routed again using the monotonic one-sided routing algorithm, and we get Figure 4 The winding effect in (d).

[0092] S2, using the A* algorithm, optimizes the legal solutions according to the objective function to obtain the optimal solution.

[0093] Specifically, based on the space-constrained iterative routing optimization algorithm, on the basis of the legal solution, the number of turns and the total length of the line are further optimized to obtain the optimal routing result. Multiple small-scale optimal path searches are performed instead of a single large-scale search, thereby reducing the impact of large-scale space on search efficiency. Specifically, the following are included:

[0094] 1. Optimizing Wiring with Space Constraints

[0095] This scheme adopts a routing optimization framework that iterates through space constraints. Figure 5 The general process of iterative optimization is shown. When performing routing optimization, a routing optimization framework that iterates through space constraints is adopted, including:

[0096] Through the existing legal wiring, a specific wiring space is defined to reduce the algorithm's search space;

[0097] By setting specific routing priorities, the algorithm can optimize the number of turns in the route after multiple iterations;

[0098] Routing is optimized through multiple passes in a specific order to optimize the turns and lengths of multiple routes.

[0099] In order to improve the calculation efficiency, as a further optimization of the present invention, on the basis of a legal line, the space near it (for example, an area of ​​N times the line width, and the specific area range can be designed according to the actual calculation complexity and accuracy requirements) is delineated as the iteration space. In the next round of iteration, the A* algorithm is used to find an optimal path in the iteration space. This process is repeated until the optimal path in the iteration space no longer changes. The design of spatial iteration directly limits the scope of the search, and replaces a large-scale search with multiple small-scale iterative optimization searches. This design greatly reduces the search space of the algorithm, improves the efficiency of a single search, and avoids the impact of the degradation of the A* algorithm when optimizing the number of turns, thereby enhancing the stability of the search process.

[0100] In addition, according to the routing result characteristics of the one-sided routing algorithm, all lines are closely arranged on one side, and only the last line has the most sufficient remaining routing space. Based on this, as a further optimization of the present invention, the lines are optimized one by one in reverse order to release the remaining space, freeing up routing resources for the lines at the front of the line sequence.

[0101] To improve computational efficiency, as a further optimization of the present invention, this solution adopts a multi-layer A* search algorithm, where the number of search layers represents the number of turns of the current search route, in order to solve the problem of optimizing the number of turns. The algorithm first attempts to search for a feasible shortest path with 0 turns. If unsuccessful, the number of search layers, that is, the number of turns of the route, is gradually increased until the end point can be reached. The candidate points in the heap of the open set of the A* algorithm can be represented from high to low according to three priorities: the route with the least number of turns, the length of the route plus the heuristic evaluation is the shortest, and the route with the longest length. The evaluation of the line length can directly use the Manhattan distance calculated by the coordinate difference, or pre-calculate the estimated distance of each grid to the escape edge by the Maze Routing method.

[0102] 2. Open lazy set

[0103] Since a combined wiring template consists of at most two arcs, in the current search layer, at most two layers of candidate points will be generated. In addition, before the candidate points of the current layer are consumed, the candidate points of the next two layers will not be used. Through this feature, a "lazy open set" can be constructed to optimize the maintenance efficiency of the minimum heap.

[0104] During the process of inserting elements, if the new candidate point does not increase the number of turns, it is directly inserted into the heap, otherwise it is temporarily stored in a temporary list according to the type value of the template.

[0105] When the element with the minimum heuristic function value needs to be popped, if the heap is not empty, it is popped directly. Otherwise, it means that the next layer needs to be searched, and then the heap is constructed through a temporary list.

[0106] That is, when performing wiring optimization, an open lazy set structure is used to optimize the wiring speed of the line, including:

[0107] A multi-layer A* search algorithm is used, and the number of search layers represents the number of turns in the current search route;

[0108] A lazy open set design is adopted to delay the time for candidate line nodes to participate in heap maintenance, thereby reducing the heap size and maintenance cost.

[0109] Lazy open sets delay the time when non-essential data in the open set participate in the heap maintenance. On the one hand, it greatly reduces the size of the heap maintained during the search process. On the other hand, at the end of the algorithm, the candidate points of the last two layers do not participate in the construction of the heap, but are directly cached in the list, reducing the number of nodes participating in the minimum heap construction. Lazy open sets are very consistent with the wiring problem structure of multi-level optimization and reduce the maintenance cost of the minimum heap. Through some simple cache design and engineering optimization, the design of lazy open sets can stably and effectively improve the search efficiency of the A* algorithm in the wiring optimization process.

[0110] An embodiment of the present invention provides an electronic device, including: a computer-readable storage medium and a processor;

[0111] The computer-readable storage medium is used to store executable instructions;

[0112] The processor is used to read the executable instructions stored in the computer-readable storage medium and execute the method described in any of the above embodiments.

[0113] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the method described in any of the above embodiments.

[0114] An embodiment of the present invention provides a computer program product, including a computer program or instructions, and when the computer program or instructions are executed by a processor, the method described in any of the above embodiments is implemented.

[0115] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A superconducting quantum chip automatic wiring and optimization method, characterized in that: include: The layout to be wired is gridded, and under preset constraints, the optimal wiring result of the superconducting quantum chip is obtained by minimizing the number of turns and the total length of the line. The optimal wiring result includes the wiring solutions of n read lines and m control lines, each wiring solution includes multiple wiring templates and the type value of each wiring template, the actual line length, the number of grids offset between the template end point and the starting point on the x-axis and y-axis, and the number of grids at d1, d2, and d b The relative coordinates of all grids passed within the range and the starting point, and the turning mode of the wiring template relative to the forward direction; The preset constraints include: Line geometry constraints: The line is composed of multiple wiring templates spliced ​​in sequence; the wiring templates include a straight line template, a turning template and an offset template, the turning template is a 1 / 4 arc, and the offset template is a splicing of arcs corresponding to the inner angles at the diagonal of a parallelogram, the minimum side length of a set of parallel sides of the parallelogram is r, the length of the diagonal is 2r, and the minimum radius of the arc is r; the type values ​​of the straight line template, the turning template, and the offset template are 0, 1, and 2 respectively; the type value is used to simultaneously characterize the type of the wiring template and the number of turns; Line connectivity constraints: The endpoints of the read line and the control line correspond to a unique non-empty line solution; in a line solution, the starting point of the first wiring template is the starting point of the line, the end point of the last wiring template is the end point of the line, the starting point of the current wiring template is the end point of the previous wiring template, and the end point of the current wiring template is the starting point of the next wiring template; Line spacing constraints: The minimum spacing between control lines or between control lines and read lines is d1, the minimum spacing between read lines is d2, and the minimum spacing between microwave transmission lines and wiring obstacles is d b .

2. The method according to claim 1, characterized in that The following solution method is used to calculate and obtain the optimal wiring result: S1, using a single-side routing algorithm to obtain d1 and d2 that meet the line geometry constraints, line connectivity constraints, and line spacing constraints b The solution of a single line with constraints; the tree search method is used to obtain the wiring order between the lines that meet the line connectivity constraints, and after the current read line is routed, if the d2 constraint in the line spacing constraint is violated and the previous line is a control line, the wiring order of the current read line and the control line is exchanged to obtain a legal solution for the line; S2, using the A* algorithm, optimizes the legal solutions according to the objective function to obtain the optimal solution.

3. The method according to claim 2, characterized in that In step S2, a preset area where any legal route in the legal solution of the route is located is used as an iteration space. In the next round of iteration, an A* algorithm is used to find an optimal path in the iteration space. This process is repeated until the optimal path in the iteration space no longer changes.

4. The method according to claim 2 or 3, characterized in that In step S2, the lines in the legal solution are optimized one by one in reverse order to release the remaining space.

5. The method according to claim 2 or 3, wherein the A* algorithm is a multi-layer A* algorithm; in, The search layer number represents the number of turns in the current search route; The candidate points in the open set heap of the multi-layer A* algorithm are represented according to three priorities from high to low: the number of turns in the route traveled is the least, the length of the route traveled plus the length of the heuristic evaluation is the shortest, and the route traveled is the longest; in the current search level, at most two layers of candidate points are generated, and before the candidate points in the current level are consumed, the candidate points in the next two levels will not be used; During the process of inserting elements, if the new candidate point does not increase the number of turns, it is directly inserted into the heap, otherwise it is temporarily stored in a temporary list according to the type of template; When the element with the minimum heuristic function value needs to be popped, if the heap is not empty, it is popped directly, otherwise the heap is built through a temporary list.

6. An electronic device, characterized in that: include: A computer readable storage medium and a processor; The computer-readable storage medium is used to store executable instructions; The processor is used to read the executable instructions stored in the computer-readable storage medium and execute the method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the method according to any one of claims 1 to 5.

8. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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