Compiler software design method and system supporting IP generation of multiple memories

Abstract

The invention provides a compiler software design method and system supporting multiple memory IP generation, and relates to the technical field of compilers, and the method comprises the steps: calling a corresponding memory IP template file according to memory IP parameters, and based on the memory IP template file, adopting a placeholder replacement mode, filling the corresponding positions of the Verilog code with the memory capacity, the memory frequency and the memory bit width to generate a Verilog source file; calling a Verilog compiler, performing grammar check on the Verilog source file, and generating a netlist file of a memory IP; calling a time sequence constraint file based on the netlist file, performing time sequence constraint and physical constraint, and generating a layout design file of the memory IP; packaging parameters input by a user are received, a packaging script is called, the layout design file and the packaging parameters are input into the packaging script, a GDSII file of the memory IP is generated, and layout and wiring of the memory IP are completed.

Description

Technical Field

[0001] The present invention relates to compiler technology, and in particular to a compiler software design method and system that supports the generation of multiple memory IPs. Background Art

[0002] In the field of memory IP design, compiler software plays a vital role. Traditional memory IP design methods usually rely on manual design and optimization, which is not only time-consuming and labor-intensive, but also difficult to adapt to rapidly changing market demands. With the continuous development of integrated circuit technology and the increasing diversification of application scenarios, the demand for compiler software that can support the rapid generation of multiple memory IPs is becoming increasingly urgent.

[0003] The existing memory IP compiler software has the following main problems:

[0004] Insufficient flexibility: Most compiler software can only support the generation of a limited number of memory IPs, and it is difficult to meet the diverse requirements of different application scenarios for memory type, capacity, bit width and other parameters. Limited performance optimization: Existing compiler software often adopts fixed optimization strategies when generating memory IPs, and it is difficult to flexibly tune performance for different process nodes and application requirements. Poor compatibility: Many compiler software are bound to specific EDA tools, which are difficult to migrate and integrate between different design platforms, limiting their scope of application. Low degree of automation: Some compiler software still requires a lot of manual intervention, especially in parameter configuration, layout generation and verification, which affects design efficiency.

[0005] In view of the above problems, developing an efficient, flexible and intelligent compiler software that can support the generation of multiple memory IPs has become an important research direction in the current memory IP design field. Summary of the invention

[0006] The embodiments of the present invention provide a compiler software design method and system that supports the generation of multiple memory IPs, which can solve the problems in the prior art.

[0007] According to a first aspect of the embodiments of the present invention,

[0008] Provides compiler software design methodologies that support the generation of a variety of memory IP, including:

[0009] Receive memory IP parameters of memory IP type, memory capacity, memory frequency, and memory bit width input by a user; call a corresponding memory IP template file according to the memory IP parameters, wherein the memory IP template file includes a Verilog code matching the memory IP type; based on the memory IP template file, fill the memory capacity, memory frequency, and memory bit width into corresponding positions of the Verilog code by placeholder replacement to generate a Verilog source file;

[0010] Calling a Verilog compiler, performing a syntax check on the Verilog source file, and generating a netlist file of the memory IP; based on the netlist file, calling a timing constraint file, performing timing constraints and physical constraints, and generating a layout design file of the memory IP; receiving packaging parameters input by a user, calling a packaging script, and inputting the layout design file and the packaging parameters into the packaging script, generating a GDSII file of the memory IP, and completing the layout and routing of the memory IP;

[0011] The GDSII file and the Verilog source file are input into the layout verification tool together, and LVS verification, DRC verification and antenna rule check are performed. After confirming that the layout verification is correct, the final memory IP description file is formed for calling during SOC design.

[0012] In an optional embodiment,

[0013] Based on the memory IP template file, the memory capacity, memory frequency, and memory bit width are filled into the corresponding positions of the Verilog code by using placeholder replacement, and the Verilog source file is generated, including:

[0014] Receive memory parameters of memory capacity, memory frequency, and memory bit width input by a user;

[0015] Obtain a pre-prepared memory IP template file, wherein the memory IP template file is described using parameterized Verilog code, wherein key parameters of memory capacity, memory frequency, and memory bit width are represented in the form of placeholders;

[0016] Read the content of the memory IP template file, and replace the placeholder with a numerical value corresponding to the memory parameter by string replacement to obtain a filled Verilog code;

[0017] Writing the filled Verilog code into a new file to obtain a Verilog source file of the memory IP, wherein the file name of the Verilog source file is named according to the value of the memory parameter;

[0018] In the above string replacement process, a memory address bit width parameter is calculated according to the memory capacity parameter, and the address bit width parameter is filled into the corresponding position of the Verilog code;

[0019] Before performing the above string replacement, a Verilog parsing tool is called to perform a syntax check on the memory IP template file to ensure that the memory IP template file complies with the Verilog syntax specification.

[0020] In an optional embodiment,

[0021] Calling the Verilog compiler, performing syntax check on the Verilog source file, and generating a netlist file of the memory IP; based on the netlist file, calling the timing constraint file, performing timing constraints and physical constraints, and generating a layout design file of the memory IP includes:

[0022] Calling the Verilog compiler to perform syntax checking on the Verilog source file, wherein the syntax checking includes lexical analysis, grammatical analysis and semantic analysis, and checks the correctness of variable declarations, module interfaces and statement structures;

[0023] Generate a netlist file of the memory IP based on the Verilog source file that passes the syntax check, wherein the netlist file includes the logic function and signal connection relationship of the memory IP;

[0024] Obtain a predefined timing constraint file and a physical constraint file, wherein the timing constraint file defines the clock frequency, setup time and hold time of the memory IP, and the physical constraint file defines the chip area, pin location and power supply network of the memory IP;

[0025] Input the netlist file, the timing constraint file and the physical constraint file into a physical design tool to perform layout and routing of the memory IP; during the layout and routing process, map the logic cells in the netlist file to the physical cell library, determine the specific location of each cell, and complete the routing of the signal lines while balancing the timing performance, power consumption and area;

[0026] Based on the layout and routing results, a layout design file of the memory IP is generated, wherein the layout design file contains the geometric shape and hierarchical structure information of the memory IP; the layout design file is subjected to design rule checking and layout and circuit matching. Figure 1 Consistency checks verify that the layout complies with process rules and is functionally consistent with the original design.

[0027] In an optional embodiment,

[0028] Receiving the packaging parameters input by the user, calling the packaging script, and inputting the layout design file and the packaging parameters into the packaging script to generate a GDSII file of the memory IP, and completing the layout and routing of the memory IP includes:

[0029] Receiving packaging parameters input by a user, wherein the packaging parameters include packaging type, number of pins, pin spacing, chip size, and heat dissipation requirements;

[0030] Calling a pre-prepared encapsulation script, wherein the encapsulation script can handle a variety of encapsulation types and parameter combinations;

[0031] Inputting a layout design file of the memory IP into the packaging script, the layout design file including geometry and hierarchical structure information of the memory IP;

[0032] Generate an outline of a packaging substrate according to the chip size and the packaging type;

[0033] Arranging pads on the packaging substrate according to the number of pins and the pin spacing;

[0034] Matching and connecting the I / O units in the layout design file with the pads on the package substrate;

[0035] Designing an interconnection structure between the chip and the packaging substrate, wherein the interconnection structure includes bonding wires or flip-chip bumps;

[0036] According to the heat dissipation requirements, a heat dissipation structure is designed, wherein the heat dissipation structure includes a heat dissipation fin or a heat dissipation ball;

[0037] During the design process, the design rules are checked in real time to ensure that the generated package structure meets the manufacturing process requirements;

[0038] Generate a GDSII file of the memory IP containing chip layout information and detailed design of the package structure, wherein the GDSII file contains a hierarchical structure of the package substrate, a pad layout, and a bonding wire path;

[0039] Perform design rule checking, layout and circuit analysis on the GDSII file Figure 1 Conformance checking and electrical rule checking verify whether there are shorts, opens, or excessive parasitic capacitance in the design.

[0040] In an optional embodiment,

[0041] The GDSII file and the Verilog source file are input into the layout verification tool together, and LVS verification, DRC verification and antenna rule check are performed. After confirming that the layout verification is correct, the final memory IP description file is formed for calling during SOC design, including:

[0042] Receiving packaging parameters input by a user, wherein the packaging parameters include packaging type, number of pins, pin spacing, chip size, and heat dissipation requirements;

[0043] Calling a pre-prepared encapsulation script, wherein the encapsulation script can handle a variety of encapsulation types and parameter combinations;

[0044] Inputting a layout design file of the memory IP into the packaging script, the layout design file including geometry and hierarchical structure information of the memory IP;

[0045] Generate an outline of a packaging substrate according to the chip size and the packaging type;

[0046] Arranging pads on the packaging substrate according to the number of pins and the pin spacing;

[0047] Matching and connecting the I / O units in the layout design file with the pads on the package substrate;

[0048] Designing an interconnection structure between the chip and the packaging substrate, wherein the interconnection structure includes bonding wires or flip-chip bumps;

[0049] According to the heat dissipation requirements, a heat dissipation structure is designed, wherein the heat dissipation structure includes a heat dissipation fin or a heat dissipation ball;

[0050] During the design process, the design rules are checked in real time to ensure that the generated package structure meets the manufacturing process requirements;

[0051] Generate a GDSII file of the memory IP containing chip layout information and detailed design of the package structure, wherein the GDSII file contains a hierarchical structure of the package substrate, a pad layout, and a bonding wire path;

[0052] Perform design rule checking, layout and circuit analysis on the GDSII file Figure 1 Conformance checking and electrical rule checking verify whether there are shorts, opens, or excessive parasitic capacitance in the design.

[0053] According to a second aspect of the embodiments of the present invention,

[0054] Provides compiler software design system that supports generation of a wide range of memory IP, including:

[0055] The first unit is used to receive memory IP parameters of memory IP type, memory capacity, memory frequency, and memory bit width input by a user; according to the memory IP parameters, call a corresponding memory IP template file, wherein the memory IP template file includes a Verilog code matching the memory IP type; based on the memory IP template file, fill the memory capacity, memory frequency, and memory bit width into corresponding positions of the Verilog code by placeholder replacement to generate a Verilog source file;

[0056] The second unit is used to call the Verilog compiler, perform syntax check on the Verilog source file, and generate a netlist file of the memory IP; based on the netlist file, call the timing constraint file, perform timing constraints and physical constraints, and generate a layout design file of the memory IP; receive the packaging parameters input by the user, call the packaging script, and input the layout design file and the packaging parameters into the packaging script to generate a GDSII file of the memory IP, and complete the layout and routing of the memory IP;

[0057] The third unit is used to input the GDSII file and the Verilog source file into the layout verification tool, perform LVS verification, DRC verification and antenna rule check, and after confirming that the layout verification is correct, form the final memory IP description file for calling during SOC design.

[0058] According to a third aspect of the embodiments of the present invention,

[0059] An electronic device is provided, comprising:

[0060] processor;

[0061] a memory for storing processor-executable instructions;

[0062] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0063] According to a fourth aspect of the embodiments of the present invention,

[0064] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 A flowchart of a compiler software design method that supports generation of multiple memory IPs according to an embodiment of the present invention;

[0066] Figure 2A schematic diagram of the structure of a compiler software design system that supports the generation of multiple memory IPs according to an embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0068] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0069] Figure 1 FIG. 1 is a flow chart of a compiler software design method for supporting multiple memory IP generation according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0070] S101. Receive memory IP parameters of memory IP type, memory capacity, memory frequency, and memory bit width input by a user; call a corresponding memory IP template file according to the memory IP parameters, wherein the memory IP template file includes a Verilog code matching the memory IP type; based on the memory IP template file, fill the memory capacity, memory frequency, and memory bit width into corresponding positions of the Verilog code by placeholder replacement to generate a Verilog source file;

[0071] S102. Calling the Verilog compiler, performing syntax check on the Verilog source file, and generating a netlist file of the memory IP; based on the netlist file, calling the timing constraint file, performing timing constraints and physical constraints, and generating a layout design file of the memory IP; receiving the packaging parameters input by the user, calling the packaging script, and inputting the layout design file and the packaging parameters into the packaging script, generating a GDSII file of the memory IP, and completing the layout and routing of the memory IP;

[0072] S103. Input the GDSII file and the Verilog source file into the layout verification tool, perform LVS verification, DRC verification and antenna rule check, and after confirming that the layout verification is correct, form the final memory IP description file for calling during SOC design.

[0073] In an optional embodiment,

[0074] Based on the memory IP template file, the memory capacity, memory frequency, and memory bit width are filled into the corresponding positions of the Verilog code by using placeholder replacement, and the Verilog source file is generated, including:

[0075] Receive memory parameters of memory capacity, memory frequency, and memory bit width input by a user;

[0076] Obtain a pre-prepared memory IP template file, wherein the memory IP template file is described using parameterized Verilog code, wherein key parameters of memory capacity, memory frequency, and memory bit width are represented in the form of placeholders;

[0077] Read the content of the memory IP template file, and replace the placeholder with a numerical value corresponding to the memory parameter by string replacement to obtain a filled Verilog code;

[0078] Writing the filled Verilog code into a new file to obtain a Verilog source file of the memory IP, wherein the file name of the Verilog source file is named according to the value of the memory parameter;

[0079] In the above string replacement process, a memory address bit width parameter is calculated according to the memory capacity parameter, and the address bit width parameter is filled into the corresponding position of the Verilog code;

[0080] Before performing the above string replacement, a Verilog parsing tool is called to perform a syntax check on the memory IP template file to ensure that the memory IP template file complies with the Verilog syntax specification.

[0081] In an optional embodiment,

[0082] Calling the Verilog compiler, performing syntax check on the Verilog source file, and generating a netlist file of the memory IP; based on the netlist file, calling the timing constraint file, performing timing constraints and physical constraints, and generating a layout design file of the memory IP includes:

[0083] Calling the Verilog compiler to perform syntax checking on the Verilog source file, wherein the syntax checking includes lexical analysis, grammatical analysis and semantic analysis, and checks the correctness of variable declarations, module interfaces and statement structures;

[0084] Generate a netlist file of the memory IP based on the Verilog source file that passes the syntax check, wherein the netlist file includes the logic function and signal connection relationship of the memory IP;

[0085] Obtain a predefined timing constraint file and a physical constraint file, wherein the timing constraint file defines the clock frequency, setup time and hold time of the memory IP, and the physical constraint file defines the chip area, pin location and power supply network of the memory IP;

[0086] Input the netlist file, the timing constraint file and the physical constraint file into a physical design tool to perform layout and routing of the memory IP; during the layout and routing process, map the logic cells in the netlist file to the physical cell library, determine the specific location of each cell, and complete the routing of the signal lines while balancing the timing performance, power consumption and area;

[0087] Based on the layout and routing results, a layout design file of the memory IP is generated, wherein the layout design file contains the geometric shape and hierarchical structure information of the memory IP; the layout design file is subjected to design rule checking and layout and circuit matching. Figure 1 Consistency checks verify that the layout complies with process rules and is functionally consistent with the original design.

[0088] In an optional embodiment,

[0089] Receiving the packaging parameters input by the user, calling the packaging script, and inputting the layout design file and the packaging parameters into the packaging script to generate a GDSII file of the memory IP, and completing the layout and routing of the memory IP includes:

[0090] Receiving packaging parameters input by a user, wherein the packaging parameters include packaging type, number of pins, pin spacing, chip size, and heat dissipation requirements;

[0091] Calling a pre-prepared encapsulation script, wherein the encapsulation script can handle a variety of encapsulation types and parameter combinations;

[0092] Inputting a layout design file of the memory IP into the packaging script, the layout design file including geometry and hierarchical structure information of the memory IP;

[0093] Generate an outline of a packaging substrate according to the chip size and the packaging type;

[0094] Arranging pads on the packaging substrate according to the number of pins and the pin spacing;

[0095] Matching and connecting the I / O units in the layout design file with the pads on the package substrate;

[0096] Designing an interconnection structure between the chip and the packaging substrate, wherein the interconnection structure includes bonding wires or flip-chip bumps;

[0097] According to the heat dissipation requirements, a heat dissipation structure is designed, wherein the heat dissipation structure includes a heat dissipation fin or a heat dissipation ball;

[0098] During the design process, the design rules are checked in real time to ensure that the generated package structure meets the manufacturing process requirements;

[0099] Generate a GDSII file of the memory IP containing chip layout information and detailed design of the package structure, wherein the GDSII file contains a hierarchical structure of the package substrate, a pad layout, and a bonding wire path;

[0100] Perform design rule checking, layout and circuit analysis on the GDSII file Figure 1 Conformance checking and electrical rule checking verify whether there are shorts, opens, or excessive parasitic capacitance in the design.

[0101] In an optional embodiment,

[0102] The GDSII file and the Verilog source file are input into the layout verification tool together, and LVS verification, DRC verification and antenna rule check are performed. After confirming that the layout verification is correct, the final memory IP description file is formed for calling during SOC design, including:

[0103] Receiving packaging parameters input by a user, wherein the packaging parameters include packaging type, number of pins, pin spacing, chip size, and heat dissipation requirements;

[0104] Calling a pre-prepared encapsulation script, wherein the encapsulation script can handle a variety of encapsulation types and parameter combinations;

[0105] Inputting a layout design file of the memory IP into the packaging script, the layout design file including geometry and hierarchical structure information of the memory IP;

[0106] Generate an outline of a packaging substrate according to the chip size and the packaging type;

[0107] Arranging pads on the packaging substrate according to the number of pins and the pin spacing;

[0108] Matching and connecting the I / O units in the layout design file with the pads on the package substrate;

[0109] Designing an interconnection structure between the chip and the packaging substrate, wherein the interconnection structure includes bonding wires or flip-chip bumps;

[0110] According to the heat dissipation requirements, a heat dissipation structure is designed, wherein the heat dissipation structure includes a heat dissipation fin or a heat dissipation ball;

[0111] During the design process, the design rules are checked in real time to ensure that the generated package structure meets the manufacturing process requirements;

[0112] Generate a GDSII file of the memory IP containing chip layout information and detailed design of the package structure, wherein the GDSII file contains a hierarchical structure of the package substrate, a pad layout, and a bonding wire path;

[0113] Perform design rule checking, layout and circuit analysis on the GDSII file Figure 1 Conformance checking and electrical rule checking verify whether there are shorts, opens, or excessive parasitic capacitance in the design.

[0114] Another embodiment of the present application is as follows:

[0115] The design of compiler software that supports the generation of multiple memory IPs is a complex and systematic process involving multiple key steps and technical details. This design methodology aims to provide a flexible and efficient memory IP generation solution that can adapt to the requirements of different memory types and parameters.

[0116] First, the compiler software receives the memory IP parameters entered by the user. These parameters include memory IP type (such as SRAM, ROM, DRAM, etc.), memory capacity (such as 1KB, 4MB, etc.), memory frequency (such as 100MHz, 1GHz, etc.) and memory bit width (such as 8-bit, 32-bit, etc.). These parameters determine the basic characteristics and performance indicators of the generated memory IP.

[0117] Next, based on the memory IP type entered by the user, the system calls the corresponding memory IP template file. These template files are prepared in advance and contain the Verilog code framework that matches the specific memory IP type. For example, for an SRAM type memory, the template file may contain the basic structure of the read-write control logic, address decoder, and storage cell array.

[0118] The compiler software then uses placeholder replacement to fill the memory capacity, frequency, and bit width entered by the user into the corresponding positions of the Verilog code. This process first reads the contents of the memory IP template file, and then uses the string replacement method to replace the placeholders in the template with specific parameter values. For example, for a 4KB, 100MHz, 32-bit wide SRAM, the system will replace the capacity-related placeholder with 4096, the frequency-related placeholder with 100000000, and the bit width-related placeholder with 32.

[0119] When performing parameter replacement, the system will automatically calculate the address width based on the memory capacity. For example, for a 4KB memory, the address width is 12 bits (2 to the 12th power equals 4096). This calculated address width will also be filled into the corresponding position of the Verilog code.

[0120] Before performing string replacement, the system will call the Verilog parsing tool to perform syntax check on the memory IP template file to ensure that the template file itself complies with the Verilog syntax specification. This step can effectively avoid subsequent problems caused by syntax errors in the template file itself.

[0121] After completing the parameter replacement, the system writes the generated Verilog code into a new file to obtain the Verilog source file of the memory IP. The name of this file usually reflects the key parameters of the memory, such as "SRAM_4KB_100MHz_32bit.v", to facilitate subsequent identification and management.

[0122] After the Verilog source file is generated, the system calls the Verilog compiler to perform a comprehensive syntax check on it. This process includes lexical analysis, syntax analysis, and semantic analysis, and checks the correctness of variable declarations, module interfaces, and statement structures. For example, it checks whether there are undeclared variables, whether the module ports match, and whether there are syntax structure errors.

[0123] After passing the syntax check, the compiler generates a netlist file for the memory IP based on the Verilog source file. The netlist file describes the logical functions and signal connection relationships of the memory IP and is the basis for subsequent physical design. For example, the netlist file will contain connection information for modules such as storage cells, address decoders, and read / write control logic.

[0124] Next, the system obtains the pre-defined timing constraint file and physical constraint file. The timing constraint file defines the key timing parameters of the memory IP, such as clock frequency, setup time, and hold time. For example, for a 100MHz memory, the clock cycle is set to 10ns. The physical constraint file defines the physical implementation parameters of the memory IP, such as chip area, pin location, and power network layout.

[0125] The system inputs the netlist file, timing constraint file, and physical constraint file into the physical design tool to perform the layout and routing of the memory IP. In this process, the logic cells in the netlist file are mapped to specific cells in the physical cell library, the position of each cell is determined, and the specific routing of the signal line is also completed. At the same time, the system needs to balance multiple design goals such as timing performance, power consumption, and area.

[0126] After completing the layout and routing, the system generates a layout design file for the memory IP. This file contains detailed geometry and hierarchical information of the memory IP. Subsequently, the system performs design rule checking (DRC) and layout and circuit matching on the layout design file. Figure 1LVS is performed to ensure that the layout complies with process rules and is functionally consistent with the original design.

[0127] Next, the system processes the packaging parameters entered by the user, including package type (such as BGA, QFP, etc.), number of pins, pin pitch, chip size, and heat dissipation requirements. These parameters determine the physical packaging characteristics of the memory IP.

[0128] The system calls a pre-prepared package script that can handle a variety of package types and parameter combinations. For example, for BGA packages, the script can automatically generate a ball grid array layout based on the number of pins and pitch.

[0129] Input the layout design file of the memory IP into the packaging script, and the script generates the outline of the package substrate based on the chip size and package type. For example, for a 10mm x 10mm chip, the system may generate a 12mm x 12mm package substrate outline, leaving enough margin space.

[0130] Based on the number of pins and the pitch, the system arranges the pads on the package substrate. For example, for a 256-pin, 0.8mm pitch BGA package, the system arranges the pads on the substrate in a 16x16 matrix.

[0131] The system then matches and connects the I / O cells in the layout design file to the pads on the package substrate. This process takes into account signal integrity and power integrity to ensure that each I / O signal is correctly connected to the corresponding package pin.

[0132] The system designs the interconnect structure between the chip and the package substrate, which may be bond wires or flip-chip bumps. For example, for a package with bond wires, the system generates a gold wire connection path from the chip pad to the package substrate pad.

[0133] According to the heat dissipation requirements, the system designs the corresponding heat dissipation structure, such as heat sink or heat dissipation ball. For example, for high-power memory IP, a large heat sink may be added to the top of the package, or multiple heat dissipation balls may be arranged at the bottom.

[0134] During the entire design process, the system checks the design rules in real time to ensure that the generated package structure meets the manufacturing process requirements. For example, it checks whether the length and angle of the bonding wire are within the allowable range, and whether the heat dissipation structure interferes with other components.

[0135] Finally, the system generates a GDSII file of the memory IP containing chip layout information and detailed package structure design. This file contains comprehensive information such as the hierarchy of the package substrate, pad layout, and bonding wire path.

[0136] The system performs final verification on the generated GDSII file, including design rule checking, layout and circuit Figure 1 This step verifies that there are no shorts, opens, or excessive parasitic capacitance in the design.

[0137] After the above comprehensive design and verification process, the system finally forms a complete description file of the memory IP, including Verilog source file, netlist file, layout file and GDSII file, etc. These files constitute a complete memory IP and can be directly integrated into SOC design.

[0138] This automated memory IP generation method can greatly improve the design efficiency and quality of memory IP and meet the diverse memory requirements of different application scenarios.

[0139] Figure 2 FIG. 1 is a schematic diagram of a compiler software design system supporting multiple memory IP generation according to an embodiment of the present invention. Figure 2 As shown, the system comprises:

[0140] The first unit is used to receive memory IP parameters of memory IP type, memory capacity, memory frequency, and memory bit width input by a user; according to the memory IP parameters, call a corresponding memory IP template file, wherein the memory IP template file includes a Verilog code matching the memory IP type; based on the memory IP template file, fill the memory capacity, memory frequency, and memory bit width into corresponding positions of the Verilog code by placeholder replacement to generate a Verilog source file;

[0141] The second unit is used to call the Verilog compiler, perform syntax check on the Verilog source file, and generate a netlist file of the memory IP; based on the netlist file, call the timing constraint file, perform timing constraints and physical constraints, and generate a layout design file of the memory IP; receive the packaging parameters input by the user, call the packaging script, and input the layout design file and the packaging parameters into the packaging script to generate a GDSII file of the memory IP, and complete the layout and routing of the memory IP;

[0142] The third unit is used to input the GDSII file and the Verilog source file into the layout verification tool, perform LVS verification, DRC verification and antenna rule check, and after confirming that the layout verification is correct, form the final memory IP description file for calling during SOC design.

[0143] According to a third aspect of the embodiments of the present invention,

[0144] An electronic device is provided, comprising:

[0145] processor;

[0146] a memory for storing processor-executable instructions;

[0147] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0148] According to a fourth aspect of the embodiments of the present invention,

[0149] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0150] The present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present invention.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A compiler software design method supporting the generation of multiple memory IPs, characterized in that: include: Receive memory IP parameters of memory IP type, memory capacity, memory frequency, and memory bit width input by the user; According to the memory IP parameters, calling a corresponding memory IP template file, wherein the memory IP template file includes a Verilog code matching the memory IP type; Based on the memory IP template file, the memory capacity, memory frequency, and memory bit width are filled into corresponding positions of the Verilog code by using placeholder replacement to generate a Verilog source file; Calling a Verilog compiler to perform syntax checking on the Verilog source file and generate a netlist file of the memory IP; Based on the netlist file, the timing constraint file is called to perform timing constraints and physical constraints, and a layout design file of the memory IP is generated; the packaging parameters input by the user are received, the packaging script is called, and the layout design file and the packaging parameters are input into the packaging script to generate a GDSII file of the memory IP, and the layout and routing of the memory IP are completed; The GDSII file and the Verilog source file are input into the layout verification tool together, and LVS verification, DRC verification and antenna rule check are performed. After confirming that the layout verification is correct, the final memory IP description file is formed for calling during SOC design.

2. The method according to claim 1, characterized in that Based on the memory IP template file, the memory capacity, memory frequency, and memory bit width are filled into the corresponding positions of the Verilog code by using placeholder replacement, and the Verilog source file is generated, including: Receive memory parameters of memory capacity, memory frequency, and memory bit width input by a user; Obtain a pre-prepared memory IP template file, wherein the memory IP template file is described using parameterized Verilog code, wherein key parameters of memory capacity, memory frequency, and memory bit width are represented in the form of placeholders; Read the content of the memory IP template file, and replace the placeholder with a numerical value corresponding to the memory parameter by string replacement to obtain a filled Verilog code; Writing the filled Verilog code into a new file to obtain a Verilog source file of the memory IP, wherein the file name of the Verilog source file is named according to the value of the memory parameter; In the above string replacement process, a memory address bit width parameter is calculated according to the memory capacity parameter, and the address bit width parameter is filled into the corresponding position of the Verilog code; Before performing the above string replacement, a Verilog parsing tool is called to perform a syntax check on the memory IP template file to ensure that the memory IP template file complies with the Verilog syntax specification.

3. The method according to claim 1, characterized in that Calling a Verilog compiler to perform syntax checking on the Verilog source file and generate a netlist file of the memory IP; Based on the netlist file, the timing constraint file is called to perform timing constraints and physical constraints, and the layout design file of the memory IP is generated, including: Calling the Verilog compiler to perform syntax checking on the Verilog source file, wherein the syntax checking includes lexical analysis, grammatical analysis and semantic analysis, and checks the correctness of variable declarations, module interfaces and statement structures; Generate a netlist file of the memory IP based on the Verilog source file that passes the syntax check, wherein the netlist file includes the logic function and signal connection relationship of the memory IP; Obtain a predefined timing constraint file and a physical constraint file, wherein the timing constraint file defines the clock frequency, setup time and hold time of the memory IP, and the physical constraint file defines the chip area, pin location and power supply network of the memory IP; Input the netlist file, the timing constraint file and the physical constraint file into a physical design tool to perform layout and routing of the memory IP; during the layout and routing process, map the logic cells in the netlist file to the physical cell library, determine the specific location of each cell, and complete the routing of the signal lines while balancing the timing performance, power consumption and area; Based on the layout and routing results, a layout design file of the memory IP is generated, and the layout design file contains the geometry and hierarchical structure information of the memory IP; the layout design file is subjected to a design rule check and a layout and circuit diagram consistency check to verify whether the layout complies with the process rules and is functionally consistent with the original design.

4. The method according to claim 1, characterized in that: Receiving the packaging parameters input by the user, calling the packaging script, and inputting the layout design file and the packaging parameters into the packaging script to generate a GDSII file of the memory IP, and completing the layout and routing of the memory IP includes: Receiving packaging parameters input by a user, wherein the packaging parameters include packaging type, number of pins, pin spacing, chip size, and heat dissipation requirements; Calling a pre-prepared encapsulation script, wherein the encapsulation script can handle a variety of encapsulation types and parameter combinations; Inputting a layout design file of the memory IP into the packaging script, the layout design file including geometry and hierarchical structure information of the memory IP; Generate an outline of a packaging substrate according to the chip size and the packaging type; Arranging pads on the packaging substrate according to the number of pins and the pin spacing; Matching and connecting the I / O units in the layout design file with the pads on the package substrate; Designing an interconnection structure between the chip and the packaging substrate, wherein the interconnection structure includes bonding wires or flip-chip bumps; According to the heat dissipation requirements, a heat dissipation structure is designed, wherein the heat dissipation structure includes a heat dissipation fin or a heat dissipation ball; During the design process, the design rules are checked in real time to ensure that the generated package structure meets the manufacturing process requirements; Generate a GDSI I file of the memory IP containing chip layout information and detailed packaging structure design, wherein the GDSI I file contains the hierarchy of the packaging substrate, pad layout and bonding wire path; The GDSII file is subjected to a design rule check, a layout and circuit diagram consistency check, and an electrical rule check to verify whether there are short circuits, open circuits, or excessive parasitic capacitance in the design.

5. The method according to claim 1, characterized in that The GDSII file and the Veri log source file are input into the layout verification tool together, and LVS verification, DRC verification and antenna rule check are performed. After confirming that the layout verification is correct, the final memory IP description file is formed for calling during SOC design, including: Receiving packaging parameters input by a user, wherein the packaging parameters include packaging type, number of pins, pin spacing, chip size, and heat dissipation requirements; Calling a pre-prepared encapsulation script, wherein the encapsulation script can handle a variety of encapsulation types and parameter combinations; Inputting a layout design file of the memory IP into the packaging script, the layout design file including geometry and hierarchical structure information of the memory IP; Generate an outline of a packaging substrate according to the chip size and the packaging type; Arranging pads on the packaging substrate according to the number of pins and the pin spacing; Matching and connecting the I / O units in the layout design file with the pads on the package substrate; Designing an interconnection structure between the chip and the packaging substrate, wherein the interconnection structure includes bonding wires or flip-chip bumps; According to the heat dissipation requirements, a heat dissipation structure is designed, wherein the heat dissipation structure includes a heat dissipation fin or a heat dissipation ball; During the design process, the design rules are checked in real time to ensure that the generated package structure meets the manufacturing process requirements; Generate a GDSII file of the memory IP containing chip layout information and detailed design of the package structure, wherein the GDSII file contains a hierarchical structure of the package substrate, a pad layout, and a bonding wire path; The GDSII file is subjected to a design rule check, a layout and circuit diagram consistency check, and an electrical rule check to verify whether there are short circuits, open circuits, or excessive parasitic capacitance in the design.

6. A compiler software design system supporting the generation of multiple memory IPs, used to implement the method according to any one of claims 1 to 5, characterized in that: include: The first unit is used to receive memory IP parameters of memory IP type, memory capacity, memory frequency, and memory bit width input by a user; According to the memory IP parameters, calling a corresponding memory IP template file, wherein the memory IP template file includes a Verilog code matching the memory IP type; Based on the memory IP template file, the memory capacity, memory frequency, and memory bit width are filled into corresponding positions of the Verilog code by using placeholder replacement to generate a Verilog source file; The second unit is used to call the Verilog compiler, perform syntax check on the Verilog source file, and generate a netlist file of the memory IP; Based on the netlist file, the timing constraint file is called to perform timing constraints and physical constraints, and a layout design file of the memory IP is generated; the packaging parameters input by the user are received, the packaging script is called, and the layout design file and the packaging parameters are input into the packaging script to generate a GDSII file of the memory IP, and the layout and routing of the memory IP are completed; The third unit is used to input the GDSII file and the Veri log source file into the layout verification tool, perform LVS verification, DRC verification and antenna rule check, and after confirming that the layout verification is correct, form the final memory IP description file for calling during SOC design.

7. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 1 to 5.

8. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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