Multi-node server access method and device, computer equipment and storage medium

Abstract

The invention relates to a multi-node server access method and device, computer equipment and a storage medium, the multi-node server access device comprises a back plate, a power supply unit and a plurality of node plates, each node plate comprises a first processor and a second processor, and the second processor is connected with the back plate through multiple universal input and output channels. The method comprises the following steps: acquiring in-place information of a plurality of node plates; configuration information is obtained from the first processor, and the second processor is controlled to configure universal input and output pin levels corresponding to the node plates according to the in-place information and the configuration information; reading the value of each universal input / output pin and respectively storing the value in a corresponding register; and determining whether the node plate has the access authority of the power supply unit or not according to the in-place information and the values of the plurality of registers in response to the node plate reading the values of the plurality of registers through the plurality of universal input and output channels. By adopting the method, the access conflict problem occurring when multiple nodes access the power supply unit at the same time can be solved.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a multi-node server access method, device, computer equipment and storage medium. Background Art

[0002] At present, commonly used power management technologies mainly include centralized management and distributed management. In centralized management, a central controller (such as the main BMC) is responsible for managing and allocating PSU (Power Supply Unit) access rights of all node boards. This method is simple in structure and easy to implement. However, once the central controller fails, the power management of the entire system will be affected. In distributed management, each node board has a BMC, which independently manages access rights to the PSU. This method improves the redundancy and reliability of the system, but also increases the complexity of the system. It is necessary to coordinate the work of multiple BMCs, which is prone to conflicts and inconsistencies.

[0003] In the PC-FARM field, since there are multiple nodes sharing one or several PSUs and each node has a BMC, I2C bus conflicts will occur when multiple nodes try to access the PSU at the same time, which also involves the problem of node failure and access by another node. Summary of the invention

[0004] Based on this, it is necessary to provide a multi-node server access method, device, computer equipment and storage medium that can avoid access conflicts in response to the above technical problems.

[0005] On the one hand, a method for accessing a multi-node server is provided, wherein the multi-node server comprises a backplane, a power supply unit and a plurality of node boards, wherein the node board comprises a first processor and a second processor, wherein the second processor is connected to the backplane via a plurality of universal input and output channels, wherein the universal input and output channels correspond to the node boards one by one, and the method comprises:

[0006] Acquiring the in-place information of the plurality of node plates;

[0007] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information;

[0008] Reading the values ​​of each general purpose input and output pin and storing them in corresponding registers respectively, wherein the registers correspond to the node boards one by one;

[0009] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers.

[0010] In one embodiment, the backplane includes a plurality of slots, and obtaining the in-place information of the plurality of node boards includes:

[0011] Obtaining slot numbers and in-place signals of the plurality of slots respectively through the second processor;

[0012] Whether the node plate is in place is judged according to the slot number and the in-place signal, and the position of the node plate is determined.

[0013] In one embodiment, controlling the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information includes:

[0014] In response to the node board being in place, controlling the second processor to set the corresponding general purpose input and output pin to a high level or a low level according to the configuration information;

[0015] In response to the node board being not in place, the second processor is controlled to set the corresponding general purpose input and output pin to a low level.

[0016] In one embodiment, in response to the node board reading the values ​​of multiple registers through the multi-way universal input and output channels, determining whether the node board has access rights to the power supply unit according to the in-place information and the values ​​of the multiple registers includes:

[0017] In response to the second processor reading the values ​​of the plurality of registers through the multi-way general purpose input and output channels, transmitting the values ​​of the plurality of registers and the in-place information of the plurality of node boards to the first processor of each node board;

[0018] Checking a watchdog timer of the first processor to determine whether the first processor is in a normal working state;

[0019] In response to the first processor being in a normal working state, determining in-place node boards and corresponding slot numbers according to the in-place information, and sorting the in-place node boards in ascending order according to the slot numbers;

[0020] Read the values ​​of the registers corresponding to the in-place node boards in sequence according to the sorting results;

[0021] In response to the register value being a first preset value, the in-place node board is used as a target node board, and the access rights of the power supply unit are allocated to the target node board, so that other node boards cannot access the power supply unit;

[0022] In response to the register value being the second preset value, the value of the register corresponding to the next in-place node board is read in sequence according to the sorting result.

[0023] In one embodiment, in response to the register value being a first preset value, taking the in-place node board as a target node board, and assigning the access rights of the power supply unit to the target node board, comprises:

[0024] Sending a first enable signal to a target second processor via a target first processor;

[0025] In response to the target second processor receiving the first enable signal, a second enable signal is sent to an integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

[0026] In one embodiment, the step of sequentially reading the values ​​of the registers corresponding to the in-place node boards according to the sorting results further includes:

[0027] In response to the register value being a second preset value, determining a target node board according to values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software;

[0028] The values ​​of the multiple registers are repeatedly obtained until the in-place node board obtains access rights to the power supply unit.

[0029] In one embodiment, the method further comprises:

[0030] In response to a watchdog exception of the target first processor, or the target first processor failing to regularly send a watchdog timer signal to the target second processor, determining that the target first processor fails;

[0031] Setting the corresponding general purpose input / output pin to a low level through the target second processor and resetting the second enable signal to release the access rights of the target first processor;

[0032] It is determined whether the next node board in place has access rights to the power supply unit according to the sorting result.

[0033] On the other hand, a multi-node server access device is provided, the device comprising:

[0034] A first acquisition module, used to acquire the in-place information of the plurality of node plates;

[0035] A configuration module, used to obtain configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information;

[0036] A second acquisition module is used to read the value of each general input and output pin and store them in a corresponding register, wherein the register corresponds to the node board one by one;

[0037] The control module is used for determining whether the node board has access rights to the power supply unit according to the in-place information and the values ​​of the multiple registers in response to the node board reading the values ​​of the multiple registers through the multiple universal input and output channels.

[0038] In another aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0039] Acquiring the in-place information of the plurality of node plates;

[0040] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information;

[0041] Reading the values ​​of each general purpose input and output pin and storing them in corresponding registers respectively, wherein the registers correspond to the node boards one by one;

[0042] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers.

[0043] In another aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0044] Acquiring the in-place information of the plurality of node plates;

[0045] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information;

[0046] Reading the values ​​of each general purpose input and output pin and storing them in corresponding registers respectively, wherein the registers correspond to the node boards one by one;

[0047] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers.

[0048] The above-mentioned multi-node server access method, device, computer equipment and storage medium integrate multiple GPIO channels as communication and arbitration media in the backplane circuit design. When multiple nodes access the PSU at the same time, by configuring the GPIO and reading the value of the corresponding register, it is possible to identify and specify which channel will play the master role of the I2C bus, thereby obtaining access rights to the PSU, ensuring that at any given moment, only one node can access one or more PSUs, solving the I2C bus conflict problem that occurs when multiple nodes access the PSU at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of the structure of a multi-node server in an embodiment;

[0050] Figure 2 A schematic diagram of a flow chart of a multi-node server access method in one embodiment;

[0051] Figure 3 A schematic diagram of a flow chart of a multi-node server access step in an embodiment;

[0052] Figure 4 A schematic diagram of the connection between SLOT_ID and PRESENT signals in one embodiment;

[0053] Figure 5 A structural block diagram of a multi-node server access device in one embodiment;

[0054] Figure 6 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0056] On the server motherboard, the common practice of powering nodes is to use PSU, which usually outputs +12V voltage to the node. The node accesses the PSU through I2C signals to read PSU power, voltage, current, temperature and other information. The node is the master device and the PSU is the slave device. If the line between the two is directly connected, when multiple nodes access the PSU at the same time, the slave device cannot identify which master device is accessing it, and an access conflict will occur, resulting in system diagnosis failure.

[0057] The present application integrates multiple GPIO (General Purpose Input Output) channels in the backplane circuit design. These channels are specifically used as communication and arbitration media. They can identify and specify which channel will play the master role of the I2C bus, thereby obtaining access rights to the PSU, ensuring that at any given moment, only one node can access one or more PSUs, and solving the I2C bus conflict problem that occurs when multiple nodes try to access multiple PSUs at the same time.

[0058] like Figure 1 As shown, the 4-node design of the PC-FARM 4U chassis is taken as an example for explanation. The system is mainly composed of a backplane, a node board and a PSU module. The node board integrates components such as the CPU, memory, BMC (Baseboard Management Controller), CPLD (Complex Programmable Logic Device), hard disk drive and various external interfaces. It should be noted that since some components are not directly related to the design core of the present invention, they are not all shown in the schematic diagram. In short, each node board is essentially equivalent to a compact personal computer. When multiple such node boards are combined together, an array is formed, thus forming a complete PC-FARM device.

[0059] In the present application, the first processor is BMC, the second processor is CPLD, each node board and PSU module are plugged into the backplane through corresponding connectors, and each node board is connected to four GPIO channels and SLOT ID signals, as well as PRESENT signals through CPLD. The I2C communication signal is connected to the backplane through I2C BUFFER (I2C buffer), and the enable control pin EN of I2C BUFFER is controlled by CPLD. In addition, BMC and CPLD are also connected through I2C0 channel and an indication signal EN_I2C for controlling I2C.

[0060] In one embodiment, Figure 2-4As shown, a multi-node server access method is provided, comprising the following steps:

[0061] Step S1, obtaining the in-place information of the plurality of node plates.

[0062] In an optional embodiment, the backplane includes multiple slots, and obtaining the presence information of the multiple node boards includes: obtaining the slot numbers and presence signals of the multiple slots respectively through the second processor; judging whether the node board is in place according to the slot numbers and the presence signals, and determining the position of the node board.

[0063] The slot number SLOT_ID is used to identify each slot and can be represented by two GPIOs, for example, 00, 01, 10, and 11 represent different slot information. The presence signal PRESENT is used to indicate whether a node board is inserted in a slot and can be represented by one GPIO. A high level 1 indicates not in place and a low level 0 indicates in place.

[0064] like Figure 4 As shown, both the slot label SLOT_ID and the presence signal PRESENT can be grounded at different slot pins on the backplane. The signals on the node board are connected to the power supply through pull-up resistors. When the node board is inserted into the slot, these pins will be pulled low. The second processor CPLD determines whether the node board is in place and the slot position by reading the status of these pins, ensuring that the node can accurately identify and locate the position where each node board should be.

[0065] Step S2, obtaining configuration information from the first processor, and controlling the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information.

[0066] In an optional embodiment, controlling the complex programmable logic device to configure the general input / output pin levels corresponding to each node board according to the in-place information and the configuration information includes: in response to the node board being in place, controlling the second processor to set the corresponding general input / output pin to a high level or a low level according to the configuration information; in response to the node board not being in place, controlling the second processor to set the corresponding general input / output pin to a low level.

[0067] Specifically, the system predefines the configuration information of each node board, including the functions of the node board and the required GPIO pins, etc., which are stored in the first processor BMC. The second processor CPLD reads the SLOT_ID and PRESENT signals, and configures the corresponding GPIO pin levels in combination with the configuration information passed by the BMC. Each node board can be flexibly configured and managed according to actual needs to adapt to different application scenarios and configuration requirements.

[0068] Preferably, the CPLD determines the working status of the BMC based on the signal received from the BMC, for example, confirming its function through means such as heartbeat monitoring and watchdog mechanism. When the BMC is operating normally, the CPLD will perform the corresponding GPIO setting operation. This ensures that the system can correctly configure the GPIO according to the status of the BMC, thereby preventing the BMC from freezing, resulting in no node being able to access the PSU and losing operation and maintenance information.

[0069] Step S3, reading the value of each general input and output pin and storing them in the corresponding register respectively, wherein the register corresponds to the node board one by one.

[0070] Specifically, the CPLD of each node reads the corresponding GPIO pin level and stores it in the corresponding register. For example, the register corresponding to node 0 is A0, and the register corresponding to node 1 is A1. The values ​​stored in these registers determine the access priority order of each node.

[0071] Step S4, in response to the node board reading the values ​​of multiple registers through the multi-way universal input and output channels, determining whether the node board has access rights to the power supply unit according to the in-place information and the values ​​of the multiple registers.

[0072] In an optional embodiment, in response to the node board reading the values ​​of multiple registers through the multi-way universal input and output channels, determining whether the node board has access rights to the power supply unit according to the in-place information and the values ​​of the multiple registers includes: in response to the second processor reading the values ​​of the multiple registers through the multi-way universal input and output channels, transmitting the values ​​of the multiple registers and the in-place information of the multiple node boards to the first processor of each node board; checking the watchdog timer of the first processor, and periodically sending a watchdog timer signal to the second processor through the first processor to determine whether the first processor is in in normal working state; in response to the first processor being in normal working state, determining the in-place node board and the corresponding slot number according to the in-place information, and sorting the in-place node boards from small to large according to the slot number; reading the values ​​of the registers corresponding to the in-place node boards in sequence according to the sorting result; in response to the value of the register being a first preset value, taking the in-place node board as the target node board, and assigning the access rights of the power supply unit to the target node board, so that other node boards cannot access the power supply unit; in response to the value of the register being a second preset value, reading the value of the register corresponding to the next in-place node board in sequence according to the sorting result.

[0073] For example, it is detected that nodes 0-3 are all in place. At this time, register A0 corresponding to node 0 is read first in the order of slot number. If the value of A0 is 1, node 0 preferentially uses the I2C bus to access the PSU. If the value of A0 is 0, register A1 corresponding to node 1 is read in sequence. Similarly, the value of A1 is used to determine whether node 1 has access rights to the PSU. Therefore, permission management and task scheduling can be performed more accurately at the software level.

[0074] Among them, multiple GPIO channels play the dual roles of communication and arbitration. Each CPLD reads the values ​​of all registers through multiple GPIO channels and passes them to BMC through I2C0. BMC determines which node is accessing PSU based on the values ​​of these registers and the corresponding SLOT_ID. Through this GPIO arbitration mechanism, not only is it ensured that only one node can access PSU at any time, but other nodes can also monitor in real time and know which node is currently performing the access operation, thereby solving the problem of multi-node access conflicts and improving the stability and security of the system.

[0075] In an optional embodiment, the configuration information also includes a priority value, and the priority value is used to control the second processor to configure one or more second general input and output pin levels corresponding to each node board, and the values ​​of the one or more second general input and output pin levels are stored in the corresponding second register; in response to the node board reading the values ​​of multiple registers through the multiple general input and output channels, determining whether the node board has access rights to the power supply unit according to the in-place information and the values ​​of the multiple registers, also includes: in response to the second processor reading the values ​​of the multiple second registers through the multiple general input and output channels, transmitting the values ​​of the multiple second registers and the in-place information of the multiple node boards to the first processor of each node board; obtaining the node board with the highest priority among the in-place node boards as the target node board according to the values ​​of the multiple second registers and the in-place information, and assigning the access rights of the power supply unit to the target node board; in response to the value of the second register changing, judging whether to reallocate the access rights according to the changed value.

[0076] In an optional embodiment, in response to the value of the register being a first preset value, the in-place node board is used as a target node board, and the access rights of the power supply unit are allocated to the target node board, including: sending a first enable signal to a target second processor through a target first processor; in response to the target second processor receiving the first enable signal, sending a second enable signal to an integrated circuit bus buffer, so that the target first processor can access the power supply unit through the integrated circuit bus buffer.

[0077] Specifically, for the target BMC that obtains access rights, EN_I2C, i.e., the first enable signal, is set to notify the CPLD that it needs to access I2C1. After obtaining the EN_I2C information, the CPLD sets EN, i.e., the second enable signal, thereby enabling the I2C BUFFER and allowing the target BMC to access the PSU, thereby completing the allocation of access rights to the PSU.

[0078] In an optional embodiment, the method of sequentially reading the values ​​of the registers corresponding to the in-place node boards according to the sorting results also includes: in response to the value of the register being a second preset value, determining a target node board according to the values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software; repeatedly obtaining the values ​​of the multiple registers until the in-place node board obtains access rights to the power supply unit.

[0079] Specifically, when node 0 obtains access rights to the PSU, the BMC of node 1 detects that the value of register A0 is 1, and it is considered that the BMC of node 0 is accessing the PSU, so node 1 no longer accesses the PSU to avoid conflicts. Therefore, through this GPIO arbitration mechanism, the BMCs of other nodes that have not obtained access rights can also understand which node is accessing the PSU, effectively solving the common I2C bus access conflict problem in multi-node systems. At the same time, this information can be updated to the BMC operation and maintenance software to facilitate equipment maintenance.

[0080] In an optional embodiment, the method also includes: in response to a watchdog exception of the target first processor, or the target first processor fails to regularly send a watchdog timer signal to the target second processor, determining that the target first processor has a fault; setting the corresponding general input and output pin to a low level by the target second processor, and resetting the second enable signal to release access rights to the target first processor; and determining whether the next in-place node board has access rights to the power supply unit based on the sorting result.

[0081] Specifically, by monitoring the working status of BMC, it is possible to eliminate the resource occupation of abnormal BMCs. At the same time, it also ensures that the system can correctly configure GPIO according to the status of BMC, prevent the BMC from freezing and causing no node to access PSU, avoid loss of operation and maintenance information, and enhance system stability.

[0082] It should be understood that although Figure 2-3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2-3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0083] In one embodiment, Figure 5 As shown, a multi-node server access device is provided, including: a first acquisition module, a configuration module, a second acquisition module and a control module, wherein:

[0084] A first acquisition module, used to acquire the in-place information of the plurality of node plates;

[0085] A configuration module, used to obtain configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information;

[0086] A second acquisition module is used to read the value of each general input and output pin and store them in a corresponding register, wherein the register corresponds to the node board one by one;

[0087] The control module is used for determining whether the node board has access rights to the power supply unit according to the in-place information and the values ​​of the multiple registers in response to the node board reading the values ​​of the multiple registers through the multiple universal input and output channels.

[0088] In one embodiment, the first acquisition module is further used to respectively acquire the slot numbers and in-place signals of the multiple slots through the second processor; determine whether the node board is in place according to the slot numbers and the in-place signals, and determine the position of the node board.

[0089] In one embodiment, the configuration module is also used to control the second processor to set the corresponding general input and output pin to a high level or a low level according to the configuration information in response to the node board being in place; and to control the second processor to set the corresponding general input and output pin to a low level in response to the node board not being in place.

[0090] In one embodiment, the control module is also used to transmit the values ​​of the multiple registers and the in-place information of the multiple node boards to the first processor of each node board in response to the second processor reading the values ​​of the multiple registers through the multi-way general input and output channels; check the watchdog timer of the first processor, and periodically send a watchdog timer signal to the second processor through the first processor to determine whether the first processor is in a normal working state; in response to the first processor being in a normal working state, determine the in-place node board and the corresponding slot number according to the in-place information, and sort the in-place node boards from small to large according to the slot number; read the values ​​of the registers corresponding to the in-place node boards in sequence according to the sorting result, and determine whether the value of the register is 1; in response to the value of the register being 1, use the in-place node board as the target node board, and assign the access rights of the power supply unit to the target node board, so that other node boards cannot access the power supply unit; in response to the value of the register being 0, read the value of the register corresponding to the next in-place node board in sequence according to the sorting result.

[0091] In one embodiment, the control module is also used to send a first enable signal to a target second processor through a target first processor; in response to the target second processor receiving the first enable signal, send a second enable signal to an integrated circuit bus buffer so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

[0092] In one embodiment, the control module is also used to respond to the value of the register being 0, determine the target node board according to the values ​​of other registers, and display the slot number of the target node board on the operation and maintenance software; repeatedly obtain the values ​​of the multiple registers until the in-place node board obtains access rights to the power supply unit.

[0093] In one embodiment, the device also includes a reset module, which is used to respond to a watchdog exception of the target first processor, or the target first processor fails to send a watchdog timer signal to the target second processor, to determine that the target first processor has a fault; set the corresponding general input and output pin to a low level through the target second processor, and reset the second enable signal, so that the target first processor cannot access the power supply unit; and determine whether the next in-place node board has access to the power supply unit based on the sorting result.

[0094] For the specific definition of the multi-node server access device, please refer to the definition of the multi-node server access method above, which will not be repeated here. Each module in the above multi-node server access device can be implemented in whole or in part by software, hardware and a combination thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0095] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 6 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store GPIO register data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a multi-node server access method is implemented.

[0096] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0097] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0098] Acquiring the in-place information of the plurality of node plates;

[0099] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information;

[0100] Reading the values ​​of each general purpose input and output pin and storing them in corresponding registers respectively, wherein the registers correspond to the node boards one by one;

[0101] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers.

[0102] In one embodiment, when the processor executes the computer program, the following steps are also implemented: obtaining the slot numbers and in-place signals of the multiple slots respectively through the second processor; judging whether the node board is in place according to the slot numbers and the in-place signals, and determining the position of the node board.

[0103] In one embodiment, when the processor executes the computer program, the following steps are also implemented: in response to the node board being in place, controlling the second processor to set the corresponding general input and output pin to a high level or a low level according to the configuration information; in response to the node board not being in place, controlling the second processor to set the corresponding general input and output pin to a low level.

[0104] In one embodiment, when the processor executes the computer program, the following steps are also implemented: in response to the second processor reading the values ​​of the multiple registers through the multi-way universal input and output channels, the values ​​of the multiple registers and the in-place information of the multiple node boards are transmitted to the first processor of each node board; the watchdog timer of the first processor is checked, and a watchdog timer signal is periodically sent to the second processor through the first processor to determine whether the first processor is in a normal working state; in response to the first processor being in a normal working state, the in-place node board and the corresponding slot number are determined according to the in-place information, and the in-place node boards are sorted from small to large according to the slot number; according to the sorting result, the values ​​of the registers corresponding to the in-place node boards are read in sequence, and it is determined whether the values ​​of the registers are 1; in response to the value of the register being 1, the in-place node board is used as the target node board, and the access rights of the power supply unit are assigned to the target node board, so that other node boards cannot access the power supply unit; in response to the value of the register being 0, the values ​​of the registers corresponding to the next in-place node board are read in sequence according to the sorting result.

[0105] In one embodiment, when the processor executes the computer program, the following steps are also implemented: sending a first enable signal to a target second processor through a target first processor; in response to the target second processor receiving the first enable signal, sending a second enable signal to an integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

[0106] In one embodiment, when the processor executes the computer program, the following steps are also implemented: in response to the value of the register being 0, determining the target node board according to the values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software; repeatedly obtaining the values ​​of the multiple registers until the in-place node board obtains access rights to the power supply unit.

[0107] In one embodiment, the processor further implements the following steps when executing the computer program: in response to a watchdog exception of the target first processor, or the target first processor failing to regularly send a watchdog timer signal to the target second processor, determining that the target first processor has failed; setting the corresponding general input / output pin to a low level through the target second processor, and resetting the second enable signal to release access rights to the target first processor; and determining whether the next in-place node board has access rights to the power supply unit based on the sorting result.

[0108] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0109] Acquiring the in-place information of the plurality of node plates;

[0110] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information;

[0111] Reading the values ​​of each general purpose input and output pin and storing them in corresponding registers respectively, wherein the registers correspond to the node boards one by one;

[0112] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers.

[0113] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the slot numbers and in-place signals of the multiple slots are respectively obtained by the second processor; whether the node board is in place is determined based on the slot numbers and the in-place signals, and the position of the node board is determined.

[0114] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the node board being in place, controlling the second processor to set the corresponding general input and output pin to a high level or a low level according to the configuration information; in response to the node board not being in place, controlling the second processor to set the corresponding general input and output pin to a low level.

[0115] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the second processor reading the values ​​of the multiple registers through the multiple universal input and output channels, the values ​​of the multiple registers and the in-place information of the multiple node boards are transmitted to the first processor of each node board; the watchdog timer of the first processor is checked, and a watchdog timer signal is periodically sent to the second processor through the first processor to determine whether the first processor is in a normal working state; in response to the first processor being in a normal working state, the in-place node board and the corresponding slot number are determined according to the in-place information, and the in-place node boards are sorted from small to large according to the slot number; according to the sorting result, the values ​​of the registers corresponding to the in-place node boards are read in sequence, and it is determined whether the values ​​of the registers are 1; in response to the value of the register being 1, the in-place node board is used as the target node board, and the access rights of the power supply unit are assigned to the target node board, so that other node boards cannot access the power supply unit; in response to the value of the register being 0, the values ​​of the registers corresponding to the next in-place node board are read in sequence according to the sorting result.

[0116] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: sending a first enable signal to a target second processor through a target first processor; in response to the target second processor receiving the first enable signal, sending a second enable signal to an integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

[0117] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the value of the register being 0, determining the target node board according to the values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software; repeatedly obtaining the values ​​of the multiple registers until the in-place node board obtains access rights to the power supply unit.

[0118] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to a watchdog exception of the target first processor, or the target first processor fails to regularly send a watchdog timer signal to the target second processor, determining that the target first processor has a fault; setting the corresponding general input and output pin to a low level through the target second processor, and resetting the second enable signal to release access rights to the target first processor; and determining whether the next in-place node board has access rights to the power supply unit based on the sorting result.

[0119] In one embodiment, a computer product is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0120] Acquiring the in-place information of the plurality of node plates;

[0121] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information;

[0122] Reading the values ​​of each general purpose input and output pin and storing them in corresponding registers respectively, wherein the registers correspond to the node boards one by one;

[0123] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers.

[0124] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the slot numbers and in-place signals of the multiple slots are respectively obtained by the second processor; whether the node board is in place is determined based on the slot numbers and the in-place signals, and the position of the node board is determined.

[0125] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the node board being in place, controlling the second processor to set the corresponding general input and output pin to a high level or a low level according to the configuration information; in response to the node board not being in place, controlling the second processor to set the corresponding general input and output pin to a low level.

[0126] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the second processor reading the values ​​of the multiple registers through the multiple universal input and output channels, the values ​​of the multiple registers and the in-place information of the multiple node boards are transmitted to the first processor of each node board; the watchdog timer of the first processor is checked, and a watchdog timer signal is periodically sent to the second processor through the first processor to determine whether the first processor is in a normal working state; in response to the first processor being in a normal working state, the in-place node board and the corresponding slot number are determined according to the in-place information, and the in-place node boards are sorted from small to large according to the slot number; according to the sorting result, the values ​​of the registers corresponding to the in-place node boards are read in sequence, and it is determined whether the values ​​of the registers are 1; in response to the value of the register being 1, the in-place node board is used as the target node board, and the access rights of the power supply unit are assigned to the target node board, so that other node boards cannot access the power supply unit; in response to the value of the register being 0, the values ​​of the registers corresponding to the next in-place node board are read in sequence according to the sorting result.

[0127] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: sending a first enable signal to a target second processor through a target first processor; in response to the target second processor receiving the first enable signal, sending a second enable signal to an integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

[0128] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the value of the register being 0, determining the target node board according to the values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software; repeatedly obtaining the values ​​of the multiple registers until the in-place node board obtains access rights to the power supply unit.

[0129] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to a watchdog exception of the target first processor, or the target first processor fails to regularly send a watchdog timer signal to the target second processor, determining that the target first processor has a fault; setting the corresponding general input and output pin to a low level through the target second processor, and resetting the second enable signal to release access rights to the target first processor; and determining whether the next in-place node board has access rights to the power supply unit based on the sorting result.

[0130] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0131] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A multi-node server access method, characterized in that: The multi-node server comprises a backplane, a power supply unit and a plurality of node boards, the node board comprises a first processor and a second processor, the second processor is connected to the backplane via a plurality of universal input and output channels, wherein the universal input and output channels correspond to the node boards one by one, and the method comprises: Acquiring the in-place information of the plurality of node plates; Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information; Reading the values ​​of each general purpose input and output pin and storing them in corresponding registers respectively, wherein the registers correspond to the node boards one by one; In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers.

2. The multi-node server access method according to claim 1, characterized in that: The backplane includes a plurality of slots, and the acquiring the in-place information of the plurality of node boards includes: Obtaining slot numbers and in-place signals of the plurality of slots respectively through the second processor; Whether the node plate is in place is judged according to the slot number and the in-place signal, and the position of the node plate is determined.

3. The multi-node server access method according to claim 1 or 2, characterized in that: The controlling the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information includes: In response to the node board being in place, controlling the second processor to set the corresponding general purpose input and output pin to a high level or a low level according to the configuration information; In response to the node board being not in place, the second processor is controlled to set the corresponding general purpose input and output pin to a low level.

4. The multi-node server access method according to claim 2, characterized in that: In response to the node board reading the values ​​of the multiple registers through the multi-way universal input and output channels, determining whether the node board has access rights to the power supply unit according to the in-place information and the values ​​of the multiple registers includes: In response to the second processor reading the values ​​of the plurality of registers through the multi-way general purpose input and output channels, transmitting the values ​​of the plurality of registers and the in-place information of the plurality of node boards to the first processor of each node board; Checking a watchdog timer of the first processor, and periodically sending a watchdog timer signal to the second processor through the first processor to determine whether the first processor is in a normal working state; In response to the first processor being in a normal working state, determining in-place node boards and corresponding slot numbers according to the in-place information, and sorting the in-place node boards in ascending order according to the slot numbers; Read the values ​​of the registers corresponding to the in-place node boards in sequence according to the sorting results; In response to the register value being a first preset value, the in-place node board is used as a target node board, and the access rights of the power supply unit are allocated to the target node board, so that other node boards cannot access the power supply unit; In response to the register value being the second preset value, the value of the register corresponding to the next in-place node board is read in sequence according to the sorting result.

5. The multi-node server access method according to claim 4, characterized in that: In response to the register value being a first preset value, taking the in-place node board as a target node board, and assigning the access rights of the power supply unit to the target node board, comprises: Sending a first enable signal to a target second processor via a target first processor; In response to the target second processor receiving the first enable signal, a second enable signal is sent to an integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

6. The multi-node server access method according to claim 4, characterized in that: The step of sequentially reading the values ​​of the registers corresponding to the in-place node boards according to the sorting results also includes: In response to the register value being a second preset value, determining a target node board according to values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software; The values ​​of the multiple registers are repeatedly obtained until the in-place node board obtains access rights to the power supply unit.

7. The multi-node server access method according to claim 5, characterized in that: The method further comprises: In response to a watchdog exception of the target first processor, or the target first processor failing to regularly send a watchdog timer signal to the target second processor, determining that the target first processor fails; Setting the corresponding general purpose input / output pin to a low level through the target second processor and resetting the second enable signal to release the access rights of the target first processor; It is determined whether the next node board in place has access rights to the power supply unit according to the sorting result.

8. A multi-node server access device, applied to the multi-node server access method described in right 1, characterized in that: The device comprises: A first acquisition module, used to acquire the in-place information of the plurality of node plates; A configuration module, used to obtain configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-place information and the configuration information; A second acquisition module is used to read the value of each general input and output pin and store them in a corresponding register, wherein the register corresponds to the node board one by one; The control module is used for determining whether the node board has access rights to the power supply unit according to the in-place information and the values ​​of the multiple registers in response to the node board reading the values ​​of the multiple registers through the multiple universal input and output channels.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images