Parallel charging circuit for double-channel Type-C interface

Abstract

The utility model provides a parallel charging circuit for a double-channel Type-C interface, which comprises a main equipment power supply in power supply connection with a parallel charging main control circuit, and the parallel charging main control circuit is in control connection with a Type-C0 interface circuit and a Type-C1 interface circuit. The output end of the Type-C0 interface circuit and the output end of the Type-C1 interface circuit are in feedback connection with the input end of the parallel charging main control circuit, the output end of the Type-C0 interface circuit and the output end of the Type-C1 interface circuit are further connected with the input end of the 20V limiting charging circuit, and the output end of the 20V limiting charging circuit is in power supply connection with the main equipment power supply. The Type-C interface parallel charging device has the beneficial effects that parallel charging of the two Type-C interfaces can be realized, the supply chain stability risk and the production cost are reduced, and the two-way power supply stability and the system reliability are improved.

Description

Technical Field

[0001] This utility model relates to the field of detection circuit technology, specifically to a parallel charging circuit for dual Type-C interfaces. Background Technology

[0002] Type-C is a type of USB interface that can be inserted in either direction. It measures approximately 8.3mm x 2.5mm and, like other interfaces, supports USB standard functions such as charging, data transfer, and display output. Type-C was developed by the USB Implementers Forum and began to gain widespread adoption after receiving support from manufacturers such as Apple, Google, Intel, and Microsoft in 2014.

[0003] Currently, mainstream Type-C fast charging solutions generally use imported chip combinations, such as Type-C controllers based on American TI series chips or British Flyton Cypress series chips, paired with ITE series EC chips, and products with such chip combinations generally have multiple Type-C interfaces.

[0004] In daily use, not everyone is familiar with the multiple Type-C ports on these chip-based products. Often, users may simultaneously plug multiple high-power adapters into multiple Type-C ports to charge other electronic devices. This can lead to overload, crashes, or even hardware damage to the electronic devices using these ports. Furthermore, these electronic devices employing imported chip combinations also have the following drawbacks:

[0005] 1. It heavily relies on imported chips, posing risks to supply chain stability and resulting in persistently high costs;

[0006] 2. Imported Type-C controllers cannot be independently expanded due to their closed source code, making it difficult to resolve conflicts that arise during parallel charging of dual Type-C interfaces. This necessitates relying on custom firmware from imported original manufacturers, resulting in poor compatibility and significantly increased development costs. Utility Model Content

[0007] To address the problems in existing technologies, this utility model provides a parallel charging circuit for dual Type-C interfaces. By incorporating a cooperating main device power supply, a parallel charging main control circuit, a Type-C0 interface circuit, a Type-C1 interface circuit, and a 20V limiting charging circuit, the parallel charging main control circuit can control the output power of the Type-C0 and Type-C1 interface circuits based on their connection status. The 20V limiting charging circuit restricts the minimum voltage for the Type-C0 and Type-C1 interface circuits to operate as main device power supplies and for charging to 20V. This enables parallel charging of dual Type-C interfaces, significantly reducing supply chain stability risks and production costs, and greatly improving the stability and reliability of dual power supply. It also solves the problems of parallel charging conflicts and high production and development costs associated with imported chip combinations in existing Type-C fast charging solutions.

[0008] This utility model provides a parallel charging circuit for dual Type-C interfaces, including a main device power supply, a parallel charging main control circuit, a Type-C0 interface circuit, a Type-C1 interface circuit, and a 20V limiting charging circuit. The output terminal of the main device power supply is connected to the parallel charging main control circuit for power supply. The output terminal of the parallel charging main control circuit is controlled to be connected to the input terminals of the Type-C0 interface circuit and the Type-C1 interface circuit. The output terminals of the Type-C0 interface circuit and the Type-C1 interface circuit can both be connected to external Type-C interface electronic devices. The output terminals of the Type-C0 and Type-C1 interface circuits are also fed back to the input terminal of the parallel charging main control circuit. The output terminals of the Type-C0 and Type-C1 interface circuits are also connected to the input terminal of the 20V limiting charging circuit. The output terminal of the 20V limiting charging circuit is connected to the main device power supply. The parallel charging main control circuit can control the output power of the Type-C0 and Type-C1 interface circuits according to their connection status.

[0009] This utility model is further improved by including a main control chip U11 in the parallel charging main control circuit. The main control chip U11 has 124 pins. Pins 11, 26, 50, 92, 114, 121, and 127 of the main control chip U11 are connected to the output terminal of the main device power supply. Pins 110 and 111 of the main control chip U11 are connected to the input terminals of the Type-C0 interface circuit and the Type-C1 interface circuit, respectively. Pin 56 of the main control chip U11 is connected to the output terminal of the Type-C0 interface circuit, and pin 73 of the main control chip U11 is connected to the output terminal of the Type-C1 interface circuit.

[0010] This utility model is further improved by including a Type-C control chip U12 in the Type-C0 interface circuit. The Type-C control chip U12 has 48 pins. Pins 37 and 38 of the Type-C control chip U12 are connected to pins 111 and 110 of the main control chip U11, respectively. Pin 40 of the Type-C control chip U12 is connected to pin 56 of the main control chip U11. Pin 35 of the Type-C control chip U12 is connected to the input terminal of the 20V limiting charging circuit. Pin 23 of the Type-C control chip U12 can be connected to power an external Type-C interface electronic device.

[0011] This utility model is further improved by including a Type-C control chip U13 in the Type-C1 interface circuit. The Type-C control chip U13 has 48 pins. Pins 37 and 38 of the Type-C control chip U13 are connected to pins 111 and 110 of the main control chip U11, respectively. Pin 40 of the Type-C control chip U13 is connected to pin 56 of the main control chip U11. Pin 35 of the Type-C control chip U13 is connected to the input terminal of the 20V limiting charging circuit. Pin 23 of the Type-C control chip U13 can be connected to power an external Type-C interface electronic device.

[0012] This utility model is further improved by including a field-effect transistor (FET) Q38, a field-effect transistor (FET) Q39, a field-effect transistor (FET) Q40, a field-effect transistor (FET) Q41, and resistors R165, R166, R167, R168, and R169 within the 20V charging circuit. The source of FET Q39 is connected to one end of resistor R166, pin 35 of Type-C control chip U12, and pin 35 of Type-C control chip U13. The gate of FET Q39 is connected to the other end of resistor R166 and one end of resistor R167. The drain of FET Q39 is connected to the drain of FET Q38. The source of the field-effect transistor Q38 is connected to one end of the resistor R165 and the main power supply. The gate of the field-effect transistor Q38 is connected to the other end of the resistor R165 and one end of the resistor R168. The other end of the resistor R168 is connected to the drain of the field-effect transistor Q41. The other end of the resistor R167 is connected to the drain of the field-effect transistor Q40. The gate of the field-effect transistor Q40 is connected to the gate of the field-effect transistor Q41 and one end of the resistor R169. The other end of the resistor R169 is connected to the main power supply. The sources of the field-effect transistors Q40 and Q41 are grounded.

[0013] This utility model is further improved, and the main control chip U11 is model FIC6288I.

[0014] This utility model is further improved in that the Type-C control chip U12 and the Type-C control chip U13 are both model ANX7447QN-AC-R.

[0015] Compared with the prior art, the beneficial effects of this utility model are: it provides a parallel charging circuit for dual Type-C interfaces. By setting up a cooperating main device power supply, a parallel charging main control circuit, a Type-C0 interface circuit, a Type-C1 interface circuit, and a 20V limiting charging circuit in the parallel charging circuit for dual Type-C interfaces, the parallel charging main control circuit can control the output power of the Type-C0 and Type-C1 interface circuits according to their connection status. The 20V limiting charging circuit can limit the minimum voltage for the Type-C0 and Type-C1 interface circuits to operate as main device power supplies and for charging to 20V, thus enabling dual Type-C interfaces to operate and charge. Parallel charging via the Type-C interface utilizes a domestically produced chip combination. The EC chip is the FIC6288I from Yihe Microelectronics, and the Type-C controller is the ANX7447QN-AC-R. This eliminates reliance on imported chips, significantly reducing supply chain stability risks and production costs. Based on the ANX7447QN-AC-R Type-C controller, the manufacturer provides an open-source architecture, which can flexibly resolve conflicts when charging two Type-C interfaces in parallel. This eliminates the need for customized firmware from the original manufacturer, significantly improving product compatibility and reducing development costs. It also greatly enhances the stability and reliability of dual-power supply, solving the problems of parallel charging conflicts and high production and development costs associated with imported chip combinations in existing Type-C fast charging solutions. Attached Figure Description

[0016] To more clearly illustrate the solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a parallel charging circuit for dual Type-C interfaces according to the present invention.

[0018] Figure 2 The circuit diagram is of the parallel charging main control circuit of this utility model.

[0019] Figure 3 This is a circuit diagram of the Type-C0 interface circuit of this utility model;

[0020] Figure 4 This is a circuit diagram of the Type-C1 interface circuit of this utility model;

[0021] Figure 5 This is a circuit diagram of the 20V charging circuit of this utility model. Detailed Implementation

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this invention are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or accompanying drawings of this invention are used to distinguish different objects, not to describe a particular order.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0025] like Figures 1-5As shown, this utility model provides a parallel charging circuit for dual Type-C interfaces, including a main device power supply, a parallel charging main control circuit, a Type-C0 interface circuit, a Type-C1 interface circuit, and a 20V limiting charging circuit. The output terminal of the main device power supply is connected to the parallel charging main control circuit for power supply. The output terminal of the parallel charging main control circuit is connected to the input terminals of the Type-C0 and Type-C1 interface circuits for control. The output terminals of the Type-C0 and Type-C1 interface circuits can both be connected to external Type-C interface electronic devices. The output terminals of the Type-C0 and Type-C1 interface circuits are also connected to the input terminal of the parallel charging main control circuit for feedback. The output terminals of the Type-C0 and Type-C1 interface circuits are also connected to the input terminal of the 20V limiting charging circuit. The output terminal of the 20V limiting charging circuit is connected to the main device power supply for power supply. In this embodiment, when the main device power supply supplies power and charges external Type-C interface electronic devices through the Type-C0 and Type-C1 interface circuits, the parallel charging main control circuit can control the output power of the Type-C0 and Type-C1 interface circuits according to their connection status. When only the Type-C0 interface is connected to the external Type-C interface electronic device, the charging power of the Type-C0 interface is set to 20V*5A=100W. When only the Type-C1 interface is connected to the external Type-C interface electronic device, the charging power of the Type-C1 interface is set to 20V*5A=100W. When both the Type-C0 and Type-C1 interfaces are connected to the external Type-C interface electronic device, the Type-C0 interface is given high priority by default, and its charging power is set to 20V*5A=100W, while the charging power of the Type-C1 interface is set to 5V*0.9A=4.5W. When the main device power supply is charged and powered by an external power source through the Type-C0 and Type-C1 interface circuits, the 20V limiting charging circuit can limit the minimum voltage for the Type-C0 and Type-C1 interface circuits to operate and charge the main device power supply to 20V. This enables parallel charging of the dual Type-C interfaces, significantly reducing supply chain stability risks and production costs, and greatly improving the stability and system reliability of the dual power supply.

[0026] like Figure 2As shown, the parallel charging main control circuit includes a main control chip U11, model FIC6288I. The main control chip U11 has 124 pins. Pins 11, 26, 50, 92, 114, 121, and 127 of the main control chip U11 are connected to the output of the main device power supply. Pins 110 and 111 of the main control chip U11 are connected to the input of the Type-C0 interface circuit and the input of the Type-C1 interface circuit, respectively. Pin 56 of the main control chip U11 is connected to the output of the Type-C0 interface circuit, and pin 73 of the main control chip U11 is connected to the output of the Type-C1 interface circuit. In this embodiment, when the main device power supply supplies power and charges external Type-C interface electronic devices through the Type-C0 and Type-C1 interface circuits, the parallel charging main control circuit controls the output power of the Type-C0 and Type-C1 interface circuits according to their connection status. When only the Type-C0 interface is connected to the external Type-C interface electronic device, the charging power of the Type-C0 interface is set to 20V*5A=100W. When only the Type-C1 interface is connected to the external Type-C interface electronic device, the charging power of the Type-C1 interface is set to 20V*5A=100W. When both the Type-C0 and Type-C1 interfaces are connected to the external Type-C interface electronic device, the Type-C0 interface is given high priority by default, and its charging power is set to 20V*5A=100W, while the charging power of the Type-C1 interface is set to 5V*0.9A=4.5W.

[0027] like Figures 3-4As shown, the Type-C0 interface circuit includes a Type-C control chip U12, model ANX7447QN-AC-R. The Type-C control chip U12 has 48 pins. Pins 37 and 38 of the Type-C control chip U12 are connected to pins 111 and 110 of the main control chip U11, respectively. Pin 40 of the Type-C control chip U12 is connected to pin 56 of the main control chip U11. Pin 35 of the Type-C control chip U12 is connected to the input of the 20V charging circuit. Pin 23 of the Type-C control chip U12 can be connected to the power supply of external Type-C interface electronic devices. The Type-C1 interface circuit contains a Type-C control chip U13, model ANX7447QN-AC-R. The Type-C control chip U13 has 48 pins. Pins 37 and 38 of the Type-C control chip U13 are connected to pins 111 and 110 of the main control chip U11, respectively. Pin 40 of the Type-C control chip U13 is connected to pin 56 of the main control chip U11. Pin 35 of the Type-C control chip U13 is connected to the input of the 20V charging circuit. Pin 23 of the Type-C control chip U13 can be connected to power external Type-C interface electronic devices. In this embodiment, the Type-C0 interface circuit and the Type-C1 interface circuit are used to adjust the output power to external Type-C interface electronic devices according to the control instructions of the parallel charging main control circuit. When only the Type-C0 interface is connected to an external Type-C interface electronic device, the charging power of the Type-C0 interface is set to 20V*5A=100W. When only the Type-C1 interface is connected to an external Type-C interface electronic device, the charging power of the Type-C1 interface is set to 20V*5A=100W. When both the Type-C0 and Type-C1 interfaces are connected to external Type-C interface electronic devices, the Type-C0 interface is given high priority by default, and the charging power of the Type-C0 interface is set to 20V*5A=100W, while the charging power of the Type-C1 interface is set to 5V*0.9A=4.5W.

[0028] like Figure 5As shown, the 20V charging circuit includes MOSFETs Q38, Q39, Q40, and Q41, as well as resistors R165, R166, R167, R168, and R169. The source of MOSFET Q39 is connected to one end of resistor R166, pin 35 of Type-C control chip U12, and pin 35 of Type-C control chip U13. The gate of MOSFET Q39 is connected to the other end of resistor R166 and one end of resistor R167. The drain of MOSFET Q39 is connected to the... The drains of MOSFET Q38 are connected. The source of MOSFET Q38 is connected to one end of resistor R165 and the main device power supply. The gate of MOSFET Q38 is connected to the other end of resistor R165 and one end of resistor R168. The other end of resistor R168 is connected to the drain of MOSFET Q41. The other end of resistor R167 is connected to the drain of MOSFET Q40. The gate of MOSFET Q40 is connected to the gate of MOSFET Q41 and one end of resistor R169. The other end of resistor R169 is connected to the main device power supply. The sources of MOSFET Q40 and MOSFET Q41 are grounded. In this embodiment, when the main device power supply is charged by an external power source through the Type-C0 and Type-C1 interface circuits, the 20V charging limit circuit is used to limit the minimum voltage for the Type-C0 and Type-C1 interface circuits to operate and charge the main device power supply to 20V.

[0029] As can be seen from the above, this utility model provides a parallel charging circuit for dual Type-C interfaces. By setting up a cooperating main device power supply, a parallel charging main control circuit, a Type-C0 interface circuit, a Type-C1 interface circuit, and a 20V limiting charging circuit in the parallel charging circuit for dual Type-C interfaces, the parallel charging main control circuit can control the output power of the Type-C0 and Type-C1 interface circuits according to their connection status. The 20V limiting charging circuit can limit the minimum voltage for the Type-C0 and Type-C1 interface circuits to operate as main device power supplies and for charging to 20V, thus enabling dual Type-C interfaces... The parallel charging of the two Type-C ports utilizes a domestically produced chip combination. The EC chip is the FIC6288I from Yihe Microelectronics, and the Type-C controller is the ANX7447QN-AC-R. This eliminates the need to rely on imported chips, significantly reducing supply chain stability risks and production costs. Based on the ANX7447QN-AC-R Type-C controller, the manufacturer provides an open-source architecture that can flexibly resolve conflicts when charging two Type-C ports in parallel. This eliminates the need for customized firmware from the original manufacturer, significantly improving product compatibility and reducing development costs. It also greatly enhances the stability and reliability of dual-power supply, solving the problems of parallel charging conflicts and high production and development costs associated with imported chip combinations in existing Type-C fast charging solutions.

[0030] The specific embodiments described above are preferred embodiments of this utility model, and are not intended to limit the specific scope of this utility model. The scope of this utility model includes but is not limited to the specific embodiments described above. All equivalent changes made in accordance with this utility model are within the protection scope of this utility model.

Claims

1. A parallel charging circuit for dual Type-C interfaces, characterized in that: The device includes a main power supply, a parallel charging main control circuit, a Type-C0 interface circuit, a Type-C1 interface circuit, and a 20V limiting charging circuit. The output of the main power supply is connected to the parallel charging main control circuit. The output of the parallel charging main control circuit is connected to the inputs of the Type-C0 and Type-C1 interface circuits. The outputs of the Type-C0 and Type-C1 interface circuits can connect to external Type-C interface electronic devices. The outputs of the Type-C0 and Type-C1 interface circuits are also connected to the input of the parallel charging main control circuit. The outputs of the Type-C0 and Type-C1 interface circuits are also connected to the input of the 20V limiting charging circuit. The output of the 20V limiting charging circuit is connected to the main power supply. The parallel charging main control circuit can control the output power of the Type-C0 and Type-C1 interface circuits according to their connection status.

2. The parallel charging circuit for dual Type-C interfaces according to claim 1, characterized in that: The parallel charging main control circuit includes a main control chip U11 with 124 pins. Pins 11, 26, 50, 92, 114, 121, and 127 of the main control chip U11 are connected to the output of the main device power supply. Pins 110 and 111 of the main control chip U11 are connected to the input of the Type-C0 interface circuit and the input of the Type-C1 interface circuit, respectively. Pin 56 of the main control chip U11 is connected to the output of the Type-C0 interface circuit, and pin 73 of the main control chip U11 is connected to the output of the Type-C1 interface circuit.

3. The parallel charging circuit for dual Type-C interfaces according to claim 2, characterized in that: The Type-C0 interface circuit includes a Type-C control chip U12 with 48 pins. Pins 37 and 38 of the Type-C control chip U12 are connected to pins 111 and 110 of the main control chip U11, respectively. Pin 40 of the Type-C control chip U12 is connected to pin 56 of the main control chip U11. Pin 35 of the Type-C control chip U12 is connected to the input terminal of the 20V charging circuit. Pin 23 of the Type-C control chip U12 can be connected to power external Type-C interface electronic devices.

4. The parallel charging circuit for dual Type-C interfaces according to claim 3, characterized in that: The Type-C1 interface circuit includes a Type-C control chip U13 with 48 pins. Pins 37 and 38 of the Type-C control chip U13 are connected to pins 111 and 110 of the main control chip U11, respectively. Pin 40 of the Type-C control chip U13 is connected to pin 56 of the main control chip U11. Pin 35 of the Type-C control chip U13 is connected to the input terminal of the 20V charging circuit. Pin 23 of the Type-C control chip U13 can be connected to power external Type-C interface electronic devices.

5. The parallel charging circuit for dual Type-C interfaces according to claim 4, characterized in that: The 20V charging circuit includes field-effect transistors Q38, Q39, Q40, and Q41, as well as resistors R165, R166, R167, R168, and R169. The source of field-effect transistor Q39 is connected to one end of resistor R166, pin 35 of Type-C control chip U12, and pin 35 of Type-C control chip U13. The gate of field-effect transistor Q39 is connected to the other end of resistor R166 and one end of resistor R167. The drain of field-effect transistor Q39 is connected to the drain of field-effect transistor Q38. The source of transistor Q38 is connected to one end of resistor R165 and the main power supply of the device. The gate of transistor Q38 is connected to the other end of resistor R165 and one end of resistor R168. The other end of resistor R168 is connected to the drain of transistor Q41. The other end of resistor R167 is connected to the drain of transistor Q40. The gate of transistor Q40 is connected to the gate of transistor Q41 and one end of resistor R169. The other end of resistor R169 is connected to the main power supply of the device. The sources of transistors Q40 and Q41 are grounded.

6. The parallel charging circuit for dual Type-C interfaces according to claim 5, characterized in that: The main control chip U11 is model FIC6288I.

7. The parallel charging circuit for dual Type-C interfaces according to claim 6, characterized in that: The Type-C control chip U12 and the Type-C control chip U13 are both model ANX7447QN-AC-R.

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