Relaxation oscillator with temperature compensation and application thereof

Abstract

The invention discloses a relaxation oscillator with temperature compensation and application thereof.The relaxation oscillator comprises a first bias module, a second bias module, an oscillation module and a clock signal output module, the first bias module generates a first bias current and outputs a first bias voltage, the second bias module generates a second bias current and outputs a second bias voltage, the oscillation module generates a reset pulse irrelevant to temperature, and the clock signal output module is connected to the oscillation module and configured to be used for generating a charge-discharge control signal and feeding back the charge-discharge control signal to the oscillation module and generating and outputting a stable clock signal. The relaxation oscillator can effectively carry out temperature compensation so as to realize stable frequency output of clock signals at different temperatures, and the circuit is simple in structure, high in reliability, high in practical value and wide in application prospect.

Description

Technical Field

[0001] The invention relates to the technical field of circuit design, and in particular to a relaxation oscillator with temperature compensation and application thereof. Background Art

[0002] The clock signal is a key component of the integrated circuit. It is mainly used to provide a unified time reference for various units inside the chip to ensure the synchronous transmission and processing of data. The frequency and stability of the clock signal are crucial to the working effect of the entire chip. Therefore, the generation of the clock signal must ensure its stability and accuracy. Usually, an oscillator or crystal oscillator is used to generate a stable clock signal. However, since the off-chip crystal oscillator requires an external quartz crystal, it has natural disadvantages in cost and area, and is difficult to integrate into the Soc, and cannot meet the requirements of high integration.

[0003] Currently, there are three mainstream oscillators: LC oscillator, ring oscillator and RC relaxation oscillator. The ring oscillator has a simple structure and low power consumption, but its stability is very low; the LC oscillator has good stability, but requires inductor components and is expensive; the RC relaxation oscillator is widely used due to its low cost and high stability.

[0004] Figure 1 It is a traditional RC relaxation oscillator. The half cycle of the oscillator output OSC is determined by the charge and discharge time of the capacitor C. The discharge time of the capacitor C1 is uncontrollable, which will affect the accuracy of the oscillator. In addition, the reference current in this type of oscillator circuit structure is greatly affected by temperature, which affects the stable output of the clock signal frequency. Therefore, designing an oscillator circuit with high accuracy and output that is not affected by temperature has become an urgent problem to be solved. Summary of the invention

[0005] In view of the deficiencies of the prior art, the present invention provides a relaxation oscillator with temperature compensation, which can effectively perform temperature compensation, thereby achieving a stable frequency output of a clock signal that is not affected by temperature.

[0006] The present invention solves the technical problem by adopting the following technical solution:

[0007] The present invention provides a relaxation oscillator with temperature compensation, comprising a first bias module, a second bias module, an oscillation module and a clock signal output module, wherein:

[0008] The first bias module is connected to the power supply circuit and is configured to generate a first bias current negatively correlated with temperature and output a first bias voltage;

[0009] The second bias module is connected to the power supply circuit and is configured to generate a second bias current that is positively correlated with temperature and output a second bias voltage;

[0010] The oscillation module is respectively connected to the first bias module and the second bias module, and is configured to generate a reset pulse that is independent of temperature and send it to the clock signal output module;

[0011] The clock signal output module is connected to the oscillation module and is configured to generate a charge and discharge control signal to feed back to the oscillation module and to generate and output a stable clock signal.

[0012] Preferably, generating a temperature-independent reset pulse specifically comprises:

[0013] generating a temperature-independent charging current based on the first bias current and the second bias current;

[0014] generating an integrated voltage based on the charging current;

[0015] A reset pulse is generated based on the integrated voltage.

[0016] Preferably, generating a temperature-independent charging current based on the first bias current and the second bias current specifically includes:

[0017] The first bias current and the second bias current are scaled according to a first proportional factor M1 and a second proportional factor M2, respectively, wherein M1 and M2 are designed and configured according to the principle of positive and negative correlation offset of temperature;

[0018] A temperature-independent charging current is generated based on the scaled modulation of the two bias currents.

[0019] Preferably, the first bias module specifically includes PMOS transistors PM1-PM2, transistor Q1, NMOS transistors NM1-NM2, and resistor R1, wherein:

[0020] The PMOS tubes PM1 and PM3 share a common source terminal and are connected to a power supply circuit;

[0021] The PMOS tube PM1 and the NMOS tube NM1 share a drain terminal and are respectively connected to the gate terminals of the NMOS tubes NM1 and NM2;

[0022] The PMOS tubes PM1 and PM2 have a common gate terminal and are connected to the drain terminals of the PMOS tube PM2 and the NMOS tube NM2 respectively;

[0023] The PMOS transistor PM2 and the NMOS transistor NM2 share a drain terminal and serve as a first output node to output a first bias voltage V c ;

[0024] The source end of the NMOS tube NM2 is connected to one end of the resistor R1, and the other end of the resistor R1 is respectively connected to the collector and base of the transistor Q1 and connected to the common ground terminal;

[0025] The source end of the NMOS tube NM1 is connected to the emitter of the transistor Q1.

[0026] Preferably, the second bias module specifically includes PMOS transistors PM9-PM10, NMOS transistors NM5-NM6, and resistor R3, wherein:

[0027] The PMOS tubes PM9 and PM10 share a common source terminal and are connected to a power supply circuit;

[0028] The PMOS tube PM9 and the NMOS tube NM5 share a drain terminal and are respectively connected to the gate terminals of the NMOS tubes NM5 and NM6;

[0029] The PMOS tubes PM9 and PM10 have a common gate terminal and are respectively connected to the drain terminals of the PMOS tube PM10 and the NMOS tube NM6;

[0030] The PMOS tube PM10 and the NMOS tube NM6 share a drain terminal and serve as a second output node to output a second bias voltage V p ;

[0031] The source end of the NMOS transistor NM6 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the source end of the NMOS transistor NM5 and connected to the common ground end.

[0032] Preferably, the oscillation module specifically includes PMOS tubes PM3-PM8, PM11-PM13, NMOS tubes NM3-NM4, NM7-NM11, resistor R2, inverters inv1-inv2, buffers buffer1-buffer2, wherein:

[0033] The PMOS tubes PM3, PM4, PM5, PM6, PM11 and PM12 have a common source terminal and are connected to a power supply circuit;

[0034] The gates of the PMOS transistors PM3, PM5, and PM11 are connected to a second bias voltage V p ;

[0035] The gates of the PMOS transistors PM4, PM6, and PM12 are connected to a first bias voltage V c ;

[0036] The PMOS tubes PM3 and PM4 share a drain terminal and are connected to a source terminal of the PMOS tube PM7;

[0037] The PMOS tubes PM5 and PM6 have a common drain terminal and are connected to the source terminal of the PMOS tube PM8;

[0038] The NMOS tubes NM3 and NM4 have a common gate terminal and are respectively connected to the drain terminals of the PMOS tube PM7 and the NMOS tube NM3;

[0039] The PMOS tube PM7 and the NMOS tube NM3 share a drain terminal and serve as a third output node to output a third bias voltage V b ;

[0040] The PMOS tube PM8 and the NMOS tube NM4 have a common drain terminal and are connected to the input terminal of the inverter inv1. The output terminal of the inverter inv1 is connected to the input terminal of the buffer buffer1. The output terminal of the buffer buffer1 outputs the first oscillation voltage V i1 ;

[0041] The source end of the NMOS tube NM3 is connected to one end of the resistor R2 and serves as the fourth output node to output the reference voltage V ref ;

[0042] The other end of the resistor R2, the source and drain ends of the NMOS tube NM8, and the source end of NM10 are connected to a common ground terminal;

[0043] The source end of the NMOS tube NM4 is connected to the gate end of the NMOS tube NM8 and the drain end of the NMOS tube NM10 respectively;

[0044] The PMOS tube PM13 and the NMOS tube NM7 have a common drain terminal and are connected to the input terminal of the inverter inv2. The output terminal of the inverter inv2 is connected to the input terminal of the buffer buffer2. The output terminal of the buffer buffer2 outputs the second oscillation voltage V i2 ;

[0045] The source and drain of the NMOS tube NM9 and the source of NM11 are connected to a common ground terminal;

[0046] The source end of the NMOS tube NM7 is connected to the gate end of the NMOS tube NM9 and the drain end of the NMOS tube NM11 respectively.

[0047] Preferably, the clock signal output module specifically includes an SR trigger and a buffer buffer3, wherein:

[0048] The S and R terminals of the SR trigger are respectively connected to the first oscillation voltage V i1 , the first oscillation voltage V i1；

[0049] The SR flip-flop The end is connected to the input end of the buffer buffer3, and the input end of the buffer buffer3 outputs a clock signal.

[0050] Preferably, the gate terminal of the PMOS tube PM7 is connected to an inverted enable signal ENB;

[0051] The gate end of the NMOS tube NM7 is connected to the third bias voltage V b ;

[0052] The gate terminals of the PMOS tube PM8 and the NMOS tube NM10 are connected to the Q terminal of the SR trigger;

[0053] The gate terminals of the PMOS tube PM13 and the NMOS tube NM11 are connected to the gate terminals of the SR trigger. end.

[0054] Preferably, the width-to-length ratio of the NMOS transistor NM6 is K times the width-to-length ratio of NM5, and K≥2;

[0055] The PMOS tubes PM3, PM5, PM11 have the same size and a ratio to PM10 is a first proportional factor M1;

[0056] The PMOS transistors PM4 , PM6 , and PM12 have the same size and a ratio to PM12 is a second proportional factor M2 .

[0057] The present invention further provides a chip circuit, wherein the chip circuit comprises the aforementioned relaxation oscillator with temperature compensation.

[0058] Compared with the prior art, the present invention has the following beneficial effects:

[0059] The present invention generates bias currents that are positively correlated with temperature and negatively correlated with temperature respectively through two bias circuit modules designed, and modulates the two currents to generate a reference current that is independent of temperature. Based on the reference current, a reference voltage is generated in an oscillation module, and then an NMOS tube connected in a capacitor method is continuously charged and discharged, thereby outputting a periodic oscillation waveform, so that the output clock signal has high accuracy and does not change with temperature changes, and a stable frequency output of the clock signal is achieved. The invention has high practical value and broad application prospects.

[0060] Other outstanding essential features and significant improvements of the present invention compared to the prior art are further described in detail in the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0062] Figure 1 A relaxation oscillator structure diagram of the prior art;

[0063] Figure 2 Schematic diagram of the circuit structure of the relaxation oscillator with temperature compensation in Example 1;

[0064] Figure 3 This is a schematic diagram of simulation of key nodes of a relaxation oscillator with temperature compensation in Example 1;

[0065] Figure 4 It is a schematic diagram of a clock cycle simulation of the relaxation oscillator with temperature compensation in Example 1 at -40°C, 25°C, and 125°C;

[0066] Figure 5 It is a schematic diagram of the Monte Carlo output frequency of the relaxation oscillator with temperature compensation at -40°C in Example 1;

[0067] Figure 6 It is a schematic diagram of the Monte Carlo output frequency of the relaxation oscillator with temperature compensation at 25° C. in Example 1;

[0068] Figure 7 Schematic diagram of the Monte Carlo output frequency of the relaxation oscillator with temperature compensation at 125° C. in Example 1. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0070] It should be noted that certain names are used in the specification and claims to refer to specific components. It should be understood that a person of ordinary skill in the art may use different names to refer to the same component. The specification and claims of this application do not use differences in names as a way to distinguish components, but use substantial differences in the functions of components as the criterion for distinguishing components. As used in the specification and claims of this application, "including" or "comprising" is an open term, which should be interpreted as "including but not limited to" or "including but not limited to". The embodiments described in the specific implementation section are preferred embodiments of the present invention and are not intended to limit the scope of the present invention.

[0071] Example 1

[0072] like Figure 1 As shown, this embodiment provides a relaxation oscillator with temperature compensation, including a first bias module 1, a second bias module 2, an oscillation module 3 and a clock signal output module 4, wherein:

[0073] The first bias module 1 is connected to the power supply circuit to generate a first bias current I that is negatively correlated with temperature. CTAT , and outputs the first bias voltage V c ;

[0074] The second bias module 2 is connected to the power supply circuit to generate a second bias current I that is positively correlated with temperature. PTAT , and outputs the second bias voltage V p ;

[0075] The oscillation module 3 is connected to the first bias module 1 and the second bias module 2 respectively, and is used to generate a reset pulse that is independent of temperature and send it to the clock signal output module 4. Specifically, the oscillation module 3 generates a reset pulse based on the first bias current I CTAT and the second bias current I PTAT Generates temperature-independent charging current I ref Then, an integral voltage is generated based on the charging current, which is generally obtained by charging the NMOS tube connected to the capacitor, and then a reset pulse is generated based on the integral voltage and sent to the clock signal output module 4. Further, in this embodiment, the charging current I ref It is obtained in the following way:

[0076] First, the first bias current I CTAT , the second bias current I PTAT Scaling is performed according to a first proportional factor M1 and a second proportional factor M2 respectively, wherein M1 and M2 are designed and configured according to the principle of positive and negative correlation offset of temperature;

[0077] A temperature-independent charging current is then generated based on the scaled modulation of the two bias currents.

[0078] The clock signal output module 4 in this embodiment is connected to the oscillation module 3 and is configured to generate a charge and discharge control signal to feed back to the oscillation module 3 and to generate and output a stable clock signal, wherein the charge and discharge control signal is used to control the charge and discharge of the oscillation module 3 .

[0079] like Figure 2 As shown in this embodiment, the circuit structure of the first bias module 1, the second bias module 2, the oscillation module 3 and the clock signal output module 4 is further specifically introduced:

[0080] The first bias module 1 in this embodiment specifically includes PMOS transistors PM1-PM2, transistors Q1, NMOS transistors NM1-NM2, and resistor R1. In this embodiment, the transistor Q1 is a PNP transistor, wherein:

[0081] The PMOS tubes PM1 and PM3 share a common source terminal and are connected to the power supply circuit;

[0082] The PMOS tube PM1 and the NMOS tube NM1 share a drain terminal and are connected to the gate terminals of the NMOS tubes NM1 and NM2 respectively;

[0083] The PMOS tubes PM1 and PM2 have a common gate terminal and are connected to the drain terminals of the PMOS tube PM2 and the NMOS tube NM2 respectively;

[0084] The PMOS tube PM2 and the NMOS tube NM2 share a drain terminal and serve as a first output node to output a first bias voltage V c ;

[0085] The source end of the NMOS tube NM2 is connected to one end of the resistor R1, and the other end of the resistor R1 is respectively connected to the collector and base of the transistor Q1 and connected to the common ground terminal;

[0086] The source end of the NMOS tube NM1 is connected to the emitter of the transistor Q1;

[0087] The transistor Q1 used in this module is a device with a negative temperature coefficient, which can generate a negative temperature-related current I CTAT , that is:

[0088]

[0089] Where V be1 is the voltage between the base and emitter of the transistor;

[0090] The second bias module 2 in this embodiment specifically includes PMOS transistors PM9-PM10, NMOS transistors NM5-NM6, and a resistor R3, wherein:

[0091] PMOS tubes PM9 and PM10 share a common source terminal and are connected to a power supply circuit;

[0092] The PMOS tube PM9 and the NMOS tube NM5 share a drain terminal and are connected to the gate terminals of the NMOS tubes NM5 and NM6 respectively;

[0093] The PMOS tubes PM9 and PM10 have a common gate terminal and are connected to the drain terminals of the PMOS tube PM10 and the NMOS tube NM6 respectively;

[0094] The PMOS tube PM10 and the NMOS tube NM6 share a drain terminal and serve as a second output node to output a second bias voltage V p ;

[0095] The source end of the NMOS transistor NM6 is connected to one end of the resistor R3 , and the other end of the resistor R3 is connected to the source end of the NMOS transistor NM5 and connected to the common ground end.

[0096] In this embodiment, the width-to-length ratio of the NMOS transistor NM6 is K times the width-to-length ratio of NM5, where K≥2;

[0097] In this embodiment, the temperature positively correlated current I generated by the second bias module 2 is PTAT as follows:

[0098]

[0099] Among them, μ n is the carrier mobility of the MOS tube, C ox is the gate oxide capacitance, is the width-to-length ratio of the NMOS tube NM5.

[0100] In this embodiment, the oscillation module 3 specifically includes PMOS tubes PM3-PM8, PM11-PM13, NMOS tubes NM3-NM4, NM7-NM11, resistor R2, inverters inv1-inv2, and buffers buffer1-buffer2. In this embodiment, the oscillation module includes two sub-modules, which are respectively connected to the first bias module 1 and the second bias module 2. The outputs of the two sub-modules are respectively sent to the clock signal output module, wherein:

[0101] In this embodiment, both NMOS tubes NM8 and NM9 are connected by capacitors, that is, the drain and source terminals are short-circuited, thereby forming two charging and discharging capacitors to generate an integral voltage. Further analysis:

[0102] PMOS tubes PM3, PM4, PM5, PM6, PM11, and PM12 have a common source terminal and are connected to the power supply circuit;

[0103] The gates of the PMOS tubes PM3, PM5, and PM11 are connected to the second bias voltage V p ;

[0104] The gates of the PMOS tubes PM4, PM6, and PM12 are connected to the first bias voltage V c ;

[0105] The drain terminals of PMOS tubes PM3 and PM4 are connected to the source terminal of PMOS tube PM7;

[0106] The drain terminals of PMOS tubes PM5 and PM6 are connected to the source terminal of PMOS tube PM8;

[0107] The common gate terminals of the NMOS tubes NM3 and NM4 are connected to the drain terminals of the PMOS tube PM7 and the NMOS tube NM3 respectively;

[0108] The PMOS tube PM7 and the NMOS tube NM3 share a drain terminal and serve as a third output node to output a third bias voltage V b ;

[0109] The PMOS tube PM8 and the NMOS tube NM4 have a common drain terminal and are connected to the input terminal of the inverter inv1. The output terminal of the inverter inv1 is connected to the input terminal of the buffer buffer1. The output terminal of the buffer buffer1 outputs the first oscillation voltage V i1 ;

[0110] The source end of the NMOS tube NM3 is connected to one end of the resistor R2 and serves as the fourth output node to output the reference voltage V ref ;

[0111] The other end of the resistor R2, the source and drain ends of the NMOS tube NM8, and the source end of NM10 are connected to a common ground terminal;

[0112] The source end of the NMOS tube NM4 is connected to the gate end of the NMOS tube NM8 and the drain end of the NMOS tube NM10 respectively;

[0113] The PMOS tube PM13 and the NMOS tube NM7 have a common drain terminal and are connected to the input terminal of the inverter inv2. The output terminal of the inverter inv2 is connected to the input terminal of the buffer buffer2. The output terminal of the buffer buffer2 outputs the second oscillation voltage V i2 ;

[0114] The source and drain of the NMOS tube NM9 and the source of NM11 are connected to a common ground terminal;

[0115] The source end of the NMOS tube NM7 is connected to the gate end of the NMOS tube NM9 and the drain end of the NMOS tube NM11 respectively.

[0116] In this embodiment, the PMOS transistors PM3, PM5, and PM11 have the same size and their ratio to PM10 is a first proportional factor M1;

[0117] The sizes of the PMOS tubes PM4, PM6, and PM12 are the same and their ratio to PM12 is a second proportional factor M2;

[0118] Through the above design, the reference current I ref for:

[0119] I ref =M1I PATA +M2I CTAT

[0120] Through matching design, the reference current I ref Basically not affected by temperature.

[0121] The clock signal output module 4 in this embodiment specifically includes an SR trigger and a buffer buffer3, wherein:

[0122] The S and R terminals of the SR trigger are respectively connected to the first oscillation voltage V i1 , the first oscillation voltage V i1；

[0123] SR trigger The end is connected to the input end of the buffer buffer3, and the input end of the buffer buffer3 outputs a clock signal;

[0124] At the same time, the gate terminals of the PMOS tube PM8 and the NMOS tube NM10 are connected to the Q terminal of the SR trigger;

[0125] The gate terminals of the PMOS tube PM13 and the NMOS tube NM11 are connected to the SR trigger. end;

[0126] Through the above design, on the one hand, the clock signal output module 4 generates a stable clock signal, and on the other hand, controls the charging and discharging of the oscillation module 3 .

[0127] The working principle and process of the above circuit in this embodiment are further analyzed in detail:

[0128] When the inverted enable signal ENB, that is, the switch enable signal, is pulled low, the entire oscillation module 3 starts to work, and the reference current I ref A reference voltage Vref is formed on the resistor R2. At this time, Vref does not change with temperature. In the initial state, the Q terminal of the SR trigger is at a low level. The end is high level, and the reference current Iref charges the capacitor formed by the NMOS tube NM8. When the gate voltage of NM8 is higher than Vref, the voltage at A1 reaches the flip voltage of the inverter inv1. Through the buffer buffer1, the voltage at B1 is pulled down. At this time, the Q end of the SR trigger is high level. The end is low level, at this time, NMOS tube NM10 is turned on, and the capacitor formed by NM8 is discharged quickly, the voltage at A1 is pulled down, and the voltage at B1 becomes high level. At the same time, the reference current Iref charges the capacitor formed by NMOS tube NM9. When the gate voltage of NM9 is higher than Vref, the voltage at A2 reaches the flip voltage of inverter inv2. Through buffer buffer2, the voltage at B2 is pulled down. At this time, the Q end of the SR trigger becomes low level again. The end is high level. During this period, the charging time is much longer than the discharging time. Through continuous charging and discharging, a periodic oscillation waveform is output. Half a cycle of the oscillator is when the capacitor is charged to V ref Time, because the charging current has temperature compensation, the output clock frequency is stable.

[0129] In order to further verify the superiority of the present invention, the circuit structure of the present invention is simulated and verified. Figure 3 It is a simulation diagram of some important nodes of the temperature compensated relaxation oscillator of this embodiment.

[0130] The circuit is simulated at -40℃, 25℃, and 125℃ at 2.5V voltage. Figure 4 As shown, the time of one cycle at the three temperatures is 139.58ns, 140.61ns, and 141.23ns, respectively, with very small differences;

[0131] Continue to perform Monte Carlo simulation on the circuit at -40℃, 25℃, and 125℃ under a power supply voltage of 2.5V. Figure 5-7 As shown, under 200 Monte Carlo simulations, at -40°C, the average frequency of the relaxation oscillator in this example is 7.17M, at 25°C, the average frequency of the relaxation oscillator in this example is 7.129M, and at 125°C, the average frequency of the relaxation oscillator in this example is 7.1M. It can be seen that at different temperatures, the frequency change of the relaxation oscillator in this example is extremely low, and it has a very good temperature compensation characteristic.

[0132] Therefore, through the above simulation verification, it can be further confirmed that the relaxation oscillator in this embodiment can effectively perform temperature compensation, thereby achieving stable frequency output of the clock signal at different temperatures.

[0133] Example 2

[0134] This embodiment provides a chip circuit, which includes a relaxation oscillator with temperature compensation as in the above-mentioned embodiment.

[0135] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0136] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A relaxation oscillator with temperature compensation, characterized in that: It includes a first bias module, a second bias module, an oscillation module and a clock signal output module, wherein: The first bias module is connected to the power supply circuit and is configured to generate a first bias current negatively correlated with temperature and output a first bias voltage; The second bias module is connected to the power supply circuit and is configured to generate a second bias current that is positively correlated with temperature and output a second bias voltage; The oscillation module is connected to the first bias module and the second bias module respectively, and is configured to generate a reset pulse that is independent of temperature and send it to the clock signal output module; The clock signal output module is connected to the oscillation module and is configured to generate a charge and discharge control signal to feed back to the oscillation module and to generate and output a stable clock signal.

2. A relaxation oscillator with temperature compensation according to claim 1, characterized in that: The generating of the reset pulse independent of temperature specifically comprises: generating a temperature-independent charging current based on the first bias current and the second bias current; generating an integrated voltage based on the charging current; A reset pulse is generated based on the integrated voltage.

3. A relaxation oscillator with temperature compensation according to claim 2, characterized in that: The step of generating a temperature-independent charging current based on the first bias current and the second bias current specifically includes: The first bias current and the second bias current are scaled according to a first proportional factor M1 and a second proportional factor M2, respectively, wherein M1 and M2 are designed and configured according to the principle of positive and negative correlation offset of temperature; A temperature-independent charging current is generated based on the scaled modulation of the two bias currents.

4. A relaxation oscillator with temperature compensation according to claim 3, characterized in that: The first bias module specifically includes PMOS transistors PM1-PM2, transistor Q1, NMOS transistors NM1-NM2, and resistor R1, wherein: The PMOS tubes PM1 and PM2 share a common source terminal and are connected to a power supply circuit; The PMOS tube PM1 and the NMOS tube NM1 share a drain terminal and are respectively connected to the gate terminals of the NMOS tubes NM1 and NM2; The PMOS tubes PM1 and PM2 have a common gate terminal and are connected to the drain terminals of the PMOS tube PM2 and the NMOS tube NM2 respectively; The PMOS transistor PM2 and the NMOS transistor NM2 share a drain terminal and serve as a first output node to output a first bias voltage V c ; The source end of the NMOS tube NM2 is connected to one end of the resistor R1, and the other end of the resistor R1 is respectively connected to the collector and base of the transistor Q1 and connected to the common ground terminal; The source end of the NMOS tube NM1 is connected to the emitter of the transistor Q1.

5. A relaxation oscillator with temperature compensation according to claim 4, characterized in that: The second bias module specifically includes PMOS transistors PM9-PM10, NMOS transistors NM5-NM6, and resistor R3, wherein: The PMOS tubes PM9 and PM10 share a common source terminal and are connected to a power supply circuit; The PMOS tube PM9 and the NMOS tube NM5 share a drain terminal and are respectively connected to the gate terminals of the NMOS tubes NM5 and NM6; The PMOS tubes PM9 and PM10 have a common gate terminal and are respectively connected to the drain terminals of the PMOS tube PM10 and the NMOS tube NM6; The PMOS tube PM10 and the NMOS tube NM6 share a drain terminal and serve as a second output node to output a second bias voltage V p ; The source end of the NMOS transistor NM6 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the source end of the NMOS transistor NM5 and connected to the common ground end.

6. A relaxation oscillator with temperature compensation according to claim 5, characterized in that: The oscillation module specifically includes PMOS tubes PM3-PM8, PM11-PM13, NMOS tubes NM3-NM4, NM7-NM11, resistor R2, inverters inv1-inv2, and buffers buffer1-buffer2, wherein: The PMOS tubes PM3, PM4, PM5, PM6, PM11 and PM12 have a common source terminal and are connected to a power supply circuit; The gates of the PMOS transistors PM3, PM5, and PM11 are connected to a second bias voltage V p ; The gates of the PMOS transistors PM4, PM6, and PM12 are connected to a first bias voltage V c ; The PMOS tubes PM3 and PM4 share a drain terminal and are connected to a source terminal of the PMOS tube PM7; The PMOS tubes PM5 and PM6 have a common drain terminal and are connected to the source terminal of the PMOS tube PM8; The NMOS tubes NM3 and NM4 have a common gate terminal and are respectively connected to the drain terminals of the PMOS tube PM7 and the NMOS tube NM3; The PMOS tube PM7 and the NMOS tube NM3 share a drain terminal and serve as a third output node to output a third bias voltage V b ; The PMOS tube PM8 and the NMOS tube NM4 have a common drain terminal and are connected to the input terminal of the inverter inv1. The output terminal of the inverter inv1 is connected to the input terminal of the buffer buffer1. The output terminal of the buffer buffer1 outputs the first oscillation voltage V i1 ; The source end of the NMOS tube NM3 is connected to one end of the resistor R2 and serves as the fourth output node to output the reference voltage V ref ; The other end of the resistor R2, the source and drain ends of the NMOS tube NM8, and the source end of NM10 are connected to a common ground terminal; The source end of the NMOS tube NM4 is connected to the gate end of the NMOS tube NM8 and the drain end of the NMOS tube NM10 respectively; The PMOS tube PM13 and the NMOS tube NM7 have a common drain terminal and are connected to the input terminal of the inverter inv2. The output terminal of the inverter inv2 is connected to the input terminal of the buffer buffer2. The output terminal of the buffer buffer2 outputs the second oscillation voltage V i2 ; The source and drain of the NMOS tube NM9 and the source of NM11 are connected to a common ground terminal; The source end of the NMOS tube NM7 is connected to the gate end of the NMOS tube NM9 and the drain end of the NMOS tube NM11 respectively.

7. A relaxation oscillator with temperature compensation according to claim 6, characterized in that: The clock signal output module specifically includes an SR trigger and a buffer buffer3, wherein: The S and R terminals of the SR trigger are respectively connected to the first oscillation voltage V i1 , the first oscillation voltage V i1； The SR flip-flop The end is connected to the input end of the buffer buffer3, and the input end of the buffer buffer3 outputs a clock signal.

8. A relaxation oscillator with temperature compensation according to claim 7, characterized in that: The gate terminal of the PMOS tube PM7 is connected to the inverted enable signal ENB; The gate end of the NMOS tube NM7 is connected to the third bias voltage V b ; The gate terminals of the PMOS tube PM8 and the NMOS tube NM10 are connected to the Q terminal of the SR trigger; The gate terminals of the PMOS tube PM13 and the NMOS tube NM11 are connected to the gate terminals of the SR trigger. end.

9. A relaxation oscillator with temperature compensation according to claim 8, characterized in that: The width-to-length ratio of the NMOS tube NM6 is K times the width-to-length ratio of NM5, where K≥2; The PMOS tubes PM3, PM5, PM11 have the same size and a ratio to PM10 is a first proportional factor M1; The PMOS transistors PM4 , PM6 , and PM12 have the same size and a ratio to PM12 is a second proportional factor M2 .

10. A chip circuit, characterized in that: The chip circuit includes a relaxation oscillator with temperature compensation as described in any one of claims 1 to 9.

Images