Chip system, data processing method and computer readable storage medium

Abstract

A chip system, a method of processing data, and a computer readable storage medium are provided. The chip system comprises a plurality of computing nodes and a shared memory of the plurality of computing nodes, wherein the shared memory is used for performing reduction operation on the plurality of computing nodes. By using the chip system, the reduction operation among the plurality of computing nodes can be performed by using the shared memory of the plurality of computing nodes, communication among the plurality of computing nodes is not needed, and the time delay and communication overhead of the reduction operation can be reduced, so that the computing performance of the chip system is improved.

Description

Technical Field

[0003] The present application relates to the field of chip technology, and more specifically, to a chip system, a method for processing data, and a computer-readable storage medium. Background Art

[0005] In order to simplify the computational complexity of chip systems (such as graphics processing units (GPUs)) and improve the efficiency of data processing in chip systems, reduce operations are introduced into the computational process of chip systems. How to reduce the latency and communication overhead of the reduce operation, thereby improving the computational performance of the chip system, is a technical problem that needs to be solved. Summary of the invention

[0007] The present application provides a chip system and a method for processing data to reduce the latency and communication overhead of reduction operations, thereby improving the computing performance of the chip system.

[0008] In a first aspect, a chip system is provided, the chip system comprising a plurality of computing nodes and a shared memory of the plurality of computing nodes, the shared memory being used for the plurality of computing nodes to perform a reduction operation.

[0009] As a possible implementation manner, the shared memory stores multiple data corresponding to the multiple computing nodes one by one, and the first computing node among the multiple computing nodes is used to perform the following operations: read the multiple data from the shared memory; determine a first reduction result corresponding to the reduction operation based on the multiple data; and store the first reduction result in the shared memory.

[0010] As a possible implementation manner, the shared memory includes multiple storage addresses corresponding one-to-one to the multiple computing nodes, and the first computing node stores a one-to-one correspondence between the multiple computing nodes and the multiple storage addresses, and the reading of the multiple data from the shared memory includes: reading the multiple data from the multiple storage addresses respectively according to the correspondence; and storing the first reduction result to the shared memory includes: storing the first reduction result to a target storage address, and the target storage address is a storage address corresponding to the first computing node or a storage address in the shared memory dedicated to storing reduction results.

[0011] As a possible implementation manner, the multiple computing nodes include a second computing node, and the second computing node is used to read the first reduction result from the target storage address.

[0012] As a possible implementation manner, the first reduction result is stored in a storage address in the shared memory that is dedicated to storing reduction results.

[0013] As a possible implementation manner, the first computing node is determined based on a data processing rate of the multiple computing nodes; and / or the first computing node is determined based on a current load of the multiple computing nodes.

[0014] As a possible implementation manner, the multiple computing nodes and the shared memory belong to a computing unit in the chip system, the reduction operation between the multiple computing nodes is used to determine a first reduction result within the computing unit, and the chip system includes the multiple computing units, which are communicatively connected to perform reduction operations between the multiple computing units according to the first reduction results corresponding to each of the multiple computing units.

[0015] As a possible implementation manner, the shared memory of the multiple computing nodes is a first shared memory, the chip system includes a data transmission unit, the multiple computing units are connected through the data transmission unit, and the data transmission unit includes a second shared memory; the first computing unit among the multiple computing units is used to perform the following operations: read the first reduction results corresponding to each of the multiple computing units from the second shared memory; determine the second reduction result according to the first reduction results corresponding to each of the multiple computing units; and store the second reduction result in the second shared memory.

[0016] As a possible implementation manner, the data transmission unit is an IO chip.

[0017] As a possible implementation manner, the reduction operation performed among the multiple computing units is a global reduction operation.

[0018] As a possible implementation, the computing unit is a chip that supports in-memory computing.

[0019] In a second aspect, a method for processing data is provided, the method being applied to a chip system, the chip system comprising multiple computing nodes and a shared memory of the multiple computing nodes, the shared memory storing multiple data corresponding to the multiple computing nodes one by one, the method comprising: a first computing node among the multiple computing nodes reads the multiple data from the shared memory; the first computing node determines a first reduction result corresponding to a reduction operation based on the multiple data; the first computing node stores the first reduction result in the shared memory.

[0020] As a possible implementation manner, the shared memory includes multiple storage addresses corresponding to the multiple computing nodes in one-to-one correspondence, and the first computing node stores a one-to-one correspondence between the multiple computing nodes and the multiple storage addresses. The first computing node among the multiple computing nodes reads the multiple data from the shared memory, including: the first computing node reads the multiple data from the multiple storage addresses respectively according to the correspondence; the first computing node stores the first reduction result to the shared memory, including: the first computing node stores the first reduction result to a target storage address, and the target storage address is the storage address corresponding to the first computing node or a storage address in the shared memory dedicated to storing the reduction result.

[0021] As a possible implementation manner, the multiple computing nodes include a second computing node, and the second computing node is used to read the first reduction result from the target storage address.

[0022] As a possible implementation manner, the first reduction result is stored in a storage address in the shared memory that is dedicated to storing reduction results.

[0023] As a possible implementation manner, the first computing node is determined based on a data processing rate of the multiple computing nodes; and / or the first computing node is determined based on a current load of the multiple computing nodes.

[0024] As a possible implementation manner, the multiple computing nodes and the shared memory belong to a computing unit in the chip system, the chip system includes multiple computing units, and the method further includes: the multiple computing units perform a reduction operation according to their respective corresponding first reduction results.

[0025] As a possible implementation manner, the shared memory of the multiple computing nodes is a first shared memory, the chip system includes a data transmission unit, the multiple computing units are connected through the data transmission unit, and the data transmission unit includes a second shared memory; the multiple computing units perform a reduction operation according to their respective corresponding first reduction results, including: a first computing unit among the multiple computing units reads the first reduction results corresponding to each of the multiple computing units from the second shared memory; the first computing unit determines a second reduction result according to the first reduction results corresponding to each of the multiple computing units; and the first computing unit stores the second reduction result to the second shared memory.

[0026] As a possible implementation manner, the data transmission unit is an IO chip.

[0027] As a possible implementation manner, the reduction operation performed among the multiple computing units is a global reduction operation.

[0028] As a possible implementation, the computing unit is a chip that supports in-memory computing.

[0029] According to a third aspect, a computer-readable storage medium is provided, on which a program code for executing the method according to the second aspect or any one of the implementations of the second aspect is stored.

[0030] According to a fourth aspect, a computer program product is provided, wherein the computer program product comprises a program code for executing the method as described in the second aspect or any one of the implementations of the second aspect.

[0031] The chip system in the embodiment of the present application can utilize the shared memory of multiple computing nodes to perform reduction operations between multiple computing nodes, without the need for communication between multiple computing nodes, thereby reducing the latency and communication overhead of the reduction operation, thereby improving the computing performance of the chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and other drawings obtained by ordinary technicians in this field based on these drawings fall within the scope of the present application.

[0034] Figure 1 is an example diagram of a hardware structure to which reduction operations can be applied in the related art.

[0035] Figure 2 is an example diagram of a hardware structure to which a hierarchical reduction operation can be applied in the related art.

[0036] Figure 3 This is a structural example diagram of a chip system in the related art to which a hierarchical global reduction operation can be applied.

[0037] Figure 4 This is a structural example diagram of a chip system in the related art to which a hierarchical global reduction operation can be applied.

[0038] Figure 5 This is an example diagram of the structure of the chip system provided in the embodiment of the present application.

[0039] Figure 6 It is a schematic flowchart of performing a reduction operation using shared memory provided in an embodiment of the present application.

[0040] Figure 7It is a schematic diagram of performing a reduction operation using a shared memory provided in an embodiment of the present application.

[0041] Figure 8 This is another schematic diagram of performing a reduction operation using a shared memory provided in an embodiment of the present application.

[0042] Fig. 9 It is a schematic flowchart of the method for processing data provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained based on the embodiments in the present application belong to the scope of protection of the present application.

[0045] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0046] It should be understood that the specific embodiments described below are only used to explain the present application and are not used to limit the present application.

[0047] The embodiment of the present application can be applied to the reduction operation. For ease of understanding, the reduction operation mentioned in the embodiment of the present application and the hardware architecture involved in the reduction operation are first introduced.

[0048] The computing process of chip systems (such as GPUs) often involves data reduction operations. A reduction operation can be understood as an operation that combines multiple data into a single result through a specific operation. The specific operations here may include but are not limited to summation, multiplication, maximum value, other custom functions, etc. This single result can be called a reduction result. The multiple data here can be data corresponding to different computing nodes. In other words, the reduction operation can be performed between multiple computing nodes. Figure 1 The hardware architecture shown describes how the reduction operation is performed across multiple compute nodes.

[0049] Figure 1 A hardware architecture diagram of a computing node to which a reduction operation may be applied is shown. Figure 1Four computing nodes are shown, namely computing node 0, computing node 1, computing node 2, and computing node 3. It should be understood that the process of reduction operation is introduced here by taking four computing nodes as an example. In actual applications, the reduction operation can be performed between a larger number or a smaller number of computing nodes. The memory here can be, for example, a dynamic random access memory (DRAM). Each computing node may include a memory for storing data corresponding to the computing node. The computing node may also have a computing function. In some cases, a computing node may be referred to as a cluster. The four computing nodes can communicate through a network-on-chip (NoC). The communication between the four computing nodes can be implemented, for example, based on the universal chiplet interconnect express (UCIE) protocol. Figure 1 The four computing nodes in the figure form a computing unit. The computing unit here can be, for example, a chip that supports compute-in-memory (CIM). In some cases, the chip that supports CIM can exist in the form of a die. A die can be understood as a chip that is cut from a wafer and contains a complete circuit but has not yet been packaged. The computing unit composed of the above computing nodes can belong to a chip system (chip). The chip system here can be, for example, a GPU.

[0050] The reduction operation can be performed by any one of the different computing nodes. For ease of description, the computing node that performs the reduction operation among the multiple computing nodes is referred to as the first computing node in the following text. After obtaining the result of the reduction operation, the target computing node can store the result of the reduction operation in its own memory. Assume Figure 1 The data stored in computing node 0, computing node 1, computing node 2, and computing node 3 are respectively: data 0, data 1, data 2, data 3, and the first computing node is computing node 0. Computing node 0 can obtain the data stored in the other three computing nodes by communicating with the other three computing nodes. Computing node 0 can perform a sum operation on the data stored by itself and the data of the other three computing nodes, and obtain the sum of the four data as the reduction result.

[0051] From the above description, it can be seen that in order to obtain data from other computing nodes, the first computing node performing the reduction operation needs to communicate with other computing nodes. When the number of computing nodes involved in the reduction operation described above is large, it may cause large communication overhead and delay during the reduction operation.

[0052] The reduction operation described above can be understood as a primary form of reduction operation. The global reduction (all-reduce) operation is an extension of the primary form of reduction operation described above. The global reduction operation can be implemented in many ways. Figure 1 Two possible implementations are introduced.

[0053] In some implementations, multiple computing nodes involved in the reduction operation all perform the reduction operation, and after the reduction operation is completed, the multiple computing nodes all obtain the results of the reduction operation. Figure 1 Take the hardware architecture shown in FIG. 1 as an example. In this implementation, computing node 1, computing node 2 and computing node 3 are all first computing nodes and perform the reduction operation described above. That is, computing node 1, computing node 2 and computing node 3 obtain the data stored by the other three computing nodes by communicating with the other three computing nodes, and perform sum operations on the data stored by themselves and the data of the other three computing nodes, and obtain the sum of the four data as the reduction result.

[0054] In other implementations, the global reduction operation can be combined with the reduction operation described above and the operation of distributing the results of the reduction operation. In this implementation, the global reduction operation not only involves the process of the first computing node merging multiple data into a single result through a certain specific operation, but also involves the process of distributing the results of the reduction operation to other computing nodes. Through the distribution process, other computing nodes can also obtain the results of the reduction operation. The first computing node can distribute the results of the reduction operation to other computing nodes in the form of broadcast. That is to say, after the first computing node obtains the reduction result by executing the reduction operation, it can broadcast the reduction result to other computing nodes. This means that each computing node not only participates in the reduction of the data, but also receives the final reduction result. Still with Figure 1 Taking the hardware architecture shown as an example, after computing node 0 performs a sum operation on the data of four computing nodes to obtain a reduction result, the reduction result can be broadcast to computing node 1, computing node 2, and computing node 3, so that other computing nodes can obtain the results of the reduction operation.

[0055] From the above description, it can be seen that the global reduction operation may involve more communications between computing nodes, which may lead to greater communication overhead and latency.

[0056] In large-scale systems, the number of computing nodes may be relatively large. At this time, if all computing nodes directly participate in the reduction operation, it may cause network congestion and very large communication delays. For this reason, a hierarchical reduction operation scheme is proposed in the related art. In the hierarchical reduction operation, the computing nodes are organized into a tree or other hierarchical structure, and the data reduction process is performed on multiple levels. The computing nodes at each level only communicate with their child nodes or parent nodes. The hierarchical reduction operation can reduce the number of nodes communicating at the same time, thereby reducing network congestion and improving communication efficiency. In addition, the hierarchical global reduction operation can also reduce communication overhead in a hierarchical manner.

[0057] The hierarchical reduction operation can be applied to Figure 2 The hardware architecture is shown. Figure 2 8 computing units are shown. It should be understood that the hierarchical reduction operation process is described here by taking 8 computing units as an example. In actual applications, the hierarchical reduction operation can be performed between a larger number or a smaller number of computing units. Each computing unit may include multiple computing nodes. For example, a computing node may have Figure 1 The hardware architecture shown. Multiple computing units can belong to a chip system. Multiple computing units can communicate with each other to obtain data stored in other computing units. Multiple computing units can communicate through input output (IO) chips. IO chips can be used to process input and output functions. The IO chip can be a bare chip, for example. Communication between multiple computing units can be implemented based on the UCIE protocol. In the hierarchical reduction operation, each computing unit performs the reduction operation described above to obtain a reduction operation result. Afterwards, multiple computing units can perform reduction operations according to the reduction operation results corresponding to each of the multiple computing units to obtain the final reduction operation result (or the global reduction operation result).

[0058] In order to further optimize the system performance, the hierarchical reduction operation and the global reduction operation can be combined to realize the hierarchical global reduction operation. In the hierarchical global reduction operation, the reduction operation is realized in the hierarchical form described above, while ensuring that all computing nodes can obtain the same global result when the communication ends. Figure 3 and Figure 4 The implementation process of the hierarchical reduction operation is introduced in detail.

[0059] In the following example, the chip system includes 8 CIM dies, namely CIM die 0 to CIM die 7. Each CIM die includes 4 computing clusters, namely computing cluster 0 to computing cluster 3. In other words, the chip system includes 32 computing clusters. The 8 CIM dies communicate with each other through the IO die based on the UCIE protocol. Each computing cluster has a DRAM for storing data. The 4 computing clusters in each CIM die communicate with each other through the NoC. Figure 3 The 32 computing clusters shown can perform hierarchical global reduction operations according to the process described below.

[0060] First, the four computing clusters in CIM die 0, namely, computing cluster 0, computing cluster 1, computing cluster 2, and computing cluster 3, communicate with each other through NoC to perform global reduction operations. The seven CIM dies, namely, CIM die 1, CIM die 2, ..., CIM die 7, are the same as CIM die 0. The four computing clusters in them also communicate with each other through NoC to perform global reduction operations.

[0061] Then, computing cluster 0 in CIM die 0, computing cluster 0 in CIM die 1, computing cluster 0 in CIM die 2, computing cluster 0 in CIM die 3, computing cluster 0 in CIM die 4, computing cluster 0 in CIM die 5, computing cluster 0 in CIM die 6, and computing cluster 0 in CIM die 7 communicate through the IO die, perform a global reduction operation, and obtain the result of the global reduction operation.

[0062] Next, computing cluster 0 in CIM die 0 broadcasts the result of the global reduction operation to computing cluster 1, computing cluster 2, and computing cluster 3 in CIM die 0 through NoC. Similarly, for each CIM die from CIM die 1 to CIM die 7, computing cluster 0 in the CIM die broadcasts the result of the global reduction operation to computing cluster 1, computing cluster 2, and computing cluster 3 in the CIM die 0 through NoC. Finally, all 32 computing clusters in the chip system obtain the result of the global reduction operation.

[0063] The process of the hierarchical global reduction operation described above involves three communication processes, which may cause significant latency and communication overhead.

[0064] From the above introduction to the reduction operations proposed in the related art, it can be seen that the reduction operations (such as global reduction operations, hierarchical reduction operations, and hierarchical global reduction operations) involve communication between multiple computing nodes. In large-scale systems, a considerable number of computing nodes may be involved, which may lead to large delays and communication overheads.

[0065] To solve the above technical problems, an embodiment of the present application provides a chip system. It should be understood that the chip system mentioned in the embodiment of the present application can be an independent chip or a part of a chip. The chip system includes multiple computing nodes and a shared memory of the multiple computing nodes, and the shared memory is used for the multiple computing nodes to perform reduction operations. The chip system can use the shared memory of multiple computing nodes to perform reduction operations between multiple computing nodes without communicating between multiple computing nodes, which can reduce the delay and communication overhead of the reduction operation, thereby improving the computing performance of the chip system.

[0066] Combine the following Figure 5 , the chip system 50 provided in the embodiment of the present application is introduced in more detail.

[0067] The chip system 50 provided in the embodiment of the present application may include multiple computing nodes, where the computing nodes may be, for example, the computing cluster mentioned above.

[0068] The embodiment of the present application does not specifically limit the number of computing nodes included in the chip system 50. Figure 5 4 computing nodes are shown, namely computing node 500, computing node 510, computing node 520 and computing node 530. However, the number of computing nodes included in the chip system 50 in the embodiment of the present application is not limited thereto. The chip system 50 may include a greater number or a lesser number of computing nodes.

[0069] The chip system 50 may also include a shared memory 540 of multiple computing nodes. The shared memory here can be understood as a memory area shared by multiple computing nodes. The embodiment of the present application does not specifically limit the type of shared memory. Multiple computing nodes can directly access the shared memory, so that data can be written and / or read from the shared memory. In other words, multiple data corresponding to multiple computing nodes can be stored in the shared memory. One or more computing nodes in the multiple computing nodes can directly access the shared memory to read the data corresponding to other computing nodes. In this way, a data sharing mechanism is provided, so that one or more computing nodes of the chip system can obtain data of other computing nodes by directly accessing the shared memory without communicating with other computing nodes, thereby reducing the communication overhead caused by one or more computing nodes obtaining data of other computing nodes. In addition, since the speed at which the computing node obtains the corresponding data of other computing nodes by accessing the shared memory is faster than the speed at which the computing node obtains the corresponding data of other computing nodes by communicating with other computing nodes, the use of shared memory can also reduce the delay caused by one or more computing nodes obtaining data of other computing nodes.

[0070] The above-mentioned multiple computing nodes and shared memory may belong to one computing unit. The computing unit here may have a uniform memory access (UMA) architecture. For a computing unit with a UMA architecture, the computing nodes included in the computing unit may share memory. The memory may be regarded as a unified resource pool, and the computing nodes in the computing unit may access the shared memory through the same path, so the latency of any computing node accessing any memory location is the same. The computing unit here may be a chip that supports in-memory computing.

[0071] As mentioned above, the reduction operation involves a process in which one or more computing nodes obtain data corresponding to other computing nodes, and the above-mentioned shared memory can be used for a certain (or several) computing nodes to obtain data corresponding to other computing nodes. Therefore, the shared memory 540 in the chip system 50 can be used for the above-mentioned multiple computing nodes to perform reduction operations. The reduction operation here can be, for example, the primary form of the reduction operation mentioned above, the global reduction operation. In addition, the reduction operation of multiple computing nodes can belong to a hierarchical reduction operation, or a part of a hierarchical global reduction operation. The reduction operation here can be performed by any one of the multiple computing nodes. Alternatively, the reduction operation here can also be performed by multiple computing nodes respectively. For ease of description, the node that performs the reduction operation can be referred to as the first computing node. That is, the first computing node can be a computing node among the multiple computing nodes in the chip system. As an example, the first computing node can be determined based on the data processing rate of multiple computing nodes. For example, the first computing node can be the computing node with the fastest data processing rate among the multiple computing nodes, which can improve the computing efficiency of the reduction operation. For another example, the first computing node is determined based on the current load of multiple computing nodes. For example, the first computing node may be a computing node with the lightest current load among the multiple computing nodes, which is conducive to achieving load balancing among the multiple computing nodes.

[0072] The chip system has Figure 5 Taking the structure shown as an example, the first computing node may include one of the following: computing node 500 , computing node 510 , computing node 520 , and computing node 530 .

[0073] Combine the following Figure 6 This article describes in detail the process of the first computing node using shared memory to perform the reduction operation. Figure 6 As shown, the process of the first computing node performing the reduction operation using the shared memory may include the following steps S610 to S630.

[0074] In step S610, the first computing node reads multiple data from the shared memory. The multiple data are the data corresponding to the multiple computing nodes mentioned above. The data corresponding to the multiple computing nodes are stored in the shared memory.

[0075] In step S620, the first computing node determines a first reduction result corresponding to the reduction operation according to the multiple data. After the first computing node reads the multiple data from the shared memory, it can determine the first reduction result corresponding to the reduction operation according to the multiple data. The reduction operation mentioned here may include but is not limited to summation, multiplication, maximum value, other custom functions, etc. If the reduction operation is a summation operation, the first reduction result may be the sum of the multiple data. If the reduction operation is a multiplication operation, the first reduction result may be the product of the multiple data. If the reduction operation is a maximum value, the first reduction result may be the maximum value of the multiple data.

[0076] In step S630, the first computing node stores the first reduction result in the shared memory. After obtaining the first reduction result, the first computing node may store the first reduction result in the shared memory.

[0077] Through the above steps S610 to S630, the reduction operation between multiple computing nodes in the chip system is completed by using the shared memory in the chip system. From the above description, it can be seen that in the process of performing the reduction operation, the first computing node can obtain the data corresponding to the remaining computing nodes through the shared memory, rather than obtaining the data corresponding to the remaining computing nodes by communicating with the remaining computing nodes. In addition, the first computing node allows the remaining computing nodes to obtain the result of the reduction operation by writing the result of the reduction operation to the shared memory, without sending the result of the reduction operation to the remaining computing nodes by communicating with the remaining computing nodes. Therefore, using shared memory to perform the reduction operation can reduce the delay and communication overhead of the reduction operation.

[0078] The above step S610 mentions: the first computing node reads multiple data from the shared memory. Before reading the multiple data, the first computing node needs to first obtain multiple storage addresses corresponding to the multiple data. In some implementations, the first computing node can communicate with other computing nodes to obtain the multiple storage addresses.

[0079] In some other implementations, the shared memory may include multiple storage addresses corresponding to the multiple computing nodes one by one. The first computing node may pre-store a one-to-one correspondence between the multiple computing nodes and the multiple storage addresses. In this case, the first computing node may read multiple data from the multiple storage addresses respectively according to the correspondence. Compared with the previous implementation, this implementation reduces the communication overhead between computing nodes (i.e., there is no need to determine multiple storage addresses by communication).

[0080] The above step S630 mentions: the first computing node stores the first reduction result to the shared memory. The embodiment of the present application does not specifically limit the storage location of the first reduction result in the shared memory. In some implementations, a storage address dedicated to storing the reduction result (hereinafter referred to as the target storage address for ease of description) may be set in the shared memory. After obtaining the first reduction result, the first computing node may store the first reduction result at the target storage address. In this way, other computing nodes can directly obtain the first reduction result from the target storage address without the need for the first computing node to notify other computing nodes of the storage address of the first reduction result, thereby reducing communication overhead.

[0081] Alternatively, as mentioned above, the shared memory may include multiple storage addresses corresponding to multiple computing nodes one by one. After obtaining the first reduction result, the first computing node may store the first reduction result to the storage address corresponding to the first computing node (hereinafter referred to as the target storage address). In this way, other computing nodes can directly obtain the first reduction result from the target storage address without the first computing node notifying other computing nodes of the storage address of the first reduction result, thereby reducing communication overhead.

[0082] Next, continue to combine Figure 6 The following describes in detail how to apply the chip system provided in the embodiment of the present application to the hierarchical reduction operation.

[0083] As mentioned above, the chip system provided in the embodiment of the present application may include multiple computing nodes and shared memories of the multiple computing nodes. Multiple computing nodes and shared memories of the multiple computing nodes may belong to one computing unit. In some implementations, the chip system may include multiple such computing units. That is, the chip system may include multiple computing units, each of which includes multiple computing nodes and shared memories of the multiple computing nodes. In this case, the chip system may have the following Figure 2 The hardware architecture is shown.

[0084] The multiple computing units may be chips that support in-memory computing. The chip here may be, for example, a bare chip. The embodiment of the present application does not specifically limit the number of computing units included in the chip system. The number of computing nodes included in the multiple computing units may be different. Alternatively, the number of computing nodes included in the multiple computing units may also be the same. For example, the chip system includes 8 CIM bare chips, each of which includes 4 computing clusters and 1 shared memory.

[0085] Multiple computing units can be connected to each other by communication. Optionally, in some embodiments, multiple computing units can be connected to each other by communication via an IO chip. The IO chip here can be understood as a chip specifically responsible for processing input and output functions. The IO chip can include circuits and logic required to implement data input and output. The IO chip can be, for example, an IO die. Optionally, in some embodiments, multiple computing units can communicate based on the UCIE protocol. The UCIE protocol can be understood as a communication protocol for connecting multiple chips in the same package. As a specific example, the chip system includes 8 CIM dies, and the shared memories of the 8 CIM dies can communicate based on the UCIE protocol via the IO die.

[0086] As mentioned above, a reduction operation can be performed between multiple computing nodes in a computing unit to obtain a first reduction result corresponding to the computing unit. When the chip system includes multiple computing units, the multiple computing units can all perform the above reduction operation to obtain the first reduction results corresponding to each of the multiple computing units. After obtaining the first reduction results corresponding to each of the multiple computing units, a reduction operation can be performed between the multiple computing units according to the first reduction results corresponding to each of the multiple computing units.

[0087] In some implementations, the multiple computing units may also perform reduction operations based on a shared memory. For ease of distinction, the shared memory between the multiple computing nodes mentioned above may be referred to as a first shared memory. In addition to the first shared memory, a second shared memory is provided in a data transmission unit between the multiple computing units (for example, the IO chip mentioned above, which is used for data transmission between the multiple computing units). Multiple computing units may perform reduction operations based on the second shared memory. For example, the first computing unit among the multiple computing units is used to perform the following operations: read the first reduction results corresponding to each of the multiple computing units from the second shared memory; determine the second reduction result based on the first reduction results corresponding to each of the multiple computing units; and store the second reduction result in the second shared memory. The way in which multiple computing units perform reduction operations may be similar to the way in which multiple computing nodes perform reduction operations, which will not be described in detail here.

[0088] The reduction operation performed between the multiple computing units may be a global reduction operation, which is equivalent to using the chip system including the multiple computing units for the hierarchical global reduction operation.

[0089] Optionally, the global reduction operation performed between the multiple computing units can be performed by the multiple computing units respectively. In this case, each of the multiple computing units can communicate with the remaining computing units to obtain the first reduction results corresponding to the remaining computing units. Each of the multiple computing units can perform the global reduction operation according to the first reduction result corresponding to itself and the first reduction results corresponding to the remaining computing units to obtain the result of the global reduction operation.

[0090] See below Figure 7 and Figure 8 , the chip system has Figure 2 The hardware architecture shown in FIG. 1 is a computing unit having the following features: Figure 5 The hardware architecture shown in FIG. 1 is taken as an example, and a specific example is used to describe in detail how to use the chip system provided by the embodiment of the present application to perform a hierarchical global reduction operation. In the following example, the chip system includes 8 CIM dies, each of which includes 4 computing clusters and 1 shared memory. The shared memories of the 8 CIM dies can communicate through the IO die.

[0091] See also Figure 7 In each CIM die, the data corresponding to computing cluster 0, computing cluster 1, computing cluster 2, and computing cluster 3 are recorded as d0, d1, d2, and d3 respectively. These four pieces of data are stored in the shared memory in sequence, and the sizes of these four pieces of data are the same. The reduction operation can be performed in each CIM die through the following steps 1 to 3.

[0092] In step 1, computing cluster 0 reads d0, d1, d2, and d3 from shared memory at once.

[0093] In step 2, computing cluster 0 adds d0, d1, d2, and d3 to obtain the sum of the four data as the first reduction result.

[0094] In step 3, computing cluster 0 writes the first reduction result to the shared memory and records the written data as d0. Finally, only d0 is left in the shared memory, as shown in Figure 8 shown.

[0095] The computing cluster 0 in the eight CIM dies included in the chip system all executes the above steps 1 to 3. The first reduction result d0 corresponding to each CIM die is stored in the shared memory of each CIM die.

[0096] Afterwards, each CIM die may complete the hierarchical global reduction operation by executing the following steps 4 to 6. In the following description, the first CIM die among the eight CIM die is taken as an example for illustration.

[0097] In step 4, the shared memory of the first CIM die communicates with the shared memories of the remaining seven CIM die through the IO die to obtain the first reduction result d0 stored in the shared memories of the remaining seven CIM die.

[0098] In step 5, the computing cluster 0 in the first CIM die adds together the eight first reduction results d0 corresponding to the eight CIM die, respectively, to obtain a second reduction result as a global reduction result.

[0099] In step 6, computing cluster 0 in the first CIM die stores the second reduction result in the shared memory of the first CIM die, so that computing clusters 1, 2 and 3 in the first CIM die can obtain the global reduction result from the shared memory.

[0100] After all eight CIM dies in the chip system perform steps 1 to 6 above, the hierarchical global reduction operation is completed. Finally, all 32 computing clusters in the chip system can obtain the global reduction results through shared memory.

[0101] Combination of the above Figures 2 to 8 , describes in detail an embodiment of the chip system provided by the present application. The following describes in detail a method embodiment of the present application. It should be understood that the description of the method embodiment corresponds to the description of the chip system embodiment. Therefore, the part not described in detail can refer to the description of the previous chip system embodiment.

[0102] The embodiment of the present application also provides a method for processing data, which is executed by the aforementioned chip system 50. As mentioned above, the chip system 50 includes multiple computing nodes and a shared memory of the multiple computing nodes, and the shared memory stores multiple data corresponding to the multiple computing nodes one by one. Fig. 9 FIG. 1 is a schematic flow chart of a method for processing data provided by an embodiment of the present application. Fig. 9 As shown, the method may include the following steps S910 to S930.

[0103] In step S910 , a first computing node among multiple computing nodes reads multiple data from a shared memory.

[0104] In step S920, the first computing node determines a first reduction result corresponding to the reduction operation according to the plurality of data.

[0105] In step S930 , the first computing node stores the first reduction result in the shared memory.

[0106] In some implementations, the shared memory includes multiple storage addresses corresponding one-to-one to the multiple computing nodes, and the first computing node stores a one-to-one correspondence between the multiple computing nodes and the multiple storage addresses, and the first computing node among the multiple computing nodes reads the multiple data from the shared memory, including: the first computing node reads the multiple data from the multiple storage addresses respectively according to the correspondence; the first computing node stores the first reduction result to the shared memory, including: the first computing node stores the first reduction result to a target storage address, and the target storage address is the storage address corresponding to the first computing node or a storage address in the shared memory dedicated to storing reduction results.

[0107] In some implementations, the plurality of computing nodes include a second computing node configured to read the first reduction result from the target storage address.

[0108] In some implementations, the first reduction result is stored at a storage address in the shared memory dedicated to storing reduction results.

[0109] In some implementations, the first computing node is determined based on data processing rates of the plurality of computing nodes; and / or the first computing node is determined based on current loads of the plurality of computing nodes.

[0110] In some implementations, the multiple computing nodes and the shared memory belong to a computing unit in the chip system, the chip system includes multiple computing units, and the method further includes: the multiple computing units perform a reduction operation according to their respective corresponding first reduction results.

[0111] In some implementations, the shared memory of the multiple computing nodes is a first shared memory, the chip system includes a data transmission unit, the multiple computing units are connected through the data transmission unit, and the data transmission unit includes a second shared memory; the multiple computing units perform a reduction operation according to their respective corresponding first reduction results, including: a first computing unit among the multiple computing units reads the first reduction results corresponding to each of the multiple computing units from the second shared memory; the first computing unit determines a second reduction result according to the first reduction results corresponding to each of the multiple computing units; and the first computing unit stores the second reduction result to the second shared memory.

[0112] In some implementations, the data transmission unit is an IO chip.

[0113] In some implementations, the reduction operation performed between the multiple computing units is a global reduction operation.

[0114] In some implementations, the computing unit is a chip that supports in-memory computing.

[0115] The embodiment of the present application further provides a computer-readable storage medium having program codes stored thereon, and the program codes can be used to execute the method for processing data in any of the above embodiments.

[0116] The embodiment of the present application further provides a computer program product, which includes program code for executing the method for processing data in any of the above embodiments.

[0117] It should be understood that in the embodiment of the present application, determining B based on A does not mean determining B only based on A, but B can also be determined based on A and / or other information.

[0118] It should be understood that in the embodiment of the present application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0119] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0120] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0121] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0122] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0123] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0124] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that can be read by a computer or a data storage device such as a server or data center that contains one or more available media integrated. The available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, digital video disc (DVD)), or semiconductor media (eg, solid state disk (SSD)), etc.

[0125] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip system, characterized in that: It includes multiple computing nodes and shared memory of the multiple computing nodes, and the shared memory is used for the multiple computing nodes to perform reduction operations.

2. The chip system according to claim 1, characterized in that: The shared memory stores a plurality of data corresponding to the plurality of computing nodes one by one, and the first computing node among the plurality of computing nodes is used to perform the following operations: Reading the plurality of data from the shared memory; Determine a first reduction result corresponding to the reduction operation according to the multiple data; The first reduction result is stored in the shared memory.

3. The chip system according to claim 2, characterized in that: The shared memory includes a plurality of storage addresses corresponding to the plurality of computing nodes one by one, and the first computing node stores a one-to-one correspondence between the plurality of computing nodes and the plurality of storage addresses, The reading the plurality of data from the shared memory comprises: According to the corresponding relationship, read the multiple data from the multiple storage addresses respectively; The storing the first reduction result to the shared memory includes: The first reduction result is stored in a target storage address, where the target storage address is a storage address corresponding to the first computing node or a storage address in the shared memory dedicated to storing reduction results.

4. The chip system according to claim 3, characterized in that: The plurality of computing nodes include a second computing node, and the second computing node is configured to read the first reduction result from the target storage address.

5. The chip system according to claim 2, characterized in that: The first reduction result is stored in a storage address in the shared memory dedicated to storing reduction results.

6. The chip system according to claim 2, characterized in that: The first computing node is determined based on the data processing rate of the plurality of computing nodes; and / or, The first computing node is determined based on current loads of the plurality of computing nodes.

7. The chip system according to any one of claims 1 to 6, characterized in that: The multiple computing nodes and the shared memory belong to a computing unit in the chip system, the reduction operation between the multiple computing nodes is used to determine a first reduction result in the computing unit, and the chip system includes the multiple computing units, which are communicatively connected to perform reduction operations between the multiple computing units according to the first reduction results corresponding to each of the multiple computing units.

8. The chip system according to claim 7, characterized in that: The shared memory of the multiple computing nodes is a first shared memory, the chip system includes a data transmission unit, the multiple computing units are connected through the data transmission unit, and the data transmission unit includes a second shared memory; The first computing unit among the plurality of computing units is configured to perform the following operations: Reading from the second shared memory the first reduction results corresponding to each of the plurality of computing units; Determine a second reduction result according to the first reduction results corresponding to each of the plurality of computing units; The second reduction result is stored in the second shared memory.

9. The chip system according to claim 8, characterized in that: The data transmission unit is an IO chip.

10. The chip system according to claim 7, characterized in that: The reduction operation performed among the multiple computing units is a global reduction operation.

11. The chip system according to claim 7, characterized in that: The computing unit is a chip that supports in-memory computing.

12. A method for processing data, characterized in that: The method is applied to a chip system, which includes a plurality of computing nodes and a shared memory of the plurality of computing nodes, wherein the shared memory stores a plurality of data corresponding to the plurality of computing nodes one by one. The method comprises: A first computing node among the multiple computing nodes reads the multiple data from the shared memory; The first computing node determines a first reduction result corresponding to the reduction operation according to the multiple data; The first computing node stores the first reduction result in the shared memory.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code for executing the method of claim 12.

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