Digital array antenna and digital circuit synchronization method, device, equipment and medium

Abstract

The invention relates to a digital array antenna and digital circuit synchronization method, device, equipment and medium, and the digital array antenna and digital circuit synchronization method comprises the steps: carrying out the module preprocessing of a master module and a slave module, and the module preprocessing comprises the configuration of FPGA codes for the master module and the slave module and the initialization of a radio frequency transceiver; the master module triggers a module handshake request to the slave module, and obtains a signal receiving state of the slave module according to the module handshake request; the master module sends a synchronous trigger signal, a synchronous pulse generator is triggered to generate a synchronous pulse signal, and the master module and all the slave modules perform radio frequency transceiver local oscillator phase synchronization through a clock signal and a first pulse of the synchronous pulse signal; and the master module and all the slave modules perform sampling clock synchronization, digital clock synchronization and interface synchronization of the A / D converter and the D / A converter through the clock signal and the second pulse of the synchronization pulse signal to complete synchronization. According to the invention, the digital array antenna and the digital circuit can be synchronized.

Description

Technical Field

[0001] The present application relates to the technical field of antenna and digital circuit synchronization, and in particular to a method, device, equipment and medium for synchronizing a digital array antenna and a digital circuit. Background Art

[0002] At present, digital array antennas that can generate multiple beams are essential devices for mobile phone direct connection and Internet communication satellites. Among them, the multi-beam forming system is the key to the digital array antenna. It has two main functions: one is to convert the RF signal received by each element of the array antenna into a digital signal, and form multiple receiving beams for it, generate digital baseband signals received by each beam, and transmit them to the communication device, thereby completing multi-beam reception; the other is to receive the digital baseband signals of each beam from the communication device, form multiple transmitting beams for it, generate digital signals corresponding to each element of the array antenna, and then convert the digital signal into a RF transmitting signal, and transmit it to each element of the array antenna, thereby realizing multi-beam transmission.

[0003] Low-orbit communication satellites used in the commercial aerospace field are limited by cost, volume, weight and power consumption, requiring products to be as small and lightweight as possible. The array signal processing in the digital array antenna requires a large number of RF receiving channels, transmitting channels, local oscillator frequency synthesizers, A / D converters, D / A converters, large-bandwidth interface circuits, resource-rich processing circuits and complex synchronization circuits. It is a large, distributed, integrated RF circuit and digital circuit, high-speed computing and transmission complex system. This requires simplifying the circuit design as much as possible, compressing the circuit scale, and using large-scale integrated circuits and system-on-chip (SoC) as much as possible, and finally realizing an integrated, miniaturized, distributed satellite-borne digital array antenna multi-beamforming system.

[0004] The digital array antenna multi-beamforming system is a phase-coherent system. In order to ensure that the received signals and the transmitted signals are aligned in time and fully coherent in phase, it is necessary to ensure the phase synchronization between the mixed local oscillator signals of all receiving channels in the system, the phase synchronization between the mixed local oscillator signals of all transmitting channels, the synchronization of all A / D converter sampling clocks, the synchronization of all D / A converter sampling clocks, the synchronization of all digital signal processing clocks (i.e., digital clocks), and the synchronization of all high-speed digital interfaces.

[0005] The invention patent with patent number CN109194360A discloses a 16-channel digital multi-beam transceiver front-end component, which uses the same reference clock to generate a local oscillator signal, and then uses a power divider and amplifier circuit to convert one local oscillator signal into 16 signals, providing fully coherent local oscillator sources for the mixers of the 16 receiving channels. This solution is suitable for situations where the number of digital array antenna elements is small and the local oscillator frequency synthesizer and the transceiver channel can be integrated into one module. When the number of array antenna elements is large, the scale of the above-mentioned power divider and amplifier circuit and its interconnection cable with the receiving channel will be unacceptably large.

[0006] The invention patent with patent number CN109683137A discloses a multi-channel synchronization method applied to phased array radar. The patent discloses a high sampling frequency digital multi-channel system, which consists of a common component and multiple digital components. The common component generates the power supply, clock, common signal and synchronization trigger signal required by the digital component. The common signal and the clock signal need to be strictly synchronized, that is, the transmission path of the signal to each digital component must be of equal length, and there is no strict requirement for the trigger signal. The digital component is mainly composed of an A / D converter, a D / A converter and an FPGA. The A / D converter, the D / A converter and the FPGA are connected through the JESD204B high-speed serial port. In order to realize the sampling clock synchronization of the A / D converter and the D / A converter between different digital components and the JESD204B serial port synchronization, it is necessary to provide strictly synchronized clock signals and synchronization pulse signals for all digital components. The method disclosed in the patent is: a common component generates a clock signal, a common signal, and a trigger signal that is strictly synchronized between all digital components. The common signal is a pulse signal with an initial level of high level. The common component generates a trigger signal at its first falling edge. The trigger signal is a pulse signal with an effective level of high level, and its pulse width is much smaller than the pulse width of the common signal. The clock signal and the common signal transmitted from the common component to each digital component in the system are strictly equal in length and have the same transmission delay. The trigger signal is not required to be equal in length, and the transmission delay can be different. In each digital component, the FPGA latches the level of the trigger signal at the first clock signal rising edge after the first falling edge of the common signal, and generates a synchronization pulse signal at the first clock signal rising edge after the second falling edge of the common signal. If the difference between the maximum transmission delay and the minimum transmission delay of the trigger signal transmitted from the common component to each digital component is less than the pulse width of a common signal, the synchronization pulse signal generated by each digital component can ensure strict synchronization. The patent discloses a method for achieving synchronization between each digital component, but does not disclose how to maintain strict synchronization between multiple A / D converters, D / A converters, and FPGAs in each digital component. In fact, the synchronization pulse signal generated by FPGA needs to regenerate multiple synchronization pulse signals to distribute to all A / D converters and D / A converters inside the digital components. If FPGA is used to generate multiple synchronization pulse signals, the signal routing paths inside the FPGA are different, and the transmission delay is also different. Moreover, every time the FPGA code is recompiled and synthesized, it is difficult to ensure that the transmission delay between code versions remains consistent. Therefore, it is difficult to ensure that each synchronization pulse and clock signal time maintain the necessary synchronization relationship, which greatly increases the difficulty of system synchronization. In addition, when the number of digital components is large, the interconnection signal resources between the common components and each digital component are limited and very valuable, and the number of unnecessary signals transmitted between components should be minimized. The method published in this patent requires a special trigger signal, which increases the burden of system interconnection.

[0007] Therefore, a synchronization method for the RF local oscillator synchronization, A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and high-speed digital interface synchronization of a miniaturized, distributed satellite-borne digital array antenna multi-beamforming system is needed. Summary of the invention

[0008] In order to synchronize a digital array antenna and a digital circuit, the present application provides a method, apparatus, device and medium for synchronizing a digital array antenna and a digital circuit.

[0009] The above-mentioned invention objective of the present application is achieved through the following technical solutions: A digital array antenna and digital circuit synchronization method, comprising a backplane, a master module connected to the backplane, and a plurality of slave modules, the digital array antenna and digital circuit synchronization method comprising: Performing module preprocessing on the master module and the slave module, wherein the module preprocessing includes configuring FPGA code and initializing a radio frequency transceiver on the master module and the slave module; The master module triggers a module handshake request to the slave module, and acquires a signal receiving state of the slave module according to the module handshake request; The master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal, and the master module and all the slave modules perform phase synchronization of the local oscillator of the radio frequency transceiver through the clock signal and the first pulse of the synchronization pulse signal; The master module and all the slave modules perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete the synchronization.

[0010] By adopting the above technical solution, firstly, by performing module preprocessing on the master module and the slave module, it is ensured that each module can correctly configure the FPGA code and initialize the RF transceiver at startup. This preprocessing step lays the foundation for subsequent synchronization operations and ensures that all modules are in the same initial state, thereby reducing the risk of synchronization failure caused by inconsistent initial states. Secondly, the master module triggers a module handshake request to the slave module to obtain the signal reception status of the slave module. This process is implemented through a serial bus interface, ensuring that the master module can accurately understand the status of each slave module. Specifically, the master module sends a clock signal handshake request and a synchronization pulse handshake request, which are combined into a module handshake request. After receiving these requests, the slave module will feedback its own clock signal reception status and synchronization pulse reception status. After collecting these status information, the master module can determine which slave modules are ready to receive the synchronization signal and which ones need further adjustment. This step effectively avoids the overall synchronization failure caused by the unpreparedness of some modules during the synchronization process, and improves the reliability of the system. Then, the master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. This synchronization pulse signal is one of the core signals for system synchronization, which is used to ensure that all modules start to perform synchronization operations at the same time. The master module and all slave modules synchronize the RF transceiver local oscillator phase through the clock signal and the first pulse of the synchronization pulse signal. In this process, the role of the synchronization pulse signal is to provide an accurate time reference so that the mixed local oscillator signals of all RF transceivers can reach the same phase at the same time. In this way, it is ensured that all RF transceivers maintain full coherence when receiving and transmitting signals, which is crucial for multi-beam forming. Subsequently, the master module and all slave modules synchronize the A / D converter and D / A converter sampling clock, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal. In this step, the second pulse of the clock signal and the synchronization pulse signal is used to calibrate the sampling clocks of the A / D converter and D / A converter in each module to ensure that they are sampled at the same time. At the same time, digital clock synchronization is also performed to ensure that the digital signal processing circuits in all modules run at the same time point. Finally, the synchronization of the JESD204B interface is completed, which is an important interface for data transmission between the RF transceiver and the FPGA, ensuring that there will be no timing errors in the data transmission process. During the entire synchronization process, by adjusting the transmission delay of the clock distributor and synchronization pulse distributor inside each module, it is ensured that the clock rising edge and synchronization pulse between all modules maintain a fixed timing relationship. This method not only simplifies the hardware design and reduces the difficulty of printed circuit board wiring, but also improves the stability and reliability of the system.In this way, the present invention successfully solves the problems existing in the prior art such as the large variety of synchronization signals and the shortage of interconnection signal resources, and realizes the efficient synchronization of a highly integrated, miniaturized, distributed satellite-borne digital array antenna multi-beam forming system.

[0011] In a preferred example, the present application may be further configured as follows: the master module triggers a module handshake request to the slave module, and acquires the signal receiving state of the slave module according to the module handshake request, specifically including: The master module triggers a clock signal handshake request and a synchronization pulse handshake request, and combines the clock signal handshake request and the synchronization pulse signal handshake request into the module handshake request; A clock signal receiving state and a synchronization pulse receiving state are acquired from each of the slave modules, and the clock signal receiving state and the synchronization pulse receiving state are combined into the signal receiving state and sent to the master module.

[0012] By adopting the above technical solution, the master module can efficiently and accurately perform handshake operations with the slave modules to ensure the reliability of system synchronization. The master module first triggers the clock signal handshake request and the synchronization pulse handshake request, and these two requests are combined into a module handshake request. This process ensures that the master module can actively initiate a synchronization request at the beginning of the system startup to avoid synchronization failure caused by the failure of the slave module to respond in time. The clock signal reception status and the synchronization pulse reception status are obtained from each slave module, and these two states are combined into a signal reception status and sent back to the master module. This step is crucial because it not only verifies that the slave module has successfully received the clock signal and the synchronization pulse signal, but also provides basic data for subsequent synchronization operations. Through the above handshake process, the master module can confirm that all slave modules are ready to receive and process the clock signal and the synchronization pulse signal. This step eliminates the time deviation problem caused by inconsistent signal transmission paths, ensures that all modules start synchronous operation at the same time, and improves the overall synchronization accuracy of the system. The board level resource manager (BMC) realizes handshake and control information interaction between modules through the serial bus interface. This design reduces the number of signal lines inside the system, reduces the difficulty of wiring, and also improves the reliability and stability of the system. Each clock signal and synchronization pulse signal can independently adjust the transmission delay in rough and fine adjustments, without the need for long wiring such as printed circuit boards. This feature allows the system to more flexibly respond to various environmental changes in practical applications, further improving the adaptability of the system. By dividing the multi-beam transceiver processing module into a master module and a slave module, the only difference between the two modules is that the master module needs to provide a clock signal and a synchronization pulse signal. This design not only simplifies the system architecture, but also facilitates production and maintenance, reducing costs.

[0013] In a preferred example, the present application can be further configured as follows: the master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal, and the master module and all the slave modules perform RF transceiver local oscillation phase synchronization through the clock signal and the first pulse of the synchronization pulse signal, specifically including: The clock signal and the synchronization pulse signal sent by the main module are received through the backplane.

[0014] By adopting the above technical solution, the master module and all slave modules can receive the clock signal and synchronization pulse signal sent by the master module through the backplane, ensuring that the clock signal and synchronization pulse signal received by each module are consistent in time and phase, thereby achieving accurate synchronization of the local oscillator phase of the RF transceiver. This synchronization mechanism reduces the delay difference caused by unequal signal transmission paths and improves the stability and reliability of the system.

[0015] In a preferred example, the present application can be further configured as follows: the master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal, and the master module and all the slave modules perform RF transceiver local oscillation phase synchronization through the clock signal and the first pulse of the synchronization pulse signal, specifically including: Acquire the signal establishment time and signal duration corresponding to the synchronization pulse signal and the clock signal; The timing relationship between the rising edge of the synchronization pulse signal and the clock signal is acquired according to the signal establishment time and the signal duration, and the local oscillator phase synchronization is performed according to the timing relationship.

[0016] By adopting the above technical solution, after the master module sends the synchronization trigger signal, the synchronization pulse generator is triggered to generate the synchronization pulse signal. At this time, the master module and all slave modules first receive the clock signal and the synchronization pulse signal. In order to ensure the accurate synchronization of the local oscillator phase of the RF transceiver, it is necessary to accurately obtain the setup time and duration of the synchronization pulse signal and the clock signal. When the master module sends the synchronization trigger signal, the synchronization pulse generator will generate a synchronization pulse signal. This synchronization pulse signal is transmitted to each slave module together with the clock signal generated by the master module. After each slave module receives these two signals, it first detects the signal stability to ensure that the signal quality meets the requirements. Subsequently, the clock distributor and synchronization pulse distributor in the slave module will further process these signals to ensure that their propagation delays in their respective modules are consistent. Next, the slave module will read the setup time and duration of the synchronization pulse signal and the clock signal. The setup time here refers to the minimum time interval that the clock signal must be stable before the synchronization pulse signal arrives; the duration refers to the minimum time interval that the clock signal must remain stable after the synchronization pulse signal arrives. By accurately measuring these parameters, it can be ensured that the timing relationship between the synchronization pulse signal and the clock signal remains fixed at all times. After determining the timing relationship between the rising edge of the synchronization pulse signal and the clock signal, the master module and the slave module will synchronize the phase of the RF transceiver local oscillator according to this timing relationship. Specifically, the mixer local oscillator circuit inside each RF transceiver will be reset at the rising edge of the synchronization pulse signal, so that the phase of the local oscillator signal of all RF transceivers is consistent at the same time. In this way, whether in receiving mode or transmitting mode, the local oscillator signal of each RF transceiver can maintain strict phase synchronization, thereby ensuring the coherence of the entire multi-beam forming system. In addition, in order to further improve the synchronization accuracy, the time delay caused by the unequal transmission path length can be compensated by adjusting the internal delay of the clock and synchronization pulse generator in the master module. This means that even in actual applications, due to physical layout reasons, the length of the signal transmission path between different modules may be different, and this dynamic adjustment mechanism can be used to ensure that the timing relationship between all modules always meets the requirements.

[0017] In a preferred example, the present application can be further configured as follows: the master module and all the slave modules perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete synchronization, specifically including: The synchronization status of each slave module is obtained, and the synchronization status is sent to the master module to complete the synchronization.

[0018] By adopting the above technical solution, it is possible to ensure that the master module and all slave modules can accurately complete the A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization under the action of the clock signal and the second pulse of the synchronization pulse signal. Through the communication mechanism between the master module and the slave module, the master module can monitor the synchronization state of each slave module in real time to ensure that each slave module has successfully completed the synchronization operation. Once the slave module completes the synchronization, it will feed back its synchronization state to the master module, and the master module confirms the synchronization state of the entire system based on these feedback information, thereby ensuring that all modules complete the synchronization operation at the same time. After receiving the synchronization confirmation from all slave modules, the master module confirms that the entire system has completed the synchronization, ensuring the stability and reliability of the system. This technical solution ensures accurate synchronization between multiple modules by monitoring and feeding back the synchronization state of each slave module, thereby improving the overall performance and stability of the system.

[0019] The second object of the invention is achieved by the following technical solutions: A digital array antenna and digital circuit synchronization device, the digital array antenna and digital circuit synchronization device comprising: An initialization module, used for performing module preprocessing on the master module and the slave module, wherein the module preprocessing includes configuring FPGA code and initializing a radio frequency transceiver on the master module and the slave module; A handshake request module, used for the master module to trigger a module handshake request to the slave module, and obtain a signal receiving state of the slave module according to the module handshake request; A first synchronization module, used for the master module to send a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal, and the master module and all the slave modules perform phase synchronization of the local oscillator of the radio frequency transceiver through the clock signal and the first pulse of the synchronization pulse signal; The second synchronization module is used for the master module and all the slave modules to perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete the synchronization.

[0020] By adopting the above technical solution, firstly, by performing module preprocessing on the master module and the slave module, it is ensured that each module can correctly configure the FPGA code and initialize the RF transceiver at startup. This preprocessing step lays the foundation for subsequent synchronization operations and ensures that all modules are in the same initial state, thereby reducing the risk of synchronization failure caused by inconsistent initial states. Secondly, the master module triggers a module handshake request to the slave module to obtain the signal reception status of the slave module. This process is implemented through a serial bus interface, ensuring that the master module can accurately understand the status of each slave module. Specifically, the master module sends a clock signal handshake request and a synchronization pulse handshake request, which are combined into a module handshake request. After receiving these requests, the slave module will feedback its own clock signal reception status and synchronization pulse reception status. After collecting these status information, the master module can determine which slave modules are ready to receive the synchronization signal and which ones need further adjustment. This step effectively avoids the overall synchronization failure caused by the unpreparedness of some modules during the synchronization process, and improves the reliability of the system. Then, the master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. This synchronization pulse signal is one of the core signals for system synchronization, which is used to ensure that all modules start to perform synchronization operations at the same time. The master module and all slave modules synchronize the RF transceiver local oscillator phase through the clock signal and the first pulse of the synchronization pulse signal. In this process, the role of the synchronization pulse signal is to provide an accurate time reference so that the mixed local oscillator signals of all RF transceivers can reach the same phase at the same time. In this way, it is ensured that all RF transceivers maintain full coherence when receiving and transmitting signals, which is crucial for multi-beam forming. Subsequently, the master module and all slave modules synchronize the A / D converter and D / A converter sampling clock, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal. In this step, the second pulse of the clock signal and the synchronization pulse signal is used to calibrate the sampling clocks of the A / D converter and D / A converter in each module to ensure that they are sampled at the same time. At the same time, digital clock synchronization is also performed to ensure that the digital signal processing circuits in all modules run at the same time point. Finally, the synchronization of the JESD204B interface is completed, which is an important interface for data transmission between the RF transceiver and the FPGA, ensuring that there will be no timing errors in the data transmission process. During the entire synchronization process, by adjusting the transmission delay of the clock distributor and synchronization pulse distributor inside each module, it is ensured that the clock rising edge and synchronization pulse between all modules maintain a fixed timing relationship. This method not only simplifies the hardware design and reduces the difficulty of printed circuit board wiring, but also improves the stability and reliability of the system.In this way, the present invention successfully solves the problems existing in the prior art such as the large variety of synchronization signals and the shortage of interconnection signal resources, and realizes the efficient synchronization of a highly integrated, miniaturized, distributed satellite-borne digital array antenna multi-beam forming system.

[0021] The third objective of the present application is achieved through the following technical solutions: A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned method for synchronizing a digital array antenna and a digital circuit when executing the computer program.

[0022] The fourth objective of the present application is achieved through the following technical solutions: A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the digital array antenna and digital circuit synchronization method.

[0023] In summary, the present application includes at least one of the following beneficial technical effects: 1. Through the coordinated work of the master module and the slave module, a highly integrated RF transceiver is used to achieve synchronization of the mixer local oscillator phase, A / D converter and D / A converter sampling clock, digital clock and high-speed digital interface, solving the problem of high system complexity and cost in traditional methods when the number of array elements is large; 2. Each clock signal and synchronization pulse signal can independently adjust the transmission delay in rough and fine manner, without the need for long wiring of printed circuit boards, which greatly reduces the wiring difficulty of the multi-beam transceiver processing module and the printed circuit boards inside the backplane, and improves the flexibility and reliability of the system; 3. The board manager (BMC) implements handshake and control information interaction between modules through the serial bus interface, which simplifies system design and improves the overall coordination and stability of the system; 4. During the system synchronization process, the RF transceiver local oscillator phase is synchronized through the clock signal and the first pulse of the synchronization pulse signal, ensuring that the phase of the mixed local oscillator signals of all receiving channels and transmitting channels is consistent, thereby improving the accuracy and stability of multi-beam forming. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a block diagram of the multi-beam forming system of the satellite-borne digital array antenna in this embodiment.

[0025] Figure 2 This is a block diagram of the main circuit components of the RF transceiver chip in this embodiment.

[0026] Figure 3It is a block diagram of the clock and synchronization pulse generator in this embodiment.

[0027] Figure 4 It is a block diagram of the clock distributor in this embodiment.

[0028] Figure 5 It is a block diagram of the synchronous pulse distributor in this embodiment.

[0029] Figure 6 It is a flowchart of system synchronization processing in this embodiment.

[0030] Figure 7 This is the first example diagram of the timing relationship between the clock and the synchronization pulse in this embodiment.

[0031] Figure 8 This is the second example diagram of the timing relationship between the clock and the synchronization pulse in this embodiment.

[0032] Fig. 9 It is a schematic diagram of a device in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The present application is further described in detail below in conjunction with the accompanying drawings.

[0034] according to Figure 1 As shown in FIG. 1 , the system consists of a multi-beam transceiver processing master module A, M multi-beam transceiver processing slave modules B, and a backplane. In order to clearly describe the synchronization principle of the system, only the signal interconnection relationship related to synchronization is given in the figure, and other interconnections unrelated to synchronization are not given.

[0035] The master module A is mainly composed of N RF transceivers, a large-scale FPGA with rich on-chip resources, a board-level resource manager (BMC), clock and synchronization pulse distribution circuits, and clock and synchronization pulse generators. The only difference between the master module A and the slave module B is that the master module A provides the clock signal (DCLK) and synchronization pulse signal (SYSREF) for the entire system (including one master module A and M slave modules B). Except for the lack of clock and synchronization pulse generator, the other components of the slave module B are the same as those of the master module A. The same printed circuit board can be used to produce both master and slave modules by soldering different components.

[0036] The main function of the RF transceiver is to convert multi-channel RF receive signals into zero-IF baseband receive signals and transmit them to the FPGA, and convert the zero-IF baseband transmit signals sent by the FPGA into multi-channel RF transmit signals. The main function of the FPGA is to implement the digital beamforming algorithm for all RF transmit and receive channels of this module and to realize the synchronization interface with the RF transceiver.

[0037] The function of the board resource manager (BMC) is to implement board resource management within the multi-beam transceiver processing module and to implement handshake and control information interaction between modules through the serial bus interface. The serial bus interface can be an SPI interface, I 2 C interface, CAN bus interface or RS-485 bus interface, etc.

[0038] The function of the clock and synchronization pulse generator (only the master module A has this part of the circuit) is to generate M+1 clock signals and synchronization pulse signals required for the master module A and M slave modules B to synchronize the system.

[0039] The function of the clock and synchronization pulse distribution circuit is to receive the clock and synchronization pulse signals from the main module A and transmitted through the backplane, and to generate multiple clock signals and synchronization pulse signals required by N RF transceivers and FPGAs in this module. Although the number of clock and synchronization pulse signals given to the FPGA described in the figure is the same as the number of RF transceivers, different design schemes are allowed to use fewer clock and synchronization pulse signals.

[0040] The RF transceiver is a highly integrated, high-performance system-on-chip (SoC) chip that integrates RF circuits, mixed analog and digital circuits, and digital signal processing circuits in one chip. Its main function is to realize the transmission and reception of multiple RF signals. Specifically, its functions include: mixing, analog filtering, A / D conversion, digital filtering, extraction, DC offset correction, orthogonal error correction of RF receive signals, and transmitting baseband receive data to FPGA; interpolation, digital filtering, orthogonal error correction, local oscillator leakage correction, D / A conversion, analog filtering, orthogonal mixing of baseband transmit data from FPGA, generating RF transmit signals and outputting them.

[0041] according to Figure 2 As shown, Figure 2 The specific RF transceiver given in the specification has four receiving channels and four transmitting channels. RF transceivers with different numbers of RF receiving and transmitting channels may also be used. Currently available RF transceivers may have two receiving and two transmitting channels, four receiving and four transmitting channels, or eight receiving and eight transmitting channels on a single chip.

[0042] from Figure 2 It can be seen that the RF transceiver adopts an orthogonal mixing scheme and consists of multiple transceiver channels, multiple frequency synthesizers, clock generation and synchronization circuits, JESD204B high-speed interface and other parts.

[0043] Among them, the transceiver channel consists of two parts: the receiving channel and the transmitting channel: the receiving channel consists of a digitally controlled attenuator, an orthogonal mixer, a bandwidth-programmable low-pass filter, a high-speed A / D converter, a receiving digital processing circuit (including digital filtering, extraction, DC offset correction, orthogonal error correction), etc.; the transmitting channel consists of a transmitting digital processing circuit (including interpolation, digital filtering, local oscillator leakage correction, orthogonal error correction), a high-speed D / A converter, a bandwidth-programmable low-pass filter, an orthogonal mixer, a digitally controlled attenuator, etc.

[0044] The frequency synthesizer consists of three parts: the receiving local oscillator frequency synthesizer, the transmitting local oscillator frequency synthesizer and the digital clock frequency synthesizer, which respectively generate the receiving channel mixing local oscillator, the transmitting channel mixing local oscillator and the digital clock (including A / D converter, D / A converter, receiving digital processing circuit, transmitting digital processing circuit and the clock required for the JESD204B interface).

[0045] The function of the clock generation and synchronization circuit is to receive the clock and synchronization pulse signals input from the outside of the chip, generate the multi-channel clock signals and synchronization pulse signals required by the three frequency synthesizers, and also generate the synchronization pulse signals required by the JESD204B high-speed digital interface.

[0046] The function of the JESD204B high-speed digital interface is to synchronously transmit digital baseband signals (including receive signals and transmit signals) between the RF transceiver and the FPGA.

[0047] The function of the clock and synchronization pulse generator (only the master module A has this part of the circuit) is to generate M+1 clock signals and synchronization pulse signals required for system synchronization of a master module A and M slave modules B. Its composition block diagram is shown in Figure 3 The reference clock (REFCLK) in the figure can be either an onboard clock or an external reference clock provided by the backplane. The reference clock is input to the frequency synthesizer, which generates the clock source required by the system. The frequency synthesizer can be either integer-divided or fractional-divided.

[0048] The clock source generated by the frequency synthesizer is input to an integrated circuit called "clock distribution, synchronization generation and distributor". Inside the integrated circuit, the input clock is driven by the driver and sent to the clock distributor and the synchronization pulse generator. The clock distributor converts a common input clock into M+1 output clocks. The transmission delay of each clock can be coarsely adjusted and finely adjusted. The coarse adjustment step is half of the input clock cycle, the fine adjustment step is generally tens of picoseconds, and the adjustment range is generally hundreds of picoseconds. The synchronization pulse generator uses the input clock signal as the working clock. After receiving the synchronization trigger signal from the board resource manager (BMC), it generates the required synchronization pulse signal. The synchronization pulse signal can be a single pulse or a pulse sequence composed of multiple pulses. The synchronization pulse signal enters the synchronization pulse divider, which converts a common synchronization pulse signal into M+1 synchronization pulse signals. The transmission delay of each step pulse signal can be coarsely adjusted and finely adjusted. The coarse adjustment step is half of the input clock cycle, the fine adjustment step is generally tens of picoseconds, and the adjustment range is generally hundreds of picoseconds.

[0049] The output signals of clock distribution, synchronization generation and distributor are generally differential levels that require transmission impedance matching, including but not limited to LVPECL, LVDS, HSTL, CML, etc. By controlling the characteristic impedance of the transmission line and the receiving terminal impedance, the rising and falling edges of the clock and synchronization pulse signals are guaranteed to be steep enough, and the rise time and fall time are short enough, generally between 100ps and 1000ps. Clock distribution, synchronization generation and distributor have the above-mentioned transmission delay adjustment function, so there is no need to require the transmission paths of M+1 clock signals and synchronization pulse signals to be strictly equal in length. It is only necessary to control the difference in transmission line delay within the integrated circuit delay adjustment range, which greatly reduces the difficulty of printed circuit board wiring of the multi-beam transceiver processing module and the backplane.

[0050] Both the master module A and the slave module B have clock and synchronization pulse distribution circuits, whose functions are: receiving clock and synchronization pulse signals from the master module A and transmitted through the backplane, and generating multiple clock signals and synchronization pulse signals required by N RF transceivers and FPGAs in this module.

[0051] The clock and synchronization pulse distribution circuit is divided into two parts: clock distributor and synchronization pulse distributor. The block diagrams are shown in Figure 4 and Figure 5 The circuit structure of the clock distributor and the synchronous pulse distributor is the same, the difference is that the clock signal is a pulse signal with a high and low level duty cycle of 50%, so the circuit coupling method can be DC coupling or AC coupling; the synchronous pulse signal is a burst pulse signal with a high level and a very low duty cycle, so the circuit coupling method can only be DC coupling, and cannot be AC ​​coupling.

[0052] The clock distributor and the synchronization pulse distributor both have the function of coarse and fine adjustment of transmission delay, and the adjustment range is the same as the delay adjustment range of the clock distribution, synchronization generation and distributor mentioned above. Since the delay can be adjusted through configuration, there is no need to require the transmission paths of 2N clock signals and synchronization pulse signals to be strictly equal in length. It is only necessary to control the difference in transmission line delay within the integrated circuit delay adjustment range, which greatly reduces the difficulty of printed circuit board wiring inside the multi-beam transceiver processing module.

[0053] In one embodiment, if Figure 6 As shown, the present application discloses a digital array antenna and digital circuit synchronization method, which specifically includes the following steps: S10: performing module preprocessing on the master module and the slave module, wherein the module preprocessing includes configuring FPGA codes and initializing radio frequency transceivers on the master module and the slave module.

[0054] Specifically, after the master module and the slave module are powered on, the FPGA code is configured, and the RF transceivers of the master module and each slave module are initialized accordingly.

[0055] S20: The master module triggers a module handshake request to the slave module, and obtains a signal receiving status of the slave module according to the module handshake request.

[0056] S21: The master module triggers a clock signal handshake request and a synchronization pulse handshake request, and combines the clock signal handshake request and the synchronization pulse signal handshake request into a module handshake request.

[0057] S22: Acquire the clock signal receiving state and the synchronization pulse receiving state from each slave module, combine the clock signal receiving state and the synchronization pulse receiving state into a signal receiving state and send it to the master module.

[0058] Specifically, the master module's board level resource manager (BMC) sends a module handshake request through the serial bus interface to query whether each slave module is ready to receive the clock and synchronization pulse signals. The board level resource manager (BMC) of each slave module sends the corresponding clock signal reception status and synchronization pulse signal reception status to the master module through the serial bus interface. After all slave modules are ready, the master module's board level resource manager (BMC) starts to initialize the onboard clock circuit and generate a clock signal.

[0059] S30: The master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. The master module and all slave modules perform RF transceiver local oscillation phase synchronization through the clock signal and the first pulse of the synchronization pulse signal.

[0060] S31: Receives the clock signal and synchronization pulse signal sent by the main module through the backplane.

[0061] S311: Acquire the signal establishment time and signal duration corresponding to the synchronization pulse signal and the clock signal.

[0062] S312: Acquire the timing relationship between the rising edge of the synchronization pulse signal and the clock signal according to the signal establishment time and the signal duration, and perform local oscillator phase synchronization according to the timing relationship.

[0063] S40: The master module and all slave modules perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete the synchronization.

[0064] S41: Acquire the synchronization status of each slave module, send the synchronization status to the master module, and complete the synchronization.

[0065] For all RF transceivers and FPGAs in the multi-beamforming system, their clocks should be kept in phase, and the rising edge of their clocks and the synchronization pulse should maintain a fixed timing relationship. Figure 3 As shown, by adjusting the clock of the main module A and the internal delay of the synchronization pulse generator to compensate for the transmission path delay caused by the unequal length of the signal lines inside the module and the backplane, it is ensured that the rising edge of the clock and the synchronization pulse between all modules maintain a fixed timing relationship. Figure 4 and Figure 5 As shown, the transmission path delay caused by the unequal length of the signal lines inside the module is compensated by adjusting the internal delay of the clock distributor and the synchronization pulse divider of each module, ensuring that a fixed timing relationship is maintained between the clock rising edge and the synchronization pulse between all RF transceivers and between FPGAs.

[0066] After alignment, the timing relationship between the clock and the synchronization pulse (Example 1) is shown in Figure 7 . Figure 7 The timing relationship between the sync pulse and the rising edge of the clock is determined by the setup time t S and hold time t H It is determined that different devices have different requirements for setup time and hold time. By adjusting the above transmission delay, it is easy to meet the timing requirements of specific devices.

[0067] like Figure 7 As shown, the first synchronization pulse is used to synchronize the phase of the internal mixing local oscillator signal of all RF transceivers in the system, and the second synchronization pulse is used to synchronize the sampling clock synchronization and digital clock synchronization of the A / D converter and D / A converter inside all RF transceivers in the system. It is also used for JESD204B interface synchronization between all RF transceivers and the FPGA interconnected therewith.

[0068] The number of synchronization pulses is not limited to two, and various synchronization pulse forms required can be flexibly generated. Figure 8 An example of a common clock and sync pulse timing relationship is given. Figure 8 The number of synchronization pulse groups and the number of synchronization pulses in each group can be flexibly configured.

[0069] In this embodiment, a high-integration, high-performance RF transceiver is used that integrates RF circuits, digital-analog hybrid circuits, and digital signal processing circuits in one chip, thereby realizing the miniaturization of the device and system. It is composed of a master module and M slave modules, each module has N RF transceivers, each RF transceiver has four receiving channels and four transmitting channels, thus forming a digital array antenna multi-beam forming system with (1+M)×N×4 antenna elements. According to the idea of ​​the present invention, by expanding the number of output signals of the clock and synchronization pulse generator, the clock distributor, and the synchronization pulse distributor, a digital array antenna multi-beam forming system with a huge number of elements can be easily designed.

[0070] The multi-beam transceiver processing module is divided into a master module and a slave module. The difference between the two modules is that the master module A provides clock signals and synchronization pulse signals for the entire system. The slave module has the same components as the master module except that it does not have a clock and synchronization pulse generator. The master and slave modules can be produced by welding different components on the same printed circuit board.

[0071] Radio frequency transceivers with different numbers of radio frequency receiving and transmitting channels may be used. Currently available radio frequency transceivers may have two receiving and two transmitting channels, four receiving and four transmitting channels, or eight receiving and eight transmitting channels on a single chip.

[0072] Only two signals, clock signal and synchronization pulse, are used to achieve synchronization of mixing local oscillator, sampling clock synchronization of A / D converter and D / A converter, digital clock synchronization, and JESD204B interface synchronization between RF transceiver and interconnected FPGA, thus minimizing the types of synchronization signals.

[0073] Each clock signal and synchronization pulse signal can independently adjust the transmission delay in coarse and fine steps, eliminating the need for transmission signal lines to be strictly equal in length, greatly reducing the difficulty of wiring printed circuit boards inside the module and backplane.

[0074] The board manager (BMC) implements handshake and control information exchange between modules through the serial bus interface. The serial bus interface can be in any form, including but not limited to SPI interface, I 2 C interface, CAN bus interface, RS-485 bus interface, etc.

[0075] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0076] In one embodiment, a digital array antenna and digital circuit synchronization device is provided, which corresponds to the digital array antenna and digital circuit synchronization method in the above embodiment. The digital array antenna and digital circuit synchronization device includes an initialization module, a handshake request module, a first synchronization module and a second synchronization module. Each functional module is described in detail as follows: An initialization module, used for performing module preprocessing on the master module and the slave module, wherein the module preprocessing includes configuring FPGA code on the master module and the slave module and initializing the RF transceiver; A handshake request module, used for the master module to trigger a module handshake request to the slave module, and obtain the signal receiving status of the slave module according to the module handshake request; The first synchronization module is used for the master module to send a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. The master module and all slave modules perform phase synchronization of the local oscillator of the RF transceiver through the clock signal and the first pulse of the synchronization pulse signal; The second synchronization module is used for the master module and all slave modules to perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete the synchronization.

[0077] Optionally, the handshake request module includes: The handshake request sending submodule is used for the main module to trigger the clock signal handshake request and the synchronization pulse handshake request, and to combine the clock signal handshake request and the synchronization pulse signal handshake request into a module handshake request; The handshake request response submodule is used to obtain the clock signal receiving state and the synchronization pulse receiving state from each slave module, combine the clock signal receiving state and the synchronization pulse receiving state into a signal receiving state and send it to the master module.

[0078] Optionally, the first synchronization module includes: The signal sending submodule is used to receive the clock signal and synchronization pulse signal sent by the main module through the backplane.

[0079] Optionally, the first synchronization module includes: A time acquisition submodule, used to acquire the signal establishment time and signal duration corresponding to the synchronization pulse signal and the clock signal; The first synchronization submodule is used to obtain the timing relationship between the rising edge of the synchronization pulse signal and the clock signal according to the signal establishment time and the signal duration, and perform local oscillator phase synchronization according to the timing relationship.

[0080] Optionally, the second synchronization module includes: The synchronization feedback submodule is used to obtain the synchronization status of each slave module and send the synchronization status to the master module to complete the synchronization.

[0081] For the specific definition of the digital array antenna and digital circuit synchronization device, please refer to the definition of the digital array antenna and digital circuit synchronization method above, which will not be repeated here. Each module in the above-mentioned digital array antenna and digital circuit synchronization device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0082] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig. 9 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a digital array antenna and a digital circuit synchronization method is implemented.

[0083] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: Performing module preprocessing on the master module and the slave module, wherein the module preprocessing includes configuring FPGA code and initializing RF transceiver on the master module and the slave module; The master module triggers a module handshake request to the slave module, and obtains the signal receiving status of the slave module according to the module handshake request; The master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. The master module and all slave modules perform RF transceiver local oscillation phase synchronization through the clock signal and the first pulse of the synchronization pulse signal. The master module and all slave modules perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete the synchronization.

[0084] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: Performing module preprocessing on the master module and the slave module, wherein the module preprocessing includes configuring FPGA code and initializing RF transceiver on the master module and the slave module; The master module triggers a module handshake request to the slave module, and obtains the signal receiving status of the slave module according to the module handshake request; The master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. The master module and all slave modules perform RF transceiver local oscillation phase synchronization through the clock signal and the first pulse of the synchronization pulse signal. The master module and all slave modules perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete the synchronization.

[0085] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0086] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0087] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A digital array antenna and digital circuit synchronization method, characterized in that: The method comprises a backplane, a main module connected to the backplane, and several slave modules. The method for synchronizing a digital array antenna and a digital circuit comprises: Performing module preprocessing on the master module and the slave module, wherein the module preprocessing includes configuring FPGA code and initializing a radio frequency transceiver on the master module and the slave module; The master module triggers a module handshake request to the slave module, and acquires a signal receiving state of the slave module according to the module handshake request; The master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal, and the master module and all the slave modules perform phase synchronization of the local oscillator of the radio frequency transceiver through the clock signal and the first pulse of the synchronization pulse signal; The master module and all the slave modules perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete the synchronization.

2. The digital array antenna and digital circuit synchronization method according to claim 1, characterized in that: The master module triggers a module handshake request to the slave module, and acquires a signal receiving state of the slave module according to the module handshake request, specifically including: The master module triggers a clock signal handshake request and a synchronization pulse handshake request, and combines the clock signal handshake request and the synchronization pulse signal handshake request into the module handshake request; A clock signal receiving state and a synchronization pulse receiving state are acquired from each of the slave modules, and the clock signal receiving state and the synchronization pulse receiving state are combined into the signal receiving state and sent to the master module.

3. The digital array antenna and digital circuit synchronization method according to claim 1, characterized in that: The master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal, and the master module and all the slave modules perform phase synchronization of the local oscillator of the radio frequency transceiver through the clock signal and the first pulse of the synchronization pulse signal, specifically including: The clock signal and the synchronization pulse signal sent by the main module are received through the backplane.

4. The digital array antenna and digital circuit synchronization method according to claim 3, characterized in that: The master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal, and the master module and all the slave modules perform phase synchronization of the local oscillator of the radio frequency transceiver through the clock signal and the first pulse of the synchronization pulse signal, specifically including: Acquire the signal establishment time and signal duration corresponding to the synchronization pulse signal and the clock signal; The timing relationship between the rising edge of the synchronization pulse signal and the clock signal is acquired according to the signal establishment time and the signal duration, and the local oscillator phase synchronization is performed according to the timing relationship.

5. The digital array antenna and digital circuit synchronization method according to claim 1, characterized in that: The master module and all the slave modules perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete the synchronization, which specifically includes: The synchronization status of each slave module is obtained, and the synchronization status is sent to the master module to complete the synchronization.

6. A digital array antenna and digital circuit synchronization device, characterized in that: The digital array antenna and digital circuit synchronization device comprises: An initialization module, used for performing module preprocessing on the master module and the slave module, wherein the module preprocessing includes configuring FPGA code and initializing a radio frequency transceiver on the master module and the slave module; A handshake request module, used for the master module to trigger a module handshake request to the slave module, and obtain a signal receiving state of the slave module according to the module handshake request; A first synchronization module, used for the master module to send a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal, and the master module and all the slave modules perform phase synchronization of the local oscillator of the radio frequency transceiver through the clock signal and the first pulse of the synchronization pulse signal; The second synchronization module is used for the master module and all the slave modules to perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete the synchronization.

7. The digital array antenna and digital circuit synchronization device according to claim 6, characterized in that: The handshake request module comprises: A handshake request sending submodule, used for the main module to trigger a clock signal handshake request and a synchronization pulse handshake request, and to combine the clock signal handshake request and the synchronization pulse signal handshake request into the module handshake request; The handshake request response submodule is used to obtain the clock signal receiving state and the synchronization pulse receiving state from each of the slave modules, combine the clock signal receiving state and the synchronization pulse receiving state into the signal receiving state and send it to the master module.

8. The digital array antenna and digital circuit synchronization device according to claim 6, characterized in that: The first synchronization module includes: The signal sending submodule is used to receive the clock signal and the synchronization pulse signal sent by the main module through the backplane.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the digital array antenna and digital circuit synchronization method according to any one of claims 1 to 5 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the digital array antenna and digital circuit synchronization method according to any one of claims 1 to 5 are implemented.

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