Single-transistor dynamic random access memory structure based on bipolar injection effect

Abstract

The invention discloses a single-transistor dynamic random access memory structure based on a bipolar injection effect, belongs to the technical field of semiconductor devices, and solves the problems of destructive reading and process incompatibility of an existing memory device 1T1C-DRAM and large memory cell area of a 2T-DRAM and a 3T-DRAM. And non-destructive reading, low read crosstalk and compact unit area are considered. Comprising two layers of transistors which are vertically stacked, a reading transistor is composed of a metal-oxide-semiconductor field effect transistor, a writing transistor is composed of a bipolar junction transistor, and a collector region of the writing transistor is connected to a back gate of the reading transistor. According to the device, the BOX capacitor is used for data storage, the device can be used as a storage unit to work under the condition that an additional capacitor is not needed, and meanwhile non-destructive reading operation is achieved while the area of the additional storage unit is not increased through the read transistor and the write transistor which are vertically stacked.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a single-transistor dynamic random access storage structure based on a bipolar injection effect. Background Art

[0002] Storage devices are an indispensable component in modern electronic systems. They are used to save data and information so that they can be quickly retrieved and used when needed. Storage devices are mainly divided into two categories: volatile memory and non-volatile memory. Volatile memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM), loses data after power failure, but they provide fast data access speed and are often used in computer memory and cache. Non-volatile memory, such as solid-state drives (SSD) and hard disk drives (HDD), can keep data from being lost even after power failure. They are usually used for long-term data storage. With the development of technology, storage devices have been significantly improved in capacity, speed and durability, meeting various storage needs from personal devices to enterprise-level servers. Storage devices play a vital role in modern electronic systems. Due to the difference in the development speed between logic devices and storage devices, memory has become the main bottleneck limiting the performance of computer systems.

[0003] SRAM-based cache memory can be used as a bridge between the CPU and main memory, but its high area cost and high power consumption limit its development. Embedded DRAM has attracted attention due to its advantages of small area and low power consumption. However, due to its incompatibility with CMOS process and the requirement of additional capacitors, traditional 1T1 C-DRAM faces challenges in capacitor scaling difficulties, shortened retention time caused by short channel effects when transistors are miniaturized, and destructive reading. 2T-DRAM achieves non-destructive reading, but using the gate of the read transistor as the storage node sacrifices the read selection function, resulting in high crosstalk and low sensing margin in the read operation. 3T-DRAM solves this problem, but increases the area of ​​the storage unit, which is not conducive to large-scale integration.

[0004] The current memory device 1T1 C-DRAM has destructive reading and process incompatibility issues, as well as the large storage cell area problem of 2T-DRAM and 3T-DRAM. It takes into account non-destructive reading, low read crosstalk and compact cell area.

[0005] Therefore, a single-transistor dynamic random access memory structure based on bipolar injection effect is proposed to solve or alleviate the above problems. Summary of the invention

[0006] The purpose of the present invention is to solve the shortcomings existing in the prior art, and a single-transistor dynamic random access storage structure based on bipolar injection effect is proposed, which adopts a dual-gate metal-oxide-semiconductor field effect transistor (MOSFET) to perform in-situ reading and low crosstalk reading of data, and utilizes an embedded bipolar junction transistor (BJT) under the BOX to write data 1 and 0, reducing the layout to an area of ​​1T, solving the problem that non-destructive reading and compact unit area are difficult to take into account at the same time, and at the same time minimizes the crosstalk problem of the reading process.

[0007] The present invention stores charge in the collector region of the write transistor under the buried oxide (BOX), directly modulates the leakage current of the top read transistor through the interface coupling effect, and retains the top gate of the read transistor as the read word line (RWL). The bipolar junction write transistor embedded in the substrate is composed of an N well (collector region), a substrate (base region), and an N+ emitter region. When writing data 1, the base and emitter are forward biased at the same time, and positive charges flow into the well; when the device is in a hold state, the reverse biased collector junction prevents the loss of stored charge, thereby realizing the storage effect; when writing data 0, the base is forward biased, the emitter is reverse biased, and negative charges are injected into the substrate and diffused to the vicinity of the collector junction and collected by the collector junction. The state of the stored charge in the collector region directly modulates the leakage current of the top read transistor through the BOX capacitor. The device can work as a storage unit without the need for additional capacitors, and the vertically stacked read transistors and write transistors realize non-destructive read operations without increasing the area of ​​additional storage units.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] A single-transistor dynamic random access storage structure based on bipolar injection effect includes a P-type substrate silicon layer, a buried oxide layer, a top silicon layer, an N-well, a shallow trench isolation region, a gate oxide layer on the top silicon layer, a gate, a gate sidewall, a raised source, a raised drain, a write transistor N+ heavily doped emitter region connected to the P substrate, a write transistor P+ heavily doped base region ohmic contact connected to the P substrate, silicon oxide interlayer isolation, a write transistor emitter region metal contact, a write transistor base region metal contact, a drain metal contact, a gate metal contact, and a source metal contact.

[0010] Preferably, the single-transistor dynamic random access memory structure based on the bipolar injection effect is based on the basic structure of SOI, the substrate can be a variety of semiconductors such as silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenic, the top layer can be a semiconductor such as silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenic, and the buried oxide layer can be an insulating material such as silicon dioxide, aluminum oxide and hafnium oxide.

[0011] Preferably, the substrate is lightly doped with P-type, and the doping concentration of the substrate is 1015 -10 17 cm -3 There is an N-type doped N-well under BOX, and the doping concentration of the N-well is 10 15 -10 21 cm -3 The top silicon is N-type or P-type lightly doped, and the doping concentration of the top silicon is 10 15 -10 17 cm -3 The raised source, raised drain and write transistor emitter region are heavily doped with N+, and the doping concentration of the three is 10 19 -10 21 cm -3 The base region ohmic contact of the write transistor is heavily doped with P+, and its doping concentration is 10 19 -10 21 cm -3 .

[0012] Preferably, the single-transistor dynamic random access storage structure based on the bipolar injection effect utilizes a BOX capacitor to realize charge storage, a BJT embedded in the substrate realizes writing of data 0 and 1, a top MOSFET realizes non-destructive reading of data, and a 1T-Layout is realized by vertically stacking a write transistor and a read transistor.

[0013] The present invention has the following beneficial effects:

[0014] The single-transistor dynamic random access storage structure based on bipolar injection effect provided by the present invention takes into account high-speed erasing and writing capabilities, non-destructive reading and low read crosstalk while maintaining a compact storage unit area. Structurally, the storage unit is composed of a metal-oxide-semiconductor field effect transistor (MOSFET) at the top and a bipolar junction transistor (BJT) embedded in the substrate, wherein the MOSFET works as a read transistor and the BJT works as a write transistor. The vertically stacked read transistor and write transistor realize non-destructive read operations without increasing the additional storage unit area. The device retains the top gate of the read transistor as a read word line, which can effectively reduce the crosstalk of the read process. The DRAM structure is fully compatible with modern CMOS processes and does not require additional capacitors. At room temperature, the device has an erasing and writing speed of up to 10ns and a storage time of more than ten seconds. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 It is a structural schematic diagram of a single-transistor dynamic random access memory device based on bipolar injection effect of the present invention;

[0017] Figure 2 hereinafter is a flow chart of preparing a single transistor dynamic random access memory device based on bipolar injection effect of the present invention;

[0018] Figure 3 It is a schematic diagram of the structures of Embodiments 2 to 8 of the single-transistor dynamic random access memory device based on the bipolar injection effect of the present invention.

[0019] 1. P-type substrate silicon layer; 2. buried oxide layer; 3. top silicon; 4. N-well; 5. shallow trench isolation area; 6. shallow trench isolation area; 7. gate oxide layer; 8. gate; 9. gate sidewall; 10. gate sidewall; 11. raised source; 12. raised drain; 13. write transistor N+ heavily doped emitter region; 14. write transistor P+ heavily doped base region ohmic contact; 15. silicon oxide layer isolation; 16. write transistor emitter region metal contact; 17. write transistor base region metal contact; 18. drain metal contact; 19. gate metal contact; 20. source metal contact. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0023] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the invention is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0024] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0025] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] A single-transistor dynamic random access storage structure based on bipolar injection effect includes two layers of transistors stacked vertically, wherein the read transistor is composed of a metal-oxide-semiconductor field effect transistor, and the write transistor is composed of a bipolar junction transistor. The collector region of the write transistor is connected to the back gate of the read transistor, and the top gate of the read transistor works as a read word line.

[0027] Specifically, the single-transistor dynamic random access storage structure based on the bipolar injection effect includes a P-type substrate silicon layer, a buried oxide layer, a top silicon, an N-well, a shallow trench isolation region, a gate oxide layer above the top silicon, a gate, a gate sidewall, a raised source, a raised drain, an N+ heavily doped emitter region of a write transistor connected to the P substrate, an ohmic contact of a P+ heavily doped base region of a write transistor connected to the P substrate, isolation between silicon oxide layers, a metal contact of the emitter region of the write transistor, a metal contact of the base region of the write transistor, a drain metal contact, a gate metal contact, and a source metal contact.

[0028] Preferably, the single-transistor dynamic random access memory structure based on the bipolar injection effect is based on the basic structure of SOI, the substrate can be a variety of semiconductors such as silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenic, the top layer can be a semiconductor such as silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenic, and the buried oxide layer can be an insulating material such as silicon dioxide, aluminum oxide and hafnium oxide.

[0029] Preferably, the substrate is lightly doped with P-type, and the doping concentration of the substrate is 10 15 -10 17 cm -3 There is an N-type doped N-well under BOX, and the doping concentration of the N-well is 10 15 -10 21 cm -3 The top silicon is N-type or P-type lightly doped, and the doping concentration of the top silicon is 10 15 -10 17 cm -3 The raised source, raised drain and write transistor emitter are heavily doped with N+, and the doping concentration of the three is 10 19 -10 21 cm -3 The base ohmic contact of the write transistor is heavily doped with P+, and its doping concentration is 10 19 -10 21 cm -3 .

[0030] Preferably, the single-transistor dynamic random access storage structure based on the bipolar injection effect utilizes BOX capacitors to realize charge storage, the BJT embedded in the substrate realizes the writing of data 0 and 1, the top MOSFET realizes the non-destructive reading of data, and the 1T-Layout is realized by vertically stacking the write transistor and the read transistor.

[0031] Preferably, the single-transistor dynamic random access memory structure based on the bipolar injection effect retains the top gate of the read transistor as a read word line (RWL) for gating the read operation, which can effectively reduce the crosstalk of the read operation. The device is based on an SOI substrate, and the back gate storage charge of the device directly regulates the leakage current of the top MOSFET.

[0032] The present invention provides a method for preparing a single transistor random access memory structure based on a bipolar injection effect, comprising the following steps:

[0033] 1. If Figure 2 In (a), the initial SOI substrate is formed into a hybrid substrate through photolithography, etching, and epitaxial growth. After further photolithography and etching of grooves, the grooves are filled with chemical vapor deposition (CVD) silicon dioxide to form two isolation sidewall STI structures, as shown in FIG. Figure 2 As shown in (b);

[0034] 2. Through photolithography and ion implantation, an N-well (collector region of the write transistor) is formed under the buried oxide layer (BOX), such as Figure 2 As shown in (c);

[0035] 3. On the surface of the device, a high-K dielectric is deposited as a gate oxide layer; polysilicon is deposited as a pseudo-gate layer, followed by a silicon nitride hard mask; the gate pattern is formed by photolithography, and the silicon nitride, polysilicon and high-K dielectric outside the gate area are removed by etching to form a gate oxide layer. Figure 2 The structure shown in (d);

[0036] 4. Deposit gate sidewall material and etch to form gate sidewalls, such as Figure 2 As shown in (e);

[0037] 5. Photolithography forms the pattern of the source and drain regions, and epitaxially grows the N+ silicon layer by in-situ doping to form Figure 2 The raised source and drain shown in (f);

[0038] 6. Photolithography and opening of the window of the N+ write transistor emitter region, ion implantation to form heavily doped N + Emission area, such as Figure 2 As shown in (g);

[0039] 7. Photolithography and opening of the window of the P+ write transistor base ohmic contact area, ion implantation to form heavily doped P + Base ohmic contact, such as Figure 2 As shown in (h);

[0040] 8. Deposit a layer of silicon oxide on the device surface, such as Figure 2 in(i);

[0041] 9. Photolithography opens the polysilicon pseudogate area; etching removes the polysilicon pseudogate, such as Figure 2 middle (j);

[0042] 10. Deposit the metal material of the growth gate to replace the original polysilicon pseudo gate and complete the replacement metal gate (Replacement metal gateRMG), such as Figure 2 Middle (k);

[0043] 11. Photolithography and etching to open the metal contact areas of the source, drain, gate, emitter and base, deposit metal electrodes, and form metal interconnects, such as Figure 2 Preferably, a method for preparing a single-transistor dynamic random access memory structure based on a bipolar injection effect comprises the following steps:

[0044] 1. If Figure 2 (a) The initial SOI wafer, whose substrate is P-type doped with a doping concentration of 10 13 -10 18 cm -3, a hybrid substrate is formed by photolithography, etching, and epitaxial growth, and then a groove is formed by photolithography and etching, and then silicon dioxide is deposited to fill the groove to form two isolation sidewall STI structures, such as Figure 2 As shown in (b); Etching can be done by dry or wet methods: dry etching generally uses fluorine-based or halogen-based gases, while wet etching generally uses strong acid or strong alkaline solutions; deposition can be done by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and other processes.

[0045] 2. Use photoresist as a mask, open a window through photolithography, and implant ions to form Figure 2 The N-well shown in (c) has a doping concentration of 10 15 -10 21 cm -3 .

[0046] 3. On the surface of the device, deposit and grow HighK dielectric materials such as hafnium oxide or aluminum oxide as the gate oxide layer; continue to deposit polysilicon as the pseudo-gate layer, and then deposit a layer of silicon nitride hard mask; photolithography forms the gate pattern, and removes the silicon nitride, polysilicon and highK dielectric outside the gate area by etching to form Figure 2 The structure shown in (d) in the figure. Deposition can be carried out by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and etching can be carried out by dry or wet methods: dry etching generally uses fluorine-based or halogen-based gases, while wet etching generally uses strong acid or strong alkaline solutions;

[0047] 4. Deposit gate sidewall materials, such as commonly used silicon nitride, silicon dioxide, or low dielectric constant dielectrics such as SiOCN and SiBCN, and etch to form gate sidewalls, such as Figure 2 As shown in (e); deposition can be carried out by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and etching can be carried out by dry or wet methods: dry etching generally uses fluorine-based or halogen-based gases, while wet etching generally uses strong acid or strong alkali solutions;

[0048] 5. Photolithography opens the source and drain area windows, epitaxially grows the N+ silicon layer, and ion implants or epitaxially dopes the surface to form Figure 2 The raised source and drain shown in (f);

[0049] 6. Photolithography and opening of the window of the N+ write transistor emitter region, ion implantation to form the N+ heavily doped region of the write transistor emitter region, with a doping concentration of 10 19 -10 21 cm -3 ,like Figure 2 Medium (g);

[0050] 7. Photolithography and opening of the window of the P+ write transistor base ohmic contact area, ion implantation to form heavily doped P + Base ohmic contact, such as Figure 2 As shown in (h);

[0051] 8. Deposit a layer of low dielectric constant material such as silicon oxide or silicon nitride on the surface of the device, such as Figure 2 In (i), deposition can be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD);

[0052] 9. Open the polysilicon pseudo-gate window by photolithography and remove the polysilicon pseudo-gate by etching. Figure 2 In (j), etching can be done by dry or wet methods: dry etching generally uses fluorine-based or halogen-based gases, while wet etching generally uses strong acid or strong alkaline solutions;

[0053] 10. Deposit the metal material of the growth gate to replace the original polysilicon pseudo gate and complete the replacement metal gate (Replacement metal gateRMG), such as Figure 2 (k). Deposition can be done by electron beam evaporation, magnetron sputtering and other processes;

[0054] 11. Photolithography and etching to open the metal contact areas of the source, drain, gate, base and emitter, deposit metal electrodes, and form metal interconnects, such as Figure 2 (l) Etching can be done by dry or wet methods: dry etching generally uses fluorine-based or halogen-based gases, while wet etching generally uses strong acid or strong alkaline solutions. Deposition can be done by electron beam evaporation, magnetron sputtering and other processes.

[0055] Next, various embodiments of the present invention are provided, and the embodiments are as follows:

[0056] Example 2 (corresponding to Figure 3 Device structure diagram in (a)

[0057] like Figure 3 As shown in (a), Example 2 is similar to the above example, except that the top MOSFET is of P type. Therefore, the process flow of this example is similar to that of Example 1, and only the source-drain doping type in step (5) needs to be reversed.

[0058] Example 3 (corresponding to Figure 3 Device structure diagram in (b)

[0059] like Figure 3As shown in (b), Example 3 is similar to the above examples, except that the write transistor under BOX is a PNP-type BJT. Therefore, it is only necessary to change the SOI initial substrate in step (1) to an N-type substrate, and change the well implantation in step (2) to a P-type ion implantation.

[0060] Example 4 (corresponding to Figure 3 Device structure diagram in (c)

[0061] like Figure 3 As shown in (c), Example 4 is similar to Example 2, except that the write transistor under BOX is a PNP-type BJT. Therefore, it is only necessary to change the SOI initial substrate in step (1) to an N-type substrate, and change the well implantation in step (2) to a P-type ion implantation.

[0062] Example 5 (corresponding to Figure 3 Device structure diagram in (d)

[0063] like Figure 3 As shown in (d), the content and principle of embodiment 5 are the same as those of the above embodiments, except that the bipolar junction write transistor embedded in the substrate is constructed differently. The specific manufacturing steps of this embodiment are:

[0064] (1) The initial SOI wafer has a P-type doped substrate with a doping concentration of 10 13 -10 18 cm -3 , a hybrid substrate is formed by photolithography, etching, and epitaxial growth, and then the grooves are further photolithographically etched, and silicon dioxide is deposited to fill the grooves to form an isolation sidewall STI structure; etching can be done by dry or wet methods: dry etching generally uses fluorine-based or halogen element gases, while wet etching generally uses strong acid or strong alkali solutions; deposition can be done by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and other processes.

[0065] (2) Using photoresist as a mask, a window is opened by photolithography, and ion implantation is performed to form an N-well with a doping concentration of 10 15 -10 21 cm -3 .

[0066] (3) On the device surface, deposit and grow High K dielectric materials such as hafnium oxide or aluminum oxide as the gate oxide layer; continue to deposit polysilicon as the pseudo-gate layer, and then deposit a layer of silicon nitride hard mask; photolithography forms the gate pattern, and removes the silicon nitride, polysilicon and high K dielectric outside the gate area by etching. Deposition can be carried out by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and other processes, and etching can be carried out by dry or wet methods: dry etching generally uses fluorine-based or halogen element gases, while wet etching generally uses strong acid or strong alkali solutions;

[0067] (4) Deposit gate sidewall materials, such as commonly used silicon nitride, silicon dioxide, or low dielectric constant dielectrics such as SiOCN and SiBCN, and etch to form gate sidewalls; deposition can be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and other processes, and etching can be performed by dry or wet methods: dry etching generally uses fluorine-based or halogen-based gases, while wet etching generally uses strong acid or strong alkali solutions;

[0068] (5) Photolithography opens windows in the source and drain regions, epitaxially grows an N+ silicon layer, and performs ion implantation or epitaxial doping on the surface to form raised source and drain regions;

[0069] (6) Photolithography and opening a window in the base region of the P-type write transistor, and ion implantation to form a P-well in the base region of the write transistor and a base P+ ohmic contact region;

[0070] (7) Photolithography and opening of the window of the N+ write transistor emitter region, ion implantation to form heavily doped N + Launch area;

[0071] (8) Depositing a layer of low dielectric constant material such as silicon oxide or silicon nitride on the surface of the device. The deposition can be carried out by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) processes;

[0072] (9) Photolithography opens the polysilicon pseudo-gate window and removes the polysilicon pseudo-gate by etching. Etching can be done by dry or wet methods: dry etching generally uses fluorine-based or halogen element gases, while wet etching generally uses strong acid or strong alkali solutions;

[0073] (10) Deposit the metal material of the growing gate to replace the original polysilicon pseudogate and complete the replacement metal gate (RMG). The deposition can be done by electron beam evaporation, magnetron sputtering and other processes;

[0074] (11) Photolithography and etching to open the metal contact areas of the source, drain, gate, base and emitter, deposit metal electrodes, and form metal interconnects;

[0075] Example 6 (corresponding to Figure 3 Device structure diagram in (e)

[0076] like Figure 3 As shown in (e), the structure of Example 6 is similar to that of Example 5, except that the top MOSFET is of P type. Therefore, the process flow of this embodiment is similar to that of Example 5, except that the type of doping of the raised source and drain in step (5) is reversed;

[0077] Example 7 (corresponding to Figure 3 Device structure diagram in (f)

[0078] like Figure 3 As shown in (f), the structure of Example 7 is similar to that of Example 5, except that the write transistor under BOX is a PNP type BJT. Therefore, the process flow of this embodiment is similar to that of Example 5, except that the initial SOI substrate type in step (1) is changed to N type, the ion implantation well in step (2) is changed to P well, and the base region and emitter region types in steps (6) and (7) are reversed.

[0079] Example 8 corresponds to Figure 3 Device structure diagram in (g)

[0080] like Figure 3 As shown in (g), the structure of Example 8 is similar to that of Example 5, except that the top MOSFET is of P type and the write transistor under BOX is of PNP type BJT. Therefore, the process flow of this embodiment is similar to that of Example 5, except that the initial SOI substrate type in step (1) is changed to N type, the ion implantation well in step (2) is changed to P well, the type of the raised source and drain in step (5) is reversed, and the types of the base region and emitter region in steps (6) and (7) are reversed.

[0081] In summary, the present invention designs a new type of single-transistor dynamic random access storage structure based on bipolar injection effect, which takes into account compact unit area, non-destructive reading, low read crosstalk and high-speed erasing and writing capabilities, and is fully compatible with CMOS technology. The storage unit consists of a metal-oxide-semiconductor field effect transistor (MOSFET) at the top and a bipolar junction transistor (BJT) embedded in the substrate, wherein the MOSFET works as a read transistor and the BJT works as a write transistor. The charge is stored in the collector region of the write transistor under the buried oxide (BOX), and the leakage current of the top read transistor is directly modulated by the interface coupling effect. At the same time, compared with the traditional 2T-DRAM, it retains the top gate of the read transistor as the read word line (RWL), solving the crosstalk problem during the read operation. The embedded write transistor is composed of an N-well (collector region), a substrate (emitter region), and an N+ emitter region. When writing data 1, the base and emitter are forward biased at the same time, and positive charges flow into the well; when the device is in the hold state, the reverse biased collector junction prevents the loss of stored charges, thereby realizing the storage effect; when writing data 0, the base is forward biased, the emitter is reverse biased, and negative charges are injected into the substrate and diffused to the vicinity of the collector junction and collected by the collector junction. Using BOX capacitors for data storage, the device can work as a storage unit without the need for additional capacitors, and the vertically stacked read transistors and write transistors realize non-destructive read operations without increasing the area of ​​additional storage units.

[0082] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A single-transistor dynamic random access memory structure based on bipolar injection effect, characterized in that: The invention comprises a P-type substrate silicon layer (1), a buried oxide layer (2), a top silicon layer (3), an N-well (4), shallow trench isolation regions (5) and (6), a gate oxide layer (7) on the top silicon layer, a gate (8), gate sidewalls (9) and (10), a raised source (11), a raised drain (12), an N+ heavily doped emitter region (13) of a write transistor connected to the P substrate (1), an ohmic contact (14) of a P+ heavily doped base region of the write transistor connected to the P substrate (1), an isolation between silicon oxide layers (15), a metal contact (16) of the emitter region of the write transistor, a metal contact (17) of the base region of the write transistor, a drain metal contact (18), a gate metal contact (19), and a source metal contact (20).

2. A single-transistor dynamic random access memory structure based on bipolar injection effect according to claim 1, characterized in that: The single-transistor dynamic random access storage structure based on the bipolar injection effect is based on the basic structure of SOI. The substrate can be a variety of semiconductors such as silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenic. The top layer can be a semiconductor such as silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenic. The buried oxide layer can be an insulating material such as silicon dioxide, aluminum oxide and hafnium oxide.

3. The single-transistor dynamic random access memory structure based on bipolar injection effect according to claim 1, characterized in that: The substrate is lightly doped with P-type, and the doping concentration of the substrate is 10 15 -10 17 cm -3 There is an N-type doped N-well under BOX, and the doping concentration of the N-well is 10 15 -10 21 cm -3 The top silicon is N-type or P-type lightly doped, and the doping concentration of the top silicon is 10 15 -10 17 cm -3 The raised source, raised drain and write transistor emitter region are heavily doped with N+, and the doping concentration of the three is 10 19 -10 21 cm -3 The base region ohmic contact of the write transistor is heavily doped with P+, and its doping concentration is 10 19 -10 21 cm -3 .

4. The single-transistor dynamic random access memory structure based on bipolar injection effect according to claim 1, characterized in that: The single-transistor dynamic random access storage structure based on the bipolar injection effect utilizes a BOX capacitor to realize charge storage, a BJT embedded in a substrate realizes writing of data 0 and 1, a top MOSFET realizes non-destructive reading of data, and a 1T-Layout is realized by vertically stacking a write transistor and a read transistor.

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