Analog circuit yield optimization method under multiple environment angles based on Bayesian neural network

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an analog circuit yield optimization method under multiple environment angles based on a Bayesian neural network. According to the method, a Bayesian neural network (BNN) is used for carrying out synchronous modeling on yield and nominal performance under multiple environment angles, and yield optimization under the multiple environment angles is executed by embedding the BNN into a Bayesian optimization framework. The BNN model provided by the invention can better learn the correlation between the yield and the performance under different environmental angles, provides a strong modeling capability for the yield and the uncertainty thereof, and improves the yield optimization efficiency. Compared with other baseline methods, under the condition that the same target yield is achieved, the circuit simulation time cost can be saved by 45.3%, under the same circuit simulation time cost, a design point with the higher yield can be obtained, and the yield is improved by 3.2%.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and relates to a method for optimizing analog circuit yield, and in particular to a method for optimizing analog circuit yield under multiple environmental angles based on a Bayesian neural network. Background Art

[0002] As the feature size of semiconductor (CMOS) manufacturing processes continues to shrink, the impact of process, voltage, and temperature (PVT) variations on the performance and yield of analog integrated circuits has increased significantly [1][2]. Industry experts believe that in order to obtain a robust design, PVT variations must be carefully considered during circuit optimization and to maximize yield [3].

[0003] In the prior art, the yield optimization framework usually includes two stages, namely yield estimation and yield improvement. In the first stage, a yield estimation algorithm is used to predict the yield of a given design. In the second stage, an optimization algorithm is used to obtain a new design that can improve the yield. By repeating the above two stages, it is expected to converge to a robust design. Practice has shown that the yield estimation in the first stage usually requires a large amount of circuit simulation to accurately estimate the yield [4]-

[11] . In order to avoid expensive yield estimation, process corner-based optimization [4]-[6] is one of the most widely used robust design methods. By using this method, the design parameters of the circuit are optimized to ensure that the design specifications are met at all PVT corners; the above process corners are carefully set with special PVT values ​​to capture the best and worst circuit performance. However, the corner-based method usually leads to over-design because it is inherently pessimistic and does not consider the changes in process fluctuations within the chip.

[0004] To predict the impact of intra-chip process variations on circuit performance, Monte Carlo (MC)-based optimization [7]-

[10] methods run a large number of circuit simulations to estimate yield, but incur a large computational cost. To reduce the computational cost, several methods have been proposed to reduce the number of transistor-level simulations required, for example, design of experiments (DOE) techniques such as Latin Hypercube Sampling (LHS) [7], Quasi-MC (QMC) [8], and Optimal Computational Budget Allocation (OCBA) techniques (e.g., Ordinal Optimization (OO)-based Randomized Scaled Differential Evolution (ORDE) [9]). However, the cost of yield optimization based on such methods is still prohibitive because the yield must be estimated multiple times in the optimization iteration

[12] . To reduce the number of yield estimates (i.e., the number of optimization iterations), Bayesian Yield Optimization (BYO)

[12] and Efficient Yield Optimization (EYO)

[13] methods have recently been proposed. BYO formulates an equivalent yield optimization problem through Bayes’ theorem and solves it efficiently using an expectation-maximization-like (EM-like) algorithm. EYO optimizes circuit yield through Bayesian optimization based on Gaussian process (GP) regression and adaptive yield estimation. Both BYO and EYO have been successfully applied to analog circuit yield optimization. However, most of the above methods (e.g., EYO

[13] , BYO

[12] , ORDE[9], etc.) only consider process fluctuations and ignore environmental changes such as power and temperature.

[0005] Based on the current state of the art, the inventors of this application propose an efficient Bayesian optimization method based on a Bayesian neural network (BNN) for analog circuit yield optimization under multiple environmental angles (BNN-BYO). The method of this application simultaneously considers the influence of process, voltage and temperature changes, and can quickly estimate the statistical characteristics of the yield under different environmental angles; the method of this application will gradually approach the optimal design that meets the yield design requirements.

[0006] The prior arts related to this application include:

[0007] [1]T.McConaghy,K.Breen,J.Dyck,and A.Gupta.Variation-Aware Design ofCustom Integrated Circuits:A Hands-on Field Guide,Springer,2012.G.Gielen,T.Eeckelaert,E.Martens,and T.McConaghy.2007.Automated synthesis of complexanalog circuits.European Conference on Circuit Theory and Design(2007),20-23.

[0008] [2]S.Borkar,T.Karnik,S.Narendra,J.Tschanz,A.Keshavarzi,andV.De.2003.Parameter variations and impact on circuits andmicroarchitecture.Design Automation Conference.

[0009] [3]R.Schwencker,F.Schenkel,M.Pronath,and H.Graeb.2002.Analog circuitsizing using adaptive worst-case parameter sets.Design,Automation&Test inEurope Conference.

[0010] [4]K.S.Eshbaugh.1992.Generation of correlated parameters forstatistical circuit simulation.IEEE Trans.on Computer-Aided Design ofIntegrated Circuits and Systems 11,10(1992),1198-1206.

[0011] [5]M.Barros,J.Guilherme,and N.Horta.2010.Analog circuits optimizationbased on evolutionary computation techniques.Integration,the VLSI journal 43,1(2010),136-155.

[0012] [6]M.Sengupta,S.Saxena,L.Daldoss,G.Kramer,S.Minehane,andJ.Cheng.2005.Application-specific worst case corners using response surfacesand statistical models.IEEE Trans.on Computer-Aided Design of IntegratedCircuits and Systems,24,9(2005),1372-1380.

[0013] [7]M.Stein.(1987).Large sample properties ofsimulations using Latinhypercube sampling.Technometrics,29,2(1987),143-151.

[0014] [8]A.Singhee,S.Singhal,and R.A.Rutenbar.2008.Practical,fast MonteCarlo statistical static timing analysis:why and how.International Conferenceon Computer-Aided Design.

[0015] [9]B.Liu,F.V.Fernández,and G.Gielen.2011.Efficient and accuratestatistical analog yield optimization and variation-aware circuit sizingbased on computational intelligence techniques.IEEE Trans.on Computer-AidedDesign of Integrated Circuits andSystems,30,6(2011),793-805.

[0016]

[10] I.Guerra-Gomez,E.Tlelo-Cuautle,and L.G.de la Fraga.2015.OCBA inthe yield optimization of analog integrated circuits by evolutionaryalgorithms.International Symposium on Circuits and Systems.

[0017]

[11] Z.Gao,J.Tao,D.Zhou and X.Zeng.2020.Efficient Parametric YieldEstimation Over Multiple Process Corners via Bayesian Inference Based onBernoulli Distribution.IEEE Trans.on Computer-Aided Design of IntegratedCircuits andSystems,39,10(2020),3144-3148.

[0018]

[12] M.Wang,F.Yang,C.Yan,X.Zeng,and X.Hu.2017.Efficient Bayesian yieldoptimization approach for analog and SRAM circuits.Design AutomationConference.

[0019]

[13] M.Wang,W.Lv,F.Yang,C.Yan,W.Cai,D.Zhou,and X.Zeng.2018.Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.IEEE Trans.on Computer-Aided Design of Integrated Circuits and Systems,37,10(2018),1929-1942.

[0020]

[14] W.Lyu,F.Yang,C.Yan,D.Zhou and X.Zeng.2018.Multi-objective Bayesian Optimization for Analog / RF Circuit Synthesis.Design Automation Conference.

[0021]

[15] Z.Gao,J.Tao,F.Yang,Y.Su,D.Zhou,and X.Zeng.2019.Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network.International Conference on Computer-Aided Design.

[0022]

[16] A.Kucukelbir,D.Tran,R.Ranganath,A.Gelman,and D.Blei.2017.Automatic differentiation variational inference.The Journal of Machine Learning Research,18,1(2017),430-474. Summary of the Invention

[0023] The purpose of the present invention is to propose an efficient Bayesian optimization method based on a Bayesian neural network (BNN) based on the current state of the prior art, which is used for analog circuit yield optimization (BNN-BYO) under multiple environmental angles. The method of the present application takes into account the influence of process, voltage and temperature changes at the same time, and can quickly estimate the statistical characteristics of the yield under different environmental angles; the method of the present application can quickly meet the design requirements of the yield at a lower time cost. The method is based on the Bayesian optimization framework and is a method of quickly obtaining the design point with the best yield through a small number of iterations.

[0024] Specifically, the present invention proposes an efficient Bayesian optimization method based on a Bayesian neural network (BNN) for analog circuit yield optimization (BNN-BYO) under multiple environmental angles. The method simultaneously considers the influence of process, voltage and temperature changes. In each iteration of Bayesian optimization, first, a BNN model is constructed to simultaneously approximate all circuit yields at all PVT angles. By sharing hidden layers / units and weights, the BNN model can implicitly learn the correlation between circuit performance under different environmental angles; the weights of the BNN can be adaptively learned through training using the automatic differential variation inference (ADVI) method

[16] . Based on this BNN model, the statistical characteristics of the yield under different environmental angles can be quickly estimated; then, the present application designs an acquisition function called weighted confidence upper bound (W-UCB). Compared with other general acquisition functions, W-UCB is designed specifically for yield optimization. By adopting the covariance matrix adaptive evolution strategy (CMA-ES) to maximize W-UCB, the method can find a new design and then use the simulation results of the design to retrain the BNN. By repeating the above process, we will gradually approach the optimal design that meets the yield design requirements.

[0025] More specifically,

[0026] In each iteration of the present invention, first, the BNN is trained using the current training set to establish a proxy model for yield estimation, and the training set includes multiple circuit design points and their corresponding yield data under multiple environmental angles estimated by actual simulation; secondly, the BNN model is applied as a proxy model to the Bayesian optimization framework, which is used to quickly estimate the yield distribution of candidate design points, and at the same time, the yield mean and variance of the design point under each environmental angle are estimated to calculate the acquisition function; then, an improved covariance matrix adaptive evolutionary strategy (CMA-ES) is used to quickly maximize the acquisition function to obtain the optimal point of the current stage; finally, the optimal point of the current stage is used for actual circuit simulation to obtain its true yield under multiple environmental angles, and the simulation results are added to the training set for the next iteration.

[0027] In the present invention, all parameters in yield optimization can be divided into three categories: design parameters x d, statistical parameter x s and environmental parameter x e [3][9]. Design parameters x d ∈ includes transistor width, resistance and capacitance, etc., where the design parameter space is determined by the upper limit x d U and the lower limit x d L Definition. Statistical parameter x s ∈ is used to model process fluctuations (e.g., oxide thickness and threshold voltage), where represents the statistical parameter space. For integrated circuit design, process design kits (PDKs) are usually provided by IC foundries [3]. Without loss of generality, most statistical parameters are assumed to be independent of each other and follow a standard normal distribution after principal component analysis (PCA) [3],

[13] . Environmental parameters x e ∈ (such as power supply voltage and temperature) describes the operating conditions of the circuit and represents the environmental parameter space. Traditional yield optimization methods [9]-

[13] focus on studying process deviation changes, while ignoring the impact of environmental changes on yield. However, when designing analog circuits, the impact of statistical parameters and environmental parameters should be considered simultaneously, because the impact of environmental variables on circuit performance is not monotonic [3]. In order to ensure robust analog circuit design, the yield under H environmental angles is considered in this invention; without loss of generality, the yield of the hth angle with a specific power supply voltage and temperature can be expressed as:

[0028] Where I(x d ,x s ) is the indicator function, p(x s ) is x s When all K circuit performances of interest (PoI) meet the specification, I(x d ,x s )=1, otherwise I(x d ,x s )=0. It can be expressed as:

[0029]

[0030] Where P k (x d ,x s ) is the kth circuit performance of interest, G k is the corresponding circuit specification; for the yield of H corners, y(x d )=[y1(x d )y2(x d )···y H (x d )] T; To ensure the worst-case performance, only the worst yield among multiple corners is considered; therefore, the goal of yield optimization is to find the design x d * , so that its worst yield meets the yield specification y spec :

[0031]

[0032] In order to optimize the yield of analog circuits under multiple environmental angles, the specific steps of this method (see the flowchart) are as follows: Figure 1 )include:

[0033] Step 1: If there is no initial sampling, perform initial sampling in the design space and perform simulation to obtain the initial training set; otherwise, use the current training set to train the BNN to establish a proxy model for yield estimation. The training set includes multiple circuit design points and their corresponding yield data under multiple environmental angles predicted by actual simulation;

[0034] Step 2: Apply the BNN model as a proxy model to the Bayesian optimization framework, which is used to quickly estimate the yield distribution of candidate design points, and at the same time estimate the yield mean and variance of the design point under various environmental angles to calculate the acquisition function;

[0035] Step 3: Use an improved covariance matrix adaptive evolution strategy (CMA-ES) algorithm to quickly maximize the acquisition function and obtain the optimal point of the current stage;

[0036] Step 4: Use the optimal point of the current stage to simulate the actual circuit to obtain its real yield under multiple environmental angles, and add the simulation results to the training set for the next iteration, that is, return to step 1 again.

[0037] In step 1 of the present invention, it is first determined whether the initial sampling has been performed, and then the BNN model is trained, which includes:

[0038] Step 1.1: Determine whether initial sampling has been performed. If not, perform initial sampling in the design space and perform performance and yield simulation under multiple process angles to obtain an initial training data set;

[0039] Step 1.2, training of the BNN model, using the current training set to train the BNN to establish a proxy model for yield estimation, the training set includes multiple circuit design points and their corresponding yield data under multiple environmental angles estimated by actual simulation; similar to traditional neural networks, BNN consists of an input layer, an output layer and several hidden layers, but all weights and output values ​​in BNN are represented by probability distributions rather than deterministic values. For example, a BNN with 3 input units, 2 output units and 2 hidden units in one hidden layer is as follows Figure 1As shown, let w = [w1 w2···w W ] T ∈W represents the weight of BNN, assuming that w follows a Gaussian distribution with mean zero before training

[21] :

[0040]

[0041] where σ w is the standard deviation, I is the identity matrix;

[0042] Use BNN to predict the yield of a circuit with design variables, i.e., y(x d ), as shown below

[0043] y(x d )=f(x d ,w)+ε. (5)

[0044] Where f(x d ,w) represents the circuit yield predicted by BNN, the approximate error ε, and the variance σ ε 2 Gaussian distribution of:

[0045]

[0046] In the input layer, the output of each unit represents the value of the design variable, such as transistor width; assuming there are L hidden layers in the BNN and K hidden layers in the i-th layer. i hidden units; in each hidden layer, use tanh(x) as the activation function:

[0047]

[0048] Then the output z of the jth unit in the i-th hidden layer is j (i It can be expressed as:

[0049]

[0050] where a i (j) Delegate activation:

[0051]

[0052] w j,0 (i) is the DC bias, w j,k (i) Represents the connection weight between the current unit and the kth unit in the previous layer; for the output layer, use minmax or sigmoid function as the activation function:

[0053] minmax(x)=max(0,min(1,x)). (10)

[0054] Therefore, the h-th unit in the output layer can be expressed as:

[0055] y h (x d )=minmax(a h )+ε. (11)

[0056] where ε is Gaussian noise, representing the modeling error of the circuit yield mentioned in (5), and:

[0057] w h,0 (L+1) is the DC bias, w h,k (L+1) represents the connection weight between the h-th output unit and the k-th unit in the last hidden layer, z k (L) represents the output of the kth (k ≥ 1) unit in the last hidden layer. The output of each unit represents the predicted yield of an environmental angle. The correlation between yields can be implicitly encoded by the hidden layer. Assume that there is a statistically independent training data set = {(x d (t) ,y t =y[x d (t) ])|t=1,2,···,T}, where each set of data contains a design parameter and its corresponding yield under each environmental angle. According to Bayes’ theorem

[24] , the posterior distribution p(w|) can be expressed as:

[0058]

[0059] where p(|w) is the probability and p(w) is the prior distribution; however, there is no analytical solution for the posterior p(w|) in BNN

[21] . Therefore, this method uses the ADVI method to estimate the true posterior distribution p(w|). The key idea of ​​ADVI is to introduce a flexible and easy-to-handle distribution q(w|θ), parameterized by θ to approximate p(w|). Then, the approximation process is transformed into an optimization problem. In order to measure the similarity between q(w|θ) and p(w|), the Kullback-Leibler divergence KL[q(w|θ)||p(w|)] can be used. Therefore, the optimization problem is expressed as

[21] :

[0060]

[0061] Where E q(w|θ)[·] represents the expectation of the function about the distribution q(w|θ). According to

[16] , the KL divergence between q(w|θ) and p(w|) can be further simplified as:

[0062] KL[q(w|θ)Pp(w|T)]=-L(θ)+logp(T). (15)

[0063] in:

[0064] L(θ)=E q(w|θ) [logp(T|w)]-KL[q(w|θ)Pp(w)]. (16)

[0065] L(θ) is often called the evidence lower bound (ELBO), and minimizing (14) is equivalent to maximizing the ELBO because log p() is a constant with respect to q(w|θ); in summary, the final optimization problem can be expressed as constrained optimization:

[0066]

[0067] where supp(q(w|θ)) and supp(p(w|)) denote the domains of q(w|θ) and p(w|), respectively:

[0068] supp(q(w|θ))={w|q(w|θ)>0,w∈W}. (18)

[0069] supp(q(w|T))={w|p(w|T)>0,w∈W}. (19)

[0070] If supp(q(w|θ)) supp(p(w|)), this method has KL(q(w|θ)||p(w|))=∞ outside p(w|). In order to solve the constrained optimization, the stochastic gradient descent method is applied; for more details on the ADVI technique, please refer to

[16] . In this method, once the optimal distribution q(w|θ) is obtained, * ), given any candidate design point x d , we can use the trained BNN model to predict the circuit yield y=y(x d ) distribution:

[0071]

[0072] However, the above integral is still difficult to handle because q(w|θ * ) is non-Gaussian, instead, we can use the MC method to obtain * ) to obtain y=y(x d ), first, a set of independent weight samples {w(m) ; m=1,2,···,M}from q(w|θ * ), then, for each weight sample w (m) According to (5), yield y = y(x d ) follows the Gaussian distribution N(y|f(x d ,w (m) ),σ ε 2 I), therefore, a set of independent samples {y (m,n) ; n = 1, 2, · · ·, N} from the PDF N(y|f(x d ,w (m) ),σ ε 2 I), that is, based on the trained BNN model, generate M×Nyield samples{y (m,n) ; m=1,2,···,M; n=1,2,···,N} total, mean and variance It can be estimated from all yield samples as follows:

[0073]

[0074]

[0075] Respectively, where diag(C) represents the column vector consisting of all diagonal elements in the matrix C;

[0076] Step 2: Apply the BNN model as a proxy model to the Bayesian optimization framework, which is used to quickly estimate the yield distribution of candidate design points, and estimate the yield mean and variance of the design point under various environmental angles to calculate the acquisition function, which is specifically divided into:

[0077] Step 2.1: Choose to use a suitable acquisition function, using the BNN model as a probability model to predict the expectation and uncertainty of the yield in different corners. In addition, the probability distribution of the relevant nominal performance is also modeled using the same BNN model; the acquisition function must be carefully designed to find promising points in the iterative process;

[0078] The present invention discusses a variety of acquisition functions in the rich literature, such as upper confidence limit (UCB)

[17] and expected improvement (EI)

[18] , which are used to balance exploration and exploitation. In the example of the present invention, the upper confidence limit (UCB) is selected as the basic part of the acquisition function, which can be expressed as follows:

[0079] UCB(y(x d ))=μ[y(x d )]+kvar[y(xd )]. (twenty three)

[0080] Where k>0 is a constant. Since the present invention considers the worst yield of multiple corners of the circuit, the worst UCB in all PVT conditions is selected as the acquisition function:

[0081] MinUCB(x d )=min(UCB1(x d ),UCB2(x d )...,UCB H (x d )). (twenty four)

[0082] UCB h (x d ) represents the UCB function at the hth environmental corner of voltage and temperature in (23). Although the acquisition function UCB has been proven to be effective in many applications, it is not designed for yield optimization. In yield optimization, in order to ensure that high-yield design points can be found, the design space is often set conservatively. This common situation leads to only a small part of the entire design space having the potential to become a high-yield design point. If a design has multiple circuit character requirements in (2), the situation will become worse, which means that the yield of most points is zero. Then it is easy to get a training set in which each design has zero yield in all corners of the initial sampling stage of Bayesian optimization. For the Bayesian optimization algorithm, this is the most undesirable situation because the mean function of BNN cannot provide information at all, and the search is only to uniformly sample the design space

[13] . In order to alleviate this problem, the present invention proposes an effective acquisition function for BNN in yield optimization: weighted confidence upper bound (W-UCB). In the early iterations of Bayesian optimization, more information is needed to find points with non-zero yield; in the present invention, the nominal performance in the environmental corner refers to the simulated performance without any process changes. High-yield design comes from the design set where the nominal performance meets the design specifications. Therefore, this method can add the above before the acquisition function

[13] ,

[19] . This method extends the output layer of the BNN to model the yield of each corner and the nominal POI of each corner, such as Figure 2 As shown. BNN has been shown to be effective in circuit performance modeling

[15] . In this method, it is assumed that all nominal performance of the circuit modeled by BNN follows a Gaussian distribution. Since the previous output of the output layer unit has a boundary of (0,1), all performance values ​​should be normalized before training. The yield and nominal performance are related, and the correlation between them is implicitly considered through the hidden units.

[0083] Without loss of generality, the modeled nominal performance and its relationship to the design requirements can be expressed as:

[0084] P k (x d )≤G k (k=1,2,…,K). (25)

[0085] Among them G k (k∈{1,2,…,K}) is the custom specification of the kth PoI. In (2), when all relevant circuit performances (PoI) of the corresponding circuit specification are met, I(x d ,x s )=1. According to (21) and (22), all nominal performances of the circuits modeled by BNN obey Gaussian distribution. This method has P for each performance. k (x d )~N(p|u k ,σ k ), at this point, the probability that the nominal performance meets the specification can be calculated:

[0086]

[0087] where Ф(·) represents the cumulative distribution function (CDF) of the standard normal distribution. Since there are multiple POIs in different corners of BNN modeling, a parameter called feasibility probability (PF) can be used to indicate promising points:

[0088]

[0089] In order to exploit the knowledge of nominal performance, the PF and UCB in (24) are combined to make W-UCB:

[0090] W-UCB(x d )=MinUCB(x d )PF(x d ). (28)

[0091] Where MinUCB(x d ) represents the worst corner point of yield, PF(x d ) is the weighting coefficient for the original UCB; intuitively, the yield model is not accurate enough at the beginning because of the lack of non-zero yield points. Therefore, W-UCB mainly relies on PF to find non-zero yield points. After multiple iterations, when enough non-zero yield points are found, the yield model is accurate, and then PF and UCB work together to help find high yield points;

[0092] Step 2.2 uses BNN to calculate the obtained function. This method expands the output layer of BNN to model the yield of each corner and the nominal POI of each corner, such as Figure 2 As shown;

[0093] Step 3: Use an improved covariance matrix adaptive evolution strategy (CMA-ES) to quickly maximize the acquisition function and obtain the optimal point of the current stage. In each iteration, it is necessary to maximize the acquisition function to obtain the current optimal design point:

[0094]

[0095] In order to effectively solve the optimization problem in (29), the CMA-ES algorithm is adopted. For details about CMA-ES, please refer to

[22] ;

[0096] Step 4: Use the optimal point of the current stage to simulate the actual circuit to obtain its real yield under multiple environmental angles, and add the simulation results to the training set for the next iteration, that is, return to step 1 again. Once the optimal design point is obtained by solving (29), the evaluator will be used to estimate the yield of the candidate design point. For the MC-based method, the number of samples N MC The relationship between y and the estimated accuracy of the circuit yield y can be expressed as

[23] :

[0097]

[0098] Where y represents the confidence interval (CI), k y represents the confidence level. For example, if y = 95% and Δy = 1%, then the CI is 94%-96%, k γ =1.645 indicates a 90% confidence level; usually, the cost of accurate estimation is very high because transistor-level simulation is very time-consuming, but a rough estimate can be obtained more easily [9]. For low-yield design points, very accurate yield estimation is not required. Therefore, in each iteration, the method first performs nominal circuit simulation. If the value of any PoI is NaN or does not meet the specification, the evaluator stops and returns zero; in particular, the simulated nominal performance can be used for performance modeling of BNN. When the nominal performance does not meet the specification, the probability of the design becoming a high yield point is small. If the specification is met, a three-stage MC-based yield estimation method is adopted, introducing three target yields {y s,i ; i=1,2,3} and CI index {Δy s,i ; i=1,2,3}, for i=1,2, the inequality y s,i <y s,i+1 and Δy s,i >Δy s,i+1 Established, in the present invention, k γ ,y s,i and Δy s,i The typical values ​​of (i = 1, 2, 3) are 1.645, [0.8, 0.9, 0.99] and [0.1, 0.05, 0.01] respectively; in each stage of the present invention, Ns,i (i=1,2,3) times simulation to obtain circuit yield y mc , they are obtained according to (30) by setting y = y s,i and Δy=Δy s,i Calculated, if y mc <y s,i -Δy s,i , the calculator stops and returns y mc , that is, the number of simulations is sufficient for the current yield, otherwise, the evaluator will enter the next stage. The basic principle of the present invention is to only allocate a large number of simulation times to promising design points.

[0099] The present invention provides a method for optimizing the yield of analog circuits under multiple environmental angles based on a Bayesian neural network. The present invention uses a Bayesian neural network (BNN) to synchronously model the yield and nominal performance under multiple environmental angles, and performs yield optimization under multiple environmental angles by embedding the BNN into a Bayesian optimization framework. The BNN model of the present invention can better learn the correlation between yield and performance under different environmental angles, provide a powerful modeling capability for the yield and its uncertainty, and improve the efficiency of yield optimization. Compared with other baseline methods, the present invention can save up to 45.3% of the circuit simulation time cost while achieving the same target yield. Under the same circuit simulation time cost, a design point with a higher yield can be obtained, and the yield is increased by 3.2%. BRIEF DESCRIPTION OF THE DRAWINGS

[0100] Figure 1 It is a flowchart of the steps of the analog / RF circuit robustness design method proposed by the present invention.

[0101] Figure 2 This is a comparison chart between BNN and general neural networks.

[0102] Figure 3 It is the performance model of BNN.

[0103] Figure 4 This is the circuit diagram of the first example in the example algorithm: a second-order amplifier.

[0104] Figure 5 This is a performance comparison chart of BNN-BYO and other methods in the first instance.

[0105] Figure 6 This is the circuit diagram of the second example in the example algorithm: the comparator. DETAILED DESCRIPTION

[0106] The advantages of the method of the present invention are now further illustrated through the implementation process of a specific example.

[0107] Implementation Example 1

[0108] In this example, consider Figure 4 The three-stage low-power amplifier shown in

[18] is implemented in industrial 0.35μm CMOS technology. The design specifications are gain ≥ 100dB, unity gain frequency (UGF) ≥ 1.45MHz, phase margin (PM) ≥ 60°, and quiescent current IQ ≥ 50μA. There are 19 circuit design parameters, including transistor width and length, resistance, capacitance, and bias current. Process and environmental variations are considered. We consider three power supply voltages of 1.9V, 2.0V, and 2.1V, and three operating temperatures of -10℃, 27℃, and 60℃. There are a total of 9 environmental corners. The target yield is 98%.

[0109] In addition, the BNN model is constructed by 3 layers, namely 1 input layer, 1 output layer and 1 hidden layer. The hidden layer consists of 15 units. The activation function of the output layer is set to the sigmoid function. 200 design points are extracted as initial samples. In this example with high-dimensional design variables, more initial sampling allows the initial model to better learn the global performance distribution and avoid too much invalid local exploration. The input part of the training data is preprocessed so that the output value of the input layer is [-0.5, 0.5], and the activation function of the hidden layer is the tanh function, as shown in (8). The number of output units is 13, of which 9 represent the yield of all corner points, and 4 represent the worst nominal performance of Gain, UGF, PM and IQ among all environmental corner points.

[0110] The Sobol sequence is used in the initial sampling because it can sample the space more uniformly. For the acquisition function, k = 0.2 is chosen for the W-UCB function in (20). CMA-ES is used in this example to find the maximum of the acquisition function because it has been shown that it can find designs with sufficiently large acquisition functions in a finite time.

[0111] For the parameters in the multi-stage yield estimator, the typical values ​​introduced in Section 3.3 are used. The multi-stage yield estimator is used for the initial sampling step and the iteration step. In this example, all methods are repeated 10 times.

[0112] Table 1 compares the efficiency of all approaches for the three-stage amplifier.

[0113] Since transistor-level simulation is very time-consuming and dominates the running time, this example uses the number of transistor-level simulations as the comparison metric

[17] . According to the results shown in Table 1, BNN-BYO achieves a smaller average time cost and a smaller standard deviation compared to other methods. In particular, for the two baseline methods used for comparison (M-EYO and M-ORDE), results with larger standard deviations are observed. Given the large standard deviations, for a fairer comparison, this method adds ten repeated experiments for each method. Figure 5 , where the ten replicate results for each method are ranked according to the number of circuit simulations, as Figure 5 As shown, it can be seen that BNN-BYO achieves better performance with fewer global circuit simulations; the better performance of BNN-BYO is mainly attributed to the fact that BNN-BYO is based on a single BNN model, which can implicitly encode the correlation between all circuit yields and performances by sharing hidden layers and weights. Using the same training data, a single BNN model will have higher accuracy than multiple separate, unrelated GP models. The higher accuracy directly leads to the ability to find design points that are more likely to be high-yield points when using the acquisition function to search for points.

[0114] Table 1. Comparison of BNN-BYO with other benchmark methods (three-stage amplifier)

[0115]

[0116] Implementation Example 2

[0117] In this experiment, we consider optimizing the yield of a comparator with a preamplifier and a latch

[18] , such as Figure 6 As shown, the circuit is implemented using industrial 0.18μm CMOS technology and 1.8V power supply, and the design specification is offset voltage V off ≤30μV, the sampling frequency is 200MHz, and a total of 12 design variables corresponding to the transistor width are considered, such as Figure 6 As shown, some symmetrical transistors need to have the same width for design requirements, so the design variables are marked in the middle of them, such as W5, W9, etc. Figure 5 In the design, process and environmental variations are taken into account, three power supply voltages of 1.7V, 1.8V, and 1.9V and three operating temperatures of 10°C, 30°C, and 50°C are considered. There are a total of 9 environmental corners, and the target yield is 98%.

[0118] In addition, the BNN model is constructed by 3 layers: input layer, output layer and hidden layer. The hidden layer consists of 15 units, and the output layer consists of 18 output units, of which 9 output units represent the yield of all environmental corner points, and the other 9 output units represent the nominal performance of the offset of all corner points. In this example, 50 design points are extracted as initial samples.

[0119] For the acquisition function, k = 0.5 is selected for the W-UCB function in (20). For the parameters in the multi-stage yield estimator, they are set to the typical values ​​introduced in Section 3.3 during the Bayesian optimization iteration, and the Sobol sequence is used for initial sampling. In order to reduce the simulation cost during initial sampling, this example sets a maximum number of simulations for each design point under the corner, that is, in the simulation of the first two stages, the number of simulations remains unchanged; if the third stage is entered, the corresponding number of simulations will be reduced so that the total number of simulations does not exceed the maximum number of simulations. The maximum number is set to 134, which is half of the number in Stage-3.

[0120] This example repeats all methods ten times to compare their performance. In this example, the upper limit of the number of simulations is set to 1E5 times. In this example, all methods failed to find the target point within the acceptable computing time. Therefore, this example records the best design point found during the Bayesian optimization iteration. For the design parameters obtained in the experiment, 1E3 simulations are run to estimate the yield at each corner point respectively. This is to allow the two methods to be compared under the same standard. The comparison results are shown in Table 2. The best, worst, average and standard deviation refer to the best performance, worst performance, average performance and performance standard deviation achieved in 10 repeated runs, respectively. The worst yield of multiple corners of the best design point found within the budget is the performance indicator of the algorithm. A higher yield means better algorithm performance. BNN-BYO achieves a larger yield average and a smaller standard deviation. A set of comparator design parameters obtained by BNN-BYO with a yield of 95.9% is shown in Table 3.

[0121] Table 2. Comparison of BNN-BYO with other baseline methods (comparator)

[0122]

[0123] Table 3. Design parameters obtained by BNN-BYO

[0124] <![CDATA[W0=5.10μm]]> <![CDATA[W1=2.02μm]]> <![CDATA[W3=2.49μm]]> <![CDATA[W5=2.49μm]]> <![CDATA[W7=4.77μm]]> <![CDATA[W9=4.96μm]]> <![CDATA[W 11 =3.65μm]]> <![CDATA[W 13 =7.55μm]]> <![CDATA[W 15 =7.49μm]]> <![CDATA[W 17 =4.12μm]]> <![CDATA[W 19 =5.22μm]]> <![CDATA[W 21 =3.02μm]]>

Claims

1. A method for optimizing analog circuit yield under multiple environmental angles based on Bayesian neural network, characterized in that: include: In each iteration of Bayesian optimization, first, the BNN is trained using the current training set to establish a proxy model for yield estimation. The training set includes multiple circuit design points and their corresponding yield data under multiple environmental angles estimated by actual simulation; secondly, the BNN model is applied to the Bayesian optimization framework as a proxy model, which is used to quickly estimate the yield distribution of candidate design points, and at the same time, the yield mean and variance of the design point under each environmental angle are estimated to calculate the acquisition function; then, an improved covariance matrix adaptive evolutionary strategy (CMA-ES) is used to quickly maximize the acquisition function to obtain the optimal point of the current stage; finally, the optimal point of the current stage is used for actual circuit simulation to obtain its true yield under multiple environmental angles, and the simulation results are added to the training set for the next iteration.

2. The analog circuit yield optimization method according to claim 1, characterized in that: It includes the steps of: Step 1: If there is no initial sampling, perform initial sampling in the design space and perform simulation to obtain the initial training set; otherwise, use the current training set to train the BNN to establish a proxy model for yield estimation. The training set includes multiple circuit design points and their corresponding yield data under multiple environmental angles estimated by actual simulation; Step 2: Apply the BNN model as a proxy model to the Bayesian optimization framework, which is used to quickly estimate the yield distribution of candidate design points, and at the same time estimate the yield mean and variance of the design point under various environmental angles to calculate the acquisition function; Step 3: Use an improved covariance matrix adaptive evolution strategy (CMA-ES) algorithm to quickly maximize the acquisition function and obtain the optimal point of the current stage; Step 4: Use the optimal point of the current stage to simulate the actual circuit to obtain its real yield under multiple environmental angles, and add the simulation results to the training set for the next iteration, that is, return to step 1 again.

3. The analog circuit yield optimization method according to claim 2, characterized in that: In step 1, it is first determined whether the initial sampling has been performed, and then the BNN model is trained, which includes: Step 1.1: Determine whether initial sampling has been performed. If not, perform initial sampling in the design space and perform performance and yield simulation under multiple process angles to obtain an initial training data set; Step 1.2, training of the BNN model. Use the current training set to train the BNN to establish a proxy model for yield estimation. The training set includes multiple circuit design points and their corresponding yield data under multiple environmental angles estimated by actual simulation. The BNN consists of an input layer, an output layer, and several hidden layers, in which all weights and output values ​​are represented by probability distributions rather than deterministic values. For example, a BNN with 3 input units, 2 output units, and 2 hidden units in one hidden layer is shown in Figure 1. Let w = [w1 w2 ··· w W ] T ∈ W represents the weight of BNN. We assume that w follows a Gaussian distribution with mean zero before training [21]: where σ w is the standard deviation, I is the identity matrix, Use BNN to predict the yield of a circuit with design variables, i.e., y(x d ), as shown below y(x d )=f(x d ,w)+ε. (2) Where f(x d ,w) represents the circuit yield predicted by BNN, the approximate error ε, and the variance σ ε 2 Gaussian distribution of: In the input layer, the output of each unit represents the value of the design variable, such as transistor width. Assume that there are L hidden layers in the BNN and K hidden layers in the i-th layer. i hidden units, in each hidden layer, using tanh(x) as the activation function: Then the output z of the jth unit in the i-th hidden layer is j (i It can be expressed as: where a i (j) Delegate activation: w j,0 (i) is the DC bias, w j,k (i) Represents the connection weight between the current unit and the kth unit in the previous layer. For the output layer, the minmax or sigmoid function is used as the activation function: minmax(x)=max(0,min(1,x)). (7) Therefore, the h-th unit in the output layer can be expressed as: y h (x d )=minmax(a h )+e. (8) where ε is Gaussian noise, representing the modeling error of the circuit yield mentioned in (5), and: w h,0 (L+1) is the DC bias, w h,k (L+1) represents the connection weight between the h-th output unit and the k-th unit in the last hidden layer, z k (L) represents the output of the kth (k ≥ 1) unit in the last hidden layer. The output of each unit represents the predicted yield of an environmental angle. The correlation between yields can be implicitly encoded by the hidden layer; Assume there is a statistically independent training data set = {(x d (t) ,y t =y[x d (t) ])|t=1,2,···,T} Each set of data contains a design parameter and its corresponding yield under each environmental angle. According to Bayesian theorem [24], the posterior distribution p(w|) can be expressed as: Where p(|w) is the possibility and p(w) is the prior distribution. There is no analytical solution for the posterior p(w|) in BNN [21]. Therefore, the ADVI method is used to estimate the true posterior distribution p(w|). The key idea of ​​ADVI is to introduce a flexible and easy-to-handle distribution q(w|θ), which is parameterized by θ to approximate p(w|). Then, the approximation process is transformed into an optimization problem. In order to measure the similarity between q(w|θ) and p(w|), the Kullback-Leibler divergence KL[q(w|θ)||p(w|)] is used. Therefore, the optimization problem can be expressed as [21]: where E q(w|θ) [[The symbol]]E[[ / The symbol]] denotes the expectation of the function with respect to the distribution q(w|θ). According to [16], the KL divergence between q(w|θ) and p(w|) can be simplified as: KL[q(w|θ)Pp(w|T)]=-L(θ)+logp(T). (12) in: L(θ)=E q(w|θ) [logp(T|w)]-KL[q(w|θ)Pp(w)]. (13) L(θ) is often called the Evidence Lower Bound (ELBO). Minimizing (14) is equivalent to maximizing the ELBO. Since log p() is a constant with respect to q(w|θ), the final optimization problem can be expressed as a constrained optimization: where supp(q(w|θ)) and supp(p(w|)) denote the domains of q(w|θ) and p(w|), respectively: supp(q(w|θ))={w|q(w|θ)>0,w∈W}. (15) supp(q(w|T))={w|p(w|T)>0,w∈W}. (16) If supp(q(w|θ)) supp(p(w|)), outside p(w|), KL(q(w|θ)||p(w|))=∞. To solve the constrained optimization, the stochastic gradient descent method is applied. Get the best distribution q(w|θ * ), given any candidate design point x d , we can use the trained BNN model to predict the circuit yield y=y(x d ) distribution: Or, using the MC method, by * ) to obtain y=y(x d ) is an unbiased estimate: First, a set of independent weight samples {w (m) ; m=1,2,···,M}from q(w|θ * ), next, for each weight sample w (m) According to (5), yield y = y(x d ) follows the Gaussian distribution N(y|f(x d ,w (m) ),σ ε 2 I), we can draw a set of independent samples {y (m,n) ; n = 1, 2, · · ·, N} from the PDF N(y|f(x d ,w (m) ),σ ε 2 I). That is, based on the trained BNN model, generate M×Nyieldsamples{y (m,n) ; m=1,2,···,M; n=1,2,···,N} total, mean and variance It can be estimated from all yield samples as follows: Respectively, where diag(C) represents the column vector consisting of all diagonal elements in the matrix C.

4. The analog circuit yield optimization method according to claim 2, characterized in that: In step 2: the BNN model is applied as a proxy model to the Bayesian optimization framework, which is used to quickly estimate the yield distribution of candidate design points, and at the same time, the yield mean and variance of the design point under various environmental angles are estimated to calculate the acquisition function, which includes: Step 2.1: Select and use a suitable acquisition function. Use the BNN model as a probability model to predict the expectation and uncertainty of the yield in different corners. In addition, the probability distribution of the relevant nominal performance is also modeled using the same BNN model. In the tender method, the upper confidence limit (UCB) is selected as the basic part of the acquisition function. They can be expressed as follows: UCB(y(x d ))=μ[y(x d )]+kvar[y(x d )]. (20) Where k>0 is a constant, considering the worst yield of multiple corners of the circuit, the worst UCB among all PVT conditions is selected as the acquisition function: MinUCB(x d )=min(UCB1(x d ),UCB2(x d )...,UCB H (x d )). (21) UCB h (x d ) represents the UCB function at the hth environmental corner of voltage and temperature in (23); In yield optimization, in order to ensure that a high yield design point can be found, the design space is often set conservatively; This method proposes an effective acquisition function for BNN in yield optimization: weighted confidence upper bound (W-UCB). In the early iterations of Bayesian optimization, more information is needed to find points with non-zero yield; In this method, the output layer of BNN is extended to model the yield of each corner and the nominal POI of each corner, as shown in Figure 2. BNN has been proven to be effective in circuit performance modeling [15]. It is assumed that all nominal performance of the circuit modeled by BNN follows a Gaussian distribution. Since the previous output of the output layer unit has a (0,1) boundary, all performance values ​​should be normalized before training. The yield and nominal performance are related, and the correlation between them is implicitly considered through the hidden units; Without loss of generality, the modeled nominal performance and its relationship to the design requirements can be expressed as: P k (x d )≤G k (k=1,2,…,K). (22) Among them G k (k∈{1,2,,K}) is the custom specification of the kth PoI. In (2), when all relevant circuit performances (PoI) of the corresponding circuit specification are met, I(x d ,x s )=1, according to (21) and (22), all nominal performances of the circuits modeled by BNN obey Gaussian distribution, and for each performance there is P k (x d )~N(p|u k ,σ k ), at this point, the probability that the nominal performance meets the specification can be calculated: Where (·) represents the cumulative distribution function (CDF) of the standard normal distribution. Since there are multiple POIs in different corners of BNN modeling, a parameter called feasibility probability (PF) can be used to indicate promising points: In order to exploit the knowledge of nominal performance, the PF and UCB in (24) are combined to make W-UCB: W-UCB(x d )=MinUCB(x d )PF(x d ). (25) Where MinUCB(x d ) represents the worst corner point of yield, PF(x d ) is used as the weighting coefficient of the original UCB, and then PF and UCB help find the high yield point together; Step 2.2 uses BNN to calculate the obtained function and expand the output layer of BNN to model the yield of each corner and the nominal POI of each corner, as shown in Figure 2.

5. The analog circuit yield optimization method according to claim 2, characterized in that: In the step 3: An improved covariance matrix adaptive evolution strategy (CMA-ES) is used to quickly maximize the acquisition function and obtain the optimal point of the current stage. In each iteration, it is necessary to find the current optimal design point by maximizing the acquisition function: In order to effectively solve the optimization problem in (29), the CMA-ES algorithm is adopted.

6. The analog circuit yield optimization method according to claim 2, characterized in that: In step 4: the optimal point of the current stage is used for actual circuit simulation to obtain the yield under the actual multi-environment angle, and the simulation result is added to the training set for the next iteration, that is, returning to step 1 again; The optimal design point is obtained by solving (29), and the yield of the candidate design point is estimated using the evaluator; For MC-based methods, the sample size N MC The relationship between the estimated accuracy of the circuit yield y is expressed as [23]: Where y represents the confidence interval (CI), k y Indicates the confidence level; for example, if y = 95% and Δy = 1%, then the CI is 94%-96%, k γ =1.645 indicates a 90% confidence level; In each iteration, the nominal circuit simulation is performed first. If the value of any PoI is NaN or does not meet the specification, the evaluator will stop and return to zero. The nominal performance simulated in this method can be used for performance modeling of BNN. When the nominal performance does not meet the specification, the probability of the design becoming a high yield point is small. If the specification is met, a three-stage MC-based yield estimation method is adopted, introducing three target yields {y s,i ; i=1,2,3} and CI index {Δy s,i ; i=1,2,3}, for i=1,2, the inequality y s,i <y s,i+1 and Δy s,i >Δy s,i+1 Established.

7. The analog circuit yield optimization method according to claim 6, characterized in that: In step 4: γ ,y s,i and Δy s,i The typical values ​​of (i=1,2,3) are 1.645, [0.8, 0.9, 0.99] and [0.1, 0.05, 0.01] respectively. At each stage, N s,i (i=1,2,3) times simulation to obtain circuit yield y mc It is obtained by setting y = y according to (30). s,i and Δy=Δy s,i To calculate, if y mc <y s,i -Δy s,i , the calculator stops and returns y mc , for the current yield, the number of simulations is sufficient.

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