An efficiency enhanced two-stage driving stacked quadrupler

Abstract

The application discloses an efficiency-enhanced two-stage driving stacked four-frequency multiplier, comprising a differential signal generating circuit, a quadrature signal generating circuit and a double-push frequency multiplier. The quadrature signal generating circuit avoids the use of a stage-to-stage balun, maximally reduces loss and improves the efficiency of the frequency multiplier. The double-push frequency multiplier adopts a series structure, a series resonance circuit is added to the input end of the first-stage double-push frequency multiplier, the output power of a transistor and the second-harmonic suppression capability are improved, the first stage is biased in A and B classes, and the source and the gate of the second-stage double-push frequency multiplier are driven. The stacked double-driving structure reduces the driving power required by the second stage to the first stage, realizes the improvement of transconductance, multiplexes current through stacking, reduces direct-current power consumption, and the second-stage double-push frequency multiplier is biased in C class, so that the output power and the drain efficiency are improved. The application has the characteristics of high drain efficiency, good harmonic suppression capability and output power.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radio frequency integrated circuits, and particularly relates to an efficiency-enhanced two-stage driving stacked quadrupler. BACKGROUND

[0002] The improvement of spatial resolution provided by millimeter wave frequencies has driven the development of improved W-band (75-110 GHz) radar systems designed for automotive radar and vital sign detection applications. However, the quality of these radar systems depends on the spectral purity of the frequency synthesis circuit. Unfortunately, high frequency oscillator circuit phase noise and tuning range can be reduced due to device parasitics, low quality factor passive devices, and transistor gain reduction, which makes the oscillator circuit a major bottleneck for practical systems. Frequency doublers alleviate these challenges by allowing the use of a low frequency oscillator whose output signal can be multiplied by the frequency doubler to obtain the desired high frequency. However, the high output power requirements of radar applications can lead to heating problems in large-scale systems, and high energy-efficient solutions suitable for radar transmitters need to be investigated.

[0003] Chinese patent (CN114759879A) discloses a push-push-based two-three frequency multiplier. The structure in the above patent uses an inter-stage balun to drive the double-push structure of the second stage, and the double-push structure of the first stage obtains two frequency multiplication. Generally, a quadrupler is usually designed by stacking or cascading two frequency doublers. However, if the structure of the above technical solution is used to realize quadrupling, since the output end of the PPD is single-ended, and the input end of the PPD is differential, an inter-stage balun is usually needed when cascading the two PPDs. These baluns will introduce additional loss, thereby affecting the signal efficiency, which is extremely detrimental to the radar transmitting end, causing a loss of transmission efficiency. In other words, a high-efficiency transmission end frequency multiplication scheme needs to reduce frequency multiplication loss.

[0004] Therefore, the present application provides a scheme for avoiding the use of an inter-stage balun to improve drain efficiency. SUMMARY

[0005] The two-stage driving stacked quadrupler of the present application includes: a differential signal generation circuit, a quadrature signal generation circuit, and a double-push frequency multiplier.

[0006] The left side of the differential signal generation circuit is provided with an input end RF Input, and the right side is provided with ports a, a ′ ;

[0007] The left side of the quadrature signal generation circuit is provided with ports b, c, and the right side is provided with ports d, d ′ , e, e ′ ;

[0008] The double-push frequency multiplier comprises a first-stage double-push frequency multiplier and a second-stage double-push frequency multiplier;

[0009] The first-stage double-push frequency multiplier is provided with ports f, f ′ , g, g ′ on the left side and ports h, j on the right side;

[0010] The second-stage double-push frequency multiplier is provided with ports k, k ′ on the left side and a port RF Output on the right side;

[0011] The right-side port a of the differential signal generating circuit is connected with the left-side port b of the quadrature signal generating circuit, and the right-side port a ′ of the differential signal generating circuit is connected with the left-side port c of the quadrature signal generating circuit;

[0012] The right-side port d of the quadrature signal generating circuit is connected with the left-side port f of the first-stage double-push frequency multiplier, and the right-side port d ′ of the quadrature signal generating circuit is connected with the left-side port g of the first-stage double-push frequency multiplier; the right-side port e of the quadrature signal generating circuit is connected with the left-side port f ′ of the first-stage double-push frequency multiplier, and the right-side port e ′ of the quadrature signal generating circuit is connected with the left-side port g ′ of the first-stage double-push frequency multiplier;

[0013] The right-side port h of the first-stage double-push frequency multiplier is connected with the second-stage double-push frequency multiplier k, and the right-side port j of the first-stage double-push frequency multiplier is connected with the second-stage double-push frequency multiplier k ′ ;

[0014] The double-push frequency multiplier of the two-stage driving stacked four-frequency multiplier adopts a series structure, a series resonance circuit is added to the input end of the first-stage double-push frequency multiplier, the output power and the second harmonic suppression capability of the transistor are improved, the output of the first-stage double-push frequency multiplier is used to drive the source and the gate of the second-stage double-push frequency multiplier, so that the required driving power of the second-stage double-push frequency multiplier to the first-stage double-push frequency multiplier is reduced, the current is multiplexed through stacking, and the direct current power consumption of the two-stage driving stacked four-frequency multiplier is reduced;

[0015] The first-stage double-push frequency multiplier is biased in A and B classes, and the second-stage double-push frequency multiplier is biased in C class.

[0016] Preferably, the differential signal generating circuit comprises a transformer TR1, a capacitor C1 and a capacitor C2.

[0017] The transformer TR1 comprises ports a1, b1, c1, d1 and e1.

[0018] The output port a of the differential signal generating circuit is composed of the d end of the transformer TR1 and one end of the capacitor C2; the port a ′ is composed of the c end of the transformer TR1 and the other end of the capacitor C2; the a end of the transformer TR1 and one end of the capacitor C1 are connected as the input end RF Input of the frequency multiplier; the other end of the capacitor C1 is grounded; the b end and the e end of the transformer TR1 are grounded.

[0019] Preferably, the quadrature signal generating circuit comprises the transformers TR2, TR3, the capacitors C3, C4, the resistors R1, R2;

[0020] The transformer TR2 comprises the ports a2, b2, c2, d2;

[0021] The transformer TR3 comprises the ports a3, b3, c3, d3;

[0022] The output port d of the quadrature signal generating circuit is connected with the input port f of the first-stage double-push frequency multiplier, the output port d' is connected with the input port g of the first-stage double-push frequency multiplier, the output port e of the quadrature signal generating circuit is connected with the input port f' of the first-stage double-push frequency multiplier, the output port e' is connected with the input port g' of the first-stage double-push frequency multiplier; the port b of the quadrature signal generating circuit is composed of the a2 end of the transformer TR2 and one end of the capacitor C3, the port c of the quadrature signal generating circuit is composed of the a2 end of the transformer TR3 and one end of the capacitor C4; the port d of the quadrature signal generating circuit is composed of the d2 end of the transformer TR2 and the other end of the capacitor C3, the port d' of the quadrature signal generating circuit is the b2 port of the transformer TR2; the c2 end of the transformer TR2 is connected with one end of the resistor R1, the other end of the resistor R1 is grounded; the port e of the quadrature signal generating circuit is composed of the d3 end of the transformer TR3 and the other end of the capacitor C4, the port e' is the b3 port of the transformer TR3, the c3 end of the transformer TR3 is connected with one end of the resistor R2, the other end of the resistor R2 is grounded.

[0023] Preferably, the first-stage double-push frequency multiplier comprises the inductors L1, L2, L3, L4, L5, L6, L7, L8, the NMOS tubes M1, M2, M3, M4, M7, the resistors R3, R4, R5, R6, R7, R8, R9, R 10 , the capacitors C5, C6, C7, C8, C9, C 10 , the capacitors C 11 , the capacitors C 12 , the bias voltage Vbias1;

[0024] The first-stage dual-push frequency multiplier consists of two dual-push frequency multipliers with series resonant circuits; the output port h of the first-stage dual-push frequency multiplier is connected to the input port k of the second-stage dual-push frequency multiplier; the output port j of the first-stage dual-push frequency multiplier is connected to the input port k' of the second-stage dual-push frequency multiplier; port f is the left port of inductor L1, port f' is the left port of inductor L2, port g is the left port of inductor L3, and port g' is the left port of inductor L4.

[0025] Port h is formed by connecting the drains of NMOS transistors M1 and M2; port j is formed by connecting the drains of NMOS transistors M3 and M4; the other end of inductor L1 is connected to one end of inductor L5, one end of resistor R3, and one end of capacitor C5; the other end of inductor L2 is connected to one end of inductor L6, one end of resistor R4, and one end of capacitor C6; the other end of inductor L3 is connected to one end of inductor L7, one end of resistor R5, and one end of capacitor C7; the other end of inductor L4 is connected to one end of inductor L8, one end of resistor R6, and one end of capacitor C8; the other end of inductor L5 is connected to the other end of inductor L6 and grounded; the other end of inductor L7 is connected to the other end of inductor L8 and grounded; the other end of resistor R3 is connected to the other end of resistor R4 and one end of inductor L9 and grounded; the other end of resistor R5 is connected to the other end of resistor R6 and inductor L... 10 One end of capacitor C5 is connected to ground; the other end of capacitor C5 is connected to one end of capacitor C9 and one end of resistor R7 and the gate of NMOS transistor M1; the other end of capacitor C6 is connected to capacitor C... 10 One end of capacitor C9 and one end of resistor R8 are connected to the gate of NMOS transistor M2, and the other end of capacitor C9 is connected to capacitor C. 10 The other end is connected to the other end of inductor L9, and the other end of capacitor C7 is connected to capacitor C. 11 One end of capacitor C8 and one end of resistor R9 are connected to the gate of NMOS transistor M3, and the other end of capacitor C8 is connected to capacitor C. 12 one end and resistor R 10 One end of the capacitor is connected to the gate of the NMOS transistor M4, and the capacitor C 11 The other end is connected to capacitor C 12 The other end and inductor L 10 The other end is connected, the other end of resistor R7 is connected to the other end of resistor R8 and the other end of resistor R9 and resistor R 10 The other end and resistor R 11 One end of the resistor is connected to the gate of NMOS transistor M7 and the gate drain of NMOS transistor M7. 11The other end is the input terminal for the bias voltage Vbias1. The source of the NMOS transistor M7 is grounded along with the sources of the NMOS transistors M1, M2, M3, and M4.

[0026] Preferably, the second-stage dual-push frequency multiplier includes: transmission lines TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8, TL9, and TL1. 10 Transmission line TL 11 Capacitor C 13 Capacitor C 14 Capacitor C 15 Capacitor C 16 Capacitor C 17 NMOS transistors M5 and M6, bias voltage Vbias2;

[0027] The second-stage dual-push frequency multiplier consists of a cross-coupled dual-push frequency multiplier. Port k' of the second-stage dual-push frequency multiplier is one port of transmission line TL1, and port k' is one port of transmission line TL4. The other end of transmission line TL1 is connected to one end of transmission line TL2 and one end of transmission line TL3. The other end of transmission line TL2 is connected to capacitor C. 13 One end is connected; the capacitor C 13 The other end of the transmission line TL4 is grounded. The other end of transmission line TL4 is connected to one end of transmission line TL5 and one end of transmission line TL6. The other end of transmission line TL5 is connected to capacitor C. 14 One end of the capacitor C is connected to the capacitor C. 14 The other end of the transmission line TL3 is grounded, and the other end of the transmission line TL3 is connected to one end of the transmission line TL7 and the gate of NMOS transistor M5 and the source of NMOS transistor M6; the other end of the transmission line TL7 is connected to capacitor C. 15 One end of the capacitor C is connected as the input terminal for the bias voltage Vbias2. 15 The other end of the transmission line TL6 is grounded. The other end of the transmission line TL6 is connected to one end of the transmission line TL8 and the gate of NMOS transistor M6 and the source of NMOS transistor M5. The other end of the transmission line TL8 is connected to capacitor C. 16 One end of the capacitor C is connected as the input terminal for the bias voltage Vbias2. 16 The other end is grounded. The drain of NMOS transistor M5 is connected to the drain of NMOS transistor M6 and one end of transmission line TL9. The other end of transmission line TL9 is connected to transmission line TL... 10 One end and transmission line TL 11 One end is connected to the transmission line TL 10 The other end is connected to capacitor C17 One end of the capacitor C is connected as the input terminal for the power supply voltage. 17 The other end of the transmission line TL is grounded. 11 The other end serves as the output terminal (RF Output) of the quadruple frequency multiplier.

[0028] Compared with the prior art, the technical solution of this application has the following technical effects:

[0029] The two-stage driven stacked quadrature frequency multiplier of this invention incorporates an orthogonal signal generation circuit to replace the use of inter-stage baluns, minimizing losses and improving the peak drain efficiency of the frequency multiplier. A series resonant circuit is added to the input of the first-stage dual-push frequency multiplier to enhance the transistor's output power and second harmonic suppression capability. The first-stage dual-push frequency multiplier is biased in classes A and B. The stacked dual-drive structure between the first and second stages reduces the drive power required by the second stage for the first stage, and the stacking enables current reuse, reducing the DC power consumption of the frequency multiplier. The second-stage dual-push frequency multiplier is biased in class C, further improving the output power and drain efficiency.

[0030] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings.

[0031] The above and other objects, advantages and features of this application will become more apparent to those skilled in the art from the following detailed description of specific embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0033] Figure 1 This is a circuit diagram of the quadruple frequency multiplier of the present invention;

[0034] Figure 2 The input matching feature S of the present invention 11 Schematic diagram;

[0035] Figure 3 The output matching characteristic S of the present invention22 Schematic diagram;

[0036] Figure 4 This is a schematic diagram showing the relationship between output power and input power at 88GHz in this invention;

[0037] Figure 5 This is a schematic diagram illustrating the relationship between conversion gain and input power at 88GHz in this invention;

[0038] Figure 6 This is a schematic diagram showing the efficiency and input power of the present invention at 88GHz;

[0039] Figure 7 This is a schematic diagram of the output power of the present invention at an input power of 5.3dBm;

[0040] Figure 8 This is a schematic diagram of the peak efficiency of the present invention at an input power of 5.3 dBm;

[0041] Figure 9 This is a schematic diagram of harmonic suppression at an input power of 5.3dBm according to the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. In the following description, specific details such as specific configurations and components are provided merely to help fully understand the embodiments of this application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. In addition, for clarity and brevity, descriptions of known functions and structures are omitted in the embodiments.

[0043] It should be understood that the phrase "an embodiment" or "this embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "an embodiment" or "this embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0044] Furthermore, reference numerals and / or letters may be repeated in different examples within this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0045] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" in this article describes another type of relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the related objects before and after it are in an "or" relationship.

[0046] In this article, the term "at least one" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0047] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.

[0048] Example 1

[0049] This embodiment mainly describes an efficiency-enhanced two-stage driven stacked quadruple frequency multiplier, such as... Figure 1 As shown, the two-stage driven stacked quadruple frequency multiplier circuit includes: a differential signal generation circuit, a quadrature signal generation circuit, and a dual-push frequency multiplier.

[0050] The differential signal generation circuit has an input terminal RF Input on the left and ports a and a' on the right. ′ ;

[0051] The quadrature signal generation circuit has ports b and c on the left and ports d and d' on the right. ′ , e, e ′ ;

[0052] The dual-push frequency multiplier includes a first-stage dual-push frequency multiplier and a second-stage dual-push frequency multiplier;

[0053] The first-stage dual-push frequency multiplier has ports f and f on its left side. ′ g, g ′ On the right, set ports h and j;

[0054] The second-stage dual-push frequency multiplier has ports k and k on the left side. ′ The RF Output port is set on the right.

[0055] The right port a of the differential signal generation circuit is connected to the left port b of the quadrature signal generation circuit. ′ Connect to port c on the left side of the quadrature signal generation circuit;

[0056] The right port d of the quadrature signal generation circuit is connected to the left port f of the first-stage dual-push frequency multiplier. ′ The left port g of the first-stage dual-push frequency multiplier is connected; the right port e of the quadrature signal generation circuit is connected to the left port f of the first-stage dual-push frequency multiplier. ′ Connect the right port e of the quadrature signal generation circuit. ′ The left port g of the first-stage dual-push frequency multiplier ′ connect;

[0057] The right-side port h of the first-stage dual-push frequency multiplier is connected to the second-stage dual-push frequency multiplier k, and the right-side port j of the first-stage dual-push frequency multiplier is connected to the second-stage dual-push frequency multiplier k. ′ connect;

[0058] The dual-push frequency multiplier of the two-stage driven stacked quadruple frequency multiplier adopts a series structure. A series resonant circuit is added to the input terminal of the first-stage dual-push frequency multiplier, which improves the output power and second harmonic suppression capability of the transistor. The output of the first-stage dual-push frequency multiplier is used to drive the source and gate of the second-stage dual-push frequency multiplier, thereby reducing the driving power required by the second-stage dual-push frequency multiplier for the first-stage dual-push frequency multiplier. The current is reused through stacking, which reduces the DC power consumption of the two-stage driven stacked quadruple frequency multiplier.

[0059] The first-stage dual-push frequency multiplier is biased in classes A and B, while the second-stage dual-push frequency multiplier is biased in class C.

[0060] Furthermore, the differential signal generation circuit includes transformer TR1, capacitor C1, and capacitor C2;

[0061] Transformer TR1 includes ports a1, b1, c1, d1, and e1;

[0062] The output port a of the differential signal generation circuit is formed by connecting the d-end of transformer TR1 to one end of capacitor C2; port a ′ It consists of connecting the c terminal of transformer TR1 to the other end of capacitor C2; the a terminal of transformer TR1 is connected to one end of capacitor C1 as the input terminal RF Input of the frequency multiplier; the other end of capacitor C1 is grounded; the b and e terminals of transformer TR1 are grounded.

[0063] Furthermore, the quadrature signal generation circuit includes transformers TR2 and TR3, capacitors C3 and C4, resistors R1 and R2;

[0064] Transformer TR2 includes ports a2, b2, c2, and d2;

[0065] Transformer TR3 includes ports a3, b3, c3, and d3;

[0066] The output port d of the quadrature signal generation circuit is connected to the input port f of the first-stage dual-push frequency multiplier, and port d' is connected to the input port g of the first-stage dual-push frequency multiplier. The output port e of the quadrature signal generation circuit is connected to the input port f' of the first-stage dual-push frequency multiplier, and port e' is connected to the input port g' of the first-stage dual-push frequency multiplier. Port b of the quadrature signal generation circuit is formed by connecting terminal a2 of transformer TR2 to one end of capacitor C3, and port c of the quadrature signal generation circuit is formed by connecting terminal a2 of transformer TR3 to one end of capacitor C4. The orthogonal signal generation circuit has port d connected to the d2 terminal of transformer TR2 and the other end of capacitor C3. Port d' is the b2 terminal of transformer TR2. The c2 terminal of transformer TR2 is connected to one end of resistor R1, and the other end of resistor R1 is grounded. The orthogonal signal generation circuit has port e connected to the d3 terminal of transformer TR3 and the other end of capacitor C4. Port e' is the b3 terminal of transformer TR3. The c3 terminal of transformer TR3 is connected to one end of resistor R2, and the other end of resistor R2 is grounded.

[0067] Furthermore, the first-stage dual-push frequency multiplier includes inductors L1, L2, L3, L4, L5, L6, L7, and L8; NMOS transistors M1, M2, M3, M4, and M7; and resistors R3, R4, R5, R6, R7, R8, R9, and R... 10 Capacitor C5, Capacitor C6, Capacitor C7, Capacitor C8, Capacitor C9, Capacitor C 10 Capacitor C 11 Capacitor C 12 Bias voltage Vbias1;

[0068] The first-stage dual-push frequency multiplier consists of two dual-push frequency multipliers with series resonant circuits; the output port h of the first-stage dual-push frequency multiplier is connected to the input port k of the second-stage dual-push frequency multiplier; the output port j of the first-stage dual-push frequency multiplier is connected to the input port k' of the second-stage dual-push frequency multiplier; port f is the left port of inductor L1, port f' is the left port of inductor L2, port g is the left port of inductor L3, and port g' is the left port of inductor L4.

[0069] Port h is formed by connecting the drains of NMOS transistors M1 and M2; port j is formed by connecting the drains of NMOS transistors M3 and M4. The other end of inductor L1 is connected to one end of inductor L5, one end of resistor R3, and one end of capacitor C5. The other end of inductor L2 is connected to one end of inductor L6, one end of resistor R4, and one end of capacitor C6. The other end of inductor L3 is connected to one end of inductor L7, one end of resistor R5, and one end of capacitor C7. The other end of inductor L4 is connected to one end of inductor L8, one end of resistor R6, and one end of capacitor C8. The other end of inductor L5 is connected to the other end of inductor L6 and grounded. The other end of inductor L7 is connected to the other end of inductor L8 and grounded. The other end of resistor R3 is connected to the other end of resistor R4 and one end of inductor L9 and grounded. The other end of resistor R5 is connected to the other end of resistor R6 and inductor L... 10 One end of capacitor C5 is connected to ground; the other end of capacitor C5 is connected to one end of capacitor C9 and one end of resistor R7 and the gate of NMOS transistor M1; the other end of capacitor C6 is connected to capacitor C... 10 One end of capacitor C9 and one end of resistor R8 are connected to the gate of NMOS transistor M2, and the other end of capacitor C9 is connected to capacitor C. 10 The other end is connected to the other end of inductor L9, and the other end of capacitor C7 is connected to capacitor C. 11 One end of capacitor C8 and one end of resistor R9 are connected to the gate of NMOS transistor M3, and the other end of capacitor C8 is connected to capacitor C. 12 one end and resistor R 10 One end is connected to the gate of NMOS transistor M4, and capacitor C 11 The other end is connected to capacitor C 12 The other end and inductor L 10 The other end is connected, the other end of resistor R7 is connected to the other end of resistor R8 and the other end of resistor R9 and resistor R 10 The other end and resistor R 11 One end is connected to the gate of NMOS transistor M7 and the gate-drain of NMOS transistor M7, and the resistor R 11 The other end is the input terminal for the bias voltage Vbias1. The source of NMOS transistor M7 is grounded along with the sources of NMOS transistors M1, M2, M3, and M4.

[0070] Furthermore, the second-stage dual-push frequency multiplier includes: transmission lines TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8, TL9, and TL1. 10 Transmission line TL 11 Capacitor C 13 Capacitor C 14 Capacitor C15 Capacitor C 16 Capacitor C 17 NMOS transistors M5 and M6, bias voltage Vbias2;

[0071] The second-stage dual-push frequency multiplier consists of a cross-coupled dual-push frequency multiplier. Port k' of the second-stage dual-push frequency multiplier is one port of transmission line TL1, and port k' is one port of transmission line TL4. The other end of transmission line TL1 is connected to one end of transmission line TL2 and one end of transmission line TL3. The other end of transmission line TL2 is connected to capacitor C. 13 One end is connected; capacitor C 13 The other end is grounded. The other end of transmission line TL4 is connected to one end of transmission line TL5 and one end of transmission line TL6. The other end of transmission line TL5 is connected to capacitor C. 14 One end is connected to capacitor C 14 The other end of transmission line TL3 is grounded, and the other end of transmission line TL3 is connected to one end of transmission line TL7 and the gate of NMOS transistor M5 and the source of NMOS transistor M6; the other end of transmission line TL7 is connected to capacitor C. 15 One end of the capacitor is connected as the input terminal for the bias voltage Vbias2. 15 The other end of the transmission line TL6 is grounded. The other end of transmission line TL6 is connected to one end of transmission line TL8, the gate of NMOS transistor M6, and the source of NMOS transistor M5. The other end of transmission line TL8 is connected to capacitor C. 16 One end of the capacitor is connected as the input terminal for the bias voltage Vbias2. 16 The other end is grounded. The drain of NMOS transistor M5 is connected to the drain of NMOS transistor M6 and one end of transmission line TL9. The other end of transmission line TL9 is connected to transmission line TL... 10 One end and transmission line TL 11 One end is connected to the transmission line TL 10 The other end is connected to capacitor C 17 One end of the capacitor is connected as the input terminal for the power supply voltage. 17 The other end is grounded, and the transmission line TL 11 The other end serves as the output terminal (RF Output) of the quadruple frequency multiplier.

[0072] This embodiment replaces the interstage balun with an orthogonal signal generation circuit, minimizing losses and improving the efficiency of the frequency multiplier. The frequency multiplier adopts a two-stage dual-push frequency multiplier cascade structure. A series resonant circuit is added to the input of the first stage, which improves the output power and second harmonic suppression capability of the transistor. The output of the first stage is used to drive the source and gate of the second stage, reducing the driving power required by the second stage for the first stage. Furthermore, current reuse is achieved through stacking, reducing the DC power consumption of the frequency multiplier. At the same time, the first-stage dual-push frequency multiplier is biased in class AB, and the second-stage dual-push frequency multiplier is also biased in class C, further improving the output power and drain efficiency.

[0073] Example 2

[0074] This embodiment, based on Embodiment 1, describes in detail a simulation experiment of an efficiency-enhanced two-stage driven stacked quadruple frequency multiplier, specifically including:

[0075] The two-stage driven stacked quadruple frequency multiplier consists of a differential signal generation circuit, a quadrature generation circuit, and two stages of dual-push frequency multipliers. The differential signal generation circuit is composed of transformer TR1, which converts the signal into a differential signal while achieving input matching. The quadrature generation circuit is composed of two transformers TR2 and TR3 with feedforward capacitors, which convert the differential signal into four signals with a 90° phase difference. The feedforward capacitors ensure that the transformers perform fine phase control, achieve an accurate 90° phase shift between the output signals, and also avoid the use of inter-stage baluns, minimizing losses and improving the efficiency of the quadruple frequency multiplier.

[0076] The input terminals of the first-stage dual-push frequency multiplier are all equipped with series resonant circuits, which increases the output power of the transistors and allows the second harmonic to be short-circuited to ground through the resonant circuit, thus improving the second harmonic suppression capability. At the same time, a shunt resistor is added to the resonator to reduce the Q value, which expands the matching bandwidth between the quadrature generation circuit and the dual-push frequency multiplier. In order to effectively drive the second-stage dual-push frequency multiplier, the first-stage dual-push frequency multiplier is biased in class AB, while the second-stage dual-push frequency multiplier is biased in class C for efficiency. The first-stage dual-push frequency multiplier is designed to drive the gate and source of the second stage. This stacked dual-drive structure reduces the drive power required by the second stage for the first stage, and the current reuse through stacking reduces the DC power consumption of the frequency multiplier. At the same time, the output power and drain efficiency are further improved.

[0077] In the simulation test, the circuit of the two-stage driven stacked quadruple frequency multiplier was designed using 90nm CMOS process, with a power supply voltage of 3V, and the operating frequency can cover 83-95GHz. The overall power consumption of the circuit is 50mW, the peak output power is 6.8dBm, the conversion gain is 2.2dB, the peak drain efficiency is 10.3%, and the harmonic suppression is greater than 31dBc.

[0078] like Figure 1 As shown, the key circuit parameters are: C1 = 186fF, C2 = 160fF, C 3，4 =142fF, C 5，6，7，8 =1pF,C 9，10，11，12 =148fF, C 13，14 =320fF, C 15，16，17 =10pF;

[0079] L ab1 =L cd1 =90pH, k1=0.75, L ab2 =L cd2 =L ab3 =L cd3 =253pH, k2=k3=0.66, L1=L2=L3=L4=120pH,

[0080] L5=L6=L7=L8=360pH, L9=L 10 =40pH, R1=R2=25Ω, R3=R4=R6=R6=100Ω, R7=R8=R9=R 10 =10kΩ,

[0081] Wm1=Wm2=Wm3=Wm4=Wm7=24um, Wm5=Wm6=30um;

[0082] TL1=TL4=50Ω / 26°, TL2=TL5=50Ω / 33°, TL3=TL6=30Ω / 24°, TL7=TL8=30Ω / 90°, TL9=35Ω / 28°, TL 10 =50Ω / 8°, TL 11 =35Ω / 20°;

[0083] like Figure 2 As shown, the input matching feature S of the present invention is given. 11 Simulation results show that S in the 20-24 GHz frequency band 11 All less than -10dB;

[0084] like Figure 3 As shown, the output matching characteristic S of the present invention is given. 22 Simulation results show that S in the 83-95GHz frequency band 22 All less than -10dB;

[0085] like Figure 4 As shown, the simulation results of the relationship between output power and input power at 88GHz are presented. When the input power is greater than 5.2dBm, the output power remains basically stable at 6.8dBm.

[0086] like Figure 5 As shown, the simulation results of the relationship between conversion gain and input power at 88GHz are presented. When the input power is 5.3dBm, the conversion gain reaches a maximum of 2.2dB.

[0087] like Figure 6 As shown, the simulation results of the relationship between drain efficiency and input power at 88GHz are presented. When the input power is 5.3dBm, the drain efficiency reaches a maximum of 10.2%.

[0088] like Figure 7 As shown, the simulation results of the output power are presented when the input power is 5.3dBm. The output power varies from 3 to 6.8dBm in the 83-95GHz frequency band, and reaches a maximum value of 6.8dBm at the center frequency.

[0089] like Figure 8 As shown, the simulation results of peak drain efficiency are presented when the input power is 5.3dBm. The output power varies from 8.3% to 10.3% in the 83-95GHz frequency band, and reaches a maximum of 10.3% at the center frequency.

[0090] like Figure 9 As shown, the simulation results of harmonic suppression at an input power of 5.3dBm are presented. In the 83-95GHz frequency band, the fundamental frequency suppression is 46dBc, the second harmonic suppression is 31dBc, and the third harmonic suppression is 35dBc.

[0091] Table 1 Comparison of Parameter Performance

[0092]

[0093] The existing technology is: BH Ku, H Chung, GM Rebeiz.A Milliwatt-Level 70-110 GHzFrequencyQuadrupler With>30 dBc Harmonic Rejection[J].IEEE TRANSACTIONS ONMICROWAVETHEORY AND TECHNIQUES, 2020, 68(5): 1697-1705.

[0094] As shown in Table 1, because the frequency multiplier of this invention incorporates a quadrature signal generation circuit, it avoids the use of interstage baluns, minimizing losses and improving the peak drain efficiency of the frequency multiplier. This results in a significant advantage in efficiency performance compared to conventional cascaded frequency multiplier schemes in the prior art. Furthermore, the output power and power consumption of this invention are also significantly better than existing technologies. These factors make this invention a superior high-efficiency quadruple frequency multiplier solution suitable for W-band transmitters.

[0095] This embodiment details a simulation experiment of an efficiency-enhanced two-stage driven stacked quadruple frequency multiplier. The simulation results show that the frequency multiplier of this invention avoids the use of interstage baluns, minimizes losses, and improves the peak drain efficiency of the frequency multiplier, exhibiting a significant advantage in efficiency performance. It becomes a high-efficiency quadruple frequency multiplier solution suitable for W-band transmitters.

[0096] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any changes, modifications, substitutions, integrations, and parameter changes made to these embodiments within the spirit and principles of the present invention, without departing from the principles and spirit of the present invention, through conventional substitutions or to achieve the same function, fall within the scope of protection of the present invention.

Claims

1. An efficiency-enhanced two-stage driven stacked quadruple frequency multiplier, characterized in that, The two-stage driven stacked quadruple frequency multiplier circuit includes: a differential signal generation circuit, a quadrature signal generation circuit, and a dual-push frequency multiplier; The differential signal generation circuit has an input terminal RF Input on the left and ports a and a' on the right. ′ ; The orthogonal signal generation circuit has ports b and c on the left and ports d and d' on the right. ′ , e, e ′ ; The dual-push frequency multiplier includes a first-stage dual-push frequency multiplier and a second-stage dual-push frequency multiplier; The first-stage dual-push frequency multiplier has ports f1 and f2 on its left side. ′ g, g ′ On the right, set ports h and j; The second-stage dual-push frequency multiplier has ports k and k on its left side. ′ The RF Output port is set on the right. The right port a of the differential signal generation circuit is connected to the left port b of the quadrature signal generation circuit. ′ Connect to port c on the left side of the quadrature signal generation circuit; The right port d of the quadrature signal generation circuit is connected to the left port f of the first-stage dual-push frequency multiplier. ′ The left port g of the first-stage dual-push frequency multiplier is connected; the right port e of the quadrature signal generation circuit is connected to the left port f of the first-stage dual-push frequency multiplier. ′ Connect the right port e of the quadrature signal generation circuit. ′ The left port g of the first-stage dual-push frequency multiplier ′ connect; The right-side port h of the first-stage dual-push frequency multiplier is connected to the second-stage dual-push frequency multiplier k, and the right-side port j of the first-stage dual-push frequency multiplier is connected to the second-stage dual-push frequency multiplier k. ′ connect; The dual-push frequency multiplier of the two-stage driven stacked quadruple frequency multiplier adopts a series structure. A series resonant circuit is added to the input terminal of the first-stage dual-push frequency multiplier, which improves the output power and second harmonic suppression capability of the transistor. The output of the first-stage dual-push frequency multiplier is used to drive the source and gate of the second-stage dual-push frequency multiplier, thereby reducing the driving power required by the second-stage dual-push frequency multiplier for the first-stage dual-push frequency multiplier. The current is reused through stacking, which reduces the DC power consumption of the two-stage driven stacked quadruple frequency multiplier. The first-stage dual-push frequency multiplier is biased in class A and B, and the second-stage dual-push frequency multiplier is biased in class C.

2. The efficiency-enhanced two-stage driven stacked quadruple frequency multiplier according to claim 1, characterized in that, The differential signal generation circuit includes a transformer TR1, a capacitor C1, and a capacitor C2; The transformer TR1 includes ports a1, b1, c1, d1, and e1; The output port a of the differential signal generation circuit is formed by connecting the d end of transformer TR1 and one end of capacitor C2; the port a ′ It is composed of the c terminal of transformer TR1 connected to the other end of capacitor C2; the a terminal of transformer TR1 is connected to one end of capacitor C1 as the input terminal RF Input of the frequency multiplier; the other end of capacitor C1 is grounded; the b and e terminals of transformer TR1 are grounded.

3. The efficiency-enhanced two-stage driven stacked quadruple frequency multiplier according to claim 1, characterized in that, The quadrature signal generation circuit includes transformers TR2 and TR3, capacitor C3, capacitor C4, resistor R1, and resistor R2. The transformer TR2 includes ports a2, b2, c2, and d2; The transformer TR3 includes ports a3, b3, c3, and d3; The output port d of the quadrature signal generation circuit is connected to the input port f of the first-stage dual-push frequency multiplier, and port d' is connected to the input port g of the first-stage dual-push frequency multiplier. The output port e of the quadrature signal generation circuit is connected to the input port f' of the first-stage dual-push frequency multiplier, and port e' is connected to the input port g' of the first-stage dual-push frequency multiplier. Port b of the quadrature signal generation circuit is formed by connecting terminal a2 of transformer TR2 to one end of capacitor C3, and port c of the quadrature signal generation circuit is formed by connecting terminal a2 of transformer TR3 to one end of capacitor C4. The port d of the quadrature signal generation circuit is formed by connecting the d2 terminal of transformer TR2 to the other end of capacitor C3. The port d' of the quadrature signal generation circuit is the v2 terminal of transformer TR2. The c2 terminal of transformer TR2 is connected to one end of resistor R1, and the other end of resistor R1 is grounded. The port e of the quadrature signal generation circuit is formed by connecting the d3 terminal of transformer TR3 to the other end of capacitor C4. The port e' is the b3 terminal of transformer TR3. The c3 terminal of transformer TR3 is connected to one end of resistor R2, and the other end of resistor R2 is grounded.

4. The efficiency-enhanced two-stage driven stacked quadruple frequency multiplier according to claim 1, characterized in that, The first-stage dual-push frequency multiplier includes inductors L1, L2, L3, L4, L5, L6, L7, and L8; NMOS transistors M1, M2, M3, M4, and M7; and resistors R3, R4, R5, R6, R7, R8, R9, and R... 10 Capacitor C5, Capacitor C6, Capacitor C7, Capacitor C8, Capacitor C9, Capacitor C 10 Capacitor C 11 Capacitor C 12 Bias voltage Vbias1; The first-stage dual-push frequency multiplier consists of two dual-push frequency multipliers with series resonant circuits; the output port h of the first-stage dual-push frequency multiplier is connected to the input port k of the second-stage dual-push frequency multiplier; the output port j of the first-stage dual-push frequency multiplier is connected to the input port k' of the second-stage dual-push frequency multiplier; port f is the left port of inductor L1, port f' is the left port of inductor L2, port g is the left port of inductor L3, and port g' is the left port of inductor L4. Port h is formed by connecting the drains of NMOS transistors M1 and M2; port j is formed by connecting the drains of NMOS transistors M3 and M4; the other end of inductor L1 is connected to one end of inductor L5, one end of resistor R3, and one end of capacitor C5; the other end of inductor L2 is connected to one end of inductor L6, one end of resistor R4, and one end of capacitor C6; the other end of inductor L3 is connected to one end of inductor L7, one end of resistor R5, and one end of capacitor C7; the other end of inductor L4 is connected to one end of inductor L8, one end of resistor R6, and one end of capacitor C8; the other end of inductor L5 is connected to the other end of inductor L6 and grounded; the other end of inductor L7 is connected to the other end of inductor L8 and grounded; the other end of resistor R3 is connected to the other end of resistor R4 and one end of inductor L9 and grounded; the other end of resistor R5 is connected to the other end of resistor R6 and inductor L... 10 One end of capacitor C5 is connected to ground; the other end of capacitor C5 is connected to one end of capacitor C9 and one end of resistor R7 and the gate of NMOS transistor M1; the other end of capacitor C6 is connected to capacitor C... 10 One end of capacitor C9 and one end of resistor R8 are connected to the gate of NMOS transistor M2, and the other end of capacitor C9 is connected to capacitor C. 10 The other end is connected to the other end of inductor L9, and the other end of capacitor C7 is connected to capacitor C. 11 One end of capacitor C8 and one end of resistor R9 are connected to the gate of NMOS transistor M3, and the other end of capacitor C8 is connected to capacitor C. 12 one end and resistor R 10 One end of the capacitor is connected to the gate of the NMOS transistor M4, and the capacitor C 11 The other end is connected to capacitor C 12 The other end and inductor L 10 The other end is connected, the other end of resistor R7 is connected to the other end of resistor R8 and the other end of resistor R9 and resistor R 10 The other end and resistor R 11 One end of the resistor is connected to the gate of NMOS transistor M7 and the gate drain of NMOS transistor M7. 11 The other end is the input terminal for the bias voltage Vbias1. The source of the NMOS transistor M7 is grounded along with the sources of the NMOS transistors M1, M2, M3, and M4.

5. The efficiency-enhanced two-stage driven stacked quadruple frequency multiplier according to claim 1, characterized in that, The second-stage dual-push frequency multiplier includes: transmission lines TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8, TL9, and TL1. 10 Transmission line TL 11 Capacitor C 13 Capacitor C 14 Capacitor C 15 Capacitor C 16 Capacitor C 17 NMOS transistors M5 and M6, bias voltage Vbias2; The second-stage dual-push frequency multiplier consists of a cross-coupled dual-push frequency multiplier. Port k' of the second-stage dual-push frequency multiplier is one port of transmission line TL1, and port k' is one port of transmission line TL4. The other end of transmission line TL1 is connected to one end of transmission line TL2 and one end of transmission line TL3. The other end of transmission line TL2 is connected to capacitor C. 13 One end of the capacitor C is connected; 13 The other end of the transmission line TL4 is grounded. The other end of transmission line TL4 is connected to one end of transmission line TL5 and one end of transmission line TL6. The other end of transmission line TL5 is connected to capacitor C. 14 One end of the capacitor C is connected to the capacitor C. 14 The other end of the transmission line TL3 is grounded, and the other end of the transmission line TL3 is connected to one end of the transmission line TL7 and the gate of NMOS transistor M5 and the source of NMOS transistor M6; the other end of the transmission line TL7 is connected to capacitor C. 15 One end of the capacitor C is connected as the input terminal for the bias voltage Vbias2. 15 The other end of the transmission line TL6 is grounded. The other end of the transmission line TL6 is connected to one end of the transmission line TL8 and the gate of NMOS transistor M6 and the source of NMOS transistor M5. The other end of the transmission line TL8 is connected to capacitor C. 16 One end of the capacitor C is connected as the input terminal for the bias voltage Vbias2. 16 The other end is grounded. The drain of NMOS transistor M5 is connected to the drain of NMOS transistor M6 and one end of transmission line TL9. The other end of transmission line TL9 is connected to transmission line TL... 10 One end and transmission line TL 11 One end is connected to the transmission line TL 10 The other end is connected to capacitor C 17 One end of the capacitor C is connected as the input terminal for the power supply voltage. 17 The other end of the transmission line TL is grounded. 11 The other end serves as the output terminal (RF Output) of the quadruple frequency multiplier.

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