Parallel computing method and system of tensor protocol and computer equipment

Abstract

The invention relates to the technical field of information processing, in particular to a parallel computing method and system for a tensor protocol and computer equipment, and the method comprises the following steps: a tensor segmentation step: dynamically segmenting a high-dimensional tensor based on a non-protocol dimension to obtain a plurality of sub-tensors; a sub-tensor distribution step: distributing a plurality of sub-tensors to a plurality of calculation processing units based on the number of the sub-tensors; a sub-tensor parallel reduction step: performing parallel reduction on the plurality of sub-tensors by the plurality of calculation processing units based on a recursive algorithm to obtain a reduction result tensor; and a reduction result tensor writing-back step: writing the reduction result tensor back to the main memory.

Description

Technical Field

[0001] The present invention relates to the field of information processing technology, and more specifically, to a tensor-reduced parallel computing method, system and computer equipment. Background Art

[0002] With the rapid development of artificial intelligence and high-performance computing, the demand for computer computing power has increased dramatically. As the core data structure in deep learning, the efficiency of tensor reduction operations (such as summation, maximum value, etc.) directly affects the training and inference speed of the model. However, existing tensor reduction methods have many problems in multi-core parallel computing environments, such as low computing efficiency, unbalanced load, and data transmission bottlenecks. For example, existing methods usually use simple multi-threaded parallel computing, which cannot fully utilize the parallel capabilities of multi-core processors, and lack dynamic adaptability when splitting and allocating tensors, resulting in some computing units being idle while other units are overloaded. In addition, the reallocation and dynamic adjustment of tensors also involve complex data transmission and synchronization operations, which further reduces computing efficiency.

[0003] Therefore, it is an urgent problem to provide a parallel computing method, system and computer device for tensor reduction with high computing efficiency and strong dynamic adaptability. Summary of the invention

[0004] The present invention provides a parallel computing method, system and computer equipment for tensor reduction, so as to at least solve the problems of low computing efficiency and lack of dynamic adaptability of the existing tensor reduction method.

[0005] To achieve the above object, the present invention provides a parallel computing method for tensor reduction, comprising: Tensor segmentation step: dynamically segment the high-dimensional tensor based on the unreduced dimension to obtain multiple sub-tensors; A sub-tensor allocation step: allocating a plurality of the sub-tensors to a plurality of computing processing units based on the number of the sub-tensors; Sub-tensor parallel reduction step: multiple computing processing units perform parallel reduction on multiple sub-tensors based on a recursive algorithm to obtain a reduction result tensor; The reduction result tensor writing back step: writing the reduction result tensor back to the main memory.

[0006] Furthermore, the tensor segmentation step includes: Traverse all non-reduced dimensions from the last dimension of the high-dimensional tensor forward to the first dimension that satisfies the storage space requirement of the sub-tensor formed from the dimension to the last dimension is not less than the local memory capacity as the splitting dimension; Acquire a segmentation step length based on the segmentation dimension and the local memory capacity; The high-dimensional tensor is segmented based on the segmentation dimension and the segmentation step to obtain a plurality of sub-tensors.

[0007] Furthermore, it is characterized in that the sub-tensor allocation step comprises: If the number of the sub-tensors is greater than the total number of slave cores, allocating the plurality of sub-tensors to the plurality of slave cores based on a cyclic allocation; If the number of the sub-tensors is less than the total number of slave cores, the sub-tensors are split twice based on the reduced dimension, the slave cores are divided into work groups based on the number of sub-tensors after the second split, and the multiple sub-tensors after the second split are allocated to multiple work groups based on cyclic allocation.

[0008] Furthermore, the sub-tensor parallel reduction step includes: The plurality of computing processing units perform recursive decomposition operations on the allocated sub-tensors in parallel until the dimension of the sub-tensors is no greater than a set threshold; a reduction operation is performed on the sub-tensors that reach the set threshold to obtain a reduced result tensor, and the reduced result tensor is recorded in a target storage location.

[0009] Furthermore, the sub-tensor parallel reduction step further includes: Reduction index calculation step: During the reduction process, the reduction index of each element in the reduction dimension is calculated in real time based on the source data offset and the data stride, and the reduction result tensor and the corresponding reduction index are recorded in the target storage location.

[0010] Furthermore, the step of writing back the reduced result tensor includes: If a single sub-tensor is processed by a single computing processing unit, the first slave core of each computing processing unit writes the reduced result tensor back to the main memory; If a single sub-tensor is processed by multiple computing processing units, the multiple computing processing units involved in the processing of the sub-tensor are traversed in turn, and the first slave core of each computing processing unit writes the reduced result tensor back to the main memory, and performs a memory synchronization operation after each write back.

[0011] The present invention provides a parallel computing system for tensor reduction, which is applied to the above-mentioned parallel computing method for tensor reduction, comprising: Tensor segmentation module: dynamically segment high-dimensional tensors based on non-reduced dimensions to obtain multiple sub-tensors; A sub-tensor allocation module: allocating a plurality of the sub-tensors to a plurality of computing processing units based on the number of the sub-tensors; Sub-tensor parallel reduction module: multiple computing processing units perform parallel reduction on multiple sub-tensors based on a recursive algorithm to obtain a reduction result tensor; The reduction result tensor write-back module writes the reduction result tensor back to the main memory.

[0012] Furthermore, the tensor segmentation module includes: Traverse all non-reduced dimensions from the last dimension of the high-dimensional tensor forward to the first dimension that satisfies the storage space requirement of the sub-tensor formed from the dimension to the last dimension is not less than the local memory capacity as the splitting dimension; Acquire a segmentation step length based on the segmentation dimension and the local memory capacity; The high-dimensional tensor is segmented based on the segmentation dimension and the segmentation step to obtain multiple tensors.

[0013] The present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the parallel computing method of tensor reduction when executing the computer program.

[0014] The present invention provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the above-mentioned parallel computing method is implemented.

[0015] Compared with the prior art, the advantages and positive effects of the present invention are: Based on the structure of tensors and the characteristics of reduction operations, the present invention performs dynamic tensor segmentation on non-reduction dimensions, thereby achieving efficient parallel processing, improving computational efficiency, simplifying the synchronization mechanism, ensuring data consistency when results are written back, and effectively avoiding potential write conflict problems. At the same time, the spatial and temporal locality of data is improved, thereby reducing the number of interactions between the slave core group and the memory and improving memory access efficiency.

[0016] The present invention adopts a load balancing strategy for dynamically determining the parallel granularity according to the number of sub-tensors, fully utilizing the data exchange capability between slave cores in a multi-core parallel computing environment and improving the parallel computing efficiency. The present invention performs recursive parallel reduction on the segmented sub-tensors, allowing data segmentation and reduction to be processed simultaneously in one traversal, thereby improving computational efficiency. At the same time, the reduction calculation can also return the index of each element in the reduced dimension to achieve data tracking and tracing, which helps to better understand and optimize the algorithm, and also helps to locate potential errors and performance bottlenecks. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the parallel computing method of tensor reduction in an embodiment of the present invention; Figure 2 A schematic diagram of a recursive equivalent relationship for reducing high-dimensional tensors in an embodiment of the present invention; Figure 3A schematic diagram of high-dimensional tensor parallel reduction in an embodiment of the present invention; Figure 4 Schematic diagram of the structure of a parallel computing system for tensor reduction in an embodiment of the present invention; Figure 5 A schematic diagram of a computer device provided in an embodiment of the present invention.

[0018] In the above picture: 40. bus; 41. processor; 42. memory; 43. communication interface; 100. tensor segmentation module; 200. sub-tensor allocation module; 300. sub-tensor parallel reduction module; 400. reduction result tensor write-back module. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "liquid level", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more.

[0021] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0022] like Figure 1-Figure 5As shown, the present invention provides a parallel computing method, system and computer device for tensor reduction, so as to at least solve the problems of low computing efficiency and lack of dynamic adaptability of existing tensor reduction methods. Figure 1-Figure 5 The tensor reduction parallel computing method, system and computer equipment provided by the present invention are described in detail.

[0023] Embodiment 1: Figure 1 FIG. 1 is a flow chart of a parallel computing method for tensor reduction in an embodiment of the present invention. Figure 1 As shown, the present invention provides a parallel computing method for tensor reduction, including a tensor splitting step S100, a sub-tensor allocation step S200, a sub-tensor parallel reduction step S300 and a reduction result tensor writing back step S400.

[0024] Tensor segmentation step S100: dynamically segment the high-dimensional tensor based on the non-reduced dimension to obtain multiple sub-tensors. Specifically, the non-reduced segmentation dimension can be found based on the reduced high-dimensional tensor.

[0025] Since tensor splitting occurs in the non-reduced dimension, each split sub-tensor is complete in the reduced dimension. This means that the result of the sub-tensor processed by each work group after reduction is unique to the sub-tensor and will not overlap with the results of other sub-tensors. This not only achieves efficient parallel processing and improves computing efficiency, but also simplifies the synchronization mechanism, ensures data consistency when the results are written back, effectively avoids potential write conflict problems, and improves the spatial and temporal locality of data, thereby reducing the number of interactions between the core group and the memory and improving memory access efficiency.

[0026] Preferably, the tensor segmentation step S100 includes: determining the segmentation dimension S101, calculating the segmentation step size S102, and generating sub-tensors S103.

[0027] Determine the split dimension S101: traverse all dimensions from the last dimension of the high-dimensional tensor forward to the first dimension that satisfies the storage space requirement of the sub-tensor formed from the dimension to the last dimension is not less than the local memory capacity as the split dimension; Calculate the segmentation step size S102: Obtain the segmentation step size based on the segmentation dimension and the local memory capacity; the segmentation dimension and the segmentation step size jointly determine the amount of data processed by each parallel task. In order to ensure that the space occupied by each sub-tensor after segmentation is less than or equal to the local memory, the data space occupied by the tensor composed of the last dimension accumulated by the segmentation stride must be less than or equal to the local memory; Generate sub-tensors S103: Split the high-dimensional tensor based on the split dimension and split step to obtain multiple sub-tensors. This split strategy is applicable to input tensors of different shapes and sizes. Through dynamic calculation and adjustment, it ensures that the size of the sub-tensor is always within the local memory capacity of the slave core, avoiding unnecessary over-segmentation while maintaining high computational efficiency.

[0028] In some embodiments, tensor splitting is performed using the original tensor T with dimensions [3, N, C, H, W] as an example. It is assumed that the dimensions of T are numbered 0, 1, 2, 3, 4 from left to right, and the 0th dimension is used as the reduced dimension for reduction. After reduction, the reduced tensor T1 is [1, N, C, H, W].

[0029] Determine the split dimension based on the reduced tensor T1, find the split dimension k in the non-reduced dimensions (i.e., the 1st to 4th dimensions), traverse all dimensions from the 4th dimension forward, and find the first dimension that satisfies the requirement that the cumulative storage space occupied by the sub-tensors [k, ..., H, W] from k to the 4th dimension is greater than or equal to the local memory capacity as the split dimension, that is:

[0030] in, It represents the cumulative storage space occupied by the sub-tensors from dimension k to the 4th dimension; M represents the local memory capacity.

[0031] Assuming that the second dimension is a dimension that meets the conditions, the second dimension is the splitting dimension.

[0032] The split step length S is calculated on the split dimension. In order to ensure that the space occupied by each sub-tensor after the split is less than or equal to the local memory capacity, the data space occupied by the tensor composed of the last dimension after the split stride accumulation must be less than or equal to the local memory capacity, that is:

[0033] The calculation formula of segmentation step length S is as follows:

[0034] Assuming that the second dimension is the split dimension and the local memory capacity is 1024, the sub-tensor after splitting based on the second dimension is [1, 1, S, H, W], and the split step size is:

[0035] Based on the split dimension and split step size, the original tensor T before reduction is divided into n sub-tensors , the dimensions of each sub-tensor are [3, 1, S, H, W].

[0036] Sub-tensor allocation step S200: allocating multiple sub-tensors to multiple computing processing units based on the number of sub-tensors; the allocation strategy is dynamically adjusted according to the number of sub-tensors and the number of slave cores to ensure load balancing and efficient use of computing resources.

[0037] Preferably, the sub-tensor allocation step S200 includes: If the number of sub-tensors is greater than the total number of slave cores, multiple sub-tensors are allocated to multiple slave cores based on cyclic allocation; If the number of sub-tensors is less than the total number of slave cores, the sub-tensors are split twice based on the reduced dimension, the slave cores are divided into work groups based on the number of sub-tensors after the second split, and multiple sub-tensors after the second split are allocated to multiple work groups based on cyclic allocation.

[0038] In some embodiments, if the number of sub-tensors is greater than the total number of slave cores, a cyclic allocation strategy is adopted to allocate the sub-tensors to each slave core in turn. Each slave core processes one sub-tensor to ensure that all sub-tensors are processed.

[0039] Assume that the original tensor T[3, N, C, H, W] above is divided into 100 sub-tensors, and assume that there are 24 slave cores in the system. Then the 100 sub-tensors are distributed to the 24 slave cores in turn in a cyclic distribution manner. Slave core 0 processes sub-tensor 0, slave core 1 processes sub-tensor 1, and so on. After slave core 23 processes sub-tensor 23, slave core 0 continues to process sub-tensor 24 until all sub-tensors are distributed.

[0040] If the total number of slave cores is greater than the number of sub-tensors, the sub-tensors are further divided based on the specification dimension, and a group of slave cores, that is, a working group, is used to process a sub-tensor to achieve finer-grained parallel processing.

[0041] After processing the sub-tensors in parallel, the slave cores in the work group need to communicate and further merge the reduction results. In order to efficiently exchange data between slave cores, there are three ways for the work group to select, namely, a row of slave cores in the slave core array, all cores in the slave core array, and all slave cores in a chip. If the work group is a row of slave cores in the slave core array, it can perform high-speed data exchange through RMA row broadcast. If the work group is all cores in the slave core array or all slave cores in a chip, it can perform high-speed data exchange through RMA intra-core group broadcast.

[0042] When a row of slave cores is used as a working group, a chip can be divided into 48 working groups, which means that 48 sub-blocks can be processed in parallel. When a slave core array is used as a working group, a chip can be divided into 6 working groups, which means that 6 sub-blocks can be processed in parallel. This leads to a load balancing strategy. When the number of sub-tensors is greater than or equal to 48, a row of slave cores is used as a working group; when the number of sub-tensors is greater than or equal to 6 but less than 48, a slave core array is used as a working group. When the number of sub-tensors is less than 6, all slave cores in a chip are used as a working group.

[0043] After completing the work group division, multiple secondary-divided sub-tensors are still allocated to multiple work groups based on cyclic allocation.

[0044] Sub-tensor parallel reduction step S300: multiple computing processing units perform parallel reduction on multiple sub-tensors based on a recursive algorithm to obtain a reduced result tensor; Preferably, the sub-tensor parallel reduction step S300 includes: Multiple computing processing units perform recursive decomposition operations on the allocated sub-tensors in parallel until the dimension of the sub-tensor is no greater than a set threshold; a reduction operation is performed on the sub-tensors that reach the set threshold to obtain a reduced result tensor, and the reduced result tensor is recorded in a target storage location.

[0045] Figure 2 It is a schematic diagram of the recursive equivalence relationship of reducing high-dimensional tensors, such as Figure 2 As shown, in some embodiments, the computing processing unit performs parallel reduction on the divided sub-tensors, and the reduction problem can be solved by a recursive algorithm. Specifically, the n-dimensional tensor The specification problem can be recursively transformed into If the sub-tensor is a single element in all dimensions, it is returned directly. Otherwise, it is recursively performed until the dimension of the sub-tensor is less than or equal to the set threshold, usually 3 dimensions, and then these sub-tensors with dimensions less than 3 are merged through reduction operations.

[0046] In some embodiments, still taking the original tensor T of dimension [3, N, C, H, W] as an example, the dimension of the sub-tensor split_src_shape after splitting along the non-reduced dimension is [3, 1, S, H, W], where the 0th dimension is the reduced dimension. The reduction problem of the 5-dimensional tensor [3, 1, S, H, W] can be recursively transformed into the solution of the sub-problem of reducing 3 4-dimensional tensors [1, S, H, W].

[0047] Figure 3 It is a schematic diagram of parallel reduction of high-dimensional tensors, such as Figure 3As shown, in some embodiments, taking slave core No. 0 as an example, when performing reduction calculations, slave core No. 0 sequentially traverses the three 4-dimensional tensors obtained by split_src_shape transformation, and accumulates the reduction operations into local storage, the dimensions of which are [1, 1, S, H, W]. That is, in the reduction dimension, these elements will be accumulated into one result, and finally the obtained result will be written back to the corresponding target storage location. This design allows data segmentation and reduction to be processed simultaneously in one traversal, thereby improving the calculation efficiency.

[0048] Preferably, the sub-tensor parallel reduction step S300 further includes: Reduction index calculation steps: During the reduction process, the reduction index of each element in the reduction dimension is calculated in real time based on the source data offset and data stride, and the reduction result tensor and the corresponding reduction index are recorded in the target storage location.

[0049] The introduction of reduced index calculation not only returns the reduced result, but also returns the index of each element in the reduced dimension, providing richer information for subsequent data analysis and processing to achieve data tracking and traceability, which helps to better understand and optimize the algorithm, and also helps to locate potential errors and performance bottlenecks.

[0050] In some embodiments, the reduced index can be calculated by the source data offset offset and the data stride src_stride. The specific algorithm steps are as follows: Starting from the first dimension, loop until the reduced dimension (not included): calculate the data offset divided by the data stride offset / src_stride[i] of the current dimension to get the index on the current dimension i; multiply this index by the stride src_stride[i] of the current dimension to get the offset contributed by this dimension; subtract this offset from the data offset offset; finally, divide the remaining offset by the stride of the reduced dimension to get the index of the reduced dimension.

[0051] In some embodiments, assume that there is a 3D tensor (2, 3, 4), the reduced dimension is 1 (the middle dimension), the source data offset is 14, and the data stride src_stride is [12, 4, 1]. For the offset 14 (corresponding to the element [1, 0, 2]), the index on the reduced dimension 1 is calculated.

[0052] The index calculated on the current dimension 0 is 14 / 12. Multiply this index by the stride of the current dimension to get the offset contributed by this dimension (14 / 12)*12. Subtract this offset from the data offset to get the remaining offset of 14 - (14 / 12)*12 = 2. Finally, divide the remaining data offset offset by the stride of the reduced dimension to get the index of the reduced dimension of 2 / 4 = 0. Return 0, which correctly indicates the index on the reduced dimension (dimension 1).

[0053] The reduction result tensor is written back in step S400: the reduction result tensor is written back to the main memory.

[0054] Preferably, the step S400 of writing back the reduced result tensor includes: If a single sub-tensor is processed by a single computing processing unit, the first slave core of each computing processing unit writes the reduced result tensor back to the main memory; this avoids conflicts that may be caused by simultaneous writing by multiple slave cores, simplifies the write-back logic, and improves the write-back efficiency.

[0055] If a single sub-tensor is processed by multiple computing processing units, the multiple computing processing units involved in the processing of the sub-tensor are traversed in turn, and the first slave core of each computing processing unit writes the reduced result tensor back to the main memory, and performs a memory synchronization operation after each write-back. This ensures the orderliness of data write-back. At the same time, the memory synchronization operation is performed after each write-back to ensure data consistency, so that subsequent processing can accurately obtain the reduced result and avoid errors caused by data asynchrony.

[0056] The write-back strategy is dynamically adjusted according to the processing method of the sub-tensor, and it can flexibly deal with tensor reduction tasks of different scales and complexities. It is applicable to a variety of computing scenarios and improves the adaptability and robustness of the system. At the same time, it fully utilizes the parallel computing capabilities of the multi-core architecture and maximizes the advantages of parallel processing through reasonable task division and write-back coordination.

[0057] Embodiment 2: Figure 4 FIG. 1 is a schematic diagram of a parallel computing system structure of a tensor reduction in an embodiment of the present invention. Figure 4 As shown, the present invention provides a parallel computing method for tensor reduction, including a tensor segmentation module 100, a sub-tensor allocation module 200, a sub-tensor parallel reduction module 300 and a reduction result tensor write-back module 400.

[0058] Tensor segmentation module 100: dynamically segment the high-dimensional tensor based on the non-reduced dimension to obtain multiple sub-tensors. Specifically, the non-reduced segmentation dimension can be found based on the reduced high-dimensional tensor.

[0059] Sub-tensor allocation module 200: allocates multiple sub-tensors to multiple computing processing units based on the number of sub-tensors; the allocation strategy is dynamically adjusted according to the number of sub-tensors and the number of slave cores to ensure load balancing and efficient use of computing resources.

[0060] Sub-tensor parallel reduction module 300: multiple computing processing units perform parallel reduction on multiple sub-tensors based on a recursive algorithm to obtain a reduced result tensor.

[0061] The reduction result tensor write-back module 400 writes the reduction result tensor back to the main memory.

[0062] The tensor segmentation module 100 includes: Traverse all non-reduced dimensions from the last dimension of the high-dimensional tensor forward to the first dimension that satisfies the storage space requirement of the sub-tensor from this dimension to the last dimension is not less than the local memory capacity as the splitting dimension; Obtain the segmentation step size based on the segmentation dimension and the local memory capacity; Split the high-dimensional tensor into multiple tensors based on the split dimension and split step.

[0063] Embodiment three: Combination Figure 5 As shown, this embodiment discloses a specific implementation of a computer device. The computer device may include a processor 41 and a memory 42 storing computer program instructions.

[0064] Specifically, the processor 41 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0065] Among them, the memory 42 may include a large-capacity memory for data or instructions. By way of example and not limitation, the memory 42 may include a hard disk drive (HDD), a floppy disk drive, a solid-state drive (SSD), a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 42 may include a removable or non-removable (or fixed) medium. Where appropriate, the memory 42 may be inside or outside the data processing device. In a specific embodiment, the memory 42 is a non-volatile memory. In a specific embodiment, the memory 42 includes a read-only memory (ROM) and a random access memory (RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (Programmable Read-Only Memory, PROM for short), an erasable PROM (Erasable ProgrammableRead-Only Memory, EPROM for short), an electrically erasable PROM (Electrically Erasable ProgrammableRead-Only Memory, EEPROM for short), an electrically alterable ROM (Electrically Alterable Read-Only Memory, EAROM for short) or a flash memory (FLASH) or a combination of two or more of these. Under appropriate circumstances, the RAM can be a static random access memory (SRAM) or a dynamic random access memory (DRAM), wherein the DRAM can be a fast page mode dynamic random access memory (FPMDRAM), an extended data output dynamic random access memory (EDODRAM), a synchronous dynamic random access memory (SDRAM), etc.

[0066] The memory 42 may be used to store or cache various data files required for processing and / or communication, as well as possible computer program instructions executed by the processor 41 .

[0067] The processor 41 implements the parallel computing method of tensor reduction in the above embodiment by reading and executing computer program instructions stored in the memory 42 .

[0068] In some of the embodiments, the computer device may further include a communication interface 43 and a bus 40. Figure 5 As shown, the processor 41, the memory 42, the communication interface 43 and the bus 40 are connected and communicate with each other.

[0069] The communication interface 43 is used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0070] The communication interface 43 can also realize data communication with other components such as external devices, image / data acquisition equipment, databases, external storage, and image / data processing workstations.

[0071] The bus 40 includes hardware, software or both, and couples the components of the computer device to each other. The bus 40 includes but is not limited to at least one of the following: a data bus, an address bus, a control bus, an expansion bus, and a local bus. By way of example and not limitation, bus 40 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses or a combination of two or more of these. Where appropriate, bus 40 may include one or more buses. Although embodiments of the present application describe and illustrate a particular bus, the present application contemplates any suitable bus or interconnect.

[0072] In addition, in combination with the parallel computing method of tensor reduction in the above embodiments, the embodiment of the present application can provide a computer-readable storage medium for implementation. The computer-readable storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any of the parallel computing methods of tensor reduction in the above embodiments is implemented. The above description is only a preferred embodiment of the present invention and does not limit the present invention in other forms. Any technician familiar with the profession may use the technical content disclosed above to change or modify it into an equivalent embodiment with equivalent changes and apply it to other fields. However, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A parallel computing method for tensor reduction, characterized in that: include: Tensor segmentation step: dynamically segment the high-dimensional tensor based on the unreduced dimension to obtain multiple sub-tensors; A sub-tensor allocation step: allocating a plurality of the sub-tensors to a plurality of computing processing units based on the number of the sub-tensors; Sub-tensor parallel reduction step: multiple computing processing units perform parallel reduction on multiple sub-tensors based on a recursive algorithm to obtain a reduction result tensor; The reduction result tensor writing back step: writing the reduction result tensor back to the main memory.

2. The parallel computing method for tensor reduction according to claim 1, characterized in that: The tensor segmentation step comprises: Traverse all non-reduced dimensions from the last dimension of the high-dimensional tensor forward to the first dimension that satisfies the storage space requirement of the sub-tensor formed from the dimension to the last dimension is not less than the local memory capacity as the splitting dimension; Acquire a segmentation step length based on the segmentation dimension and the local memory capacity; The high-dimensional tensor is segmented based on the segmentation dimension and the segmentation step to obtain a plurality of sub-tensors.

3. The parallel computing method of tensor reduction according to claim 1, characterized in that: The sub-tensor allocation step comprises: If the number of the sub-tensors is greater than the total number of slave cores, allocating the plurality of sub-tensors to the plurality of slave cores based on a cyclic allocation; If the number of the sub-tensors is less than the total number of slave cores, the sub-tensors are split twice based on the reduced dimension, the slave cores are divided into work groups based on the number of sub-tensors after the second split, and the multiple sub-tensors after the second split are allocated to multiple work groups based on cyclic allocation.

4. The parallel computing method of tensor reduction according to claim 1, characterized in that: The sub-tensor parallel reduction step comprises: The plurality of computing processing units perform recursive decomposition operations on the allocated sub-tensors in parallel until the dimension of the sub-tensors is no greater than a set threshold; a reduction operation is performed on the sub-tensors that reach the set threshold to obtain a reduced result tensor, and the reduced result tensor is recorded in a target storage location.

5. The parallel computing method of tensor reduction according to claim 4, characterized in that: The sub-tensor parallel reduction step further includes: Reduction index calculation step: During the reduction process, the reduction index of each element in the reduction dimension is calculated in real time based on the source data offset and the data stride, and the reduction result tensor and the corresponding reduction index are recorded in the target storage location.

6. The parallel computing method of tensor reduction according to claim 1, characterized in that: The step of writing back the reduced result tensor includes: If a single sub-tensor is processed by a single computing processing unit, the first slave core of each computing processing unit writes the reduced result tensor back to the main memory; If a single sub-tensor is processed by multiple computing processing units, the multiple computing processing units involved in the processing of the sub-tensor are traversed in turn, and the first slave core of each computing processing unit writes the reduced result tensor back to the main memory, and performs a memory synchronization operation after each write back.

7. A tensor-reduced parallel computing system, characterized in that: A parallel computing method for tensor reduction applied to any one of claims 1 to 6, comprising: Tensor segmentation module: dynamically segment high-dimensional tensors based on non-reduced dimensions to obtain multiple sub-tensors; A sub-tensor allocation module: allocating a plurality of the sub-tensors to a plurality of computing processing units based on the number of the sub-tensors; Sub-tensor parallel reduction module: multiple computing processing units perform parallel reduction on multiple sub-tensors based on a recursive algorithm to obtain a reduction result tensor; The reduction result tensor write-back module writes the reduction result tensor back to the main memory.

8. The tensor-reduced parallel computing system according to claim 7, characterized in that: The tensor segmentation module comprises: Traverse all non-reduced dimensions from the last dimension of the high-dimensional tensor forward to the first dimension that satisfies the storage space requirement of the sub-tensor formed from the dimension to the last dimension is not less than the local memory capacity as the splitting dimension; Acquire a segmentation step length based on the segmentation dimension and the local memory capacity; The high-dimensional tensor is segmented based on the segmentation dimension and the segmentation step to obtain multiple tensors.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the parallel computing method for tensor reduction as claimed in any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the parallel computing method for tensor reduction as described in any one of claims 1 to 6 is implemented.

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