Low-voltage differential signal communication system and its driver

Abstract

This invention discloses a low-voltage differential signaling device and its driver. The driver includes an output circuit, a bias circuit, and a first clamping circuit. The output circuit includes a push-pull circuit and a first tail current source disposed between the power supply terminal and the push-pull circuit. The bias circuit has a bias current generating unit that provides a first bias current. The first clamping circuit provides a second bias current to the bias circuit. When the enable signal is at a first level, the bias circuit provides a first preset bias voltage to the first tail current source according to the sum of the first bias current and the second bias current, and the driver is in a normal state. When the enable signal is at a second level, the bias circuit provides a second preset bias voltage to the first tail current source according to the second bias current, and the driver is in a high-impedance state. The second preset value is less than the voltage value at the power supply terminal and greater than the first preset value, thereby improving the enable speed when the output state of the LVDS driver switches from a high-impedance state to a normal state.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-voltage differential signal communication system and its driver. Background Technology

[0002] LVDS (Low Voltage Differential Signaling) is a point-to-point high-speed differential electrical interface designed for applications requiring ultra-low power consumption, low noise, and high data rates. Its core lies in using low voltage swing for high-speed differential data transmission, enabling LVDS technology to achieve low power consumption and improved interference immunity while ensuring data transmission quality.

[0003] LVDS technology offers flexible transmission media, including copper PCB (Printed Circuit Board) traces and balanced cables, making it widely applicable in various electronic devices. Because LVDS uses differential signal transmission—transmitting differential signals using a pair of signal lines—it effectively suppresses common-mode noise and other types of interference, significantly improving the signal-to-noise ratio and reducing the bit error rate. LVDS devices typically consist of an LVDS driver and a receiver. The main function of the LVDS driver is to convert the input single-ended signal into a low-swing differential signal and output it.

[0004] MLVDS (Multi-Point Low Voltage Differential Signaling) possesses all the advantages of LVDS technology and can be applied to multi-point bus systems. An LVDS communication system using MLVDS technology includes multiple LVDS drivers. Typically, at least two LVDS drivers exist on the same cable. Therefore, these LVDS drivers need to have output enable functionality to ensure that only the selected LVDS driver is outputting a signal on the same cable at any given time, while the unselected LVDS driver outputs a high-impedance state (Hi-z).

[0005] Figure 1 The timing diagram for the alternating output signals of two LVDS drivers is shown. See also... Figure 1 If two LVDS drivers in an LVDS communication system use the same cable to transmit signals alternately, when one of the LVDS drivers switches from being unselected to being selected, it needs to be woken up from the high-impedance state Hi-z. Therefore, it takes a period of time (T1) for the driver to be enabled before it can stably output the correct signal. This will limit the operating frequency of the LVDS communication system.

[0006] Therefore, a new low-voltage differential signal communication system and its driver are needed to solve the above problems. Summary of the Invention

[0007] In view of the above problems, the purpose of this invention is to provide a low-voltage differential signal communication system and its driver, thereby improving the enable speed of the low-voltage differential signal driver when the output switches from a high-impedance state to a normal state.

[0008] According to one aspect of the present invention, a low-voltage differential signal driver is provided, the driver having two output states: a high-impedance state and a normal state. The driver includes an output circuit, a bias circuit, and a first clamping circuit. The output circuit includes a push-pull circuit and a first tail current source disposed between a power supply terminal and the push-pull circuit. The push-pull circuit is used to generate a first output signal and a second output signal based on a first input signal and a second input signal. The bias circuit is used to provide a bias voltage to the first tail current source, and the bias circuit has a bias current generating unit for providing a first bias current. The first clamping circuit is connected to the bias circuit and is used to provide a second bias current to the bias circuit. Bias current; wherein the opening and closing of the bias current generating unit is controlled by an enable signal. When the enable signal is at a first level, the bias current generating unit is turned on, so that the bias circuit provides a first preset bias voltage to the first tail current source according to the sum of the first bias current and the second bias current, and the driver is in a normal state; when the enable signal is at a second level, the bias current generating unit is turned off, so that the bias circuit provides a second preset bias voltage to the first tail current source according to the second bias current, and the driver is in a high-impedance state; the second preset value is less than the voltage value at the power supply terminal and greater than the first preset value.

[0009] Optionally, the output circuit further includes a second tail current source disposed between the push-pull circuit and the ground terminal, and the driver further includes: a common-mode feedback circuit for comparing the common-mode feedback voltage of the first output signal and the second output signal with a reference voltage, so as to provide a bias voltage to the second tail current source according to the comparison result; and a second clamping circuit connected to the common-mode feedback circuit for providing a third preset bias voltage to the second tail current source when the enable signal is at the second level, wherein the third preset value is greater than the voltage value of the ground terminal and less than the range of the bias voltage provided by the common-mode feedback circuit when the driver is in normal state.

[0010] Optionally, the bias circuit includes the bias current generating unit and the second transistor. The bias current generating unit includes a first current source, a first switch, a second switch, a first transistor, and a third transistor. The first current source, the first switch, and the first transistor are sequentially connected between a power supply terminal and a ground terminal. The control terminal of the first switch receives an enable signal, and the control terminal of the first transistor is connected to its first terminal. The second switch is connected between the control terminal of the first transistor and the ground terminal, and its control terminal receives the inverted signal of the enable signal. The second transistor and the third transistor are sequentially connected between a power supply terminal and a ground terminal. The control terminal of the second transistor provides a bias voltage to the first current source, and the control terminal of the second transistor is connected to its second terminal. The control terminal of the third transistor is connected to the control terminal of the first transistor.

[0011] Optionally, the first clamping circuit includes a second current source and a fourth transistor, which are connected sequentially between the power supply terminal and the ground terminal. The control terminal of the fourth transistor is connected to its first terminal, and the second current source provides a second bias current. A fifth transistor is connected between the intermediate node of the second transistor and the third transistor and the ground terminal. The control terminal of the fifth transistor is connected to the intermediate node of the second current source and the fourth transistor, and the first terminal of the fifth transistor provides a fourth bias current.

[0012] Optionally, the current value of the first bias current is greater than the current value of the second bias current.

[0013] Optionally, the common-mode feedback circuit includes a first resistor and a second resistor, which are connected sequentially between the positive differential output terminal and the negative differential output terminal. The positive differential output terminal provides the first output signal, and the negative differential output terminal provides the second output signal. The error amplifier has its positive input terminal connected to the midpoint between the first resistor and the second resistor, its negative input terminal receiving a reference voltage, and its output terminal providing the second bias voltage to the second tail current source. The midpoint between the first resistor and the second resistor provides the common-mode feedback voltage.

[0014] Optionally, the second clamping circuit includes a third current source and a sixth transistor, which are connected sequentially between the power supply terminal and the ground terminal. The third current source provides a fifth bias current, and the control terminal of the sixth transistor is connected to its first terminal. A third switch is connected between the control terminal of the sixth transistor and the output terminal of the error amplifier, and the control terminal of the third switch receives the inverted signal of the enable signal.

[0015] Optionally, the first tail current source includes a seventh transistor, and the second tail current source includes an eighth transistor.

[0016] Optionally, the first tail current source includes a seventh transistor, the second tail current source includes an eighth transistor, and the push-pull circuit includes a ninth to a twelfth transistor. The seventh, ninth, tenth, and eighth transistors are sequentially connected between the power supply terminal and the ground terminal. The control terminal of the seventh transistor receives the first bias voltage, the control terminals of the ninth and tenth transistors receive the first input signal, the control terminal of the eighth transistor receives the second bias voltage, the intermediate node of the ninth and tenth transistors is the negative differential output terminal, and the eleventh and twelfth transistors are sequentially connected between the intermediate node of the seventh and ninth transistors and the intermediate node of the tenth and eighth transistors. The control terminals of the eleventh and twelfth transistors receive the second input signal, and the intermediate node of the eleventh and twelfth transistors is the positive differential output terminal.

[0017] According to another aspect of the present invention, a low-voltage differential signal communication system is provided, comprising at least one set of low-voltage differential signal transmission lines, wherein one end of each set of low-voltage differential signal transmission lines is connected to a low-voltage differential signal receiver, and the other end is connected to at least two low-voltage differential signal drivers as described above.

[0018] The LVDS communication system and driver provided by this invention have two output states: a high-impedance state and a normal state. When the output is in the high-impedance state, the voltage value of the first bias voltage is slightly higher than that in the normal state but lower than the voltage value at the power supply terminal. This reduces the discharge time of the first gate parasitic capacitance when the output state of the LVDS driver switches from the high-impedance state to the normal state, allowing the first bias voltage to quickly recover to the voltage value in the normal state. This improves the enable speed of the LVDS driver when switching from the high-impedance state to the normal state and reduces the operating frequency limitation of the LVDS communication system using the LVDS driver described above.

[0019] In a preferred embodiment, when the LVDS driver is in a high-impedance output state, the voltage value of the second bias voltage is close to the voltage range of the second bias voltage in the normal state and greater than the ground voltage. This reduces the charging time of the second gate parasitic capacitance when the output state of the LVDS driver switches from a high-impedance state to a normal state, allowing the second bias voltage to quickly recover to the voltage value in the normal state. This further improves the enable speed when the output state of the LVDS driver switches from a high-impedance state to a normal state and further reduces the operating frequency limitation of the LVDS communication system using the LVDS driver described above. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0021] Figure 1 The timing diagram of the alternating output signals of the two LVDS drivers is shown;

[0022] Figure 2 A circuit diagram of an LVDS driver is shown;

[0023] Figure 3 A circuit diagram of an LVDS driver according to an embodiment of the present invention is shown;

[0024] Figure 4 An LVDS driver according to an embodiment of the present invention is shown. Figure 2 The diagram shows a comparison of the timing parameters of the LVDS driver. Detailed Implementation

[0025] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0026] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0027] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0028] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0029] Figure 2 A circuit diagram of an LVDS driver is shown. See also Figure 2 The LVDS driver 100 includes a bias circuit, an output circuit, and a common-mode feedback circuit.

[0030] Specifically, the bias circuit includes a current source I1, transistors M1-M3, and switches S1-S3. Transistors M1 and M2 form a current mirror. The current source I1, switches S1, and transistor M1 are sequentially connected between the power supply voltage VDD and the ground terminal. Transistors M3 and M2 are sequentially connected between the power supply voltage VDD and the ground terminal. The control terminal of transistor M1 is connected to its first terminal and the control terminal of transistor M2. Switch S2 is also connected between the control terminal of transistor M1 and the ground terminal. Switch S3 is connected between the first and second terminals of transistor M3. The control terminal of transistor M3 is connected to its second terminal. The control terminal of switch S1 receives the enable signal EN, and the control terminals of switches S2 and S3 receive the enable signal ENB. The enable signals EN and ENB are inverted.

[0031] The output circuit includes transistors M4-M9. Transistors M4 and M3 form a current mirror. Transistors M4, M6, M8, and M5 are connected sequentially between the power supply voltage VDD and ground. Transistors M7 and M9 are connected sequentially between the intermediate nodes of transistors M4 and M6 and the intermediate nodes of transistors M8 and M5. The control terminal of transistor M4 is connected to the control terminal of transistor M3. The control terminals of transistors M6 and M8 receive the input signal Vin1, and the control terminals of transistors M7 and M9 receive the input signal Vin2. The intermediate node of transistors M7 and M9 serves as a positive differential output terminal, providing the output signal Vout+, and the intermediate node of transistors M6 and M8 serves as a negative differential output terminal, providing the output signal Vout-. The input signals Vin1 and Vin2 are inverted.

[0032] The common-mode feedback circuit includes resistors R1 and R2 and an error amplifier 110. Resistors R1 and R2 are connected sequentially between the positive differential output terminal and the negative differential output terminal. The positive input terminal of the error amplifier 110 is connected to the intermediate node of resistors R1 and R2, the negative input terminal receives the reference voltage Vref, and the output terminal is connected to the control terminal of transistor M5.

[0033] Furthermore, the positive and negative differential outputs of the LVDS driver 100 are also connected to the LVDS receiver. The LVDS receiver includes a resistor Rt, capacitors CL1 and CL2. The resistor Rt is connected between the positive and negative differential outputs, capacitor CL1 is connected between the positive differential output and ground, and capacitor CL2 is connected between the negative differential output and ground. The current flowing through the resistor Rt is the drive current Iout.

[0034] When the enable signal EN is high, the bias circuit turns on switch S1 and turns off switches S2 and S3. Transistor M2 provides bias current to transistor M3, supplying a bias voltage Vbp1 at the control terminal of transistor M3 equal to VDD - |Vgs3| (Vgs3 represents the voltage difference between the gate and source terminals of transistor M3). This turns on transistor M4, allowing it to provide tail current Is, thus enabling the output circuit to generate output signals Vout+ and Vout- normally. When the enable signal EN is low, the bias circuit turns off switch S1 and turns on switches S2 and S3, turning off transistors M2 and M3 to completely cut off the bias current path. In this case, the bias voltage Vbp1 is equal to the power supply voltage VDD, and transistor M4 is turned off. When the enable signal EN is high, the common-mode feedback circuit generates a bias voltage Vbn1 based on the comparison between the common-mode feedback voltage of output signals Vout+ and Vout- and the reference voltage Vref, stabilizing the common-mode feedback voltage near the reference voltage Vref. The common-mode feedback circuit also turns off transistor M5 when the enable signal EN is low. At this time, the bias voltage Vbn1 is equal to the ground voltage GND.

[0035] To meet the requirements of output swing and operating frequency, the tail current Is provided by transistor M4, which serves as the output current source, needs to be large, typically 3.5mA. Therefore, transistor M4 has a large aspect ratio, resulting in a large gate parasitic capacitance Cp1. This gate parasitic capacitance Cp1 causes the bias circuit to require a long time during the enable process to discharge the bias voltage Vbp1 (the control terminal voltage of transistor M4) from the power supply voltage VDD to the required potential VDD-|Vgs3|, significantly delaying the enable time of the LVDS driver 100. Furthermore, transistor M5, which also serves as a current source, has a gate parasitic capacitance Cp2. This gate parasitic capacitance Cp2 causes the common-mode feedback circuit to require a long time during the enable process to charge the bias voltage Vbn1 from the ground voltage GND to the required potential, thus extending the settling time of the common-mode feedback loop and increasing the required enable time of the LVDS driver 100.

[0036] To address the aforementioned problems, this invention provides a novel LVDS driver.

[0037] Figure 3 A circuit diagram of an LVDS driver according to an embodiment of the present invention is shown.

[0038] See Figure 3 The LVDS driver 200 provided in this embodiment of the invention has two output states: a high-impedance state and a normal state. The LVDS driver 200 includes an output circuit 210, a bias circuit 220, a first clamping circuit 230, a common-mode feedback circuit 240, and a second clamping circuit 250.

[0039] The output circuit 210 includes a first tail current source, a push-pull circuit, and a second tail current source connected sequentially between the power supply terminal and the ground terminal. The first tail current source generates a first tail current Is based on the bias voltage Vbp2, and the second tail current source generates a second tail current based on the bias voltage Vbn2. The push-pull circuit generates output signals Vout+ and Vout- based on the input signals Vin1 and Vin2. Specifically, when the LVDS driver 200 is in normal operation, the input signals Vin1 and Vin2 are inverted signals, and the output signals Vout+ and Vout- are differential output signals.

[0040] The bias circuit 220 provides a bias voltage Vbp2 to the first tail current source. The bias circuit 220 has a bias current generating unit for providing a bias current I4. A first clamping circuit 230 is connected to the bias circuit 220 and provides a bias current I5 to the bias circuit 220. An enable signal EN controls the on / off state of the bias current generating unit. When the enable signal EN is at a first level, the bias current generating unit is on, causing the bias circuit 220 to provide a first preset bias voltage Vbp2 to the first tail current source based on the sum of the bias currents I4 and I5, and the LVDS driver 200 is in a normal state. When the enable signal EN is at a second level, the bias current generating unit is off, causing the bias circuit 220 to provide a second preset bias voltage Vbp2 to the first tail current source based on the bias current I5, and the LVDS driver 200 is in a high-impedance state. The second preset value is less than the power supply voltage VDD and greater than the first preset value.

[0041] The common-mode feedback circuit 240 is used to compare the common-mode feedback voltages of the output signals Vout+ and Vout- with the reference voltage Vref when the LVDS driver 200 is in normal state, so as to provide a bias voltage Vbn2 to the second tail current source according to the comparison result, so as to adjust the output signals Vout+ and Vout- through the bias voltage Vbn2, so that the common-mode feedback voltages of the output signals Vout+ and Vout- are stabilized near the reference voltage Vref.

[0042] The second clamping circuit 250 is connected to the common-mode feedback circuit 240 and is used to provide a third preset bias voltage Vbn2 to the second tail current source when the enable signal EN is at the second level. The third preset value is greater than the voltage at the ground terminal and less than the range of the bias voltage Vbn2 provided by the common-mode feedback circuit 240 when the LVDS driver 200 is in normal operation.

[0043] The push-pull circuit includes transistors M6-M9. The first tail current source is implemented, for example, using transistor M4, and the second tail current source is implemented, for example, using transistor M5. Transistors M3 and M4 form a current mirror with a mirror ratio of 1:M. For example, M > 10. Transistors M4, M6, M8, and M5 are connected sequentially between the power supply terminal and the ground terminal. Transistors M7 and M9 are connected sequentially between the intermediate nodes of transistors M4 and M6 and the intermediate nodes of transistors M8 and M5. The control terminal of transistor M4 is connected to the control terminal of transistor M3. The control terminal of transistor M5 receives the bias voltage Vbn2. The control terminals of transistors M6 and M8 receive the input signal Vin1. The control terminals of transistors M7 and M9 receive the input signal Vin2. The intermediate node of transistors M7 and M9 serves as a positive differential output terminal, providing the output signal Vout+, and the intermediate node of transistors M6 and M8 serves as a negative differential output terminal, providing the output signal Vout-.

[0044] The bias circuit 220 also includes transistor M2. The bias current generating unit includes current source I1, transistors M1 and M3, and switches S1-S2. Transistors M1 and M2 form a current mirror, and current source I1 provides the bias current I1. Current source I1, switch S1, and transistor M1 are sequentially connected between the power supply terminal and the ground terminal. Transistors M3 and M2 are sequentially connected between the power supply terminal and the ground terminal. The control terminal of transistor M1 is connected to its first terminal and the control terminal of transistor M2. The control terminal of transistor M3 is connected to its first terminal, and the control terminal of transistor M3 provides a bias voltage Vbp2 to the first tail current source. Switch S2 is also connected between the control terminal of transistor M1 and the ground terminal. The control terminal of switch S1 receives an enable signal EN, and the control terminal of switch S2 receives an enable signal ENB. The second terminal of transistor M2 provides the bias current I4. In this context, the enable signal ENB is out of phase with the enable signal EN, and I4 = k1 * I1 (k1 > 0). k1 is equal to the mirror ratio of the current mirror formed by transistors M2 and M1. For example, k1 = 1.

[0045] The first clamping circuit 230 includes transistors M10-M11 and a current source I2, which provides a bias current I2. Current source I2 and transistor M11 are connected sequentially between the power supply terminal and the ground terminal. Transistor M10 is connected between the intermediate node of transistors M3 and M2 and the ground terminal. The control terminal of transistor M10 is connected to the intermediate node between current source I2 and transistor M11. The control terminal of transistor M11 is connected to its first terminal, which provides a bias current I5. Where I5 ​​= k2 * I2 (k2 > 0), for example, k2 = 1.

[0046] Optionally, the bias current I4 can be much larger than the bias current I5. For example, the bias current I4 can be set to be about ten times the bias current I5. By setting the current values ​​of I5 and I4 to I5 < I4, the LVDS driver 200 will not generate significant power consumption even in a high-impedance state.

[0047] When the LVDS driver 200 is in a high-impedance state, the second terminal of transistor M3 receives a bias current I5. At this time, the bias voltage Vbp2 is equal to the first preset value, namely VDD-|Vgs3_a| (Vgs3_a represents the voltage difference between the gate and source terminals of transistor M3 under the influence of the bias current I5). When the LVDS driver 200 is in a normal state, the second terminal of transistor M3 receives bias currents I4 and I5. At this time, the bias voltage Vbp2 is equal to the second preset value, namely VDD-|Vgs3_b| (Vgs3_b represents the voltage difference between the gate and source terminals of transistor M3 under the influence of the sum of bias currents I4 and I5).

[0048] The common-mode feedback circuit 240 includes resistors R1 and R2 and an error amplifier 231. Resistors R1 and R2 are connected sequentially between the positive differential output terminal and the negative differential output terminal. The positive input terminal of the error amplifier 231 is connected to the intermediate node of resistors R1 and R2, the negative input terminal receives the reference voltage Vref, and the output terminal provides a bias voltage Vbn2 to the second tail current source.

[0049] The second clamping circuit 250 includes a current source I3 and a transistor M12 connected sequentially between the power supply terminal VDD and the ground terminal. The current source I3 provides a bias current I3. The control terminal of the transistor M12 is connected to its first terminal. A switch S3 is also connected between the control terminal of the transistor M12 and the output terminal of the error amplifier 231. The control terminal of the switch S3 receives an enable signal ENB. The third preset value is equal to Vgs12 (Vgs12 represents the voltage difference between the gate and source terminals of the transistor M12 under the influence of the bias current I3).

[0050] The working principle of LVDS driver 200 is as follows: When the enable signal EN is at the second level, LVDS driver 200 is in a high-impedance state, switch S2 is turned on, and transistor M2 is turned off. At this time, although the bias current I4 supplied to transistor M3 is turned off, the bias current I5 supplied to transistor M3 is not turned off, but flows to ground through transistor M10. Therefore, the bias voltage Vbp2 is not pulled up to the voltage value VDD at the power supply terminal, but is pulled to VDD-|Vgs3_a| by the bias current I5 flowing through transistor M10, and is held by the gate parasitic capacitance Cp1 of transistor M4. At the same time, switch S3 is turned on, clamping the voltage value of bias voltage Vbn2 at Vgs12, and is held by the gate parasitic capacitance Cp2 of transistor M5. When the enable signal EN switches from the second level to the first level, transistors M1 and M2 are turned on. The bias voltage Vbp2 is quickly pulled down to VDD-|Vgs3_b| by the bias current I4 flowing through transistor M2. The tail current Is of transistor M4 is stabilized to a preset value (e.g., 3.5mA). The output of the LVDS driver 200 stabilizes in a normal state. At the same time, switch S3 is turned off, and the bias voltage Vbn2 is provided by the error amplifier 231. The common-mode feedback loop quickly stabilizes. For example, the first level is high and the second level is low.

[0051] Figure 4 An LVDS driver and an embodiment of the present invention are shown. Figure 2 The diagram shows a comparison of the timing parameters of the LVDS driver.

[0052] See Figure 4 When the enable signal EN switches from low to high, indicating that the output state of the LVDS driver needs to switch from a high-impedance state to a normal state, the bias voltage Vbp2 of the LVDS driver 200 provided in this application reaches the second voltage value within the first time T3, and Figure 2 The bias voltage Vbp1 provided by the LVDS driver 100 shown reaches the second voltage value within the second time T2. It can be seen from the figure that the first time T3 is much smaller than the second time T2. Therefore, the LVDS driver 200 provided in this application enables the output state to switch from the high impedance state to the normal state faster.

[0053] Optionally, transistors M3-M4 and M6-M7 are P-channel metal-oxide-semiconductor field-effect transistors (PMOS transistors), and transistors M1-M2, M5, and M8-M12 are N-channel metal-oxide-semiconductor field-effect transistors (NMOS transistors). The first terminal of a PMOS transistor is the source terminal, the second terminal is the drain terminal, and the control terminal is the gate terminal. The first terminal of an NMOS transistor is the drain terminal, the second terminal is the source terminal, and the control terminal is the gate terminal.

[0054] The LVDS driver 200 provided in this embodiment of the invention has two output states: a high-impedance state and a normal state. In the high-impedance output state, the bias voltage Vbp2 is set slightly higher than the bias voltage Vbp2 in the normal state but lower than the power supply voltage VDD. The bias voltage Vbn2 is set close to the range of the bias voltage Vbn2 in the normal state and higher than the ground voltage GND. This reduces the discharge time of the gate parasitic capacitance Cp1 when the output state of the LVDS driver 200 switches from the high-impedance state to the normal state, allowing the bias voltage Vbp2 to quickly recover to its normal state value. It also reduces the charging time of the gate parasitic capacitance Cp2, allowing the bias voltage Vnp2 to quickly recover to its normal state value. This improves the enable speed of the LVDS driver 200 when switching from the high-impedance state to the normal state and reduces the operating frequency limitation of the LVDS communication system using the LVDS driver 200.

[0055] Furthermore, the present invention also provides an LVDS communication system, which includes at least one set of low-voltage differential signal transmission lines. One end of each set of low-voltage differential signal transmission lines is connected to an LVDS receiver, and the other end is connected to at least two LVDS drivers 200. Each set of low-voltage differential signal transmission lines includes two transmission lines for transmitting output signals Vout+ and Vout- respectively. The LVDS receiver can, for example, employ a... Figure 2 The LVDS receiver shown is shown.

[0056] When a set of low-voltage differential signal transmission lines is transmitting signals, at least one of the two LVDS drivers 200 is in a normal state, while the others are in a high-impedance state. When an LVDS driver 200 is in a high-impedance state, its connection with the low-voltage differential signal transmission line is broken, and transistors M6-M9 are turned off by the voltage at their control terminals, so that the push-pull circuit has no signal output.

[0057] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A low-voltage differential signal driver, the driver having two output states: a high-impedance state and a normal state, the driver comprising an output circuit, a bias circuit, and a first clamping circuit; The output circuit includes a push-pull circuit and a first tail current source disposed between the power supply terminal and the push-pull circuit. The push-pull circuit is used to generate a first output signal and a second output signal based on a first input signal and a second input signal. The bias circuit is used to provide a bias voltage to the first tail current source, and the bias circuit has a bias current generating unit for providing a first bias current. The first clamping circuit is connected to the bias circuit and is used to provide a second bias current to the bias circuit; The bias current generating unit is controlled by an enable signal. When the enable signal is at a first level, the bias current generating unit is turned on, causing the bias circuit to provide a first preset bias voltage to the first tail current source based on the sum of the first bias current and the second bias current, and the driver is in a normal state. When the enable signal is at a second level, the bias current generating unit is turned off, causing the bias circuit to provide a second preset bias voltage to the first tail current source based on the second bias current, and the driver is in a high-impedance state. The second preset value is less than the voltage value at the power supply terminal and greater than the first preset value.

2. The driver according to claim 1, wherein the output circuit further comprises a second tail current source disposed between the push-pull circuit and the ground terminal, and the driver further comprises: A common-mode feedback circuit is used to compare the common-mode feedback voltage of the first output signal and the second output signal with a reference voltage, so as to provide a bias voltage to the second tail current source according to the comparison result; The second clamping circuit, connected to the common-mode feedback circuit, is used to provide a third preset bias voltage to the second tail current source when the enable signal is at the second level. The third preset value is greater than the voltage value at the ground terminal and less than the range of the bias voltage provided by the common-mode feedback circuit when the driver is in normal state.

3. The driver according to claim 1, wherein, The bias circuit includes the bias current generating unit and the second transistor. The bias current generating unit includes a first current source, a first switch, a second switch, a first transistor, and a third transistor. The first current source, the first switch, and the first transistor are connected sequentially between the power supply terminal and the ground terminal. The control terminal of the first switch receives an enable signal, and the control terminal of the first transistor is connected to its first terminal. The second switch is connected between the control terminal and the ground terminal of the first transistor, and its control terminal receives the inverted signal of the enable signal; The second transistor and the third transistor are connected sequentially between the power supply terminal and the ground terminal. The control terminal of the second transistor provides a bias voltage to the first tail current source. The control terminal of the second transistor is connected to its second terminal. The control terminal of the third transistor is connected to the control terminal of the first transistor.

4. The driver according to claim 3, wherein, The first clamping circuit includes: The second current source and the fourth transistor are connected sequentially between the power supply terminal and the ground terminal, and the control terminal of the fourth transistor is connected to its first terminal. The fifth transistor is connected between the intermediate node of the second transistor and the third transistor and the ground terminal, and the control terminal of the fifth transistor is connected to the intermediate node of the second current source and the fourth transistor.

5. The driver according to claim 1, wherein, The value of the first bias current is greater than the value of the second bias current.

6. The driver according to claim 2, wherein, The common-mode feedback circuit includes: A first resistor and a second resistor are connected sequentially between the positive differential output terminal and the negative differential output terminal. The positive differential output terminal provides the first output signal, and the negative differential output terminal provides the second output signal. The error amplifier has its positive input terminal connected to the midpoint between the first resistor and the second resistor, its negative input terminal receiving a reference voltage, and its output terminal providing a bias voltage to the second tail current source. The midpoint between the first resistor and the second resistor provides the common-mode feedback voltage.

7. The driver according to claim 6, wherein, The second clamping circuit includes: The third current source and the sixth transistor are connected sequentially between the power supply terminal and the ground terminal, and the control terminal of the sixth transistor is connected to its first terminal. The third switch is connected between the control terminal of the sixth transistor and the output terminal of the error amplifier. The control terminal of the third switch receives the inverted signal of the enable signal.

8. The driver according to claim 6, wherein, The first tail current source includes a seventh transistor, and the second tail current source includes an eighth transistor.

9. The driver according to claim 8, wherein, The push-pull circuit includes transistors nine through twelfth. The seventh, ninth, tenth, and eighth transistors are sequentially connected between the power supply terminal and the ground terminal. The control terminals of the ninth and tenth transistors receive the first input signal, and the intermediate node between the ninth and tenth transistors is the negative differential output terminal. The eleventh and twelfth transistors are connected sequentially between the intermediate node of the seventh and ninth transistors and the intermediate node of the tenth and eighth transistors. The control terminals of the eleventh and twelfth transistors receive the second input signal, and the intermediate node of the eleventh and twelfth transistors is the positive differential output terminal.

10. A low-voltage differential signal communication system, comprising: At least one set of low-voltage differential signal transmission lines, One end of each set of low-voltage differential signal transmission lines is connected to a low-voltage differential signal receiver, and the other end is connected to at least two low-voltage differential signal drivers as described in any one of claims 1-9.

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