Data processing method, data processing device and data transmission system

Abstract

At least one embodiment of the invention provides a data processing method, a data processing device and a data transmission system. The data processing method comprises the steps that coding operation is carried out based on original data to generate N independent error correction code words, each error correction code word in the N independent error correction code words comprises a data code and a check code, and N is an integer and is larger than or equal to 2; data codes and check codes included in the N independent error correction code words are interleaved to obtain interleaved data; and sending the interleaved data. According to the data processing method, the complexity of coding, decoding and error correction can be effectively reduced, the corresponding coding, decoding and error correction time is shortened, and the data transmission delay is reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data processing method, a data processing device, and a data transmission system. Background Art

[0002] In modern communication systems, the reliability of data transmission is crucial to ensure the integrity of information. However, during data transmission, channel noise and interference often lead to errors. To solve this problem, error correction coding technology is widely used in data transmission. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a data processing method, comprising: performing an encoding operation based on original data to generate N independent error correction codewords, each of the N independent error correction codewords includes a data code and a check code, N is an integer and N≥2; interleaving the data code and the check code included in the N independent error correction codewords to obtain interleaved data; and sending the interleaved data.

[0004] At least one embodiment of the present disclosure provides a data processing method, comprising: receiving interleaved data to obtain a read-back data code and a read-back error correction code, wherein the interleaved data is generated based on an encoding operation on original data to generate N independent error correction codewords, and the data code and the check code included in the N independent error correction codewords are interleaved to obtain them, each of the N independent error correction codewords includes a data code and a check code, N is an integer and N≥2; deinterleaving the read-back data code and the read-back error correction code to obtain N independent read-back error correction codewords; and decoding and error correction operations are performed on the N independent read-back error correction codewords.

[0005] At least one embodiment of the present disclosure provides a data processing device, including: an error correction codeword generation unit, configured to perform encoding operations based on original data to generate N independent error correction codewords, each of the N independent error correction codewords includes a data code and a check code, N is an integer and N≥2; an interleaving unit, configured to interleave the data code and the check code included in the N independent error correction codewords to obtain interleaved data; and a sending unit, configured to send the interleaved data to a data receiving end.

[0006] At least one embodiment of the present disclosure provides a data processing device, including: a receiving unit, configured to receive interleaved data to obtain a read-back data code and a read-back error correction code, wherein the interleaved data is generated based on an encoding operation on original data to generate N independent error correction codewords, and the data code and the check code included in the N independent error correction codewords are interleaved to obtain, each of the N independent error correction codewords includes a data code and a check code, N is an integer and N≥2; a deinterleaving unit, configured to deinterleave the read-back data code and the read-back error correction code to obtain N independent read-back error correction codewords; and a decoding and error correction unit, configured to perform decoding and error correction operations on the N independent read-back error correction codewords.

[0007] At least one embodiment of the present disclosure provides a data transmission system, comprising: any one of the data processing devices described above.

[0008] At least one embodiment of the present disclosure provides an electronic device, including: at least one processor; and at least one memory storing instructions, wherein when the instructions are executed by the processor, the processor executes the data processing method as described above.

[0009] At least one embodiment of the present disclosure provides a computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by a processor, the processor executes the data processing method as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure are briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0011] Figure 1 A schematic diagram of an exemplary end-to-end serial link system is shown;

[0012] Figure 2 A flowchart of a data processing method according to at least one embodiment of the present disclosure is shown;

[0013] Figure 3 A flowchart of a data processing method according to at least one embodiment of the present disclosure is shown;

[0014] Figure 4 A schematic diagram showing a data processing device according to at least one embodiment of the present disclosure;

[0015] Figure 5 A schematic diagram showing a data processing device according to at least one embodiment of the present disclosure;

[0016] Figure 6A schematic diagram showing a data transmission system according to at least one embodiment of the present disclosure is shown;

[0017] Figure 7 A schematic diagram showing a decoding error correction process according to at least one embodiment of the present disclosure is shown;

[0018] Figure 8 A block diagram showing a companion calculation according to at least one embodiment of the present disclosure;

[0019] Fig. 9 A block diagram showing key equations according to at least one embodiment of the present disclosure;

[0020] Fig.10 A schematic diagram of a money search circuit according to at least one embodiment of the present disclosure is shown;

[0021] Fig.11 A schematic diagram of a four-way interleaving structure according to at least one embodiment of the present disclosure is shown;

[0022] Fig.12 A schematic diagram of a four-way deinterleaving structure according to at least one embodiment of the present disclosure is shown;

[0023] Fig.13 A diagram of a four-way interleaved data structure according to at least one embodiment of the present disclosure is shown;

[0024] Fig.14 A schematic diagram showing an electronic device according to at least one embodiment of the present disclosure;

[0025] Fig.15 A schematic diagram showing a computer-readable storage medium according to at least one embodiment of the present disclosure; and

[0026] Fig.16 A schematic diagram of another electronic device according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. On the contrary, it is intended to cover changes, modifications and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0028] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0029] Note that the examples to be introduced below are only specific examples, and are not intended to limit the embodiments of the present disclosure to the specific shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct more embodiments not mentioned in the present description by reading the present description.

[0030] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0031] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0032] First, the abbreviations and related terms involved in this application are defined and explained.

[0033] ECC (Error Correction Code): Error correction code or error correction coding refers to a coding technology that can implement error checking and correction, which can improve the reliability of the system.

[0034] CE (Correctable Error): Correctable error.

[0035] UE (Uncorrectable Error): Uncorrectable error.

[0036] Symbol is also called code element: the smallest unit of ECC error correction, usually with x4 and x8 particles, and the corresponding symbol is 4 bits and 8 bits of data.

[0037] SERDES (Serializer / Deserializer): A digital communication interface technology used to convert parallel data into serial data and serial data into parallel data. It plays an important role in high-speed communication systems.

[0038] Forward Error Correction (FEC): A method for detecting and correcting errors in data transmission. It uses redundant bits to store check information when encoding data. When an error occurs during data transmission, the error location can be determined and corrected through the check information.

[0039] Link equalization: A technique used to eliminate distortion and noise in signal transmission.

[0040] RS (Reed-Solomon) coding algorithm: an error correction coding algorithm, which is a non-binary block code and is commonly used for error correction in data transmission and storage. Its basic principle is to encode the original data at the sending end, generate a certain amount of redundant data, and transmit it together with the original data. After receiving the data, the receiving end uses the redundant data for error decoding and error correction. If a correctable error occurs in the data, the receiving end can use the information in the redundant data to correct it without resending the data.

[0041] Interleaving: Bit errors in communications often occur in clusters. Channel coding is only effective in detecting and correcting single errors and not too long error clusters. When the length of the burst error exceeds the error correction capability of FEC, FEC cannot effectively reduce the bit error rate and packet loss rate. Interleaving is a technology used to reduce the impact of burst errors on the system. It divides the original data into four independent data streams and arranges these data streams alternately in a new data stream to enhance data reliability. In this way, long burst errors will be broken up into several short burst errors, which will then be corrected by several FECs respectively, thereby improving system performance.

[0042] Bit Error Rate: An indicator used to evaluate the bit error rate in digital communication systems. It indicates the proportion of errors in the bits received by the receiver during the transmission of digital signals.

[0043] Feed forward equalizer (FFE): It can be divided into pre-emphasis (Pre-Emphasis) and de-emphasis (De-Emphasis). The two methods are similar. Both change the high and low frequency components at the transmit (TX) end. The difference is that pre-emphasis increases the high frequency component, and de-emphasis reduces the low frequency component. After equalization at the TX end, the signal quality can be improved.

[0044] Continuous time linear equalizer (CTLE): An amplifier circuit with a frequency response curve that amplifies high-frequency signals and attenuates low-frequency signals to compensate for channel insertion loss.

[0045] Decision Feedback Equalizer (DFE): A digital signal processing technique used to recover digital signals that have been interfered with and distorted by the channel. DFE is usually placed after CTLE in the circuit. The implementation of DFE is similar to that of FFE.

[0046] Packet loss rate: refers to the probability that the error exceeds the error correction capability of FEC and the entire packet will be lost. After the packet is lost, the receiving end will request retransmission.

[0047] It is understandable that the terms defined above are merely exemplary definitions in specific application scenarios to facilitate a better understanding of the present application, and the embodiments of the present disclosure are not limited thereto.

[0048] As the signal rate increases, the signal quality will deteriorate in two ways. On the one hand, the impact of inherent jitter becomes more serious due to the shorter clock cycle. On the other hand, the rate increase makes the channel loss larger and the inter-symbol interference becomes more serious. Generally, this weakness can be improved through high-frequency signal compensation and equalization technology.

[0049] The role of equalization is to process the signal at the receiving port. According to the attenuation characteristics of the substrate through which the signal passes, the high-frequency components of the signal are appropriately enhanced. In this way, the low-frequency and high-frequency components can be "equalized" to a certain level, thereby enhancing the transmission speed and distance of the signal sent to the receiving port.

[0050] Equalization can be divided into transmitter equalization and receiver equalization. Transmitter equalization is called Emphasis or FFE.

[0051] There are two types of receiver equalization: CTLE and DFE. DFE can assist CTLE in improving signal quality. In addition, DFE can make adaptive adjustments in real time according to the eye diagram. It can be used to compensate for changes in links and chips (such as CTLE) caused by changes in temperature or other conditions, and increase system stability.

[0052] Figure 1 A schematic diagram of an exemplary end-to-end serial link system is shown.

[0053] See also Figure 1 At the data transmission end, the data can be encoded by the FEC encoder to generate encoded data. The encoded data can be converted into an analog signal by modulation (MOD). The analog signal can be changed into high and low frequency components by FFE, and then can be sent through the channel.

[0054] At the data receiving end, the received analog signal may be improved via CTLE and DFE, and then the analog signal may be converted back into a digital signal via demodulation (DeMOD) and the data signal may be decoded via an FEC decoder to obtain the original data.

[0055] In actual use, the eye diagram after CTLE and DFE equalization requires the cooperation of FFE, CTLE and DFE, especially when the link conditions are relatively complex. At this time, it is no longer possible to open the eye diagram by simply relying on FFE or CTLE and DFE. At this time, FFE+CTLE+DFE need to be used in cooperation with each other so that the eye diagram can be fully opened at the sampling point of the receiving end to ensure that the target bit error rate is achieved.

[0056] An exemplary FEC algorithm in high-speed protocol transmission is the RS (544, 514) algorithm, which can use 514 10-bit data symbols and 30 10-bit ECC symbols to correct errors in any 15 of the 10-bit symbols. The error correction process is extremely complex, because in order to find the positions of the 15 error symbols, it is necessary to iteratively solve 15 equations, which requires more area (for example, the area of ​​the circuit to implement the corresponding solution) and delay, but the error correction capability is stronger.

[0057] Another FEC algorithm is the RS (272, 258) algorithm, which can use 258 10-bit data symbols and 14 10-bit ECC symbols to correct errors in any 7 symbols. Compared with the RS (544, 514) algorithm, the coding and error correction involved in the RS (272, 258) algorithm are simpler, and the error correction module only needs to solve the 7-order equation, so it requires less computing resources. The RS (272, 258) algorithm is particularly suitable for processing small-scale data blocks due to its simple algorithm and fast processing speed, but its error correction capability is slightly weaker.

[0058] The market demand for high-speed information transmission is getting stronger and stronger. The higher the data transmission rate, the greater the challenge to the signal integrity of the serial link. In order to ensure the low cost of the overall link, the channel material is usually not changed, but the link architecture is improved and developed, which poses a severe challenge to the equalization technology and FEC of ultra-high-speed serial links.

[0059] The inventors of the present disclosure realize that the traditional RS (544, 514) has a large delay, but has the advantages of high code rate and strong ability to correct random errors. However, at the same time, it also puts forward higher requirements for the modulation of link equalization. On the one hand, the link equalizer must ensure that the bit error rate (BER) is lower than the basic requirement of the protocol for BER. On the other hand, the equalization ability of the equalizer cannot be too strong. On the contrary, too strong equalization ability will lead to an increase in the retransmission rate of the system and a decrease in bandwidth efficiency. Because too strong equalization ability will bring a stronger DFE coefficient, and DFE, as a nonlinear equalizer, will determine the level of the current signal based on the past judgment results. If the DFE coefficient is too large, that is, the weight given to the past signal is too large, it is possible to make an incorrect judgment on the current signal, and the error of the current signal will affect the next signal, and the error may be continuously propagated. RS (544, 514) is the FEC specified by the Ethernet protocol. It was designed for random errors from the beginning. If the errors are continuous, then on the one hand, the upper limit of the error correction capability (i.e., 5 10-bit symbols) can easily be occupied by the continuous errors caused by a large number of DFE erroneous decisions; on the other hand, the complex algorithm of RS (544, 514) is useless because the error is very likely to occur in the next symbol, so there is no need to correct "arbitrary" (random) errors.

[0060] In addition, although RS (272, 258) cannot handle the environment with the same bad BER well, because its ability to correct random errors is worse than RS (544, 514), the link can use stronger equalization capabilities to reduce the BER of the input FEC, so the number of random errors is reduced. However, the cost is that the coefficient of DFE becomes larger, and a random error may cause DFE to make an incorrect judgment, so that the random error is followed by a series of continuous errors caused by DFE. However, this continuous error can be well handled by the interleaving structure of RS (272, 258), so it is more suitable for high-speed links.

[0061] In addition, when link modulation and equalization capabilities are being tested, the FEC module at the end of the link is rarely considered. FEC is always turned on after the FFE coefficient at the TX end is determined, which can lead to reduced system performance (i.e., the FFE coefficient is determined based only on the eye diagram). Because for the entire system, the wider the eye diagram is, the better it is. There is an "optimal point". Once the link's equalization capability exceeds this optimal point, the link's retransmission rate will increase and the system performance will decrease. Therefore, the link training must be considered in terms of the comprehensive FEC capability. In order to maximize the performance of RS (544, 514), it is required to reduce the FFE coefficient at the TX end of the link. However, due to the lack of joint modeling of equalization and FEC, it is difficult to find the optimal FFE coefficient for the link, which places high demands on modulation technology.

[0062] As can be seen above, future high-speed links will need to deal with increasingly greater line losses, and the combined use of equalization technology and FEC technology will be a huge challenge.

[0063] Therefore, at least one embodiment of the present disclosure proposes a low-delay interleaved error correction structure that takes into account both random errors and burst errors, and is also friendly to link training. For example, at least one embodiment of the present disclosure proposes a low-delay RS (272, 258) multi-path interleaved error correction structure, where the reason for selecting RS (272, 258) is that it is well compatible with the original RS (544, 514) encoding and packaging method. Of course, the embodiments of the present disclosure are not limited to this, and other algorithms can be used.

[0064] At least one embodiment of the present disclosure provides a data processing method, a data processing device, a data transmission system, an electronic device and a computer-readable storage medium, which can effectively reduce the complexity of encoding and error correction, reduce the corresponding encoding and error correction time, and reduce data transmission delay.

[0065] Figure 2 FIG. 2 is a flow chart of a data processing method 200 according to at least one embodiment of the present disclosure. Figure 2 The described data processing method 200 and its additional aspects can be found below. Figure 4 The data processing method 200 is implemented in the data processing device 400, electronic device, hardware structure, software structure, or hardware structure and software structure described. In some embodiments, the data processing method 200 can be executed in a data sending end (eg, a data sending device).

[0066] See also Figure 2 , the data processing method 200 includes steps S210 to S230.

[0067] In step S210, an encoding operation is performed based on the original data to generate N independent error correction codewords, wherein each of the N independent error correction codewords includes a data code and a check code, and N is an integer and N≥2.

[0068] Raw data can be any data to be sent from a sender to a receiver.

[0069] In step S220, the data codes and check codes included in the N independent error correction code words are interleaved to obtain interleaved data.

[0070] In step S230, the interleaved data is sent.

[0071] As described above, according to the data processing method 200 of at least one embodiment of the present disclosure, multiple independent error correction codewords of the original data can be obtained, and each independent error correction codeword can be interleaved and sent, thereby enabling decoding and error correction operations to be performed on each independent error correction codeword, effectively reducing the complexity of encoding and error correction, reducing the corresponding encoding and error correction time, and reducing data transmission delay.

[0072] Some exemplary additional aspects of the data processing method 200 according to at least one embodiment of the present disclosure are described below.

[0073] For example, according to the data processing method of at least one embodiment of the present disclosure, N independent error correction codewords can be transmitted through multiple data lanes, and interleaving the data codes and check codes included in the N independent error correction codewords can include: arranging the N independent error correction codewords alternately in a new data stream, so that consecutive M symbols on each data lane in the multiple data lanes belong to different error correction codewords among the N independent error correction codewords, where M is an integer and 2≤M≤N.

[0074] In some examples, M=2, N=4, so that two consecutive symbols on each data path belong to different error correction codewords among four independent error correction codewords. Of course, the embodiments of the present disclosure are not limited thereto, and M and N may also be other values.

[0075] In this way, the data processing method according to at least one embodiment of the present disclosure can avoid error correction codewords from several consecutive symbols on each data path, thereby effectively avoiding exceeding the upper limit of the error correction capability of the corresponding algorithm due to continuous errors, for example, it can effectively deal with burst errors on the same data path.

[0076] For example, according to the data processing method of at least one embodiment of the present disclosure, M=N.

[0077] In some examples, M=4, N=4, so that four consecutive symbols on each data path belong to different error correction codewords in four independent error correction codewords. Of course, the embodiments of the present disclosure are not limited thereto, and M and N may also be other values.

[0078] In this way, the data processing method according to at least one embodiment of the present disclosure can further separate the symbols on each data path, so as to more effectively avoid exceeding the upper limit of the error correction capability of the corresponding algorithm due to continuous errors, for example, it can better and more effectively deal with burst errors on the same data path.

[0079] For example, the data processing method according to at least one embodiment of the present disclosure may also include: arranging the N independent error correction codewords alternately in a new data stream so that corresponding symbols on adjacent data paths in multiple data paths belong to different error correction codewords among the N independent error correction codewords.

[0080] In this way, the data processing method according to at least one embodiment of the present disclosure can avoid crosstalk on adjacent data paths.

[0081] For example, according to the data processing method of at least one embodiment of the present disclosure, performing encoding operations based on original data to generate N independent error correction codewords may include: dividing the original data into N independent sub-data as data codes; independently performing encoding operations on the N independent sub-data to obtain an error correction code for each of the N independent sub-data as a check code.

[0082] In this way, the data processing method according to at least one embodiment of the present disclosure can independently generate multiple error correction codewords for original data, thereby improving the efficiency of generating error correction codewords and reducing the complexity of the algorithm used to generate error correction codewords.

[0083] For example, according to the data processing method of at least one embodiment of the present disclosure, dividing the original data into N independent sub-data may include: randomly dividing the original data into N independent sub-data.

[0084] Thus, compared with fixedly dividing the original data into N independent sub-data, the data processing method according to at least one embodiment of the present disclosure can improve the error correction capability from a probabilistic level and can be applicable to more common error scenarios.

[0085] For example, the high 128B and low 128B of the 256B original data are fixedly divided into two independent sub-data, and the error correction probability of correcting two errors in each of the two sub-data is In contrast, the error correction probability of randomly dividing the 256B original data into 4 64B sub-data (instead of fixed high 128B and low 128B), and correcting 2 errors in each of the 4 sub-data is Here n is the number of symbols. In some examples, a symbol may be, for example, 1B (8 bits) or other number of bits.

[0086] For another example, in actual applications, since errors may occur randomly, in the above example, multiple errors occur in the fixed partition, for example, in the upper 128B, and cannot be corrected. In contrast, the data processing method according to at least one embodiment of the present disclosure is relatively flexible, and thus can be applied to more general application scenarios.

[0087] For example, according to the data processing method of at least one embodiment of the present disclosure, randomly dividing the original data into N independent sub-data may include: randomly dividing the original data into N independent sub-data of equal size.

[0088] In this way, the data processing method according to at least one embodiment of the present disclosure can adopt the same N encoding and / or decoding and error correction methods, which simplifies the design of the corresponding data transmission system.

[0089] For example, according to the data processing method of at least one embodiment of the present disclosure, N=4.

[0090] In this way, the data processing method according to at least one embodiment of the present disclosure can adopt four-way interleaving, so as to cope with various application scenarios.

[0091] For example, according to the data processing method of at least one embodiment of the present disclosure, the encoding operation may adopt the RS (272, 258) algorithm.

[0092] In this way, the data processing method according to at least one embodiment of the present disclosure can reduce delay and / or increase code rate compared to the RS (544, 514) algorithm.

[0093] For example, compared with the RS (544, 514) algorithm, the encoding operation and / or the subsequent decoding and error correction operation calculations using the RS (272, 258) algorithm have fewer iterations, which can reduce delay.

[0094] For another example, compared to the RS (544, 514) algorithm, which can have 5140 bits of data in every 5440 bits, the RS (272, 258) algorithm can have 5160 bits of data in every 5440 bits, and thus has a higher code rate.

[0095] For example, according to the data processing method of at least one embodiment of the present disclosure, the interleaved data can be sent via a high-speed link, and the high-speed link supports that the interleaved data can be sent in the form of at least one of a level signal and an optical signal.

[0096] As such, the data processing method according to at least one embodiment of the present disclosure may be applicable to sending and receiving data through a level signal, sending and receiving data through an optical signal, or sending and receiving data through a level signal and an optical signal.

[0097] Figure 3 FIG. 3 is a flow chart showing a data processing method 300 according to at least one embodiment of the present disclosure. Figure 3 The described data processing method 300 and its additional aspects can be found below. Figure 5The data processing method 300 is implemented in the data processing device 500, electronic device, hardware structure, software structure, or hardware structure and software structure described. In some embodiments, the data processing method 300 can be executed in a data receiving end (eg, a data receiving device).

[0098] See also Figure 3 , the data processing method 300 includes steps S310 to S330.

[0099] In step S310, the interleaved data is received to obtain a read-back data code and a read-back error correction code. The interleaved data is obtained by generating N independent error correction code words based on encoding the original data, and interleaving the data code and the check code included in the N independent error correction code words, each of the N independent error correction code words includes a data code and a check code, N is an integer and N≥2.

[0100] In step S320, the read-back data code and the read-back error correction code are deinterleaved to obtain N independent read-back error correction code words.

[0101] In step S330, decoding and error correction operations are performed on the N independent read-back error correction codewords.

[0102] As described above, the data processing method 300 according to at least one embodiment of the present disclosure can be used for example to process the data transmitted through the above-mentioned reference Figure 2 The interleaved data described is deinterleaved to obtain independent read-back error correction codewords, and the independent read-back error correction codewords can be decoded and corrected. Thus, decoding and error correction operations can be performed on each independent error correction codeword, effectively reducing the complexity of encoding and error correction, reducing the corresponding encoding and error correction time, and reducing data transmission delay.

[0103] Some exemplary additional aspects of the data processing method 300 according to at least one embodiment of the present disclosure are described below.

[0104] For example, according to the data processing method of at least one embodiment of the present disclosure, decoding and correcting N independent readback error correction codewords may include: independently decoding and correcting each of the N independent readback error correction codewords.

[0105] In this way, the data processing method according to at least one embodiment of the present disclosure can independently perform decoding and error correction operations on each independent read-back error correction codeword, thereby improving the efficiency of decoding and error correction and reducing the complexity of the algorithms used for decoding and error correction.

[0106] In other additional aspects, Figure 2 The described data processing method 200 and its additional aspects may also be applied to Figure 3The data processing method 300 described herein and its corresponding technical effects can also be mapped to Figure 3 Additional aspects of the described data processing method 300 are not described in detail here.

[0107] Corresponding to the data processing method 200 according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a data processing device. For example, the data processing device may be a data sending device.

[0108] Figure 4 FIG. 4 is a schematic diagram of a data processing device 400 according to at least one embodiment of the present disclosure.

[0109] See also Figure 4 , the data processing device 400 includes an error correction codeword generating unit 410, an interleaving unit 420 and a sending unit 430.

[0110] The error correction codeword generation unit 410 is configured to perform encoding operations based on the original data to generate N independent error correction codewords, wherein each of the N independent error correction codewords includes a data code and a check code, and N is an integer and N≥2.

[0111] The interleaving unit 420 is configured to interleave the data codes and check codes included in the N independent error correction codewords to obtain interleaved data.

[0112] The sending unit 430 is configured to send the interleaved data to a data receiving end.

[0113] As described above, the data processing device 400 according to at least one embodiment of the present disclosure can obtain multiple independent error correction codewords of the original data, and each independent error correction codeword can be interleaved and sent, thereby enabling decoding and error correction operations to be performed on each independent error correction codeword, effectively reducing the complexity of encoding and error correction, reducing the corresponding encoding and error correction time, and reducing data transmission delay.

[0114] The above-mentioned additional aspects of the data processing device 400 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the data processing method 200 according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the data processing method 200 according to at least one embodiment of the present disclosure can also be mapped to the additional aspects of the data processing device 400 according to at least one embodiment of the present disclosure, which will not be repeated here.

[0115] Corresponding to the data processing method 300 according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a data processing device. For example, the data processing device may be a data receiving device.

[0116] Figure 5FIG. 5 is a schematic diagram of a data processing device 500 according to at least one embodiment of the present disclosure.

[0117] See also Figure 5 , the data processing device 500 includes a receiving unit 510, a de-interleaving unit 520 and a decoding and error correction unit 530.

[0118] The receiving unit 510 is configured to receive the interleaved data to obtain the read-back data code and the read-back error correction code. The interleaved data is generated based on the encoding operation of the original data to generate N independent error correction code words, and the data code and the check code included in the N independent error correction code words are interleaved to obtain each error correction code word in the N independent error correction code words. Each error correction code word includes a data code and a check code, and N is an integer and N≥2.

[0119] The de-interleaving unit 520 is configured to de-interleave the read-back data code and the read-back error correction code to obtain N independent read-back error correction code words.

[0120] The decoding and error correction unit 530 is configured to perform decoding and error correction operations on N independent read-back error correction codewords.

[0121] As described above, the data processing device 500 according to at least one embodiment of the present disclosure may process, for example, Figure 2 The interleaved data described is deinterleaved to obtain independent read-back error correction codewords, and the independent read-back error correction codewords can be decoded and corrected. Thus, decoding and error correction operations can be performed on each independent error correction codeword, effectively reducing the complexity of encoding and error correction, reducing the corresponding encoding and error correction time, and reducing data transmission delay.

[0122] The above-mentioned additional aspects of the data processing device 500 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the data processing method 300 according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the data processing method 300 according to at least one embodiment of the present disclosure can also be mapped to the additional aspects of the data processing device 500 according to at least one embodiment of the present disclosure, which will not be repeated here.

[0123] Figure 6 FIG. 6 is a schematic diagram of a data transmission system 600 according to at least one embodiment of the present disclosure. Figure 6 As shown, the data transmission system 600 may include the Figure 4 The data processing apparatus 400 (and its additional aspects) described herein and see Figure 5 The data processing apparatus 500 (and its additional aspects) described herein. Figure 4 The data processing apparatus 400 (and its additional aspects) described herein and see Figure 5The described data processing apparatus 500 (and its additional aspects) may be mapped to the Figure 6 The data transmission system 600 described above will not be described in detail here.

[0124] The following describes the above combination with an example application scenario. Figures 2 to 6 It is understood that the example application scenarios described below are only examples and not limitations, and are intended to implement the above combination in specific application scenarios. Figures 2 to 6 One or more aspects described or only described to achieve the above combination Figures 2 to 6 Examples of one or more aspects described above, and the various aspects described below in conjunction with the example application scenarios can be combined with the above Figures 2 to 6 One or more aspects of the description may be combined.

[0125] This example application scenario describes a low-latency RS (272, 258) multi-path interleaved error correction structure, but the embodiment is of course not limited thereto. In other aspects, multi-path interleaved error correction structures involving other algorithms or other multi-path interleaved error correction structures of the same algorithm may be provided.

[0126] The error correction structure exemplarily mainly includes the following modules and processes: RS encoder, decoder, syndrome calculation module, key equation calculation module, money search module, multi-path interleaving module and process, decoding and error correction process. The above modules and processes will be explained in detail below.

[0127] The RS encoder is described below. For example, the RS encoder can implement one or more aspects of the above encoding operations.

[0128] The coding principle of the RS code is to add a certain redundancy according to a certain coding rule so that the data that originally had no correlation becomes correlated. For example, in this example application scenario, a division-based encoder can be used.

[0129] The exemplary flow of division-based encoding is divided into the following three steps:

[0130] (1) Pre-multiply the information polynomial m(x) by x n-k , that is, shift right by nk positions to get x n-k m(x);

[0131] (2) x n-k Dividing m(x) by the generating polynomial g(x) yields the remainder r(x), where g(x) determines the unique RS(n, k) code;

[0132] (3) By x n-k m(x)+r(x)=c(x), that is, the encoded codeword polynomial is obtained.

[0133] Of course, the embodiment is not limited thereto. For example, a matrix multiplication or other algorithm encoder may be used.

[0134] The decoding and error correction process is described below. For example, the decoding and error correction process can implement one or more aspects of the above-mentioned decoding and error correction operations.

[0135] The decoding principle is to use the data correlation generated by redundancy to correct errors occurring in the channel and restore the transmitted code sequence.

[0136] Figure 7 A schematic diagram of a decoding error correction process according to at least one embodiment of the present disclosure is shown.

[0137] See also Figure 7 , the exemplary decoding error correction process is divided into the following five steps:

[0138] (1) In block 702, syndrome calculation is performed, for example, syndrome S is obtained from the received polynomial. j ;

[0139] (2) In block 704, establish the key equation, for example, according to the syndrome S j , using, for example, the BM algorithm to solve the key equations and obtain the error polynomial and the error value polynomial;

[0140] (3) In block 706, the error position is calculated, for example, by substituting all possible error positions into the key equation and using, for example, a Chien search algorithm to solve the root of the error polynomial to obtain the error position;

[0141] (4) In block 708, calculating an error value, for example, using a Forney algorithm to calculate the error value;

[0142] (5) Subsequently, error correction can be performed based on the error position and error value to complete the error correction.

[0143] exist Figure 7 In the embodiment, the controller+frame buffer 710 can be used to control the calculation of corresponding data in each of the blocks 702-708 and cache the data and / or calculation results required for the corresponding calculation.

[0144] Of course, the embodiment is not limited thereto. For example, other algorithms may be used to implement the above decoding error correction process or other decoding error correction processes may be used.

[0145] The following description see Figure 7 More detailed exemplary aspects of the decoding error correction process are described.

[0146] First, the syndrome calculation is described.

[0147] The syndrome of RS (272, 258) code can be set as formula (1):

[0148]

[0149] in,

[0150] In practice, Horner's algorithm can be used to calculate S j , as follows formula (2):

[0151]

[0152] Substituting n=272 and b=1 into formula (2), we get:

[0153]

[0154] For example, in engineering design, pipelined hardware can be used to implement companion calculations.

[0155] Figure 8 A block diagram of a companion calculation according to at least one embodiment of the present disclosure is shown.

[0156] See also Figure 8 ,in, represents finite field multiplication, Represents finite field addition. When performing companion calculation, the module is first initialized, and then R1, R2, ..., R 271 Shift into the shift register. The 14 syndromes can be calculated after 272 clock cycles. If the syndrome coefficients are all 0, it means that all the received codewords are correct and the number of errors is 0; otherwise, the number of errors is greater than 0.

[0157] Next, the key equations are described below.

[0158] When all 14 syndromes are solved, the error position polynomial can be solved by, for example, an improved BM algorithm. Because the earliest proposed BM algorithm requires the use of finite field element inversion operations, this algorithm requires finite field division operations in each iteration, and the finite field element inversion operations / finite field division operations are very complex, and their complexity makes this algorithm unsuitable for high-speed implementation. Therefore, the exemplary improved algorithm process is as follows:

[0159] (1) Initialization: Λ( 0 )(x)=1,T( 0 )(x)=1,L( 0 )(x)=0,γ( 0 )(x)=1, k=0;

[0160] (2) The following steps are repeated from equation (4) to equation (7) until the loop ends when k = 2t-1.

[0161]

[0162] Λ (k-1) (x) = γ (k) Λ (k) (x)-Δ (k-1) T (k) (x)x (5);

[0163] When Δ (k-1) =0 or 2L (k) >k,

[0164] T (k-1) (x) = xT (k) (x), L (k+1) =L (k) , γ (k+1) =γ (k) (6);

[0165] Otherwise, when Δ (k-1) ≠0 or 2L (k) When ≤k,

[0166] T (k-1) (x) = Λ (k) (x), L (k-1) =k+1-L (k) , γ (k+1) =Δ (k-1) (7);

[0167] k=k+1.

[0168] where Λ (k-1) (x) is the error location polynomial.

[0169] In formula (4), Δ is the convolution operation of Λ(x) and S(x). In order to realize pipeline processing, for example, finite impulse response (FIR) filter technology can be used to realize pipeline processing, such as Fig. 9 shown.

[0170] Fig. 9 A block diagram illustrating key equations according to at least one embodiment of the present disclosure is shown.

[0171] See also Fig. 9 , when initialized, all registers (D) are set to 0 and then, as the rising edge of each clock arrives, S1, S2, ..., S 14 By shifting into the shift register, the coefficients of the error position polynomial Λ(x) can be finally obtained.

[0172] Then, the money search is described below.

[0173] After the error value polynomial is obtained from the key equation, in order to simplify the calculation, the Qian search method is used to find the root of the error value polynomial. The exemplary method is as follows:

[0174] set up:

[0175] R(x)=r 271 x 271 +r 270 x 270 +…+t1x+r0 (8);

[0176] To check the first r n-1 Is it wrong? Need to determine α n-1 Is it the number of wrong positions, that is, check α -(n-1) Is it a root of σ(x). If α -(n-1) =α is the root of σ(x), then:

[0177] σ(α -(n-1) )=σ(x)=1+σ1α+σ2α+…+σ t α t =0 (9);

[0178] Or: σ1α+σ2α+…+σ t α t =-1.

[0179] From this we can infer that α n-1 An error occurred on the bit. By analogy, we can get:

[0180] If σ1(α)+σ2(α)+…+σ t (α) t =-1, then α 271 There is a mistake in the position;

[0181] If σ1(α 2 )+σ2(α 2 )+…+σ t (α 2 )t=-1, then α 270 There is a mistake in the position;

[0182] …………………………………………

[0183] If σ1(α i )+σ2(α i )+…+σ t (α i ) t =-1, then α 271-i There is a mistake in the position;

[0184] If σ1(α n)+σ2(α n )+…+σ t (α n )t=-1, then α 0 There is a mistake in the position;

[0185] where α n-i x n-i Bit.

[0186] Therefore, for each α n-i (i = 1, 2, ..., n) to test, the root of the error value polynomial is obtained, and the error position δ(a i The error value when )=0 is:

[0187]

[0188] Fig.10 A schematic diagram of a money search circuit according to at least one embodiment of the present disclosure is shown. In an exemplary application scenario, the money search circuit can be used to implement error location search and error correction, and the exemplary process is as follows:

[0189] (1) t registers store σ0, σ1, σ2, ... σ t , when the actual number of errors in the output data of the register system channel v<t, then σ v+1 =σ v+2 =…=σ t =0.

[0190] (2)r n-1 Just before reading from the cache memory, t multipliers are controlled by shift pulses to perform multiplication operations and store the following values ​​in registers: σ0α, σ2a 2 ,…,σ t a t , and accumulate these values. If the value is -1, the control gate is opened and the error value and the buffer output r are added. n-1 Subtract, C n-1 Complete the pair n-1 Error correction.

[0191] (3)r n-1 After decoding, multiplication is performed again, and σ1a 2 ,σ2(a 2 ) 2 ,σ t (a t ) 2 Stored in register σ, and added and tested, r n-2 The remaining code elements (symbols) are corrected in the same way as (2).

[0192] It can be understood that the above describes an exemplary embodiment of the decoding error correction process. However, the embodiment is not limited thereto. For example, the decoding error correction process can be implemented by matrix operations or other algorithms.

[0193] The interleaved error correction structure is described below. For example, one or more exemplary aspects of the above data processing method can be implemented in the interleaved error correction structure.

[0194] The interleaved error correction structure is a coding technique for correcting data errors and resolving delays. It divides the original data into several independent data streams and arranges these data streams alternately in a new data stream to enhance the reliability of the data. In this error correction structure, each data stream can use error correction coding to correct and detect errors.

[0195] Fig.11 Schematic diagram of a four-way interleaving structure according to at least one embodiment of the present disclosure is shown. Fig.11 The described four-way interleaving structure may be used in one or more exemplary aspects of the data transmitting end or the data processing device 400 .

[0196] See also Fig.11 , the input data can be divided into 4 sub-data. The input data here can correspond to the original data described above, for example.

[0197] On the one hand, the four sub-data can be transmitted to the data interleaving module to perform an interleaving operation on the sub-data. On the other hand, the four sub-data can be input into four encoders for independent encoding to generate corresponding error correction codes. For example, the first sub-data of the four sub-data can be input into encoder 0 for encoding to generate an error correction code for the first sub-data, the second sub-data of the four sub-data can be input into encoder 1 for encoding to generate an error correction code for the second sub-data, the third sub-data of the four sub-data can be input into encoder 2 for encoding to generate an error correction code for the third sub-data, and the fourth sub-data of the four sub-data can be input into encoder 3 for encoding to generate an error correction code for the fourth sub-data.

[0198] After the respective error correction codes of the four sub-data are obtained, the error correction codes may be transmitted to an ECC interleaving module to perform an interleaving operation on the error correction codes.

[0199] In the above embodiment, 4 independent ECC words, i.e., 4 sub-data and their corresponding error correction codes, can be obtained, and the sub-data and the error correction codes can be interleaved. Of course, the embodiment is not limited thereto. In some embodiments, 4 independent ECC words can also be directly obtained by an encoder and the sub-data and the error correction codes in the 4 independent ECC words can be interleaved.

[0200] After the above interleaving operation, interleaved data can be obtained. Subsequently, the interleaved data can be transmitted (TX) via a channel or link.

[0201] Fig.12 4 shows a schematic diagram of a four-way deinterleaving structure according to at least one embodiment of the present disclosure. Fig.12 The described four-way de-interleaving structure may be used in one or more exemplary aspects of the data receiving end or the data processing device 500 .

[0202] See also Fig.12 , the interleaved data can be received (RX) via, for example, a channel or link, thereby obtaining the read-back data and the read-back error correction code. The interleaved data here can be referred to as Fig.11 Various aspects of the description generate interleaved data.

[0203] The read-back data and the read-back error correction code can be respectively passed through the data de-interleaving module and the error correction code de-interleaving module to obtain 4 independent read-back error correction code words (for example, corresponding to Fig.11 4 independent ECC words in the .

[0204] Subsequently, the four independent read-back error correction codewords can be transmitted to the decoder and the error correction module for decoding and error correction operations to obtain corrected data. For example, the four independent read-back error correction codewords can be respectively decoded and corrected by their own decoders and error correction modules. Exemplarily, the first read-back error correction codeword of the four independent read-back error correction codewords can be decoded and corrected by decoder 0 and error correction module 0, the second read-back error correction codeword of the four independent read-back error correction codewords can be decoded and corrected by decoder 1 and error correction module 1, the third read-back error correction codeword of the four independent read-back error correction codewords can be decoded and corrected by decoder 2 and error correction module 2, and the fourth read-back error correction codeword of the four independent read-back error correction codewords can be decoded and corrected by decoder 3 and error correction module 3.

[0205] Fig.13 FIG. 4 shows a four-way interleaved data structure diagram according to at least one embodiment of the present disclosure. Fig.13 The described four-way interleaved data structure may be, for example, a four-way interleaved data structure applicable to the RS (272, 258) algorithm. Of course, the embodiment is not limited thereto. For example, the four-way interleaved data structure may also be used for other algorithms. For another example, for different algorithms, interleaved data structures of other numbers may also be used.

[0206] See also Fig.13 , 4 independent error correction code words can be transmitted through 16 data paths (ie, Lanes in the figure). Of course, other numbers of data paths can be used according to different needs and / or different data transmission protocols.

[0207] See also Fig.13 , the four consecutive symbols on each data path may belong to different FEC ECC words, for example. In this case, it can be ensured that consecutive errors on the same data path can be dispersed into different FECs. For example, Fig.13 Each small block in can represent a 10-bit symbol, and the data in these 10-bit symbols all belong to the 10-bit data transmitted continuously on the same data path. Fig.13 In the data path 0, symbols of the same grayscale belong to the same FECECC word. For example, on data path 0, symbols 0, 16, 32, and 48 from top to bottom come from the first ECC word, the second ECC word, the third ECC word, and the fourth ECC word of four different ECC words, respectively; similarly, symbols 64, 80, 96, and 112 can come from the first ECC word, the second ECC word, and the third ECC word of four different ECC words, respectively, and so on. Other data paths can have the same or similar data structure as data path 0. In this way, symbols of different ECC words are arranged in an interleaved manner.

[0208] For example, combined with Fig.13 , assuming a continuous error from Fig.13 The transmission starts from the symbol numbered 18 in the ECC word, and only introduces one symbol error to each ECC word through symbols 34, 50 and 66, which can be easily corrected. For example, when the RS (272, 258) algorithm is used, the four-way interleaved error correction structure can correct any 7 such consecutive errors, thus greatly improving the bandwidth efficiency of the system.

[0209] For additional information, see Fig.13 , corresponding symbols on adjacent data paths in the plurality of data paths belong to different error correction codewords among the four independent error correction codewords. For example, symbol 0 on data path 0 and symbol 1 on data path 1 belong to different error correction codewords among the four independent error correction codewords, and symbol 16 on data path 0 and symbol 17 on data path 1 belong to different error correction codewords among the four independent error correction codewords.

[0210] Fig.13 It shows that four consecutive symbols on each data path in a plurality of data paths can belong to different ECC words, and at the same time, corresponding symbols on adjacent data paths in a plurality of data paths belong to different error correction code words in four independent error correction code words. For example, see Fig.13, the symbols from top to bottom on each data path (i.e. corresponding to each column) are sequentially from the first ECC word, the second ECC word, the third ECC word in four different ECC words, and so on; the corresponding symbols on adjacent data paths (i.e. corresponding to each column) are sequentially from the first ECC word, the second ECC word, the third ECC word in four different ECC words. Of course, the embodiment is not limited thereto, and other interleaved data structures may exist.

[0211] The example application scenario can provide a multi-path interleaved coding structure. For example, multiple FEC interleaved codes in the multi-path interleaved coding structure ensure the arrangement of symbols of different FECs interleaved on the same data path and adjacent data paths, so as to effectively deal with burst errors on the same data path and crosstalk on adjacent data paths, spread burst errors on the channel or link in time, and convert them into independent random errors, giving full play to the role of error correction codes.

[0212] The example application scenarios can provide more space for link coefficient training. For example, the error correction mechanism of interleaving and RS coding can cope with both random errors and burst errors. Even if the link equalization coefficient is not optimal, the reliability and bandwidth efficiency of system data transmission will not be significantly reduced.

[0213] The example application scenario can make the balancing strategy, system packet loss rate, delay, and area all in the optimal state, thereby improving the overall performance of the system.

[0214] For the exemplary algorithm, the example application scenario can provide, for example, an RS (272, 258) four-way interleaved error correction structure with the advantages of low latency, almost no bandwidth loss, small ECC word size, FEC design suitable for joint link equalization, and high code rate.

[0215] For example, in terms of low latency, the complexity of coding and error correction can be reduced, the number of iterations of a single FEC is small, and it has low latency compared to the traditional RS (544, 514) algorithm.

[0216] For another example, in terms of almost no bandwidth loss, a typical scenario of burst errors is that there are multiple random errors in an ECC word, and the random errors trigger DFE error judgments, resulting in a high probability that each symbol with a random error will also cause an error in the next symbol (the probability of the error propagating to the third symbol is much lower). This scenario of two consecutive symbol errors can be well handled by multi-path interleaving RS (272, 258). Single RS (544, 514) and dual-path RS (272, 258) can correct any 7 consecutive two-symbol errors. Multi-path interleaving can more effectively correct errors in transmission and improve the reliability of data transmission.

[0217] For another example, in terms of small ECC word size, compared with the existing RS (544, 514), by adopting RS (272, 258) encoding, the length of the error correction code is reduced, the complexity of the error correction module is reduced, and the frequency can be increased.

[0218] For another example, in the design of FEC suitable for joint link equalization, for the case where BER is relatively good and the error propagation coefficient burst is large, an interleaved FEC is designed, which improves the actual error correction capability, reduces latency, and optimizes the area, achieving the goal of overall optimization.

[0219] For another example, in terms of high code rate, compared with the commonly used RS (544, 514), the code rate is higher. In RS (544, 514), every 5440 bits can have 5140 bits of data, while in the multi-path interleaved RS (272, 258), every 5440 bits can have 5160 bits of data.

[0220] In addition or alternative aspects of the above-mentioned example application scenarios, the error correction structure shown can be used for various high-speed links and also supports end-to-end overall solutions. For example, future links may not only be based on level signals, but also on optical signals. The level signal can be sent to the optical transmission module by a short-distance high-speed link. The optical module converts the signal and sends it to the long-distance optical receiving module through the optical fiber. The optical receiving module then converts the optical signal into a level signal and sends it to the final receiving end of the link. Therefore, the error correction structure in the above-mentioned example application scenario can correct random errors and deal with continuous errors well, and can be applied to the above-mentioned end-to-end overall solution, such as encoding at the level sending end and decoding at the level receiving end, providing end-to-end protection, thereby saving the encoding and decoding time of the optical module and improving the efficiency and reliability of the entire system.

[0221] Fig.14 A schematic diagram of an electronic device 1400 according to at least one embodiment of the present disclosure is shown.

[0222] like Fig.14 As shown, the electronic device 1400 includes at least one processing unit 1420 and at least one memory 1410. The memory 1410 stores computer-readable instructions and is in communication with the processing unit 1420. The processing unit 1420 executes the computer-readable instructions stored in the memory 1410 to implement the data processing method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0223] For example, the memory 1410 and the processing unit 1420 may communicate with each other directly or indirectly. Fig.14As shown, the electronic device 1400 may further include a system bus 1430, and the memory 1410 and the processing unit 1420 may communicate with each other through the system bus 1430. For example, the processing unit 1420 may access the memory 1410 through the system bus 1430. For example, in other examples, components such as the memory 1410 and the processing unit 1420 may communicate through a network on chip (NOC) connection.

[0224] For example, the processing unit 1420 can control other components in the electronic device 1400 to perform desired functions. The processing unit 1420 can be a device with data processing capabilities and / or program execution capabilities, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU), and can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0225] For example, the memory 1410 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc.

[0226] For example, one or more computer-readable instructions may be stored on the memory 1410, and the processing unit 1420 may execute the computer-readable instructions to implement various functions. Various applications and various data may also be stored in the computer-readable storage medium, such as instruction processing codes and various data used and / or generated by the application.

[0227] For example, when some computer instructions stored in the memory 1410 are executed by the processing unit 1420 , one or more steps in the data processing method described above can be performed.

[0228] For example, Fig.14As shown, the electronic device 1400 may further include an input interface 1440 that allows an external device to communicate with the electronic device 1400. For example, the input interface 1440 may be used to receive instructions from an external computer device, from a user, etc. The electronic device 1400 may further include an output interface 1450 that interconnects the electronic device 1400 and one or more external devices. For example, the electronic device 1400 may output a signal to the external device 1400 through the output interface 1450, etc.

[0229] It should be noted that the electronic device 1400 according to at least one embodiment of the present disclosure is exemplary rather than restrictive, and according to actual application requirements, the electronic device 1400 may also include other conventional components or structures. For example, to realize the necessary functions of the electronic device, those skilled in the art may set other conventional components or structures according to the specific application scenario, and the embodiments of the present disclosure are not limited to this.

[0230] At least one embodiment of the present disclosure also provides a computer-readable storage medium. Fig.15 A schematic diagram of a computer-readable storage medium 1500 is shown in accordance with at least one embodiment of the present disclosure.

[0231] For example, Fig.15 As shown, the computer-readable storage medium 1500 stores computer-readable instructions 1510. When the computer-readable instructions 1510 are executed by a computer (including a processor), the data processing method and additional aspects thereof according to at least one embodiment of the present disclosure can be implemented.

[0232] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 1500. Some of the computer-readable instructions stored on the computer-readable storage medium 1500 may be, for example, instructions for implementing one or more steps in the above-mentioned data processing method.

[0233] For example, the computer-readable storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above computer-readable storage media, or other applicable storage media. For example, the computer-readable storage medium 1500 may include the memory 1410 in the above electronic device 1400.

[0234] At least some embodiments of the present disclosure also provide an electronic device. Fig.16 A schematic diagram of another electronic device 1600 is shown in accordance with at least one embodiment of the present disclosure.

[0235] The electronic device according to at least one embodiment of the present disclosure can be implemented as but not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc.

[0236] Fig.16 The electronic device 1600 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0237] For example, Fig.16 As shown, in some examples, the electronic device 1600 includes a processor 1601, which may include a processor of any of the above embodiments (e.g., an SMT processor), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1602 or a program loaded from a storage device 1608 into a random access memory (RAM) 1603. Various programs and data required for the operation of the computer system are also stored in RAM 1603. The processor 1601, ROM 1602, and RAM 1603 are connected to each other via a bus 1604. An input / output (I / O) interface 1605 is also connected to the bus 1604.

[0238] For example, the following components may be connected to the I / O interface 1605: an input device 1606 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1607 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1608 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1609 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1609 may allow the electronic device 1600 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. The drive 1610 is also connected to the I / O interface 1605 as needed. Removable media 1611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive 1610 as needed, so that the computer program read therefrom can be installed into the storage device 1608 as needed. Although Fig.16 The electronic device 1600 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0239] For example, the electronic device 1600 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1609 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0240] In addition to the above exemplary descriptions, the following points need to be explained for this disclosure:

[0241] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0242] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0243] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A data processing method, comprising: Performing an encoding operation based on the original data to generate N independent error correction codewords, each of the N independent error correction codewords includes a data code and a check code, N is an integer and N≥2; Interleaving the data codes and the check codes included in the N independent error correction codewords to obtain interleaved data; as well as The interleaved data is sent.

2. The data processing method according to claim 1, wherein: The N independent error correction code words are transmitted through a plurality of data paths, and data codes and check codes included in the N independent error correction code words are interleaved, including: The N independent error correction codewords are alternately arranged in a new data stream so that M consecutive symbols on each data path in the multiple data paths belong to different error correction codewords in the N independent error correction codewords, where M is an integer and 2≤M≤N.

3. The data processing method according to claim 2, wherein: M=N.

4. The data processing method according to claim 2 or 3, further comprising: The N independent error correction codewords are alternately arranged in a new data stream so that corresponding symbols on adjacent data paths in the plurality of data paths belong to different error correction codewords in the N independent error correction codewords.

5. The data processing method according to claim 1, wherein: Based on the original data, an encoding operation is performed to generate N independent error correction codewords, including: Dividing the original data into N independent sub-data as the data code; The encoding operation is performed independently on the N independent sub-data to obtain an error correction code for each of the N independent sub-data as the check code.

6. The data processing method according to claim 1, wherein: The original data is divided into N independent sub-data, including: The original data is randomly divided into N independent sub-data.

7. The data processing method according to claim 1, wherein: N＝4。 8. The data processing method according to claim 7, wherein: The encoding operation adopts RS (272, 258) algorithm.

9. The data processing method according to claim 1, wherein: The interleaved data is sent via a high-speed link, and the high-speed link supports sending the interleaved data in the form of at least one of a level signal and an optical signal.

10. A data processing method, comprising: Receiving interleaved data to obtain a read-back data code and a read-back error correction code, wherein the interleaved data is generated based on encoding the original data to generate N independent error correction code words, and the data code and the check code included in the N independent error correction code words are interleaved to obtain the data code and the check code, each of the N independent error correction code words includes a data code and a check code, N is an integer and N≥2; De-interleaving the read-back data code and the read-back error correction code to obtain N independent read-back error correction code words; as well as Decoding and error correction operations are performed on the N independent read-back error correction codewords.

11. The data processing method according to claim 10, wherein: Performing decoding and error correction operations on the N independent read-back error correction codewords, including: Decoding and error correction operations are performed independently on each of the N independent read-back error correction codewords.

12. A data processing device, comprising: An error correction codeword generating unit is configured to perform an encoding operation based on the original data to generate N independent error correction codewords, each of the N independent error correction codewords includes a data code and a check code, N is an integer and N≥2; an interleaving unit, configured to interleave the data code and the check code included in the N independent error correction codewords to obtain interleaved data; as well as The sending unit is configured to send the interleaved data to a data receiving end.

13. A data processing device, comprising: A receiving unit is configured to receive the interleaved data to obtain a read-back data code and a read-back error correction code, wherein the interleaved data is generated based on an encoding operation on the original data to generate N independent error correction code words, and the data code and the check code included in the N independent error correction code words are interleaved to obtain the data code and the check code, each of the N independent error correction code words includes a data code and a check code, N is an integer and N≥2; a de-interleaving unit configured to de-interleave the read-back data code and the read-back error correction code to obtain N independent read-back error correction code words; as well as The decoding and error correction unit is configured to perform decoding and error correction operations on the N independent read-back error correction code words.

14. A data transmission system, comprising: The data processing device according to claim 12; or A data processing apparatus according to claim 13.

15. An electronic device comprising: at least one processor; at least one memory having instructions stored therein, When the instruction is executed by the processor, the processor executes the data processing method as described in any one of claims 1-11.

16. A computer-readable storage medium having computer-readable instructions stored thereon, in, When the computer-readable instructions are executed by a processor, the processor is caused to perform the data processing method according to any one of claims 1 to 11.

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